Semiconductor device

Abstract

To provide a semiconductor device that can improve yield.SOLUTION: The semiconductor device includes a first insulating plate, a first metal plate provided on a first surface of the first insulating plate, a second metal plate provided on a second surface facing the first surface of the first insulating plate, a semiconductor chip provided on the second metal plate, and a resin member sealing the semiconductor chip. In the semiconductor device, there is only one semiconductor chip that is provided on the second metal plate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In high-voltage power modules used in electric vehicles, etc., semiconductor chips such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are mounted on an insulating plate. In such power modules, a large number of semiconductor chips are generally used, and therefore there is a demand for improving the yield. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4972503 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device capable of improving the yield. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes a first insulating plate, a first metal plate provided on a first surface of the first insulating plate, a second metal plate provided on a second surface opposite to the first surface of the first insulating plate, a semiconductor chip provided on the second metal plate, and a resin member that seals the semiconductor chip. In this semiconductor device, the number of semiconductor chips provided on the second metal plate is only one. [Brief description of the drawings]

[0006] [Figure 1]1 is a cross-sectional view showing a schematic structure of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 11 is a cross-sectional view showing a schematic structure of a semiconductor device according to a second embodiment. [Diagram 3] FIG. 11 is a cross-sectional view showing a schematic structure of a semiconductor device according to a modified example of the second embodiment. [Figure 4] FIG. 11 is a cross-sectional view showing a schematic structure of a semiconductor device according to a third embodiment. [Diagram 5] FIG. 13 is a cross-sectional view showing a schematic structure of a semiconductor device according to a fourth embodiment. [Figure 6] FIG. 13 is a cross-sectional view showing a schematic structure of a semiconductor device according to a fifth embodiment. [Figure 7] FIG. 13 is a cross-sectional view showing an exploded structure of a semiconductor device according to a sixth embodiment. [Figure 8] FIG. 13 is a cross-sectional view showing a schematic structure of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0008] (First embodiment) Fig. 1 is a cross-sectional view showing a schematic structure of a semiconductor device according to a first embodiment. The semiconductor device 1 shown in Fig. 1 includes a first metal plate 11, a first insulating plate 12, a second metal plate 13, a first bonding material 14, a semiconductor chip 15, a bonding wire 16, and a resin member 17.

[0009] The first metal plate 11 is joined to the rear surface (first surface) of the first insulating plate 12. The first metal plate 11 functions as a heat sink that dissipates heat generated by the operation of the semiconductor chip 15. The first metal plate 11 can be formed, for example, by processing copper (Cu) into a plate shape.

[0010] The first insulating plate 12 includes an insulating material such as silicon nitride (SiN), aluminum nitride (AlN), aluminum oxide (Al2O3), etc. The first insulating plate 12 can be formed by processing one of these insulating materials into a plate shape.

[0011] The second metal plate 13 is bonded to the surface (second surface) of the first insulating plate 12. The second metal plate 13 is a conductive plate for electrically connecting the semiconductor chip 15 to terminals (not shown in FIG. 1). The second metal plate 13 can be formed, for example, by processing copper into a plate shape. The second metal plate 13 has a circuit pattern formed thereon for individually connecting various electrodes provided on the semiconductor chip 15 to the terminals.

[0012] The first bonding material 14 is provided between the second metal plate 13 and the semiconductor chip 15. For example, a solder material or a sintered material can be used for the first bonding material 14. The sintered material contains, for example, silver or copper. When the first bonding material 14 is a sintered material, the thermal resistance can be reduced.

[0013] The semiconductor chip 15 is bonded to the second metal plate 13 by a first bonding material 14. The semiconductor chip 15 has a semiconductor element including a compound semiconductor such as SiC (silicon carbide). The semiconductor element using SiC includes, for example, a MOSFET or an IGBT.

[0014] When the semiconductor element is a MOSFET, a drain electrode is formed on the back side of the semiconductor chip 15. Meanwhile, a source electrode and a gate electrode are formed on the front side of the semiconductor chip 15. When the semiconductor element is an IGBT, a collector electrode is formed on the back side of the semiconductor chip 15. Meanwhile, an emitter electrode and a gate electrode are formed on the front side of the semiconductor chip 15.

[0015] One end of the bonding wire 16 is bonded to a source electrode (an emitter electrode if the semiconductor chip 15 is an IGBT) or a gate electrode of the semiconductor chip 15. The other end of the bonding wire 16 is bonded to the second metal plate 13. The bonding wire 16 is made of, for example, aluminum, and is bonded to the semiconductor chip 15 and the second metal plate 13 by ultrasonic bonding.

[0016] 1 shows only one bonding wire 16, there is no particular limit to the number of bonding wires 16. Also, the semiconductor chip 15 may be electrically connected to the second metal plate 13 by ribbon bonding instead of the bonding wire 16.

[0017] The resin member 17 seals the semiconductor chip 15 and the bonding wires 16. The resin member 17 is a molding resin.

[0018] In the semiconductor device 1 configured as described above, if multiple semiconductor chips 15 are mounted on one first insulating plate 12, even a non-defective semiconductor chip 15 will be treated as a defective product if even one defect occurs in an electrical test process that checks the electrical characteristics of the semiconductor chip 15. This will result in a decrease in yield.

[0019] On the other hand, in the semiconductor device 1 according to this embodiment, only one semiconductor chip 15 is mounted on one first insulating plate 12. This makes it possible to prevent a non-defective semiconductor chip 15 from being treated as a defective product. This makes it possible to improve the yield.

[0020] Second embodiment 2 is a cross-sectional view showing a schematic structure of a semiconductor device according to the second embodiment. The same components as those in the first embodiment described above are given the same reference numerals, and detailed description thereof will be omitted.

[0021] 2, a third metal plate 18 is bonded to the surface of a semiconductor chip 15 by a second bonding material 19. The third metal plate 18 is made of a copper plate, similar to the first metal plate 11 and the second metal plate 13 described in the first embodiment. The second bonding material 19 is made of a solder material or a sintered material, similar to the first bonding material 14.

[0022] The third metal plate 18 has a first portion 181 and a second portion 182. The first portion 181 is electrically connected to the gate electrode of the semiconductor chip 15. On the other hand, the second portion 182 is electrically connected to the emitter electrode or the source electrode of the semiconductor chip 15.

[0023] Fig. 3 is a cross-sectional view showing a schematic structure of a semiconductor device according to a modified example of the second embodiment. A semiconductor device 2b shown in Fig. 3 is provided with a semiconductor chip 151 instead of the semiconductor chip 15. The semiconductor chip 151 is a flip chip. That is, the semiconductor chip 15 shown in Fig. 2 is inverted 180 degrees with respect to the first insulating plate 12. Therefore, a source electrode (an emitter electrode if the semiconductor chip 151 is an IGBT) and a gate electrode are disposed on the back side of the semiconductor chip 151, and a drain electrode (a collector electrode if the semiconductor chip 151 is an IGBT) is disposed on the front side of the semiconductor chip 151.

[0024] In the semiconductor device 2b according to this modification, the first portion 181 of the third metal plate 18 is joined to the first portion 131 of the second metal plate 13 by the third bonding material 20. The second portion 182 of the third metal plate 18 is joined to the second portion 132 of the second metal plate 13 by the third bonding material 20. The third bonding material 20 is made of a solder material or a sintered material, like the first bonding material 14 and the second bonding material 19.

[0025] In this modification, the thickness of the third metal plate 18 is preferably within a range of 50 μm to 200 μm in order to function as a stress relaxation layer. The thickness of the third bonding material 20 is thinner than the thickness of the third metal plate 18. However, if the thickness of the third bonding material 20 is too thin, the bonding between the third metal plate 18 and the second metal plate 13 may be insufficient. Therefore, the thickness of the third bonding material 20 is preferably within a range of, for example, 20 μm to 40 μm.

[0026] Furthermore, in the semiconductor device 2b according to this modification, the fourth metal plate 21 is bonded to the surface of the semiconductor chip 151 by the first bonding material 14. The fourth metal plate 21 is a copper plate like the other metal plates. The fourth metal plate 21 is electrically connected to the drain electrode of the semiconductor chip 15 (the collector electrode when the semiconductor chip 15 is an IGBT).

[0027] In the semiconductor device 2a according to the present embodiment described above, the number of semiconductor chips 15 mounted on the first insulating plate 12 is only one. In the semiconductor device 2b according to the present modification, the number of semiconductor chips 151 mounted on the first insulating plate 12 is only one. Therefore, also in this embodiment, it is possible to avoid treating a non-defective semiconductor chip as a defective one. Thus, it is possible to improve the yield.

[0028] Third embodiment 4 is a cross-sectional view showing a schematic structure of a semiconductor device according to the third embodiment. The same components as those in the first and second embodiments described above are given the same reference numerals, and detailed description thereof will be omitted.

[0029] 4, a first recess 133 is provided on the upper part of the second metal plate 13. A semiconductor chip 15 is disposed in this first recess 133. In the semiconductor device 3 according to this embodiment, a plating layer 22 is formed on each surface of the first metal plate 11, the second metal plate 13, and the third metal plate 18.

[0030] The plating layer 22 can be formed by, for example, electroless plating. In this embodiment, a planarization process of the plating layer 22 is performed after the electroless plating process. In this planarization process, the plating layer 22 is ground so that a height h1 from the bottom of the first recess 133 to the plating layer 22 formed on the upper end of the first recess 133 and a height h2 from the bottom of the first recess 133 to the plating layer 22 formed on the upper surface of the third metal plate 18 are equal to each other. This planarization process allows three wirings connected to the gate electrode, the drain electrode (collector electrode when the semiconductor chip 15 is an IGBT), and the emitter electrode (source power), respectively, to be formed on the same wiring layer.

[0031] In the present embodiment described above, the number of semiconductor chips 15 mounted on the first insulating plate 12 is only one. Therefore, similar to the first and second embodiments described above, it is possible to prevent a non-defective semiconductor chip 15 from being treated as a defective product. This makes it possible to improve the yield.

[0032] (Fourth embodiment) Fig. 5 is a cross-sectional view showing a schematic structure of a semiconductor device according to the fourth embodiment. The semiconductor device 4 shown in Fig. 5 is a case-type power module in which a plurality of semiconductor devices 1 described in the first embodiment are housed in a case 43.

[0033] In this embodiment, each semiconductor device 1 is individually bonded to a base material 42 by a fourth bonding material 41. That is, the semiconductor device 4 is provided with the same number of base materials 42 as the semiconductor devices 1. The fourth bonding material 41 is, for example, a solder material. The base material 42 also functions as a heat sink for dissipating heat generated in the semiconductor chip 15 of the semiconductor device 1. The base material 42 contains, for example, copper or aluminum.

[0034] In the semiconductor device 4 according to this embodiment, each semiconductor device 1 is individually placed on a base material 42. That is, a base material 42 is provided for each semiconductor device 1. The back surface of the base material 42 is exposed from a case 43. The case 43 is formed of, for example, resin.

[0035] The case 43 is fixed to the heat dissipation fins 40 using screws 47 and washers 48. Grease material 49 is applied between the case 43 and the heat dissipation fins 40. The grease material 49 fills the gap formed between the case 43 and the heat dissipation fins 40, so that the heat generated by the semiconductor chip 15 can be efficiently transferred to the heat dissipation fins 40.

[0036] The case 43 is filled with a sealant 44. For example, a transparent gel is used as the sealant 44. The upper opening of the case 43 is sealed with a lid 45. In this way, each semiconductor device 1 is sealed in the case 43.

[0037] Furthermore, the case 43 is provided with a terminal 46. One end of the terminal 46 is joined to the second metal plate 13 of each semiconductor device 1. The other end of the terminal 46 is exposed to the outside of the case 43.

[0038] When the semiconductor device 4 is mounted in a power converter such as an inverter, the power converted from DC to AC by the switching operation of each semiconductor chip 15 is supplied to a load such as a motor connected to the other end of the terminal 46. In this manner, the terminal 46 can function as a power terminal.

[0039] Furthermore, one end of the terminal 46 may be connected to a gate electrode of the semiconductor chip 15. In this case, the other end of the terminal 46 is connected to a gate drive circuit (not shown). The gate drive circuit generates a control signal that turns the semiconductor chip 15 on and off. The switching operation of the semiconductor chip 15 is controlled by this control signal. In this manner, the terminal 46 can also function as a signal terminal.

[0040] In the present embodiment described above, one power module is configured by incorporating a plurality of semiconductor devices 1. In the incorporated semiconductor device 1, only one semiconductor chip 15 is mounted on one first insulating plate 12. This makes it possible to prevent a semiconductor chip 15 that is a non-defective product before being incorporated into a power module from being treated as a defective product. Therefore, this embodiment also makes it possible to improve the yield.

[0041] Fifth embodiment Fig. 6 is a cross-sectional view showing a schematic structure of a semiconductor device according to the fifth embodiment. The semiconductor device 5 shown in Fig. 6 is a double-sided heat dissipation type power module that dissipates heat from both sides of the semiconductor chip 15 and the semiconductor chip 151 described in the second embodiment.

[0042] In this embodiment, the semiconductor device 2a and the semiconductor device 2b are sealed with a resin member 50. The resin member 50 is, for example, a molded resin. In the resin member 50, the third metal plate 18 of the semiconductor device 2a is joined to a seventh metal plate 52 by a fifth bonding material 51. The fifth bonding material 51 is, for example, a solder material. The seventh metal plate 52 is, for example, a copper plate.

[0043] The seventh metal plate 52 is bonded to the rear surface of the third insulating plate 53. The third insulating plate 53 contains an insulating material such as silicon nitride (SiN), aluminum nitride (AlN), or aluminum oxide (Al2O3) like the first insulating plate 12. An eighth metal plate 54 is bonded to the front surface of the third insulating plate 53. The top surface of the eighth metal plate 54 is exposed from the resin member 50. The eighth metal plate 54 is, for example, a copper plate.

[0044] In the semiconductor device 2a according to this embodiment, heat generated on the front surface side of the semiconductor chip 15 is transmitted through the seventh metal plate 52 and the third insulating plate 53, and is finally dissipated from the eighth metal plate .

[0045] In addition, within the resin member 50, the fourth metal plate 21 of the semiconductor device 2b is joined to a fifth metal plate 57 by a sixth bonding material 56. The sixth bonding material 56 is, for example, a solder material. The fifth metal plate 57 is, for example, a copper plate.

[0046] The fifth metal plate 57 is bonded to the rear surface of the second insulating plate 58. The second insulating plate 58 contains an insulating material such as silicon nitride (SiN), aluminum nitride (AlN), or aluminum oxide (Al2O3) like the first insulating plate 12. A sixth metal plate 59 is bonded to the front surface of the second insulating plate 58. The top surface of the sixth metal plate 59 is exposed from the resin member 50. The sixth metal plate 59 is, for example, a copper plate.

[0047] In the semiconductor device 2 b according to this embodiment, heat generated on the front surface side of the semiconductor chip 151 is transmitted through the fifth metal plate 57 and the second insulating plate 58 , and is finally dissipated from the sixth metal plate 59 .

[0048] In the semiconductor device 5 according to this embodiment, a terminal 55a is bonded to the second metal plate 13 of the semiconductor device 2a. The terminal 55a can function as a power terminal electrically connected to a drain electrode of the semiconductor chip 15 (a collector electrode when the semiconductor chip 15 is an IGBT). In addition, a terminal 55b is bonded to the first portion 131 of the second metal plate 13 of the semiconductor device 2b. The terminal 55b can function as a signal terminal electrically connected to a gate electrode of the semiconductor chip 151.

[0049] In the present embodiment described above, one power module is constructed by incorporating the semiconductor device 2a and the semiconductor device 2b. In the incorporated semiconductor device 2a and the semiconductor device 2b, the number of the semiconductor chip 15 and the semiconductor chip 151 mounted on one first insulating plate 12 is only one each. Therefore, it is possible to prevent the semiconductor chip 15 and the semiconductor chip 151, which are non-defective before being incorporated into the power module, from being treated as defective. Therefore, the present embodiment also makes it possible to improve the yield.

[0050] Sixth embodiment Fig. 7 is a cross-sectional view showing an exploded structure of a semiconductor device according to a sixth embodiment. Fig. 8 is a cross-sectional view showing a schematic structure of a semiconductor device according to a sixth embodiment. The semiconductor device 6 shown in Figs. 7 and 8 is a power module having a component-embedded structure in which the semiconductor device 3 described in the third embodiment is embedded in a printed circuit board 60. Although only one semiconductor device 3 is embedded in the printed circuit board 60 in Figs. 7 and 8, the number of semiconductor devices 3 may be at least one.

[0051] In the semiconductor device 6 according to this embodiment, the printed circuit board 60 is formed using an epoxy resin. A second recess 601 is provided on the lower side of the printed circuit board 60 as shown in FIG. 7. The semiconductor device 3 is embedded in the second recess 601. At this time, a part of the semiconductor device 3 is embedded in the second recess 601 as shown in FIG. 8. For example, in order to avoid deterioration of heat dissipation characteristics while ensuring the sealing characteristics of the semiconductor chip 15, the semiconductor chip 15, the second metal plate 13, and the third metal plate 18 are disposed in the second recess 601, and the first metal plate 11 and the first insulating plate 12 are exposed from the second recess 601.

[0052] Furthermore, a plurality of wirings 61 are provided within the printed circuit board 60. Each wiring 61 is formed of, for example, a plated metal wire. The plurality of wirings 61 are individually connected to the gate electrode, the drain electrode (collector electrode if the semiconductor chip 15 is an IGBT), and the source electrode (emitter electrode if the semiconductor chip 15 is an IGBT) of the semiconductor chip 15.

[0053] In the semiconductor device 3, as described in the third embodiment, the height h1 from the bottom of the first recess 133 to the plating layer 22 formed on the upper end of the first recess 133 is equal to the height h2 from the bottom of the first recess 133 to the plating layer 22 formed on the upper surface of the third metal plate 18. Therefore, the wiring 61 connected to each electrode of the semiconductor chip 15 can be formed in the same wiring layer. This makes it possible to reduce electrical loss and thermal loss occurring in the wiring 61. Note that, although the plating layer 22 is not connected to the wiring 61 in FIG. 8, they are connected via, for example, a contact plug (not shown).

[0054] In the semiconductor device 6 according to this embodiment, a pad 62 is formed on a portion of the printed circuit board 60. An electronic component 63 is mounted on the pad 62. The pad 62 is made of, for example, copper foil. The electronic component 63 includes passive components such as a capacitor or a coil, and active components such as an LSI (Large Scale Integration). The passive components are used in, for example, circuit elements such as a DC-DC converter. The active components are used in, for example, a gate drive circuit of the semiconductor chip 15.

[0055] In the present embodiment described above, one power module is configured by embedding at least one semiconductor device 3 in a printed circuit board 60. In the embedded semiconductor device 3, only one semiconductor chip 15 is mounted on one first insulating plate 12. This makes it possible to prevent a non-defective semiconductor chip 15 from being treated as a defective product before being embedded in the printed circuit board 60. Therefore, this embodiment also makes it possible to improve the yield.

[0056] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0057] 1-6: Semiconductor device 11: 1st metal plate 12: First insulating plate 13:Second metal plate 15, 151: Semiconductor chips 16: Bonding wire 17: Resin material 18:Third metal plate 20:Third bonding material 21: 4th metal plate 22: Plating layer 42: Base material 43: Case 50: Resin material 57: 5th metal plate 59: 6th metal plate 60: Printed circuit board 63: Electronic parts 133: First recess 601: Second recess

Claims

1. A first insulating plate; a first metal plate provided on a first surface of the first insulating plate; a second metal plate provided on a second surface of the first insulating plate opposite to the first surface; a semiconductor chip provided on the second metal plate; a resin member that seals the semiconductor chip; Equipped with The semiconductor device, wherein the number of the semiconductor chips provided on the second metal plate is only one.

2. a bonding wire having one end bonded to the semiconductor chip and the other end bonded to the second metal plate; 2. The semiconductor device according to claim 1, wherein the bonding wires are sealed in the resin member together with the semiconductor chip.

3. A third metal plate is provided on the semiconductor chip. The semiconductor device according to claim 1 , wherein the third metal plate is sealed together with the semiconductor chip in the resin member.

4. the semiconductor chip is a flip chip, a third metal plate provided between the flip chip and the second metal plate; A bonding material provided between the second metal plate and the third metal plate; The semiconductor device according to claim 1 , further comprising:

5. The thickness of the third metal plate is within a range of 50 μm to 200 μm, 5. The semiconductor device according to claim 4, wherein the thickness of the bonding material is within a range of 20 μm to 40 μm.

6. a first recess in which the semiconductor chip is disposed is provided on an upper portion of the second metal plate; a third metal plate provided on the semiconductor chip; a plating layer provided on an upper end portion of the first recess and on an upper surface of the third metal plate; The semiconductor device according to claim 1 , further comprising:

7. 7. The semiconductor device according to claim 6, wherein a height from a bottom of the recess to a plating layer provided on the upper end of the recess is equal to a height from the bottom to a plating layer provided on the upper surface of the third metal plate.

8. a case for accommodating a plurality of the semiconductor devices; The semiconductor device according to claim 2 , further comprising a plurality of base members provided for each of said semiconductor devices.

9. a fourth metal plate provided on the flip chip; a fifth metal plate joined to the fourth metal plate; a second insulating plate provided on the fifth metal plate; a sixth metal plate provided on the second insulating plate; The semiconductor device according to claim 4 , further comprising:

10. the resin member is a printed circuit board, and a second recess is provided in a bottom portion of the printed circuit board, in which the semiconductor chip, the second metal plate, and the third metal plate are disposed; The semiconductor device according to claim 6 , further comprising an electronic component provided on the printed circuit board.

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