Semiconductor device

Abstract

To provide a semiconductor device having high operation stability, and including laminated structure in which a metal electrode layer is laminated on a semiconductor layer made from Si.SOLUTION: A semiconductor device is provided, including: laminated structure which has rectification and in which a first metal electrode layer is laminated on a p-type semiconductor layer made of a p-type Si; and / or laminated structure which has an ohmic property and in which a second metal electrode layer is laminated on an n-type semiconductor layer made of an n-type Si. A layered chemical compound layer made of a layered chemical compound of Sb and / or Bi, and Te is interposed into between the p-type Si semiconductor layer and the first metal electrode layer and / or the n-type semiconductor layer and the second metal electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si. [Background technology]

[0002] When a semiconductor layer made of Si is brought into contact with a metal layer, it may become a "diode junction (Schottky junction)" that exhibits rectification, or it may become an "ohmic junction" that does not exhibit such rectification. This difference depends on the size of the energy barrier between the Si semiconductor layer and the metal layer, and on whether the Si semiconductor layer is made of a p-type or n-type semiconductor, as well as the type of metal to be combined.

[0003] For example, Patent Document 1 discloses a semiconductor device including an MPS (Merged pin Schottky) structure in which Schottky diodes and pn-type diodes are alternately arranged on one surface of a semiconductor element, and a Schottky junction is provided in the n-type semiconductor region and an Ohmic junction is provided in the p-type semiconductor region. This document describes that the interface is not stable when a NiAl alloy is bonded to form a Schottky junction on the n-type semiconductor region using SiC as a semiconductor substrate, and then describes that the Schottky junction layer in the n-type semiconductor region and the Ohmic junction layer in the p-type semiconductor region should be formed from different materials. Specifically, it describes that the Ohmic junction layer is made of an alloy containing aluminum and titanium, and the Schottky junction layer is made of a metal mainly composed of molybdenum. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2010-50267 A Summary of the Invention [Problem to be solved by the invention]

[0005] When a semiconductor layer made of Si is brought into contact with a metal layer, whether the contact is rectifying or ohmic, if the contact interface is not stable, operational stability cannot be obtained. As described above, it has been confirmed that even if a high-melting-point metal such as molybdenum is used, the contact interface becomes wavy and sufficient operational stability cannot be obtained.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device having a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si, and having high operational stability. [Means for solving the problem]

[0007] The inventors of the present application have noted that, for example, even W, which is a high-melting point metal, does not form a sufficiently flat interface when bonded to Si, resulting in a lack of operational stability in the semiconductor device, such as rectification and ohmic properties.

[0008] That is, the semiconductor device according to the present invention is a semiconductor device including a laminated structure exhibiting rectifying properties in which a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and / or a laminated structure exhibiting ohmic properties in which a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si, and is characterized in that a layered compound layer made of a layered compound of Sb and / or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer and / or between the n-type semiconductor layer and the second metal electrode layer.

[0009] According to such features, a semiconductor device with high operational stability can be obtained by interposing a layered compound layer which exhibits rectification and ohmic properties between the semiconductor layer and has high interface smoothness.

[0010] In the above-mentioned invention, the layered compound layer may contain an amorphous phase. With this feature, good interface smoothness can be obtained, and a semiconductor device with high operational stability can be obtained.

[0011] In the above-described invention, the layered compound layer may be characterized by having a thickness of 1 to 10 nm. According to such a feature, a semiconductor device with high operating stability can be obtained regardless of the metal species of the metal electrode layer.

[0012] In the above-described invention, the layered compound may be characterized by consisting of (Sb x Bi 1-x )2Te3 (where 0 < x < 1). According to such a feature, a semiconductor device that exhibits good rectifying properties and ohmic properties, provides good interface smoothness, and has high operating stability can be obtained.

[0013] The p-type Si may be characterized by containing Ge in Si. Also, the n-type Si may be characterized by containing C in Si. According to such a feature, a semiconductor device that exhibits good rectifying properties and ohmic properties and has high operating stability can be obtained.

Brief Description of the Drawings

[0014] [Figure 1] It is a diagram showing a stacked structure in which a metal electrode layer is stacked on a semiconductor layer according to the present invention. [Diagram 2] It is a band diagram when a metal electrode layer and a (b) layered compound layer are respectively connected to an n-type Si semiconductor. [Diagram 3] It is a cross-sectional STEM (scanning transmission electron microscope) image near the connection interface when a metal electrode layer and a (b) layered compound layer are respectively connected to a semiconductor layer. [Figure 4] It is a cross-sectional view showing a joint portion between a semiconductor layer and a layered compound layer according to the present invention. [Diagram 5] It is a band diagram of a Si semiconductor and Sb2Te3 and Bi2Te3. [Figure 6] It is a diagram showing the potential barrier height for n-type Si. [Figure 7] It is a graph of the heat treatment temperature and potential barrier height of a layered compound layer joined to a p-type Si semiconductor (resistivity: 5 Ωcm). [Figure 8]1 is a graph showing the relationship between the applied voltage and the current for a junction structure of an n-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and for a junction structure in which Sb2Te3 is formed between them. [Figure 9] This is a graph showing the relationship between the applied voltage and the current for a junction structure of a p-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and a junction structure in which Sb2Te3 is formed between them. [Figure 10] 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

[0016] First, a method for manufacturing a semiconductor device and the semiconductor device obtained will be described with reference to FIG.

[0017] As shown in FIG. 1, first, a layered compound layer 4 made of an amorphous film made of Sb and / or Bi and Te is formed on a semiconductor layer 2. The semiconductor layer 2 is made of a Si semiconductor. The Si semiconductor is selected from either a p-type semiconductor made of p-type Si or an n-type semiconductor made of n-type Si. It may be made of a Si semiconductor containing C or Ge. Then, a metal electrode layer 3 is provided on the layered compound layer 4. As a result, the layered compound layer 4 made of a layered compound made of Sb and / or Bi and Te is interposed between the semiconductor layer 2 and the metal electrode layer 3.

[0018] There is no particular limitation on the material of the metal electrode layer 3, and for example, tungsten (W), cobalt (Co), ruthenium (Ru), etc. can be used.

[0019] The material of the layered compound layer 4 is Sb x Te 1-x , Bi x Te 1-x , (Bi x Sb 1-x )2Te3, where 0 <x<1である。

[0020] Next, the amorphous film of the layered compound layer 4 is crystallized by heat treatment. The amorphous film is crystallized by heat treatment at an appropriate temperature to become a layered compound with a crystalline phase. As described later, the layered compound layer 4 may contain an amorphous phase and may not be heat treated. Also, a crystallized layered compound layer 4 can be obtained by forming the layered compound layer 4 on the semiconductor layer 2 while performing heat treatment.

[0021] The semiconductor device 1 thus obtained includes a laminated structure of a metal electrode layer / semiconductor layer, and compared to a case where the metal electrode layer and the semiconductor layer are directly bonded, the height of the potential barrier between these layers can be changed, and for example, the contact resistance can be reduced or the on / off ratio of the diode current can be improved.

[0022] 2(a), in general, when an n-type Si semiconductor (n-Si) is bonded to a metal electrode layer 3 (W) as the semiconductor layer 2, a diode junction with a high potential barrier height (BH) is formed due to the difference between the work function of the metal and the work function of the semiconductor layer, and due to Fermi level pinning caused by metal induced gap states (MIGS). Therefore, when the metal electrode layer 3 is bonded to the semiconductor layer 2 made of an n-type Si semiconductor, the contact resistance increases.

[0023] 2(b), in the structure of the semiconductor device 1 of this embodiment, when the layered compound layer 4 made of Sb2Te3 is joined to the semiconductor layer 2, the pinning position of the Fermi level is changed, and the potential barrier height (BH) can be lowered. This reduces the contact resistance compared to when a metal electrode layer is directly joined to the semiconductor layer, and makes it possible to form an ohmic junction that exhibits ohmic properties.

[0024] Also, as shown in FIG. 3(a), it is generally difficult to obtain a flat bonded interface when the semiconductor layer 2 and the metal electrode layer 3 are bonded. On the other hand, as shown in FIG. 3(b), in the laminated structure of this embodiment, a bonded interface that is flat at the atomic level can be obtained between the semiconductor layer 2 and the layered compound layer 4. The layered compound layer 4 has a lower limit of thickness of about 1 nm, which is the thickness of one layer that is the smallest unit of the layered compound. In addition, the layered compound layer 4 is preferably made to have a thickness of 10 nm or less so as not to excessively increase the resistance. This upper limit of thickness is based on the fact that the resistivity in the vertical direction of the layered compound layer 4 is about 0.01 Ωcm. For example, when the specific contact resistivity is 10 -8 Ωcm 2 In order to obtain the following, the film thickness can be calculated to be 10 nm or less, assuming that the resistivity in the vertical direction×film thickness=specific contact resistivity. In other words, the thickness of the layered compound layer 4 is preferably within the range of 1 to 10 nm.

[0025] In addition, as shown in Fig. 4, by obtaining such an atomically flat bonding surface, a defect-free interface that is ideal as a bonding surface can be formed between the semiconductor layer 2 (Si semiconductor) and the layered compound layer 4 (Te-based layered material), which allows a semiconductor device with high operational stability to be obtained.

[0026] Furthermore, as shown in FIG. 5, the Si used in the semiconductor layer 2 has the highest valence band E V , the lowest E of the conduction band C According to the example in the figure, n-type Si has a band gap between the lowest conduction band E CIt is advantageous to use a layered compound layer 4 having a work function close to that of the valence band, for example, Sb2Te3. V For example, Bi2Te3 is preferably used. Thus, the layered compound made of Sb and / or Bi and Te used in the layered compound layer 4 has a characteristic band alignment with respect to a Si semiconductor.

[0027] In particular, (Bi x Sb 1-x In a layered compound consisting of Sb2Te3, when the composition ratio is changed by changing the value of x within the range of 0 to 1, the work function changes between the work function of Sb2Te3 and the work function of Bi2Te3. x Sb 1-x The work function of 2Te3 is the lowest conduction band of Si, E, depending on the composition ratio of x. C From around the top of the Si valence band, E V Therefore, the barrier height for electrons due to contact between the semiconductor layer 2 and the metal electrode layer 3 is not merely changed, but can be adjusted according to the change in the work function.

[0028] As shown in Fig. 6, in the past, no material was found that has a potential barrier height with n-type Si close to the Ec (conduction band) edge, except for rare earth elements such as lanthanides. However, the layered compounds of Sb and Te used in the layered compound layer 4 of this embodiment can make the potential barrier height with Si close to the Ec edge to a degree comparable to that of rare earth elements. As a result, the layered compound layer 4 made of an SbTe-based compound can reduce the contact resistance between the semiconductor layer 2 made of n-type Si and the metal electrode layer 3.

[0029] As shown in Fig. 7, it was found that the potential barrier height (BH) is higher when the metal layer (W) is bonded via the layered compound layer of Sb2Te3 than when the metal layer (W) is directly bonded to the semiconductor layer 2 made of a p-type Si semiconductor with a resistivity of 5 Ωcm (W / Si). It was also confirmed that there is almost no change in the potential barrier height of the layered compound layer when it is as-deposited as an amorphous film and when it is heat-treated at four different heat treatment temperatures (annealing temperatures) of 100, 200, 300, and 400°C. In other words, it was found that the potential barrier height can be obtained in the amorphous phase as well as in the crystalline phase.

[0030] Also, as shown in FIG. 8, in the stacked structure of this embodiment using Sb2Te3 as the layered compound layer, the current is larger when a reverse voltage is applied compared to a Schottky barrier diode using a conventional metal junction with an n-type Si semiconductor having a resistivity of 5 Ωcm. There is almost no difference in the current when a forward voltage is applied. In this way, a characteristic with a low on / off ratio can be obtained compared to the conventional metal junction. In other words, a stacked structure with an ohmic junction with low contact resistance can be obtained.

[0031] On the other hand, as shown in FIG. 9, in the stacked structure of this embodiment using Sb2Te3 for the layered compound layer, the current when a reverse voltage is applied is smaller than that of a conventional Schottky barrier diode using a p-type Si semiconductor with a resistivity of 5 Ωcm. There is almost no difference in the current when a forward voltage is applied. In this way, a characteristic with a high on / off ratio can be obtained compared to the conventional metal junction. In other words, a stacked structure with a diode junction that has excellent rectification and little leakage current can be obtained.

[0032] That is, compared to the conventional junction between a semiconductor layer and a metal electrode layer, it can be expressed as follows: When an SbTe-based thin film is used for the layered compound layer, the contact resistance can be reduced by using an n-type Si semiconductor for the semiconductor layer, and the on / off ratio of the current can be increased by using a p-type Si semiconductor for the semiconductor layer.

[0033] 5 again, the following is also clear in comparison with the conventional junction between a semiconductor layer and a metal electrode layer: When a BiTe-based thin film is used as the layered compound layer, the contact resistance can be reduced by using a p-type Si semiconductor for the semiconductor layer, and the on / off ratio of the current can be increased by using an n-type Si semiconductor for the semiconductor layer.

[0034] As described above, according to these embodiments, it is possible to change the height of the potential barrier caused by contact between the semiconductor layer and the metal electrode layer.

[0035] Next, a manufacturing example of a transistor as the semiconductor device 1 will be described.

[0036] 10 to 13 show a manufacturing process of a top-gate type field effect transistor (FET) as an example of a semiconductor device to which the above-mentioned stacked structure is applied.

[0037] As shown in Fig. 10(a), first, an insulating film 8 is formed on a semiconductor substrate 6 by atomic layer deposition (ALD). Further, as shown in Fig. 10(b), a gate electrode layer 9 is formed on the insulating film 8. Then, as shown in Fig. 10(c), a gate region is patterned by lithography, and the gate electrode layer 9 is dry etched to form a gate electrode.

[0038] 11(a), the insulating film 8 is etched, and as shown in FIG. 11(b), a layered compound layer 4 which is an amorphous film made of Sb and / or Bi and Te is deposited to a thickness of 10 nm or less by, for example, a sputtering method on the semiconductor substrate 6. Then, as shown in FIG. 11(c), the layered compound layer 4 other than the source / drain regions is removed by lithography and dry etching.

[0039] The material of the semiconductor substrate 6 is a Si semiconductor.

[0040] The insulating film 8 is formed of any material, and for example, an oxide film such as SiO2, Al2O3, HfO2, ZrO2, Y2O3, or La2O3 can be used.

[0041] The material of the gate electrode layer 9 is not particularly limited, and examples thereof include tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), and alloys or laminated films containing two or more of these.

[0042] Then, as shown in Fig. 12(a), the amorphous film of the layered compound layer 4 is crystallized by heat treatment at an appropriate temperature to form a layered compound with a crystalline phase. Thereafter, as shown in Fig. 12(b), an interlayer insulating film 10 is formed, and as shown in Fig. 12(c), a contact hole 10' is etched.

[0043] Furthermore, as shown in FIG. 13(a), a metal electrode layer 3 that will become a plug electrode is formed, and as shown in FIG. 13(b), a plug electrode is formed from the metal electrode layer 3 by lithography and dry etching. This makes it possible to obtain a FET as a semiconductor device in which a layered compound layer 4 is interposed between a semiconductor layer 2 (semiconductor substrate 6) made of a Si semiconductor and the metal electrode layer 3. This makes it possible to obtain a top-gate type field effect transistor with reduced contact resistance. The temperature of the heat treatment is preferably set within the range of, for example, 100° C. or higher.

[0044] By thus interposing the layered compound layer 4 between the semiconductor layer 2 made of a Si semiconductor and the metal electrode layer 3, the contact resistance between the semiconductor layer 2 and the metal electrode layer 3 can be reduced.

[0045] The above-described stacked structure can be applied to semiconductor devices such as any electronic device or optical device having a junction between a metal electrode layer and a semiconductor layer made of a Si semiconductor, in addition to transistors, such as Schottky diodes, light-emitting diodes, solar cells, and thermoelectric conversion elements.

[0046] Although the embodiments of the present invention and modifications based thereon have been described above, the present invention is not necessarily limited to these examples. In addition, a person skilled in the art will be able to find various alternative embodiments and modifications without departing from the spirit of the present invention or the scope of the appended claims. [Explanation of symbols]

[0047] 1 Semiconductor device 2. Semiconductor layer 3 Metal electrode layer (plug) 4 Layered Compound Layer 6. Semiconductor Substrates 8. Insulating film 9 Gate electrode layer 10 Interlayer insulating film

Claims

1. A semiconductor device including a laminated structure exhibiting rectification properties in which a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and / or a laminated structure exhibiting ohmic properties in which a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si, A semiconductor device, characterized in that a layered compound layer made of a layered compound of Sb and / or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer, and / or between the n-type semiconductor layer and the second metal electrode layer.

2. 2. The semiconductor device according to claim 1, wherein the layered compound layer includes an amorphous phase.

3. 3. The semiconductor device according to claim 1, wherein the layered compound layer has a thickness of 1 to 10 nm.

4. The layered compound is (Sb ｘ Bi １－ｘ ) ２ Te ３ 3. The semiconductor device according to claim 1, wherein x is an integer of 0 to 1, and x is an integer of 0 to 1.

5. 5. The semiconductor device according to claim 4, wherein the p-type Si contains Ge.

6. 5. The semiconductor device according to claim 4, wherein the n-type Si contains C.

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