Semiconductor device

Abstract

To reduce a cost of a semiconductor device containing a Seebeck element to improve a producibility.SOLUTION: By forming complementary field effect transistors (CMOSFET) Q1 and Q2 constructing an integrated circuit and a seebeck element Z1 to the same semiconductor substrate SUB, the seebeck element Z1 is manufactured in a CMOS process. A p-type semiconductor substrate SUB includes: a CMOSFET formation region R1; and a seebeck element formation region R2. The seebeck element Z1 includes: a p-type semiconductor region formed on the semiconductor substrate SUB; an n-type semiconductor substrate NSD that is formed on the semiconductor substrate SUB, and is arranged so as to be separated from the p-type semiconductor substrate region; and a heating part HP that is electrically connected to the p-type semiconductor region and the n-type semiconductor substrate NSD via a PLG1 and a PLG2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and for example, to a technique that is effective when applied to a semiconductor device including a Seebeck element. [Background technology]

[0002] Non-Patent Document 1 describes a technique relating to a thermoelectric conversion element. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Nesrine Jaziri et.al “A comprehensive review of Thermoelectric Generators: Technologies and common applications” Energy Reports 6 (2020) 264-287 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, Seebeck elements (thermoelectric conversion elements), which are typified by temperature power generation devices and temperature sensors, are elements that utilize the Seebeck effect, which is a phenomenon in which a potential difference occurs between both ends of a substance when a temperature difference is applied across the two ends.

[0005] In this regard, a temperature power generation device that uses the Seebeck effect is an element that extracts electricity from a supplied temperature difference. On the other hand, a temperature sensor that uses the Seebeck effect is an element that estimates the temperature difference by back-calculating from the potential difference. Such Seebeck elements often use semiconductor materials with a large Seebeck effect, and are in practical use as semiconductor elements.

[0006] Here, in semiconductor devices including Seebeck elements, there is a demand for improved manufacturing efficiency, as is required for general semiconductor devices in general. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes complementary field effect transistors formed on a semiconductor substrate, and a Seebeck element formed on the semiconductor substrate. Effect of the Invention

[0008] According to one embodiment, it is possible to improve the manufacturing efficiency of a semiconductor device including a Seebeck element. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a device structure of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a plan view showing a planar layout of a Seebeck element. [Diagram 3] 1 is a graph showing the relationship between the length of a p-type semiconductor region (n-type semiconductor region) and the open circuit voltage in a temperature power generating device. [Figure 4] 1 is a graph showing the relationship between the length of a p-type semiconductor region (n-type semiconductor region) and short-circuit current in a temperature power generating device. [Diagram 5] 1 is a graph showing the relationship between the length of a p-type semiconductor region (n-type semiconductor region) and maximum power in a temperature power generating device. [Figure 6] FIG. 2 is a schematic plan view showing the configuration of a temperature power generating element. [Figure 7] FIG. 7 is a cross-sectional view taken along line AA in FIG. 6. [Figure 8] FIG. 2 is a schematic plan view showing a configuration of a temperature sensor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0011] <Consideration of improvements> Currently, Seebeck elements are manufactured as components separate from semiconductor devices on which integrated circuits are formed. Specifically, currently, Seebeck elements are manufactured as components to be externally attached to semiconductor devices on which integrated circuits are formed. Furthermore, currently, Seebeck elements are sometimes manufactured as components of MEMS devices (Micro Electro Mechanical Systems).

[0012] For this reason, the current Seebeck element is manufactured separately from an integrated circuit and then combined with the integrated circuit, which tends to increase the manufacturing cost of a semiconductor device including a Seebeck element. In other words, there is room for improvement in the current semiconductor device including a Seebeck element from the viewpoint of reducing the manufacturing cost. Therefore, in this embodiment, a device is devised to overcome this room for improvement. The technical idea of ​​this embodiment in which the device is devised will be described below.

[0013] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to manufacture a Seebeck element by a CMOS process by forming a complementary field effect transistor (sometimes referred to as CMOSFET in this specification) constituting an integrated circuit and a Seebeck element on the same semiconductor substrate. In other words, the basic idea is to realize a device structure of a Seebeck element that can be mounted on a semiconductor substrate on which a CMOSFET is formed so that the Seebeck element can be manufactured by a CMOS process.

[0014] According to this basic concept, the CMOSFET and the Seebeck element can be manufactured by a CMOS process, which reduces manufacturing costs compared to the case where an integrated circuit and a Seebeck element are manufactured by separate manufacturing processes. In other words, according to this basic concept, it is possible to improve the manufacturing efficiency of a semiconductor device including a CMOSFET and a Seebeck element.

[0015] Furthermore, according to the basic concept, the Seebeck element can be manufactured by a CMOS process with high processing accuracy, and an integrated circuit including a CMOSFET and the Seebeck element can be formed on the same semiconductor chip. Therefore, according to the basic concept, a system including an integrated circuit and a Seebeck element can be miniaturized. In other words, the basic concept is a useful technical concept in that it not only reduces the manufacturing cost of a system including an integrated circuit and a Seebeck element, but also enables the system to be miniaturized.

[0016] The following describes an embodiment that embodies the basic concept.

[0017] <Embodiment> <<Device Structure of Semiconductor Device>> FIG. 1 is a cross-sectional view showing a device structure of a semiconductor device according to an embodiment.

[0018] 1, for example, a p-type semiconductor substrate SUB has a CMOSFET formation region R1 and a Seebeck element formation region R2. A p-channel MOSFET Q1 and an n-channel MOSFET Q2 constituting the CMOSFET are formed in the CMOSFET formation region R1. Meanwhile, a Seebeck element Z1 is formed in the Seebeck element formation region R2. That is, the semiconductor device in the embodied embodiment includes a CMOSFET formed in the semiconductor substrate SUB and a Seebeck element Z1 formed in the semiconductor substrate SUB. The Seebeck element Z1 is, for example, a temperature power generation device or a temperature sensor.

[0019] The semiconductor substrate SUB has a front surface and a back surface, and a CMOSFET and a Seebeck element Z1 are formed on the front surface. If the thickness direction of the semiconductor substrate SUB from the back surface to the front surface is defined as a first direction and a direction perpendicular to the first direction is defined as a second direction, the CMOSFET and the Seebeck element Z1 are arranged to be aligned in the second direction. In other words, the CMOSFET and the Seebeck element Z1 are arranged to be aligned in the left-right direction of FIG. 1.

[0020] First, the device structure of the CMOSFET will be explained. Specifically, since the CMOSFET is composed of a p-channel MOSFET Q1 and an n-channel MOSFET Q2, the device structures of the p-channel MOSFET Q1 and the n-channel MOSFET Q2 will be explained below with reference to FIG.

[0021] The p-channel MOSFET Q1 is formed in an n-type well NWL1 provided in a semiconductor substrate SUB. Specifically, the p-channel MOSFET Q1 has a gate insulating film GOX1 formed on the surface of the n-type well NWL1, and a gate electrode GE1 formed on the gate insulating film GOX1. Furthermore, the p-channel MOSFET Q1 has a source region SR1 and a drain region DR1 provided separately from each other inside the n-type well NWL1. Each of the source region SR1 and the drain region DR1 is made of a p-type semiconductor region, and a channel formation region is formed between the source region SR1 and the drain region DR1. The gate electrode GE1 is formed on this channel formation region via the above-mentioned gate insulating film GOX1. Moreover, the p-channel MOSFET Q1 has an n-type semiconductor region NR1 electrically connected to the n-type well NWL1 inside the n-type well NWL1. In the above-mentioned manner, the p-channel MOSFET Q1 is configured.

[0022] Next, the n-channel MOSFET Q2 has a gate insulating film GOX2 formed on the surface of the semiconductor substrate SUB, and a gate electrode GE2 formed on the gate insulating film GOX2. Furthermore, the n-channel MOSFET Q2 has a source region SR2 and a drain region DR2 provided separately from each other inside the semiconductor substrate SUB. Each of the source region SR2 and the drain region DR2 is composed of an n-type semiconductor region, and a channel formation region is formed between the source region SR2 and the drain region DR2. The gate electrode GE2 is formed on this channel formation region via the above-mentioned gate insulating film GOX2. Moreover, the n-channel MOSFET Q2 has a p-type semiconductor region PR1 electrically connected to the semiconductor substrate SUB inside the semiconductor substrate SUB. In the above-mentioned manner, the n-channel MOSFET Q2 is configured.

[0023] An interlayer insulating film IL is formed so as to cover the CMOSFET configured in this manner, and a plug PLG is formed in this interlayer insulating film IL. A wiring WL electrically connected to the plug PLG is formed on the interlayer insulating film IL. Thus, the CMOSFET is electrically connected by the wiring WL via the plug PLG. As a result, an integrated circuit made up of CMOSFETs electrically connected by the wiring WL is formed on the semiconductor substrate SUB.

[0024] Next, the device structure of the Seebeck element Z1 will be described.

[0025] As shown in FIG. 1, the Seebeck element Z1 has a p-type semiconductor region PSD formed in the semiconductor substrate SUB, an n-type semiconductor region NSD formed in the semiconductor substrate SUB and disposed apart from the p-type semiconductor region PSD, and a heating part HP connected to the p-type semiconductor region PSD and the n-type semiconductor region NSD. In detail, the Seebeck element Z1 further has an n-type well NWL2 that includes the p-type semiconductor region PSD in a plan view and is formed to a deeper position in the semiconductor substrate SUB than the p-type semiconductor region PSD. Here, the heating part HP is configured to be able to heat the semiconductor substrate SUB to a temperature higher than the temperature of the back surface thereof. And, as shown in FIG. 1, a wiring layer is provided above the semiconductor substrate SUB, and the heating part HP is provided in the wiring layer. That is, an interlayer insulating film IL is formed on the semiconductor substrate SUB, and the heating part HP is provided on the interlayer insulating film IL.

[0026] The heating part HP is electrically connected to one end of the p-type semiconductor region PSD through a plug PLG1 provided to penetrate the interlayer insulating film IL. Similarly, the heating part HP is electrically connected to one end of the n-type semiconductor region NSD through a plug PLG2 provided to penetrate the interlayer insulating film IL. Therefore, the heating part HP electrically connects the p-type semiconductor region PSD and the n-type semiconductor region NSD through the plug PLG1 and the plug PLG2. In addition, the other end of the p-type semiconductor region PSD is electrically connected to the wiring WL1 provided on the interlayer insulating film IL through a plug PLG3 provided to penetrate the interlayer insulating film IL. Similarly, the other end of the n-type semiconductor region NSD is electrically connected to the wiring WL2 provided on the interlayer insulating film IL through a plug PLG4 provided to penetrate the interlayer insulating film IL.

[0027] FIG. 2 is a plan view showing the planar layout of the Seebeck element Z1.

[0028] As shown in Fig. 2, an n-type well NWL2 is formed in the semiconductor substrate SUB, and a p-type semiconductor region PSD is formed so as to be contained in this n-type well NWL2. An n-type semiconductor region NSD is formed in the semiconductor substrate SUB so as to be spaced apart from the p-type semiconductor region PSD in the Y direction, and a heating part HP is disposed so as to straddle the p-type semiconductor region PSD and the n-type semiconductor region NSD. This heating part HP is electrically connected to one end of the p-type semiconductor region PSD and is also electrically connected to one end of the n-type semiconductor region NSD. The other end of the p-type semiconductor region PSD is electrically connected to the wiring WL1, while the other end of the n-type semiconductor region NSD is electrically connected to the wiring WL2.

[0029] The Seebeck element Z1 is constructed as described above.

[0030] <<Operation of Semiconductor Device>> Next, the operation of the semiconductor device will be described.

[0031] First, the operation of the Seebeck element Z1 when used as a temperature power generation device will be described. In FIG. 1, by supplying thermal energy to the heating part HP, the heating part HP is heated to a temperature higher than the temperature of the rear surface of the semiconductor substrate SUB. As a result, one end of the p-type semiconductor region PSD connected to the heating part HP via the plug PLG1 is heated. On the other hand, the wiring WL1 connected to the other end of the p-type semiconductor region PSD via the plug PLG3 is naturally cooled. Therefore, a temperature difference occurs between one end of the p-type semiconductor region PSD and the other end of the p-type semiconductor region PSD. As a result, a potential difference occurs between one end of the p-type semiconductor region PSD and the other end of the p-type semiconductor region PSD due to the Seebeck effect.

[0032] Similarly, one end of the n-type semiconductor region NSD connected to the heating unit HP via the plug PLG2 is heated. On the other hand, the wiring WL2 connected to the other end of the n-type semiconductor region NSD via the plug PLG4 is naturally cooled. Therefore, a temperature difference is also generated between one end of the n-type semiconductor region NSD and the other end of the n-type semiconductor region NSD. As a result, a potential difference is also generated between one end of the n-type semiconductor region NSD and the other end of the n-type semiconductor region NSD due to the Seebeck effect. As a result, a potential difference (electromotive force) is generated between the wiring WL1 and the wiring WL2. Then, an electromotive force based on the above-mentioned potential difference is supplied to an integrated circuit including a CMOSFET formed on the semiconductor substrate SUB through the wiring WL1 and the wiring WL2. This causes the integrated circuit to operate. In this way, when the Seebeck element Z1 is used as a temperature power generation device, the electromotive force generated by the Seebeck element Z1 is supplied to an integrated circuit including a CMOSFET mounted on the same semiconductor substrate SUB as the Seebeck element Z1, and the integrated circuit can be operated.

[0033] Next, the operation of the Seebeck element Z1 when used as a temperature sensor will be described. In Fig. 1, the heating part HP is placed close to the object whose temperature is to be measured. As a result, the temperature of the heating part HP becomes almost the same as the temperature of the object.

[0034] As a result, the temperature of one end of the p-type semiconductor region PSD connected to the heating part HP via the plug PLG1 becomes approximately the same as the temperature of the heating part HP. On the other hand, the wiring WL1 connected to the other end of the p-type semiconductor region PSD via the plug PLG3 is naturally cooled. Therefore, a temperature difference occurs between one end of the p-type semiconductor region PSD and the other end of the p-type semiconductor region PSD. As a result, a potential difference according to the temperature of the measurement object occurs between one end of the p-type semiconductor region PSD and the other end of the p-type semiconductor region PSD due to the Seebeck effect.

[0035] Similarly, the temperature of one end of the n-type semiconductor region NSD connected to the heating part HP via the plug PLG2 is approximately the same as the temperature of the heating part HP. On the other hand, the wiring WL2 connected to the other end of the n-type semiconductor region NSD via the plug PLG4 is naturally cooled. Therefore, a temperature difference occurs between one end of the n-type semiconductor region NSD and the other end of the n-type semiconductor region NSD. As a result, a potential difference according to the temperature of the measurement object occurs between one end of the n-type semiconductor region NSD and the other end of the n-type semiconductor region NSD due to the Seebeck effect.

[0036] Therefore, by detecting the potential difference between the wires WL1 and WL2, the temperature of the object to be measured corresponding to the potential difference can be estimated. Specifically, the potential difference between the wires WL1 and WL2 is output to a detection circuit formed of an integrated circuit including a CMOSFET mounted on the same semiconductor substrate SUB as the Seebeck element Z1. This makes it possible to estimate the temperature of the object to be measured from the input potential difference in the detection circuit, for example, based on data that associates the potential difference with temperature. In this way, the Seebeck element Z1 can also be used as a temperature sensor, and the temperature of the object to be measured can be estimated.

[0037] <<Method of manufacturing semiconductor device>> Next, a method for manufacturing a semiconductor device in the embodied embodiment will be described.

[0038] For example, the CMOSFET is manufactured by a CMOS process. Specifically, for example, in FIG. 1, an n-type well NWL1 is formed in a semiconductor substrate SUB by using an ion implantation method. Then, a gate insulating film GOX1 (GOX2) is formed on the semiconductor substrate SUB on which the n-type well NWL1 is formed by using, for example, a thermal oxidation method, and then a gate electrode GE1 (GE2) is formed on the gate insulating film GOX1 (GOX2) by using, for example, a patterning technique. Thereafter, a source region SR1 (p-type semiconductor region) and a drain region DR1 (p-type semiconductor region) that match the gate electrode GE1 are formed in the n-type well NWL1 by using, for example, an ion implantation method, while a source region SR2 (n-type semiconductor region) and a drain region DR2 (n-type semiconductor region) that match the gate electrode GE2 are formed in the semiconductor substrate SUB. In this manner, a p-channel MOSFET Q1 and an n-channel MOSFET Q2 that constitute a CMOSFET can be manufactured. Next, for example, an interlayer insulating film IL is formed so as to cover the CMOSFET, and then a contact hole is formed in the interlayer insulating film IL by using photolithography and etching techniques. Subsequently, a conductive film is embedded in the contact hole to form a plug PLG, and then a wiring WL is formed in the interlayer insulating film IL with the plug PLG formed therein by using, for example, a patterning technique. In this manner, a semiconductor device including a CMOSFET can be manufactured by using the CMOS process.

[0039] Here, in the semiconductor device in the embodiment shown in FIG. 1, the Seebeck element Z1 can be manufactured by using the above-mentioned CMOS process. Specifically, the n-type well NWL2 can be formed in the same process as the process of forming the n-type well NWL1. On the other hand, the p-type semiconductor region PSD of the Seebeck element Z1 can be formed in the same process as the process of forming the source region SR1 and the drain region DR1 of the p-channel MOSFET Q1. Also, the n-type semiconductor region NSD of the Seebeck element Z1 can be formed in the same process as the process of forming the source region SR2 and the drain region DR2 of the n-channel MOSFET Q2. Furthermore, the heating part HP can be formed by utilizing the process of forming the wiring WL. That is, the heating part HP can be formed by utilizing the wiring process of the CMOS process. In this way, according to the embodiment, the CMOSFET and the Seebeck element Z1 mounted on one semiconductor substrate SUB can be manufactured by the CMOS process.

[0040] <<Features of the Realization>> Next, features of the embodiment will be described.

[0041] A feature of the embodiment is that, for example, as shown in FIG. 1, a CMOSFET (a p-channel MOSFET Q1 and an n-channel MOSFET Q2) and a Seebeck element Z1 are provided on one semiconductor substrate SUB, and the device structure of the Seebeck element Z1 is configured so as to be manufacturable by a CMOS process.

[0042] According to a feature of this embodiment, the CMOSFET and the Seebeck element Z1 can be manufactured by a CMOS process, so that the manufacturing cost can be reduced compared to the case where the integrated circuit and the Seebeck element are manufactured by separate manufacturing processes.

[0043] Furthermore, according to the feature, the Seebeck element Z1 can be manufactured by a CMOS process with high processing accuracy, and an integrated circuit including a CMOSFET and the Seebeck element Z1 can be formed on a single semiconductor chip. Therefore, according to the feature, a system including an integrated circuit and the Seebeck element Z1 can be miniaturized. In other words, according to the feature, not only can the manufacturing cost of a system including an integrated circuit and the Seebeck element Z1 be reduced, but the system can also be miniaturized.

[0044] The Seebeck element Z1 in the embodiment is used as, for example, a temperature power generating device or a temperature sensor. Therefore, in the following, first, the temperature power generating device using the Seebeck element Z1 in the embodiment will be described in detail, and then the temperature sensor using the Seebeck element Z1 in the embodiment will be described in detail.

[0045] <<Details of the temperature harvesting device>> Fig. 3 is a graph showing the relationship between the length of the p-type semiconductor region PSD (n-type semiconductor region NSD) and the open-circuit voltage in the temperature power generation device. Eight graphs at different temperatures are shown in Fig. 3. Note that the graph showing the relationship between the length of the p-type semiconductor region PSD and the open-circuit voltage is the same as the graph showing the relationship between the length of the n-type semiconductor region NSD and the open-circuit voltage, so the following description will focus on the relationship between the p-type semiconductor region PSD and the open-circuit voltage.

[0046] In FIG. 3, it can be seen that the longer the length of the p-type semiconductor region PSD, the larger the open-circuit voltage becomes, and when the length of the p-type semiconductor region PSD is about 1000 μm, the value of the open-circuit voltage becomes saturated. This can be qualitatively understood for the following reasons. That is, the longer the length of the p-type semiconductor region PSD, the longer the distance between one end of the p-type semiconductor region PSD connected to the heating part HP in FIG. 1 and the other end located on the opposite side of the one end and naturally cooled becomes longer, which means that the temperature difference between the one end and the other end becomes larger. That is, the longer the distance between the one end and the other end, the larger the temperature difference between the one end and the other end becomes, and this causes the potential difference (open-circuit voltage) generated between the one end and the other end to become larger. Then, when the distance between the one end and the other end becomes a certain value or more, the temperature difference between the one end and the other end becomes saturated, and as a result, the open-circuit voltage becomes saturated. In this way, the tendency of the graph shown in FIG. 3 can be explained.

[0047] Next, Fig. 4 is a graph showing the relationship between the length of the p-type semiconductor region PSD (n-type semiconductor region NSD) in the temperature power generation device and the short-circuit current. Eight graphs at different temperatures are shown in Fig. 4. Note that the graph showing the relationship between the length of the p-type semiconductor region PSD and the short-circuit current is equivalent to the graph showing the relationship between the length of the n-type semiconductor region NSD and the short-circuit current, so the following description will focus on the relationship between the p-type semiconductor region PSD and the short-circuit current.

[0048] It can be seen from Fig. 4 that the longer the length of the p-type semiconductor region PSD, the smaller the short-circuit current tends to be. This can be qualitatively understood for the following reasons. That is, the longer the length of the p-type semiconductor region PSD, the greater the resistance value of the p-type semiconductor region PSD, and the tendency of the graph shown in Fig. 4 can be understood from the mechanism in which the short-circuit current decreases due to the increase in resistance value.

[0049] From the above, based on the graphs shown in Fig. 3 and Fig. 4, as the length of the p-type semiconductor region PSD increases, the open-circuit voltage increases while the short-circuit current decreases. In other words, the open-circuit voltage and the short-circuit current are in a trade-off relationship with each other with respect to the length of the p-type semiconductor region PSD. In this regard, a temperature power generation device is a device that converts a temperature difference into power by the Seebeck effect and extracts it, and power is expressed as the product of the potential difference (open-circuit voltage) and the current (short-circuit current). Therefore, since power is determined by the open-circuit voltage and the short-circuit current, which are in a trade-off relationship with each other, it is expected that the graph of maximum power with respect to the length of the p-type semiconductor region PSD will not be a graph that monotonically increases or decreases, but will be a graph that takes a maximum value.

[0050] FIG. 5 is a graph showing the relationship between the length of the p-type semiconductor region PSD (n-type semiconductor region NSD) and the maximum power in a temperature power generating device. As shown in FIG. 5, when the length of the p-type semiconductor region PSD starts to increase, the maximum power increases, but as the length of the p-type semiconductor region PSD increases further, the maximum power decreases. That is, as expected above, the graph of the maximum power versus the length of the p-type semiconductor region PSD is a graph that takes a maximum value. And, based on FIG. 5, it is understood that in a temperature power generating device, from the viewpoint of increasing the maximum power that can be extracted, the length of the p-type semiconductor region PSD is desirably 10 μm or more and 30 μm or less.

[0051] Furthermore, as shown in Fig. 5, it can be seen that the range of the maximum value hardly changes even when the temperature changes. In other words, when the Seebeck element Z1 in the embodied embodiment is used as a temperature power generation device, it has an excellent characteristic that the length of the p-type semiconductor region PSD at which the maximum power becomes the maximum value is not easily dependent on the temperature. Therefore, according to the embodied embodiment, once the length of the p-type semiconductor region PSD is designed to be 10 µm or more and 30 µm or less, it is very excellent in that a temperature power generation device with a wide operating temperature range and high efficiency can be provided.

[0052] The above can be summarized as follows. That is, in Fig. 1, the Seebeck element Z1 is a temperature power generation device, and the semiconductor substrate SUB has a front surface and a back surface. In this case, if the thickness direction of the semiconductor substrate SUB from the back surface to the front surface is defined as a first direction (the up-down direction in Fig. 1) and the direction perpendicular to the first direction is defined as a second direction (the left-right direction in Fig. 1), the width of the p-type semiconductor region PSD in the second direction is 10 µm or more and 30 µm or less, and the width of the n-type semiconductor region NSD in the second direction is 10 µm or more and 30 µm or less.

[0053] <<<The need for series connection of temperature power generation devices>>> For example, as shown in FIG. 3, the voltage output from the temperature power generating device is about several mV. In contrast, the operating voltage for operating an integrated circuit including a CMOSFET is about several V. Therefore, in a semiconductor device including a temperature power generating device and a CMOSFET mounted on one semiconductor substrate, it is difficult to operate the CMOSFET using the voltage generated by the temperature power generating device. Therefore, it is possible to increase the output voltage by connecting multiple temperature power generating devices in series. That is, in order to operate the CMOSFET with the output voltage from the temperature power generating device, it is necessary to increase the output voltage by connecting multiple temperature power generating devices in series. In this case, it is necessary to mount multiple temperature power generating devices connected in series together with the CMOSFET on one semiconductor substrate. In this regard, in the embodiment, ingenuity is given to the device structure of the temperature power generating device in order to mount multiple temperature power generating devices connected in series together with the CMOSFET on one semiconductor substrate. The ingenuity is described below.

[0054] <<<Techniques for achieving series connection>>> The first ingenuity is that, for example, as shown in Fig. 1, the p-type semiconductor region PSD and the n-type semiconductor region NSD are arranged laterally. In other words, in the embodiment, the p-type semiconductor region PSD and the n-type semiconductor region NSD are arranged in the left-right direction (horizontal direction) of Fig. 1. As a result, according to the embodiment, it is possible to arrange a plurality of p-type semiconductor regions PSD and n-type semiconductor regions NSD in the horizontal direction, and as a result, it becomes easy to mount a plurality of temperature power generation devices together with CMOSFETs. In other words, the configuration in which the p-type semiconductor region PSD and the n-type semiconductor region NSD are arranged laterally has the technical significance of easily realizing a configuration in which a plurality of temperature power generation devices are mounted together with CMOSFETs on one semiconductor substrate SUB.

[0055] The second ingenuity is, for example, as shown in Fig. 1, that an n-type well NWL2 is provided in the semiconductor substrate SUB, and a p-type semiconductor region PSD is provided so as to be contained in this n-type well NWL2. As a result, for example, when a plurality of temperature power generating devices are arranged on one semiconductor substrate SUB, the respective p-type semiconductor regions PSD are electrically isolated from the semiconductor substrate SUB by the n-type well NWL2 provided in each of the plurality of temperature power generating devices. As a result, a plurality of temperature power generating devices can be connected in series.

[0056] That is, since the semiconductor substrate SUB is p-type, if the n-type well NWL2 is not provided, the semiconductor substrate SUB and the p-type semiconductor region PSD are electrically connected. In other words, if the n-type well NWL2 is not provided, the p-type semiconductor region PSD of each of the plurality of temperature power generating devices is electrically connected to the semiconductor substrate SUB, and as a result, the plurality of temperature power generating devices cannot be connected in series. In contrast, by providing the n-type well NWL2 in each of the plurality of temperature power generating devices and providing the p-type semiconductor region PSD inside this n-type well NWL2, the p-type semiconductor region PSD of each of the plurality of temperature power generating devices is electrically isolated from the semiconductor substrate SUB. As a result, it becomes possible to connect the plurality of temperature power generating devices in series, and thus the output voltages of the plurality of temperature power generating devices can be added and output. In this way, the n-type well NWL2 containing the p-type semiconductor region PSD has the technical significance of cutting off the electrical connection between the p-type semiconductor region PSD and the semiconductor substrate SUB, and enabling the plurality of temperature power generating devices to be connected in series.

[0057] <<<Series connection example>>> An example configuration in which a plurality of temperature power generation devices are connected in series will be described below.

[0058] In this specification, a structure made up of a plurality of temperature power generating devices connected in series will be referred to as a temperature power generating body 100.

[0059] FIG. 6 is a schematic plan view showing the configuration of the temperature power generating device 100. As shown in FIG.

[0060] As shown in FIG. 6, the temperature power generating device 100 includes a pad PD provided at the center in a planar view, and a plurality of cells CL arranged to surround the pad PD in a planar view, and the plurality of cells CL are connected in series.

[0061] At this time, each of the multiple cells CL has a p-type semiconductor region PSD formed on the semiconductor substrate SUB, an n-type semiconductor region NSD formed on the semiconductor substrate SUB and arranged apart from the p-type semiconductor region PSD, and a heating part HP connected to the p-type semiconductor region PSD and the n-type semiconductor region NSD. The heating part HP provided in each of the multiple cells CL is connected to a pad PD. Here, heat is supplied to this pad PD, and the heat supplied to the pad PD is transferred to each heating part HP of the multiple cells CL arranged around the pad PD. Therefore, the pad PD functions as a heating part HP that supplies heat to each of the multiple cells CL.

[0062] Next, FIG. 7 is a cross-sectional view taken along line AA in FIG.

[0063] 7, the temperature power generating device 100 has a multilayer wiring layer ML provided above a semiconductor substrate SUB, and the multilayer wiring layer ML is provided with a plurality of wires and a plurality of plugs. Each of the plurality of cells CL is connected to a pad PD by the plurality of wires and a plurality of plugs provided in the multilayer wiring layer ML.

[0064] The temperature power generating body 100 configured in this manner has a plurality of cells CL connected in series, so that it is possible to increase the output voltage from the temperature power generating body 100. As a result, for example, an integrated circuit including a CMOSFET provided on the same semiconductor substrate SUB as the temperature power generating body 100 can be operated with the output voltage output from the temperature power generating body 100.

[0065] Furthermore, since the temperature power generator 100 uses a multilayer wiring layer ML (using a wiring process) and a plurality of cells (using a substrate process) manufactured by a CMOS process, the temperature power generator 100 can be configured from a plurality of cells CL arranged at high density by the integration technology of the CMOS process. Therefore, it is possible to reduce the manufacturing cost of a system including an integrated circuit and the temperature power generator 100, and to miniaturize the system.

[0066] <<Temperature sensor details>> The Seebeck element Z1 in the embodiment can be used not only as a temperature power generation device but also as a temperature sensor. Specifically, the temperature of the object to be measured can be estimated by back-calculating the temperature difference based on the Seebeck effect from the potential difference (open circuit voltage) output from the Seebeck element Z1.

[0067] FIG. 3 is a graph showing the relationship between the length of the p-type semiconductor region PSD (n-type semiconductor region NSD) and the open-circuit voltage in the temperature power generation device as well as in the temperature sensor.

[0068] Eight graphs at different temperatures are shown in Fig. 3. Note that the graph showing the relationship between the length of the p-type semiconductor region PSD and the open-circuit voltage is equivalent to the graph showing the relationship between the length of the n-type semiconductor region NSD and the open-circuit voltage, so the following description will be focused on the relationship between the p-type semiconductor region PSD and the open-circuit voltage.

[0069] 3, it can be seen that the longer the length of the p-type semiconductor region PSD, the larger the open-circuit voltage becomes, and the value of the open-circuit voltage saturates when the length of the p-type semiconductor region PSD is about 1000 μm. Therefore, while the performance of the temperature sensor is better as the open-circuit voltage becomes larger, considering that the value of the open-circuit voltage saturates when the length of the p-type semiconductor region PSD is about 1000 μm, it is desirable to set the length of the p-type semiconductor region PSD appropriately, and specifically, it is desirable for the length of the p-type semiconductor region PSD to be 100 μm or more and 1 mm or less.

[0070] The above can be summarized as follows. That is, in Fig. 1, the Seebeck element Z1 is a temperature sensor, and the semiconductor substrate SUB has a front surface and a back surface. In this case, if the thickness direction of the semiconductor substrate SUB from the back surface to the front surface is defined as a first direction (the vertical direction in Fig. 1) and the direction perpendicular to the first direction is defined as a second direction (the horizontal direction in Fig. 1), the width of the p-type semiconductor region PSD in the second direction is 100 µm or more and 1 mm or less, and the width of the n-type semiconductor region NSD in the second direction is 100 µm or more and 1 mm or less.

[0071] Next, a configuration example of the temperature sensor will be described.

[0072] FIG. 8 is a schematic plan view showing the configuration of the temperature sensor 200. As shown in FIG.

[0073] 8, the temperature sensor 200 is composed of a single cell. At this time, the cell has a p-type semiconductor region PSD formed in the semiconductor substrate SUB, an n-type semiconductor region NSD formed in the semiconductor substrate SUB and disposed apart from the p-type semiconductor region PSD, and a heating part HP connected to the p-type semiconductor region PSD and the n-type semiconductor region NSD.

[0074] The p-type semiconductor region PSD and the n-type semiconductor region NSD are disposed adjacent to each other in the up-down direction (Y direction) in a plan view, while the heating part HP is disposed adjacent to each of the p-type semiconductor region PSD and the n-type semiconductor region NSD in the left-right direction (X direction) in a plan view. In addition, in a plan view, the p-type semiconductor region PSD is configured in a spiral shape. Similarly, in a plan view, the n-type semiconductor region NSD is also configured in a spiral shape. This allows the length of the p-type semiconductor region PSD and the length of the n-type semiconductor region NSD to be increased without increasing the planar size of the temperature sensor 200. As a result, the output voltage (open voltage) of the temperature sensor 200 can be increased, thereby improving the temperature measurement accuracy by the temperature sensor 200.

[0075] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0076] 100 Temperature generator 200 Temperature Sensor CL Cell DR1 Drain region DR2 Drain region GE1 Gate electrode GE2 Gate electrode GOX1 Gate insulating film GOX2 Gate insulating film HP heating section IL Interlayer insulating film ML multilayer wiring layer NR1 n-type semiconductor region NSD n-type semiconductor region NWL1 n-type well NWL2 n-type well PD Pad PLG Plug PLG1 Plug PLG2 plug PLG3 Plug PLG4 plug PR1 p-type semiconductor region PSD p-type semiconductor region Q1 p-channel MOSFET Q2 n-channel MOSFET R1 CMOSFET formation area R2 Seebeck element formation region SR1 source region SR2 Source Region SUB Semiconductor Substrate WL wiring WL1 Wiring WL2 Wiring Z1 Seebeck element

Claims

1. a complementary field effect transistor formed on a semiconductor substrate; A Seebeck element formed on the semiconductor substrate; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The Seebeck element is a temperature power generating device or a temperature sensor.

3. 2. The semiconductor device according to claim 1, the semiconductor substrate has a front surface and a back surface; a thickness direction of the semiconductor substrate from the back surface to the front surface is defined as a first direction; When a direction perpendicular to the first direction is a second direction, The complementary field effect transistors and the Seebeck element are arranged to be aligned in the second direction.

4. 2. The semiconductor device according to claim 1, the semiconductor substrate is made of a substrate of a first conductivity type; The Seebeck element is a first semiconductor region of the first conductivity type formed in the semiconductor substrate; a second semiconductor region formed in the semiconductor substrate, the second semiconductor region having a second conductivity type opposite to the first conductivity type and spaced apart from the first semiconductor region; a heating section connected to the first semiconductor region and the second semiconductor region; has.

5. 5. The semiconductor device according to claim 4, The heating section is configured to be capable of heating the semiconductor substrate to a temperature higher than the temperature of the rear surface of the semiconductor substrate.

6. 5. The semiconductor device according to claim 4, The semiconductor device further includes a well region of the second conductivity type, the well region including the first semiconductor region in a plan view, formed to a deeper position in the semiconductor substrate than the first semiconductor region.

7. 5. The semiconductor device according to claim 4, The semiconductor device has a wiring layer provided above the semiconductor substrate, The heating portion is provided in the wiring layer.

8. 8. The semiconductor device according to claim 7, The semiconductor device includes: a first plug connecting the first semiconductor region and the heating unit; a second plug connecting the second semiconductor region and the heating unit; has.

9. 2. The semiconductor device according to claim 1, the semiconductor substrate is made of a substrate of a first conductivity type; The Seebeck element is composed of a plurality of cells connected in series, Each of the plurality of cells is a first semiconductor region of the first conductivity type formed in the semiconductor substrate; a second semiconductor region formed in the semiconductor substrate, the second semiconductor region having a second conductivity type opposite to the first conductivity type and spaced apart from the first semiconductor region; a heating section connected to the first semiconductor region and the second semiconductor region; has.

10. 10. The semiconductor device according to claim 9, The semiconductor device has a multilayer wiring layer provided above the semiconductor substrate, The multi-layer wiring layer includes a plurality of wirings and a plurality of plugs, Each of the plurality of cells is connected to a pad by the plurality of wires and the plurality of plugs provided in the multi-layer wiring layer.

11. 10. The semiconductor device according to claim 9, The Seebeck element is a temperature power generating device, The semiconductor device includes: A pad provided at a center portion in a plan view; The plurality of cells are provided so as to surround the periphery of the pad in a plan view; Includes.

12. 2. The semiconductor device according to claim 1, the semiconductor substrate is made of a substrate of a first conductivity type; The Seebeck element is composed of a single cell, The cell comprises: a first semiconductor region of the first conductivity type formed in the semiconductor substrate; a second semiconductor region formed in the semiconductor substrate, the second semiconductor region having a second conductivity type opposite to the first conductivity type and spaced apart from the first semiconductor region; a heating section connected to the first semiconductor region and the second semiconductor region; has.

13. 13. The semiconductor device according to claim 12, The Seebeck element is a temperature sensor, the first semiconductor region and the second semiconductor region are disposed at adjacent positions in a third direction in a plan view, the heating portion is disposed at a position adjacent to each of the first semiconductor region and the second semiconductor region in a fourth direction in a plan view, the third direction and the fourth direction are perpendicular to each other, In a plan view, the first semiconductor region is configured in a spiral shape, In a plan view, the second semiconductor region has a spiral shape.

14. 5. The semiconductor device according to claim 4, The Seebeck element is a temperature power generating device, the semiconductor substrate has a front surface and a back surface; a thickness direction of the semiconductor substrate from the back surface to the front surface is defined as a first direction; When a direction perpendicular to the first direction is a second direction, The width of the first semiconductor region in the second direction is not less than 10 μm and not more than 30 μm, The width of the second semiconductor region in the second direction is not less than 10 μm and not more than 30 μm.

15. 5. The semiconductor device according to claim 4, The Seebeck element is a temperature sensor, the semiconductor substrate has a front surface and a back surface; a thickness direction of the semiconductor substrate from the back surface to the front surface is defined as a first direction; When a direction perpendicular to the first direction is a second direction, The width of the first semiconductor region in the second direction is not less than 100 μm and not more than 1 mm, The width of the second semiconductor region in the second direction is not less than 100 μm and not more than 1 mm.

Images