Semiconductor device

Abstract

To provide a circuit with reduced leak current.SOLUTION: A first transistor, a third transistor, and a second transistor are serially and electrically connected in this order. A drain of the second transistor and a source of the third transistor are electrically connected to each other, and also electrically connected to an output node. The first transistor is a p-type transistor. The second and third transistors are n-type transistors. A semiconductor region is formed of an oxide semiconductor. The third transistor functions as a switch controlling electric connection between a drain of the first transistor and an output node of the circuit. In a standby state, the third transistor is in a non-conductive state.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a driving method thereof.

[0002] The invention disclosed in the specification, drawings, and claims of this application (hereinafter referred to as the specification, etc.) The present invention is not limited to the above technical fields. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or assembly. The technical field of one aspect of the present invention is semiconductor Devices such as display devices, light-emitting devices, lighting devices, power storage devices, and storage devices, and driving devices for the devices Examples include a method for operating the device and a method for fabricating the device. [Background technology]

[0003] As transistors in semiconductor devices become smaller, static power consumption increases due to leakage current. As a technology for reducing power consumption in semiconductor devices, there is a problem of clocking circuits that are not required for operation. Clock gating technology stops the input of signals, and power gating cuts off the power supply. Clock gating is known to reduce dynamic power consumption, but static power consumption is also reduced. However, it is not possible to sufficiently reduce the overall power consumption.

[0004] A clock tree is used to provide a single clock signal to multiple circuits. For example, The clock tree is generated by controlling the supply of power potential to the logic gate circuits that make up the clock tree. It has been proposed to reduce the leakage current of the circuit tree (see, for example, Patent Documents 1 to 3). ).

[0005] A transistor in which a semiconductor region is formed using an oxide semiconductor (hereinafter referred to as an “OS transistor”) Various semiconductor devices to which the power supply is applied have been proposed. By using OS transistors as the transistors that are turned off, the standby power consumption of logic circuits can be reduced. It is said that it is possible to reduce the amount of heat generated by the heat treatment (for example, see Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-287552 A [Patent Document 2] JP 2008-053976 A [Patent Document 3] JP 2011-114817 A [Patent Document 4] JP 2011-120222 A Summary of the Invention [Problem to be solved by the invention]

[0007] One embodiment of the present invention is to provide a novel semiconductor device, a driving method thereof, or a manufacturing method thereof. For example, an object of one embodiment of the present invention is to reduce power consumption. To provide a semiconductor device capable of suppressing area overhead. The present invention provides a conductor device.

[0008] Problems other than those listed above will become apparent from the description of this specification, etc. In addition, for each embodiment of the present invention, it is possible to extract other problems. The description of the subject matter does not preclude the existence of each other's problems, and one aspect of the present invention is It is not necessary to solve all of the problems. [Means for solving the problem]

[0009] One aspect of the present invention is a transistor including an output node, first and second nodes, and first to third transistors. and a second signal output from an output node of the first signal processing circuit. A first power supply potential is input to the first node, and a second power supply potential is input to the second node. In the first transistor, the second power supply potential is input, the first power supply potential is higher than the second power supply potential, and the first transistor the first transistor is a p-type transistor, the second and third transistors are n-type transistors, The semiconductor regions of the second and third transistors have oxide semiconductor layers. The third transistor and the second transistor are electrically connected in series in this order, and the first transistor The source of the second transistor is electrically connected to the first node, and the drain of the second transistor is connected to the output node. the source of the second transistor is electrically connected to the second node, and the source of the first transistor is electrically connected to the second node; and the potential of the gate of the second transistor is controlled by one or more first signals; A third signal is input to the gate of the transistor.

[0010] In the above embodiment, a p-type transistor may be provided in place of the third transistor. The circuit may also be a circuit that performs logical operations such as negation, NAND, and NOR. Cut.

[0011] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. In some cases, the word "number" is added to indicate the order of the items. It is not something that can be done.

[0012] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics and is a semiconductor element ( A semiconductor is a circuit that contains a semiconductor element (such as a transistor or diode) or a device that has such a circuit. This refers to any device that can function by utilizing the characteristics of the device. For example, an integrated circuit, The chip is an example of a semiconductor device. In some cases, electronic devices and the like are themselves semiconductor devices or include semiconductor devices.

[0013] A transistor has three nodes (terminals) called the gate, source, and drain. The gate is a node that functions as a control node to control the conductive state of the transistor. The pair of input / output nodes that function as the source or drain are determined by the type and Depending on the level of the potential applied to each node (terminal), one becomes the source and the other becomes the drain. Generally, in an n-type transistor, the node to which a low potential is applied is called the source. The node to which the higher potential is applied is called the drain. The node to which a low potential is applied is called the drain, and the node to which a high potential is applied is called the source. It is called s.

[0014] In this specification, in order to facilitate understanding of the circuit configuration and its operation, the two input and output terminals of a transistor are In some cases, the explanation will be limited to one of the power nodes being the source and the other being the drain. Depending on the driving method, the magnitude relationship of the potentials applied to the three terminals of the transistor changes, The source and drain may be interchanged. The distinction between the source and drain of a transistor is not limited to the description in the specification and drawings. do not have.

[0015] In addition, in this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes cases where Y is directly connected to Y. For example, the connection relationships are not limited to those described in this specification, etc. Here, X and Y are objects (e.g., devices, elements, circuits, etc.). , wiring, electrodes, terminals, conductive films, layers, etc.).

[0016] An example of a connection relationship in which X and Y are electrically connected is Possible elements (e.g., switches, transistors, capacitive elements, inductors, resistive elements, One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be turned on and off. A switch can be in a conducting (on) or non-conducting (off) state, allowing current to flow. The switch has the function of controlling whether or not current flows. It has the function of selecting and switching between them.

[0017] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0018] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) (i.e., there is a separate circuit between X and Y) and (i.e., X and Y are functionally connected). When X and Y are connected functionally through a gap, they are connected in a straight line. (When X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it does not simply mean that it is connected. "" is the same as if it were expressly stated that

[0019] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0020] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the object (e.g., the device , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0021] In this specification, the term "active element" refers to an active element (e.g., a transistor, a diode, etc.), a passive element ( For example, all terminals of the capacitor, resistor, etc., are identified as their connections. Even if the above is not specified, a person skilled in the art may be able to configure one aspect of the invention. Therefore, even if the connection destination is not specified, one aspect of the invention is clear. When the content of the specified connection is described in this specification, etc., it is considered that one aspect of the invention does not specify the connection destination. In particular, it may be possible to determine that the terminal is connected to the If multiple cases are possible, there is no need to limit the connection of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitors, resistors, etc.) By specifying the connection destination of only some of the terminals of the , which may constitute an aspect of the invention.

[0022] In this specification, if a certain circuit is specified at least as a connection destination, a person skilled in the art can understand the circuit. For example, it may be possible to identify an invention by a circuit. In some cases, a person skilled in the art can identify the invention by specifying the function. If the function of the invention is specified, the mode of the invention is clear. It may be possible to determine that one aspect is described in the present specification. Even if the function of a circuit is not specified, specifying the connection destination discloses one embodiment of the invention. The present invention can be implemented as one embodiment of the present invention. In this case, one aspect of the invention is disclosed by specifying the function without specifying the connection destination. This can constitute one aspect of the invention. Effect of the Invention

[0023] One embodiment of the present invention is to provide a novel semiconductor device, a driving method thereof, or a manufacturing method thereof. For example, according to one embodiment of the present invention, the power consumption of a semiconductor device can be reduced. It becomes possible to reduce the area overhead.

[0024] The description of these effects does not preclude the existence of other effects. However, it is not necessary to have all of these effects. For example, depending on the case or situation, the present invention An embodiment of the present invention may have effects other than those mentioned above, or may not have these effects. In one embodiment of the present invention, there are other problems, advantages, and novel configurations. This will become apparent from the description of this specification and the like. [Brief description of the drawings]

[0025] [Figure 1] 1A and 1B are block diagrams showing an example of the configuration of a semiconductor device. [Diagram 2] 1A and 1B are block diagrams showing an example of the configuration of a semiconductor device. [Diagram 3] AE: Circuit diagram showing an example of a circuit configuration. [Figure 4] AD: Circuit diagram showing an example of a circuit configuration. [Diagram 5] AD: Circuit diagram showing an example of a circuit configuration. [Figure 6] A and B are circuit diagrams showing an example of the circuit configuration. [Figure 7] 1A and 1B are circuit diagrams showing an example of the configuration of a semiconductor device. [Figure 8] 1A and 1B are circuit diagrams showing an example of the configuration of a semiconductor device. [Figure 9] 1A and 1B are circuit diagrams showing an example of the configuration of a semiconductor device. [Figure 10] A is a diagram showing an example of the configuration of a semiconductor device having a clock tree, and B is a circuit symbol of an inverter circuit. [Figure 11] A and B are circuit diagrams showing an example of a clock tree configuration. [Figure 12] 1A to 1D are diagrams illustrating an example of the structure of an OS transistor, in which A is a top view, B is a cross-sectional view along the line y1-y2, C is a cross-sectional view along the line x1-x2, and D is a cross-sectional view along the line x3-x4. [Figure 13] 1A to 1D are diagrams illustrating an example of the structure of an OS transistor, in which A is a top view, B is a cross-sectional view along the line y1-y2, C is a cross-sectional view along the line x1-x2, and D is a cross-sectional view along the line x3-x4. [Figure 14] A: Enlarged view of a portion of FIG. 13B. B: Energy band diagram of an OS transistor. [Figure 15] FIG. 1 is a plan view showing an example of a layout of a semiconductor device. [Figure 16] Cross-sectional view taken along line d1-d2 in Figure 15. [Figure 17] FIG. 2 is a block diagram showing an example of a processing unit (CPU). [Figure 18] 1A is a flowchart showing an example of a method for manufacturing an electronic component, and B is a schematic perspective view showing an example of a configuration of an electronic component. [Figure 19] AH: A diagram illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the present invention is not limited to the following description without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes can be made in form and details. Therefore, one embodiment of the present invention should not be construed as being limited to the description of the following embodiment. There is none.

[0027] Several embodiments are described below. The configuration described in one embodiment may be used in other embodiments. It is possible to combine the above with the configurations described in the embodiments as appropriate. When several configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0028] In addition, in the drawings used to explain the embodiments of the invention, the same parts or similar functions are The same reference numerals are used to denote the same parts, and the repeated explanations may be omitted. In the specification, for example, the clock signal CLK is abbreviated to simply the signal CLK, CLK, etc. This may include other components (e.g., signals, voltages, potentials, circuits, elements, The same applies to the electrodes, wiring, etc.

[0029] In this specification, a high level potential of a signal is indicated as "H", and a low level potential is indicated as "H". This is sometimes written as "L".

[0030] (Embodiment 1) <<Example of semiconductor device configuration>> A semiconductor device capable of power gating will be described. Figures 1 and 2 show the structure of the semiconductor device. 1 and 2 are diagrams for explaining an example of a semiconductor device. By providing a switch that can cut off the supply of potential VDD, leakage current in standby state is reduced. In this specification, the supply of power supply potential to a circuit is controlled. A switch that has the function of this is called a "power switch."

[0031] <Configuration example 1> A high power supply potential VDD and a low power supply potential VSS are supplied to the circuit 21 shown in FIG. Circuit 21 is a CMOS circuit that includes both n-type and p-type transistors. At least two n-type transistors (transistor Qn1 and transistor Qn2), and The transistor Qn2 is a It can function as a power switch that controls the power gating of the circuit 21.

[0032] In other words, the circuit 21 is a functional circuit equipped with a power switch. For example, a logic gate circuit capable of performing the above calculations can be applied to the circuit 21. The logic gate circuits used are inverter circuits (NOT gate circuits), NAND gate circuits, etc. , NOR gate circuits, AND gate circuits, OR gate circuits, and buffer circuits. do.

[0033] In the example of FIG. 1A, the circuit 21 can function as a one-input, one-output logic circuit. , a signal A1 input from an input node a1 is processed, and a signal B1 is output from an output node b1. The number of input nodes of the circuit 21 may be more than one. The circuit 21 has nodes p1, Node p1 has VDD input, and node p2 has VSS input. do.

[0034] The transistors Qp1 and Qn1 are transistors that constitute the logic circuit section of the circuit 21. The drains of the transistors Qp1 and Qn1 are electrically connected to each other. The drains of the transistors are electrically connected to the output node b1. The source of the transistor Qn1 is electrically connected to the node p2. The electrical connection between node p2 and node p3 may be direct or via another element such as a transistor. The potential of the gates of the transistors Qp1 and Qn1 may be indirectly connected. is determined by signal A1, and the voltages of the gates of transistors Qp1 and Qn1 are The logic level of node b1 is determined according to the position.

[0035] Transistor Qn2 is designed to cut off the supply of VDD to the source of transistor Qp1. The transistor Qn2 supplies VDD to the source of the transistor Qp1. The drain of the transistor Qn2 can function as a power switch that controls the is electrically connected to node p1. The source of transistor Qn2 is The source of transistor Qn1 is electrically connected to the source of transistor Qp1. The electrical connection between the sources of p1 may be direct or through other elements such as transistors. The signal SLP is a control signal for controlling the conductive state of the transistor Qn2. It's a signal.

[0036] The transistor Qn2 electrically connects the wiring for supplying VDD to the circuit 21. It can also function as a power switch that controls

[0037] When the circuit 21 is in normal operation, the signal SLP is set to a high level potential ("H") to activate the transistor. The transistor Qn2 is turned on. A logical operation is performed in the circuit 21. The circuit 21 is turned on. To switch the transistor Qn2 to the low-level potential ("L"), the signal SLP is set to low level potential ("L") to turn the transistor Qn2 off. The gate of the transistor Qp1 is at “H” and the transistor Qp1 is in a non-conducting state. When the transistor Qp1 is in the on state and goes into the standby state, a high-level potential is applied to the source of the transistor Qp1. Since the supply of is cut off, the leakage current between the source and drain of transistor Qp1 is It can be eliminated or reduced.

[0038] When the gate of the transistor Qn1 is at "L" and the circuit 21 is in the standby state, In order to eliminate or reduce the leakage current between the source and drain of transistor Qn1, A transistor with extremely small off-state current is used for the Qn1. This refers to the drain current in the on-state.

[0039] To reduce the off-state current of a transistor, for example, the semiconductor region is It can be made of a semiconductor. In this case, the energy gap of the semiconductor must be 2.5 eV or more. Alternatively, it is preferable that the potential is 2.7 eV or more, or 3 eV or more. For example, the off-state current of an OS transistor normalized by the channel width is The current is 10×10 at room temperature (approximately 25°C) with a source-drain voltage of 10V. -2 1 It is possible to achieve a value of 10 zeptoA / μm or less.

[0040] Currently, in our research, we have developed an OS transistor in which the semiconductor region is made of an oxide semiconductor. , and have practical characteristics that allow them to be incorporated into the same circuit together with Si transistors. Therefore, the transistor Qn1 and the transistor Qn In order to more effectively reduce the leakage current of the circuit 21, Preferably, all n-type transistors in circuit 21 are OS transistors. The leakage current of the OS transistor in the circuit 21 is 1×10 -15 A and below or 1×10 -18 A or less, or 1×10 -21 It is preferable that it is A or less.

[0041] There is no particular restriction on the material of the semiconductor region of the p-type transistor of the circuit 21. The semiconductor region of the p-type transistor of the circuit 21 contains one or more Group 14 elements such as Si, Ge, and C. The semiconductor may be made of a semiconductor containing one or more of the above-mentioned elements, or may be made of a nitride semiconductor such as gallium nitride. Typically, a p-type transistor is formed by forming a semiconductor region made of silicon. A Si transistor having such a structure may be used.

[0042] When the transistor Qn2 is in a conductive state, the threshold voltage of the transistor Qn2 Therefore, when the state of the source of the transistor Qp1 is in an intermediate state between “H” and “L”, It is preferable to set the high level potential of the signal SLP higher than VDD. During the period when 21 is in normal operating mode, the source of transistor Qp1 is made to be "H" This makes it possible to prevent malfunction of the circuit 21.

[0043] <Configuration example 2> The circuit 22 shown in FIG. 1B is a modified example of the circuit 21. As a circuit, a transistor Qn3 is provided in place of the transistor Qn2. The transistor Qn3 is also an n-type transistor like the transistor Qn2, and is an OS transistor. It is.

[0044] The source of the transistor Qp1 is electrically connected to the node p1. The electrical connection between the source of transistor 1 and node p1 may be direct or may be achieved by other means such as a transistor. An indirect connection via an element is also possible.

[0045] A signal SLP is input to the gate of the transistor Qn3. A switch that controls the conduction state between the drain of transistor Qn1 and the drain of transistor Qp1. The drain of the transistor Qn3 is connected to the drain of the transistor Qp1. The source of the transistor Qn1 is electrically connected to the drain of the transistor Qn2. .

[0046] The circuit 22 is in a standby state when the gate state of the transistor Qn1 is "H". This effectively reduces the power consumption of the circuit 22. Since the standby state is entered when the node b1 is in the standby state, the node b1 is maintained at "L" during the standby state. , the circuit 22 does not need power to restore the state of the node b1 when normal operation resumes. .

[0047] When the state of node b1 should be “H”, the effect of the threshold voltage of transistor Qn3 Therefore, when the state of the node b1 is in an intermediate state between “H” and “L”, the high level of the signal SLP is It is recommended to set the potential of the bell higher than VDD. This will allow the circuit 22 to operate in normal mode. This makes it possible to prevent malfunction of a circuit to which the output signal B1 of the circuit 22 is input.

[0048] <Configuration Examples 3 and 4> FIG. 2A is a modified example of the circuit 21. The circuit 23 shown in FIG. 2A is a modified example of the circuit 21. A p-type transistor (transistor Qp2) is provided in the circuit 24 shown in FIG. This is a modification of the circuit 22, in which the transistor Qn3 is replaced with a p-type transistor (transistor Qp3) is provided.

[0049] In addition, the circuits 22 and 24 include a power supply between the output node b1 and the drain of the transistor Qp1. Since a gate switch is provided, if a gate leak occurs in transistor Qp1 in the standby state, Even in this case, the potential of the output node b1 is hardly affected.

[0050] Since the leakage current of OS transistors can be considered to be almost zero when they are off, The circuits 21 and 22 in which S transistors are used as power switches are It is possible to reduce leakage current in the standby state more than with .

[0051] <Configuration Example 5> In the circuit 21, a back gate is provided to the transistor Qn2 that functions as a power switch. For example, a barrier may be provided separately from the gate (front gate) of the transistor Qn2. In the circuit 21, the potential of the other O The same is true for the S transistor. By changing the potential of the gate, the appropriate amount of drain current flows in the conductive state and in the non-conductive state. In this case, the leakage current can be made very small. is sometimes called the on-current.

[0052] In order to reduce the dynamic power consumption of the circuit 21, it is effective to lower VDD. The OS transistor has a sufficient on-state current so that the circuit 21 can perform a given process even at a low VDD. It is preferable that the OS transistor has an on-current characteristic. In some cases, the leakage current can be large even if the gate potential is set to VSS. In the standby mode, the leakage current of the OS transistor is controlled by controlling the back gate potential. In the normal operation mode, the on-state current of the OS transistor is The potential of the back gate may be controlled so that the potential of the back gate is increased. The same is true for the OS transistor included in the circuit 24.

[0053] As mentioned above, a power switch that controls the cutoff of VDD is provided in the circuit that performs the calculations. This reduces the leakage current of the p-type transistor, which is non-conductive in the standby state. In addition, by using OS transistors as n-type transistors, This reduces the leakage current of the n-type transistor that is in the VSS state. Therefore, there is no need to provide a power switch for cutting off VSS. The increase in circuit area due to the addition of a power switch is suppressed, and the power It will no longer be necessary.

[0054] As described above, in the above configuration example, adding a power gating function to the circuit This effectively reduces power consumption in standby mode while minimizing area overhead. It is possible.

[0055] <<Circuit configuration example>> A more specific circuit configuration of the above example will be described below. 4 and 5 are concrete examples of two-input, one-output circuits. The following shows a NAND gate circuit and a NOR gate circuit. The inverter circuit, the NAND gate circuit, and the NOR gate circuit are denoted as INV, NA Sometimes called ND or NOR.

[0056] <Inverter circuit> FIG. 3A is a specific example of the circuit 21. INV31 shown in FIG. 3A includes a p-type transistor Mp1 , an n-type transistor Mos1, and an n-type transistor Mos2. Mos1 and Mos2 are OS transistors. Transistor Mp1 and transistor Mo The transistor Mos2 in the figure constitutes a CMOS inverter circuit. This transistor corresponds to the 1A transistor Qn2.

[0057] FIG. 3B is a specific example of the circuit 22. INV32 shown in FIG. The transistor Mp1 is a p-type The transistors Mos1 and Mos3 are n-type OS transistors. The transistor Mos3 corresponds to the transistor Qn3 in FIG. 1B.

[0058] FIG. 3C is a specific example of the circuit 23. The INV33 shown in FIG. The transistor Mp2 and the transistor Mos1 are shown in FIG. This transistor corresponds to the transistor Qp2.

[0059] FIG. 3D is a specific example of the circuit 24. The INV34 shown in FIG. The transistor Mp3 and the transistor Mos1 are the same as those in FIG. This transistor corresponds to the transistor Qp3.

[0060] INV35 shown in FIG. 3E is a circuit corresponding to the above-mentioned configuration example 5, and is a modified example of INV32. Instead of the transistors Mos1 and Mos3, a transistor having a back gate is used. The back gate of the transistor Mosb1 is connected to the The signal OSB1 is input, and the signal OSB3 is input to the back gate of the transistor Mosb3. is applied. A common control signal may be input to the back gates of each of the transistors Mosb1 and Mosb3.

[0061] <NAND gate circuit> FIG. 4A shows a specific example of the circuit 21. The NAND41 shown in FIG. 4A has two input nodes a1 and a2. NAND41 is a NAND gate circuit composed of two p-type transistors (Mp11, Mp12) and two n-type transistors (Mos11, Mos12), to which a transistor Mos2 is added. The n-type transistors (Mos2, Mos11, Mos12) included in NAND41 are OS transistors. The transistor Mos2 functions as a switch for controlling the electrical connection between the node p1 and the sources of the transistors Mp11 and Mp12, and also functions as a switch that can cut off the supply of VDD to NAND41.

[0062] FIG. 4B shows a specific example of the circuit 22. The NAND42 shown in FIG. 4B is a NAND gate circuit composed of two p-type transistors (Mp11, Mp12) and two n-type transistors (Mos11, Mos12), to which a transistor Mos3 and a transistor Mos4 are added. The transistor Mos3 functions as a switch for controlling the electrical connection between the drain of the transistor Mp11 and the node b1. The transistor Mos4 functions as a switch for controlling the electrical connection between the drain of the transistor Mp12 and the node b1. The signal SLP is input to the gates of the transistors Mos3 and Mos4. That is, the transistors Mos3 and Mos4 control the supply of V to the node b1. ​​​​​It has the function of a power switch that can cut off the supply of DD.

[0063] Figure 4C is a specific example of circuit 23 and a modified example of NAND41. The NAND 43 shown in Figure 4C has transistor Mp2 instead of transistor Mos2.

[0064] Figure 4D is a specific example of circuit 24 and a modified example of NAND42. The NAND 44 shown in Figure 4D has transistors Mp3 and Mp4 instead of transistors Mos3 and Mos4. It has.

[0065] All or part of the OS transistors of NAND41 - 44 may be transistors having a back gate such as transistor Mosb1 in Figure 3E. It may be a transistor having a back gate such as transistor Mosb1 in Figure 3E.

[0066] <NOR gate circuit> Figure 5A is a specific example of circuit 21. NOR51 shown in Figure 5A is a NOR gate circuit composed of two p - type transistors (Mp21, Mp22) and two n - type transistors (Mos21, Mos22) with an additional n - type transistor Mos2 added. The n - type transistors (Mos2, Mos21, Mos22) that NOR5 1 has are OS transistors. Transistor Mos2 functions as a switch that controls the electrical connection between node p1 and the source of transistor Mp22. Transistor Mos2 functions as a switch that controls the electrical connection between node p1 and the source of transistor Mp22. It functions as a switch that controls the electrical connection between node p1 and the source of transistor Mp22.

[0067] Figure 5B is a specific example of circuit 22. NOR52 shown in Figure 5B is a NOR gate circuit composed of two p - type transistors (Mp21, Mp22) and two n - type transistors (Mos21, Mos22) with transistor Mos3 added. The transistor Mos3 is added to the NOR gate circuit composed of two p - type transistors (Mp21, Mp22) and two n - type transistors (Mos21, Mos22). The transistor The drain of the transistor Mp21 and the drain of the transistor Mos21 are connected to the It functions as a switch that controls the electrical connection between

[0068] FIG. 5C is a specific example of the circuit 23, which is a modification of the NOR 51. The NOR 53 shown in FIG. has a transistor Mp2 instead of the transistor Mos2.

[0069] FIG. 5D is a specific example of circuit 24, which is a modification of NOR 52. NOR 54 shown in FIG. has a transistor Mp3 instead of the transistor Mos3.

[0070] All or part of the OS transistors in NOR51-54 may be replaced with the transistors in FIG. A transistor having a back gate such as Mosb1 may also be used.

[0071] Logic cells (also called standard cells) are used as basic logic gate circuits, as shown in Figures 3-5. By adding a power gating function to the 16-bit MOS transistor, fine-grained power gating is possible. In addition, by using OS transistors for the n-type transistors of the logic cells, To effectively reduce leakage current of a logic cell in a standby state without providing a power switch. It is possible.

[0072] A semiconductor device such as an integrated circuit incorporates multiple logic cells. By applying the circuits 21-24 shown in FIG. 2, the power consumption of the semiconductor device is effectively reduced. An example of the configuration and operation of a semiconductor device that can suppress an increase in the circuit area will be described. Specifically, one of the two cascaded circuits has a power switch for cutting off VDD. The other circuit does not have a power switch. The transistor is an OS transistor. By using such a circuit configuration, The area overhead caused by incorporating a power gating function in the This makes it possible to effectively reduce power consumption in the standby state. These will be explained below.

[0073] <<Example of semiconductor device configuration>> <Configuration Example 1-1> FIG. 6 shows an example of a semiconductor device, which is a two-stage inverter circuit connected in cascade. Shows.

[0074] The semiconductor device 101 shown in FIG. 6A includes INV31 and INV30. A high power supply potential VDD and a low power supply potential VSS are supplied to the .

[0075] The INV30 is a typical CMOS inverter that does not have a VDD or VSS cutoff function. Even when the semiconductor device 101 is in a standby state, the source of the transistor Mp5 The INV pin is supplied with VDD, and the source of the transistor Mos5 is supplied with VSS. 30 includes an input node a11, an output node b11, a p-type transistor Mp5, and an n-type transistor The n-type transistor Mos5 is also an OS transistor. This allows the gate to be turned on even if there is no power switch for cutting off the VSS. If it is L”, the leakage current of the n-type transistor Mos5 can be reduced to almost zero.

[0076] An example of operation when the standby state occurs when the node a1 is at "H" will be described. Just before changing from "H" to "L", node a1 is "H" and node b1 is "L". Therefore, the node b11 is at "H". Therefore, in the INV30, the transistor Mp5 is turned on. In the standby state, the transistor Mos5 is in the non-conducting state, so that INV30 On the other hand, in INV31, the transistor Mp1 is in a non-conducting state. The transistor Mos1 is in a conducting state. This reduces the leakage current of the transistor Mp1. Since the potential of the output node b1 caused by the leakage current of 1 can be prevented from increasing, This prevents leakage current and shoot-through current from occurring in the INV30 in the subsequent stage. In this state, the power consumption of the entire semiconductor device 101 can be reduced.

[0077] In this case, in the standby state, the semiconductor device 101 keeps the state of the node b11 at "H". Therefore, when the semiconductor device 101 returns to normal operation, Since no power is required to charge the terminal b11, the power consumption of the semiconductor device 101 can be reduced. become.

[0078] An example of operation when the node a1 is in a standby state while it is at "L" is explained. In this case, the transistor Mos1 is in a non-conducting state, so the leakage current in INV31 is almost zero. On the other hand, since "H" is input to node a11 of INV30, Therefore, a leakage current flows through the transistor Mp5, and the potential of the output node b11 rises. For example, if an inverter circuit is connected to the output node b11, A shoot-through current flows through the inverter circuit.

[0079] In this way, in the semiconductor device 101, one of the two inverter circuits Since a power switch is provided only on the path, the standby state occurs when node a1 is at "H" and "L". The effect of reducing leakage current is different depending on the state, and when node a1 is at "L", the effect is low. On the other hand, the semiconductor device 101 corresponds to one of the two-stage CMOS inverter circuits. By providing a switch for cutting off VDD, the standby state is established when node a1 is at “H”. By changing the state to this state, leakage current is reduced and a new function called state memory is realized. The semiconductor device 101 in FIG. 6A is a two-stage CMOS inverter circuit with one power - The circuit configuration with an additional switching transistor provides the above-mentioned excellent effects. In other words, this embodiment can achieve the above by minimizing the number of elements and control signals. This makes it possible to effectively reduce power consumption.

[0080] In general clock gating, the state of the input node of a logic circuit is inaccurate when it goes into a standby state. Therefore, in order to maximize the performance of the semiconductor device 101, the standby state is When the semiconductor device 10 is in this state, the node a1 may be set to "H". One embodiment is a clock tree made up of multiple inverter circuits. More on this later.

[0081] <Configuration example 1-2> In the example of FIG. 6A, INV31 is an inverter circuit having a power switch for VDD. However, the inverter circuit of the other configuration example shown in the first embodiment (for example, INV3 2-35) can be applied. Also, INV30 is provided on the input side and INV An inverter circuit having a power switch for VDD such as 31 may be provided. A modified example of the semiconductor device 101 is shown in FIG. The semiconductor device 102 operates in the same manner as the semiconductor device 101.

[0082] 6 shows an example of a two-stage inverter circuit, but the present invention is not limited to this. In addition to the data circuit, other logic cells such as NAND gate circuits and NOR gate circuits can be applied. Other configuration examples are shown in Figures 7 and 8.

[0083] <Configuration Example 1-3> The semiconductor device 103 shown in FIG. 7A includes a NAND 40 and an INV 33, and is an AND gate circuit. The NAND40 does not have the VDD and VSS cutoff function. This is a NAND gate circuit. NAND40 is made up of two p-type transistors (Mp15, Mp 16) and two n-type transistors (Mos15, Mos16). The transistors Mos15 and Mos16 are OS transistors. , the input node a11 of INV33 is electrically connected. 3, INV31, INV32, or INV34 may be provided.

[0084] When both node a1 and node a2 are at "L", the semiconductor The power gating function of the device 103 can be effectively used. Since the transistors Mos15 and Mos16 are non-conductive, almost no leakage current flows. In NV33, the input node a11 is at “H” so that the transistor Mp1 is in a non-conducting state. However, by making the transistor Mp2 non-conductive, the leakage current of the transistor Mp1 can be reduced.

[0085] <Configuration Example 1-4> The semiconductor device 104 shown in FIG. 7B is a modified example of the semiconductor device 103. Like the semiconductor device 103, the semiconductor device 102 has a NAND gate circuit and an inverter circuit. The device 104 includes a NAND43 with a power switch for VDD, and a power switch Instead of NAND43, the NAND4 shown in FIG. 1, NAND42, or NAND44 may be provided.

[0086] When both node a1 and node a2 are at "H", the semiconductor The power gating function of the device 104 can be effectively utilized. The supply of VDD to the source of transistor Mp11 is cut off by resistor Mp2. Therefore, the leakage current of the transistors Mp11 and Mp12 can be reduced. Since the node a11 is at "L", the leakage current of INV30 can be made almost zero. In addition, since the output node b1 can be maintained at "L", the output node b11 can be maintained at "H". This allows the device to return from standby to normal operation in a short time. It is possible.

[0087] <Configuration Example 1-5> The semiconductor device 105 shown in FIG. 8A has a NOR 50 and an INV 34, and functions as an OR gate circuit. NOR50 is a normal NOx converter that does not have the VDD and VSS cutoff function. R gate circuit. NOR50 is composed of two p-type transistors (Mp17, Mp18) and and two n-type transistors (Mos17, Mos18). 17, Mos18 are OS transistors. INV34 is connected to the output node b1 of NOR50. The input node a11 of the INV34 is electrically connected to the INV34 shown in FIG. V31, INV32, or INV33 may also be provided.

[0088] When the nodes a1 and a2 are at "L", the semiconductor device 1 is in a standby state. The power gating function of the NOR50 can be effectively used. Since os17 and Mos18 are non-conductive, almost no leakage current flows. INV34 In this case, the input node a11 is at “H” and the transistor Mp3 is turned off. Therefore, the leakage current of the transistor Mp1 can be reduced in the standby state. This allows the state of the output node b11 to be maintained at "L".

[0089] <Configuration Example 1-6> The semiconductor device 106 shown in FIG. 8B is a modified example of the semiconductor device 105. Similarly, the semiconductor device 106 has a NOR gate circuit and an inverter circuit. The OR gate circuit is a NOR52 with a power switch for VDD, and the inverter circuit The path is INV30 which does not have a power switch. Instead of NOR52, OR51, NOR53 or NOR54 may be provided.

[0090] When the nodes a1 and a2 are at "H", the semiconductor device 1 is in a standby state. The power gating function of the NOR52 transistor M By making os3 non-conductive, the leakage current of transistors Mp21 and Mp22 is In INV30, the input node a11 is at “L” level, so the leakage current is The current can be suppressed to almost zero. In addition, the output node b1 can be maintained at "L". The output node b11 can be maintained at "H".

[0091] <Configuration Example 1-7> The semiconductor device 107 shown in FIG. 9A is a modified example of the semiconductor device 103, and has an INV3 On the output side, NAND40 is provided. The input node b1 of the NAND40 is electrically connected to the input node a11 of the NAND40. Instead, INV31, INV32 or INV34 may be provided.

[0092] When node a1 is "H" and node a12 is "L", the standby state is established. The power gating function of the semiconductor device 107 can be effectively utilized. By making the transistor Mp2 non-conductive, the leakage current of the transistor Mp1 can be reduced. In NAND40, the transistors Mos15 and Mos16 are non-conductive. Since the transistor is in a conductive state, the leakage current can be suppressed to almost zero.

[0093] <Configuration Example 1-8> The semiconductor device 108 shown in FIG. 9B is a modified example of the semiconductor device 105, and has an INV3 2 is provided, and NOR50 is provided on the output side. The input node b1 is electrically connected to the input node a11 of NOR50. INV31, INV33 or INV34 can be provided.

[0094] When node a1 is "H" and node a12 is "L", the standby state is established. The power gating function of the semiconductor device 108 can be effectively utilized. By making the transistor Mos3 non-conductive, the leakage current of the transistor Mp1 is reduced. In NOR50, the transistors Mos17 and Mos18 are non-conducting. Since the transistor is in a conductive state, the leakage current can be suppressed to almost zero.

[0095] <<Configuration Example 2 of Semiconductor Device>> Here, a clock tree will be described as an example of a semiconductor device.

[0096] <Clock tree configuration example> 10A shows an example of a semiconductor device having a clock tree. The tree 120 has a binary tree structure composed of inverter circuits, and its depth (number of stages) is The clock tree 120 has six stages and six outputs. The first stage of the clock tree 120 has the output of the circuit CGB. Each of the six output terminals (output nodes) is connected to a flip-flop circuit. (Hereinafter, they may be referred to as FF.) 141-146 are electrically connected.

[0097] The circuit CGB can function as a clock-gated circuit. A gated clock signal C that is synchronized to the clock signal CLK while EN is active. In the example of FIG. 10A, the circuit CGB has FF131 and NAND132. The FF 131 functions as a memory circuit that holds the signal EN. The signal CLKG is generated by performing a logical NAND operation on the signal EN and the signal CLK, and is output. In the example of 10A, the circuit CGB operates in the same manner as the signal CLK while the output of FF131 is at “H”. The signal CLKG, whose potential level changes periodically, is output to the clock tree 120. When is "L", the potential level of the signal CLKG becomes "H".

[0098] In the clock tree 120, the inverter circuit in the odd-numbered stage is INV90, and the inverter circuit in the even-numbered stage is INV90. The inverter circuit is INV91. INV90 uses a power switch to set the output node It is possible to cut off the VDD supply to the inverter. The circuit symbol shown in FIG. 10B is used as the symbol. The circuit symbol in FIG. 10B indicates the signal SL This indicates that the supply of VDD can be controlled by P.

[0099] INV90 can be applied to INV31-34 shown in Figure 3. INV91 is Like the INV30, it does not have a power switch to shut off VDD and VSS. This is a normal CMOS inverter circuit. INV90 plus INV31 or INV33 When applying this to multiple INV90s, the power switch for cutting off VDD can be shared by multiple INV90s. Such an example is shown in Figure 11.

[0100] In the clock tree 121 shown in FIG. 11A, a common power supply is provided for the INV93 in the odd-numbered stages. A switch 150 is provided. INV93 is also an n-type transistor, like INV91. This is a typical CMOS inverter circuit consisting of a p-type transistor and a p-type transistor. The switch 150 is composed of an n-type transistor Mos50. The transistor Mos50 is The channel width of the transistor Mos50 and the high level of the signal SLP The potential of the filter is determined by the number of INVs 93 controlled by the power switch 150.

[0101] 11A, the wiring 160 functions as a power supply line that supplies the power supply potential VSS. The wiring 161 functions as a power supply line that supplies a power supply potential VDD. The power switch 150 functions as a virtual power line that supplies VVDD. It has a function of controlling the conduction state between the wirings 162. The source of the transistor is electrically connected to the wiring 160. The source of the p-type transistor of INV93 is electrically connected to the wiring 161. The source is electrically connected to the wiring 162 .

[0102] FIG. 11B shows a conventional inverter circuit in which inverter circuits in the same stage are controlled by a common power switch. The clock tree 122 shown in FIG. 11B has three stages, Power switches 151, 152, and 153 are provided. The power switch 151, the power switch 152, and the power switch 153 are It is composed of transistors Mos51, Mos52, and Mos53. S51, Mos52, and Mos53 may be OS transistors. Power switch 15 11B, the wiring 163 and the wiring 1-153 may be p-type transistors. 64 and the wiring 165 function as virtual power supply lines for supplying a virtual power supply potential VVDD. do.

[0103] The power switch 151 controls the conduction state between the wiring 161 and the wiring 163. The source of the p-type transistor of the inverter circuit 93 is electrically connected to the wiring 163 . The power switch 152 controls the conduction state between the wiring 161 and the wiring 164. The source of the p-type transistor of the inverter circuit 93 is electrically connected to the wiring 164 . The power switch 153 controls the conduction state between the wiring 161 and the wiring 165. The source of the p-type transistor of the inverter circuit 93 is electrically connected to the wiring 165 .

[0104] A signal SLP is input to the gates of the transistors Mos51-Mos53. The signal SLP is input to the gates of the data buses Mos51 and Mos53 at the same time. Alternatively, the signal SLP may be input at different timings.

[0105] In addition, in the clock tree 120 shown in FIG. 10A, INV90 is configured with INV32. In this case, all INV32 in the clock tree 120 are supplied with signals at the same timing. Alternatively, for each stage (depth) of the clock tree 120, The input timing of the signal SLP may be changed. This is done by replacing INV90 with INV34. The same applies when creating a

[0106] <Example of operation> An operation example of the semiconductor device shown in FIG. 10A will be described. Here, the clock tree 120 includes the clock Assume that clock tree 121 of 1A is applied.

[0107] During the period when the signal EN is at "H", the signal CLKG is supplied to the FFs 141 to 146. During this time, the signal SLP is at "H", the transistor Mos50 is in a conducting state, and the INV91 and VDD is supplied to INV93.

[0108] To block signal CLKG for FF141 - 146, set signal EN to "L". This fixes the output of circuit CGB to "H". Thus, the output of the odd - stage INV93 is fixed to "L", and the output of the even - stage INV91 is fixed to "H". To put clock tree 121 in the standby state, after setting signal EN to "L", set signal SLP to "L" to turn off transistor Mos50. This cuts off the supply of VDD to the odd - stage INV93. Since the n - type transistor of INV93 is composed of an OS transistor, the leakage current can be considered almost zero, so the output of INV93 can be maintained at "L". Accordingly, the output of the even - stage INV91 can be maintained at "H". Therefore, in the standby state, the six output nodes of clock tree 121 can maintain the state just before the standby state.

[0109] Therefore, when restoring clock tree 121 to the normal - operation state, no power is required to set the output of the even - stage INV91 of clock tree 121 to "H". Also, the overhead time required to return from the standby state to the normal state can be shortened. When restoring clock tree 121 to the normal - operation state, set SLP to "H" and signal EN to "H".

[0110] (Embodiment 2) In this embodiment, an OS transistor and a semiconductor device having an OS transistor will be described.

[0111] <<Example Configuration of OS Transistor 1>> FIG. 12 shows an example of the configuration of an OS transistor. FIG. 12A shows one 12B is a cross-sectional view taken along line y1-y2, and FIG. 12D is a cross-sectional view taken along the line x3-x4. Here, the direction of the line y1-y2 is is sometimes called the channel length direction, and the x1-x2 line direction is sometimes called the channel width direction. 12B is a cross-sectional view of an OS transistor taken along a channel length direction, and FIG. 12C is a cross-sectional view of an OS transistor taken along a channel length direction. 12D is a cross-sectional view of the OS transistor in the channel width direction. To clarify the device structure, some components are omitted in FIG. 12A.

[0112] The OS transistor 501 shown in FIG. 12 has a back gate. 1 is formed on an insulating surface. In this example, it is formed on an insulating layer 511. The OS transistor 501 is formed on the surface of a substrate 510. The insulating layers 514 and 515 are covered with the OS transistor 501. The OS transistor can be regarded as a component of the insulating layer 512, the insulating layer 513, Oxide semiconductor (OS) layers 521-523, a conductive layer 530, a conductive layer 531, a conductive layer 541, In this embodiment, the OS layer 521, the OS layer 522, and the OS layer 542 are 23 are collectively referred to as the OS layer 520.

[0113] The insulating layer 513 has a region that functions as a gate insulating layer. The conductive layer 531 functions as a back gate electrode. The same potential or signal as that of the conductive layer 530 may be supplied, or a different potential or signal may be supplied. The conductive layer 541 and the conductive layer 542 may be supplied with different potentials or different signals. , which functions as a source electrode or a drain electrode.

[0114] As shown in FIGS. 12B-C, the OS layer 520 includes an OS layer 521, an OS layer 522, and an OS layer 523. 3 are laminated in this order. An insulating layer 513 covers this laminated portion. The conductive layer 531 overlaps with the laminated portion via the insulating layer 512. The optical fiber 501 is provided on a stack of an OS layer 521 and an OS layer 522. In the example of FIG. 12, the upper surface of the stacked film and the side surface of the stacked film in the channel length direction are in contact with each other. The conductive layers 541 and 542 are also in contact with the insulating layer 512. The OS layer 523 is formed to cover the insulating layer 522 and the conductive layers 541 and 542. The lower surface is in contact with the upper surface of the OS layer 522 .

[0115] The OS layer 523 and the insulating layer 513 may be etched by using the conductive layer 530 as a mask. In this case, the edges of the OS layer 523 and the insulating layer 513 are approximately aligned with the edges of the conductive layer 530. It becomes.

[0116] In the OS layer 520, the channel of the stacked portion of the OS layers 521-523 is formed through the insulating layer 513. A conductive layer 530 is formed to surround the panel in the width direction (see FIG. 12C). Therefore, the gate electric field is applied to this stack from both the vertical and lateral directions. In the OS transistor 501, the gate electric field is the electric field generated by the conductive layer 531 (gate electrode The electric field created by the voltage applied to the gate electrode (layer) is called the gate electric field. Since the entire stack of the OS layers 521-523 can be electrically surrounded, the OS layer 5 In some cases, a channel may be formed throughout the entirety of 22 (bulk). The transistor 501 can have high on-current characteristics.

[0117] In this specification, the term "transistor" refers to a transistor that can electrically surround a semiconductor by a gate electric field. The transistor structure is called "surrounded channel (s-channel)" The OS transistor 501 has an s-channel structure. In the nel structure, a large current can flow between the source and drain of the transistor, and the In this case, the drain current can be increased.

[0118] By forming the OS transistor 501 in an s-channel structure, In contrast, the channel formation region can be easily controlled by the gate electric field. In the case where the optical fiber extends below the OS layer 522 and faces the side surface of the OS layer 521, the controllability is further improved. As a result, the subthreshold swing value (S This makes it possible to reduce the short channel effect. This structure is suitable for miniaturization.

[0119] As shown in FIG. 12, an OS transistor is formed in a three-dimensional device structure. By using this structure, the channel length can be reduced to less than 100 nm. By miniaturizing, the circuit area can be reduced. The channel length of the OS transistor is 65n. It is preferably less than m, more preferably 30 nm or less or 20 nm or less.

[0120] The conductor that functions as the gate of the transistor is called the gate electrode, and the source of the transistor is called the The conductor that functions as the source electrode and the conductor that functions as the drain of the transistor are called the drain. The region that functions as the electrode, source of the transistor is called the source region, and the region that functions as the drain of the transistor is called the drain region. The region that functions as a gate electrode is called the drain region. The drain electrode or drain region is referred to as the drain, and the source electrode or source region is referred to as the source. There are cases.

[0121] The channel length is, for example, the length of the semiconductor (or transistor) in a top view of the transistor. The area where the gate overlaps with the transistor (the part of the semiconductor through which current flows when the transistor is on), or the transistor This refers to the distance between the source and drain in the region where the channel is formed. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is defined as any one value, maximum value, or The minimum or average value.

[0122] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate overlaps with the current flowing part, or in the region where the channel is formed The length of the part where the source and drain face each other. In a transconductance analysis, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is a value, a maximum value, a minimum value or a width in the region where the channel is formed. is the average value.

[0123] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The channel width (hereinafter referred to as the effective channel width) may be different from the channel width (hereinafter referred to as the apparent channel width) shown in the top view of the transistor. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become significant. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. In this specification, when simply referring to the channel width, it may refer to the apparent channel width. Or, in this specification, when simply referring to the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. <<Configuration Example 2 of OS Transistor>> The OS transistor 502 shown in FIG. 13 is a modified example of the OS transistor 501. FIG. 13A is a top view of the OS transistor 502. FIG. 13B is a cross-sectional view taken along the line y1 - y2, FIG. 13C is a cross-sectional view taken along the line x1 - x2, and FIG. 13D is a cross-sectional view taken along the line x3 - x4. In addition, for clarity of the device structure, some components are omitted in FIG. 13A.

[0124]

[0125]

[0126]

[0127] The OS transistor 502 shown in FIG. 13 is also an s-channel transistor, similar to the OS transistor 501. The OS transistor 502 does not have the conductive layer 531. The shapes of the conductive layer 541 and the conductive layer 542 are different from those of the OS transistor 501. The conductive layer 541 and the conductive layer 542 of 502 are formed as a laminated film of an OS layer 521 and an OS layer 522. The conductive layer 541 and the hard mask used to form the conductive layer 542 are therefore The conductive layer 542 is not in contact with the side surfaces of the OS layer 521 and the OS layer 522 (FIG. 13D). .

[0127] The OS layers 521 and 522 and the conductive layers 541 and 542 can be manufactured through the following steps. Two oxide semiconductor films constituting the OS layers 521 and 522 are formed. A single-layer or multi-layer conductive film is formed on the substrate. This conductive film is etched to form a hard mask. Using this hard mask, the two oxide semiconductor films are etched to form an O A laminated film of the S layer 521 and the OS layer 522 is formed. Next, the hard mask is etched. A conductive layer 541 and a conductive layer 542 are formed.

[0128] The components of the OS transistors 501 and 502 are described below.

[0129] <Oxide semiconductor layer> Representative semiconductor materials for the OS layers 521-523 include In-Ga oxide and In-Z n-oxide, In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd) In addition, the OS layers 521-523 are not limited to oxide layers containing indium. The layers 521-523 may be formed of, for example, Zn-Sn oxide layers or Ga-Sn oxide layers. The OS layer 522 is preferably an In-M-Zn oxide layer.

[0130] The OS layers 521-523 are formed of In-M-Zn oxide layers formed by sputtering. The case where the In-M-Zn oxide film used to form the OS layer 522 is formed will be described. The atomic ratio of the metal elements in the target for the OS layer is In:M:Zn=x1:y1:z1. The atomic ratio of metal elements in the target used for forming the OS layer 523 is In:M: Let Zn = x2:y2:z2.

[0131] In forming the OS layer 522, x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less. Therefore, z1 / y1 is 1 / 3 or more and 6 or less, and further, 1 or more and 6 or less, In-M-Zn oxide. It is preferable to use a polycrystalline target having the above formula. By setting z1 / y1 to 1 or more and 6 or less, CAAC-OS film is easily formed. A typical example of the atomic ratio of the target metal elements is as follows: There are In:M:Zn=1:1:1, In:M:Zn=3:1:2, etc. OS refers to an oxide semiconductor having crystal parts aligned along the c-axis. State.

[0132] The target used for forming the OS layer 521 and the OS layer 523 is x2 / y2 <x1 / y1 and z2 / y2 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When z2 / y2 is in the range of 1 to 6, a CAAC-OS film is easily formed. Representative examples of the atomic ratio of the target metal elements are In:M:Zn=1:3:2, In:M: Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, etc. .

[0133] (Energy band structure) Next, an OS layer 521, an OS layer 522, and an OS layer 523 are stacked. The function and effect of 520 will be described using the energy band structure diagram shown in FIG. 14B. FIG. 14A is an enlarged view of a channel region of OS transistor 502. FIG. 14B is a partially enlarged view of the portion indicated by the line z1-z2 in FIG. 14A (OS tissue). The energy band structure of the channel forming region of the transistor 502 is shown below. Although the OS transistor 502 will be described as an example, the same applies to the OS transistor 501.

[0134] In FIG. 14B, Ec512, Ec521, Ec522, Ec523, and Ec513 are The conduction bands of the insulating layer 512, the OS layer 521, the OS layer 522, the OS layer 523, and the insulating layer 513 are The lower energy is shown.

[0135] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) It can be measured using a VersaProbe.

[0136] The sputtering target used had an atomic ratio of In:Ga:Zn=1:3:2. The energy gap of the synthesized In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4 The atomic ratio of In:Ga:Zn is 1:3:4. The energy gap of the In-Ga-Zn oxide formed using the get is about 3.4 eV. The electron affinity is about 4.5 eV. The atomic ratio of In:Ga:Zn is 1:3:6. Energy gap of In-Ga-Zn oxide formed using a sputtering target The electron affinity is about 4.5 eV. The atomic ratio of In:Ga:Zn In-Ga-Zn oxide was formed using a sputtering target with a ratio of 1:6:2. The energy gap is about 3.9 eV and the electron affinity is about 4.3 eV. In-Ga formed using a sputtering target with In:Ga:Zn=1:6:8 The energy gap of -Zn oxide is about 3.5 eV and the electron affinity is about 4.4 eV. In addition, a sputtering target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the formed In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the In-Ga-Zn oxide formed using a target was approximately 3.2 eV. The electron affinity is about 4.7 eV. The atomic ratio of In:Ga:Zn is 3:1:2. Energy gap of In-Ga-Zn oxide formed using a sputtering target The electron affinity is about 5.0 eV and the electron pump is about 2.8 eV.

[0137] Since the insulating layers 512 and 513 are insulators, Ec513 and Ec512 are It is closer to the vacuum level (has lower electron affinity) than 1, Ec522, and Ec523.

[0138] Also, Ec521 is closer to the vacuum level than Ec522. More than 0.05eV, more than 0.07eV, more than 0.1eV or more than 0.15eV higher than C522 V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less at the vacuum level Close proximity is preferable.

[0139] Also, Ec523 is closer to the vacuum level than Ec522. More than 0.05eV, more than 0.07eV, more than 0.1eV or more than 0.15eV higher than C522 V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less at the vacuum level Close proximity is preferable.

[0140] In addition, in the vicinity of the interface between the OS layer 521 and the OS layer 522 and in the vicinity of the interface between the OS layer 522 and the OS layer 523 Near the interface with the ZnO, a mixed region is formed, so the energy of the conduction band edge changes continuously. That is, there are no or almost no levels at these interfaces.

[0141] Therefore, in the stacked structure having the above energy band structure, electrons mainly pass through the OS layer 522. Therefore, the interface between the OS layer 521 and the insulating layer 512 or Even if a level exists at the interface between the OS layer 523 and the insulating layer 513, the level is not affected by the movement of electrons. In addition, the interface between the OS layer 521 and the OS layer 522 and the OS layer 52 Since there is no or almost no level at the interface between the semiconductor layer 3 and the OS layer 522, The movement of electrons is not hindered. The transistor 502 may have a high field effect mobility.

[0142] As shown in FIG. 14B, the interface between the OS layer 521 and the insulating layer 512 and the OS layer 523 In the vicinity of the interface between the insulating layer 513 and the silicon dioxide layer 514, a trap level Et502 due to impurities and defects is formed. However, because of the existence of the OS layer 521 and the OS layer 523, the OS layer 522 and This can keep the trap level away.

[0143] In the OS transistor 502, the top and side surfaces of the OS layer 522 are The bottom surface of the OS layer 522 is in contact with the OS layer 521 (FIG. 13C). In this way, the OS layer 522 is covered with the OS layer 521 and the OS layer 523. Therefore, the influence of the trap levels can be further reduced.

[0144] However, if the energy difference between Ec521 or Ec523 and Ec522 is small, O Electrons in the S layer 522 may exceed the energy difference and reach the trap level. When electrons are captured in the level, a negative fixed charge is generated at the interface of the insulating film, causing a transistor The threshold voltage of the transistor is shifted in the positive direction.

[0145] Therefore, the energy difference between Ec521, Ec523 and Ec522 is 0 If the capacitance is set to 0.1 eV or more, preferably 0.15 eV or more, the change in the threshold voltage of the transistor is This is preferable because the electric characteristics of the transistor can be improved by reducing the electric field. .

[0146] The band gaps of the OS layer 521 and the OS layer 523 are the same as that of the OS layer 522. It is preferable that it is wider than the gap.

[0147] The OS layer 521 and the OS layer 523 may include, for example, Y, Zr, La, Ce, or Nd. A material containing the atomic ratio higher than that of the S layer 522 can be used. The ratio of the number of the elements is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since silicon strongly bonds to oxygen, it has the function of suppressing the formation of oxygen vacancies in oxide semiconductors. That is, the OS layers 521 and 523 have more oxygen vacancies than the OS layer 522. It can be said that this is difficult to do.

[0148] The OS layer 521, the OS layer 522, and the OS layer 523 each contain at least indium, zinc, and M( M is In-M-Zn oxide containing Ga, Y, Zr, La, Ce, or Nd. In this case, the OS layer 521 is In:M:Zn=x1:y1:z1 [atomic ratio], and the OS layer 522 is I n:M:Zn=x2:y2:z2 [atomic ratio], OS layer 523 In:M:Zn=x3: If y3:z3 [atomic ratio], y1 / x1 and y3 / x3 are greater than y2 / x2. It is preferable that y1 / x1 and y3 / x3 are 1.5 times or more larger than y2 / x2. Preferably, the number of times is two or more, and more preferably, the number of times is three or more. When y2 is equal to or larger than x2, the electrical characteristics of the transistor can be stabilized. If y2 is three times or more larger than x2, the field effect mobility of the transistor decreases. , y2 is preferably less than three times x2.

[0149] The In-M-Zn oxide film that satisfies these conditions satisfies the atomic ratio of the metal elements described above. The In-M-Zn oxide target can be used to form the In-Zn oxide.

[0150] The atomic ratio of In and M, excluding Zn and O, in the OS layers 521 and 523 is Preferably, In is less than 50 atomic % and M is greater than 50 atomic %; More preferably, In is less than 25 atomic % and M is greater than 75 atomic %. The atomic ratio of In and M, excluding Zn and O, in the OS layer 522 is preferably In is higher than 25 atomic % and M is less than 75 atomic %, more preferably In is greater than 34 atomic % and M is less than 66 atomic %.

[0151] The thickness of the OS layer 521 and the OS layer 523 is 3 nm or more and 100 nm or less, preferably 3 nm or less. The thickness of the OS layer 522 is 3 nm or more and 200 nm or less. Preferably, the thickness is 3 nm or more and 100 nm or less, and more preferably, the thickness is 3 nm or more and 50 nm or less. In addition, the OS layer 523 is preferably thinner than the OS layers 521 and 522 .

[0152] In order to give stable electrical characteristics to an OS transistor with an oxide semiconductor channel, The present invention relates to a method for reducing the impurity concentration in an oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is 1× 10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 Less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0153] In addition, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity levels can become traps and degrade the electrical characteristics of the transistor. Therefore, in the OS layer 521, the OS layer 522, and the OS layer 523 and at their interfaces, It is preferable to reduce the impurity concentration in the

[0154] To determine whether an oxide semiconductor is intrinsic or substantially intrinsic, secondary ion mass spectrometry (SIMS) is used. ) at a certain depth or in a certain region of the oxide semiconductor. In the region, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than The hydrogen concentration is determined, for example, at a certain depth in the oxide semiconductor or In the area with the conductor, 2×10 20 atoms / cm 3 Less than or equal to 5×10 1 9 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 The following is further Preferably 5 x 10 18 atoms / cm 3 The nitrogen concentration is, for example, At a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, 19 atoms / cm 3 Less than 5 x 10 18atoms / cm 3 The following is better Preferably 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atom s / cm 3 The following applies.

[0155] In addition, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the oxide semiconductor In order to prevent the crystallinity of the oxide semiconductor from being reduced, For example, at a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, Silicon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 The portion that is less than In addition, for example, at a certain depth of the oxide semiconductor or In a given area of ​​the body, the carbon concentration is increased to 1×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 It is sufficient that the part is less than

[0156] In addition, a transistor using the highly purified oxide semiconductor for a channel formation region as described above can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V or 5 V, , or about 10 V, the off-state current normalized by the channel width of the transistor is It is possible to reduce the flux density from several yA / μm to several zA / μm.

[0157] <Crystal structure of oxide semiconductor> The structure of the oxide semiconductor film forming the OS layer 520 will be described below.

[0158] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0159] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0160] Oxide semiconductors are roughly classified into non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. As an oxide semiconductor, CAAC-OS (C Axis Aligned Crystal lline Oxide Semiconductor), polycrystalline oxide semiconductor, microcrystalline Oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor conductor, pseudo-amorphous oxide semiconductor (a-like OS) s-like oxide semiconductor), amorphous oxide semiconductor, etc. say.

[0161] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0162] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0163] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0164] (CAAC-OS) CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. The crystalline part of CAAC-OS is nanocrystalline (nc: nanocrysta CAAC-OS can also be called CANC (C-Axis Aligned The oxide semiconductor may also be referred to as an oxide semiconductor having nanocrystals.

[0165] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of CAAC-OS were obtained by using a high-resolution microscope. By observing the high-resolution TEM image, multiple crystals can be confirmed. On the other hand, the boundaries between crystals, i.e., grain boundaries (grain bows), are clearly visible even in high-resolution TEM images. Therefore, CAAC-OS is not able to confirm the grain boundary. This means that the decrease in electron mobility caused by magnetic fields is unlikely to occur.

[0166] When a high-resolution TEM image of the cross section of CAAC-OS was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. reflects the unevenness of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed) or the upper surface. The CAAC-OS has a shape similar to that of the crystalline silicon, and is arranged parallel to the surface on which the CAAC-OS is formed or the upper surface.

[0167] On the other hand, a high-resolution TEM image of the CAAC-OS plane was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal regions.

[0168] CAAC- analyzed by X-ray diffraction (XRD) Let us explain about OS. For example, for CAAC-OS with InGaZnO4 crystal, When the structure was analyzed by the out-of-plane method, the diffraction angle (2θ) was peaked at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is aligned with the surface on which the CAAC-OS is formed or the upper surface. It can be seen that the direction is approximately perpendicular to the

[0169] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. CAAC-OS shows a peak at 2θ of around 31° and a peak at 2θ of around 36°. It is preferred that no peaks are exhibited.

[0170] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are The removal of oxygen from the oxide semiconductor disrupts the atomic arrangement of the oxide semiconductor, which is a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Since the radius of the oxide semiconductor is large, when the oxide semiconductor is contained in the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed. Impurities contained in an oxide semiconductor can cause carrier transport and lead to a decrease in crystallinity. These may be sources of tripping or carrier generation.

[0171] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. In contrast, no clear peaks appear when a φ scan is performed on the InGaZnO4 single crystal. In the case of a crystalline oxide semiconductor, when 2θ is fixed at around 56° and φ is scanned, (110 ) plane are observed. From the structural analysis, it was confirmed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. do.

[0172] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0173] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0174] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0175] CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen vacancies can act as carrier traps or trap hydrogen, reducing carrier generation. It can be a source of

[0176] A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor has a small carrier generation source. Therefore, the carrier density can be reduced. The transistor has electrical characteristics in which the threshold voltage is negative (also called normally on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is unlikely to cause a problem. Therefore, the transistor using the oxide semiconductor has low electric characteristics. The carrier transport in the oxide semiconductor is small, resulting in a highly reliable transistor. The charge trapped in the wrap takes a long time to be released, and acts as if it were a fixed charge. Therefore, oxide semiconductors with high impurity concentrations and high density of defect states are A transistor using such a material may have unstable electrical characteristics.

[0177] The electrical characteristics of the CAAC-OS transistor change when irradiated with visible or ultraviolet light. The movement is small.

[0178] (nc-OS, microcrystalline oxide semiconductor) Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. In addition, the microcrystalline oxide semiconductor film has a region in which a crystal part cannot be clearly identified. The crystal part contained is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, fine crystals with sizes between 1 nm and 10 nm or between 1 nm and 3 nm are often An oxide semiconductor having nanocrystals (nc) is called nc-O. S (nanocrystalline oxide semiconductor) In addition, the grain boundaries of nc-OS cannot be clearly identified in high-resolution TEM images, for example. There are cases where this is the case.

[0179] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The atomic arrangement has periodicity in the region of less than 1 nm. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a diameter larger than the crystal part is used for nc-OS. When the structure was analyzed using the out-of-plane method, peaks indicating crystal planes were In addition, the probe diameter (e.g. 5 mm) is larger than the crystal area of ​​the nc-OS. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a wavelength of 0.0 nm or more, halo On the other hand, the size of the crystal part is smaller than that of the nc-OS. When nanobeam electron diffraction is performed using an electron beam with a probe diameter close to or smaller than the crystal part, In addition, when nanobeam electron diffraction is performed on nc-OS, a circular spot is observed. In some cases, a bright area (ring-shaped) may be observed. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. do.

[0180] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0181] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. In the case of nc-OS, there is no regularity in the crystal orientation between different crystal parts. The defect density is higher than that of C-OS.

[0182] (a-like OS, amorphous oxide semiconductor film) An amorphous oxide semiconductor is an oxide semiconductor in which the atomic arrangement is irregular and does not have crystal parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0183] In the case of amorphous oxide semiconductors, no crystalline parts can be confirmed in high-resolution TEM images. When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-plane In the analysis by the NE method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. In contrast, when nanobeam electron diffraction is performed, no spots are observed, but a halo pattern is observed. do.

[0184] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. A-like OS is a conductor. In high-resolution TEM images, it appears as voids. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. OS crystallizes when exposed to a small amount of electrons, the level observed with a TEM. On the other hand, if the nc-OS is of good quality, the microscopic size observed by TEM can be seen. Almost no crystallization was observed due to the large amount of electron irradiation.

[0185] The size of the crystals in a-like OS and nc-OS was measured using high-resolution TEM images. For example, the crystal of InGaZnO4 has a layered structure, and the In-O layer The unit cell of the InGaZnO4 crystal is In- The ZnO layer is three layers, and the Ga-Zn-O layer is six layers. A total of nine layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is the lattice spacing of the (009) plane. (also called the d value), and the value was determined to be 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in the high-resolution TEM image and found that the spacing between the lattice fringes is 0.28 In the area where the thickness is between 0.30 nm and 0.5 nm, the lattice fringes of InGaZnO4 This corresponds to the ab plane of the crystal.

[0186] Oxide semiconductors may have different densities depending on their structure. For example, the composition of a certain oxide semiconductor If the density of the oxide semiconductor layer is known, it can be compared with the density of a single crystal oxide semiconductor having the same composition. For example, the density of a single-crystal oxide semiconductor can be estimated. On the other hand, the density of a-like OS is between 78.6% and 92.3%. For example, the densities of the nc-OS and CAAC-OS are The density is 92.3% or more and less than 100%. %, it is difficult to form a film of an oxide semiconductor having a conductivity of less than 100%.

[0187] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor that satisfies the [number ratio], the single crystal InGaZnO4 with a rhombohedral crystal structure Density is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1[ In the case of an oxide semiconductor that satisfies the atomic ratio, the density of the a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 [ In the oxide semiconductor that satisfies the [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0188] Note that there may be cases where single crystal oxide semiconductors having the same composition do not exist. In such cases, By combining single crystal oxide semiconductors with different compositions, it is possible to obtain a single crystal oxide semiconductor having a desired composition. The density of a single crystal oxide semiconductor having a desired composition can be calculated. is calculated by using a weighted average of the ratio of combinations of single crystal oxide semiconductors with different compositions. However, the density should be reduced by combining as few types of single-crystal oxide semiconductors as possible. It is preferable to calculate it by combining the above.

[0189] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. A stacked film including two or more of a microcrystalline oxide semiconductor and a CAAC-OS may be used. .

[0190] <Substrate> The substrate 510 is not limited to being a simple support material, but may also be a substrate on which other devices such as transistors are formed. In this case, the conductive layer 530 and the conductive layer 541 of the OS transistor 501 may be a substrate. , and one of the conductive layers 542 may be in electrical communication with other devices described above.

[0191] <Undercoating insulating film> The insulating layer 511 serves to prevent the diffusion of impurities from the substrate 510. It is preferable that the insulating layer 51 has a role of supplying oxygen to the OS layer 520. 2 is preferably an insulating film containing oxygen, and the insulating film contains oxygen in a larger amount than the stoichiometric composition. For example, TDS (Thermal Desorption In thermal desorption spectroscopy, the surface temperature of the film was 100°C or higher. The amount of oxygen molecules released in the range of 100°C to 500°C or 700°C to 700°C is 1 .0×10 18 [molecules / cm 3 The substrate 510 is a film on which other devices are formed. In the case of a substrate that has been subjected to chemical mechanical polishing (CMP), the insulating layer 511 is polished to a flat surface. It is preferable to perform a flattening process using a method such as Al-Mechanical Polishing. It is.

[0192] The insulating layers 511 and 512 are made of aluminum oxide, aluminum oxynitride, or magnesium oxide. , silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide Insulating materials such as silicon nitride, silicon oxynitride, aluminum oxynitride, or The insulating film may be formed by using a mixture of these materials. is a material that contains more oxygen than nitrogen, and oxynitride is a material that contains more nitrogen than oxygen. It is a large amount of material.

[0193] <Gate electrode> The conductive layer 530 may be made of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Nickel Ni, Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (Co) , ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt) It is made of a low-resistance material, an alloy, or a compound that contains these as its main components. It is preferable. The conductive layer 530 may have a single layer structure or a stacked structure of two or more layers. Single-layer structure of aluminum film containing com, and double-layer structure of titanium film laminated on aluminum film A two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film is laminated on a titanium nitride film A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. A two-layer structure is formed by laminating a titanium film and an aluminum film on the titanium film, and then laminating the titanium film on top of that. Three-layer structure forming a titanium film, single-layer structure of Cu-Mn alloy film, Cu film on Cu-Mn alloy film A two-layer structure in which a Cu film is laminated on a Cu-Mn alloy film, and a Cu-Mn film is laminated on top of that. In particular, Cu-Mn alloy films have low electrical resistance and Manganese oxide is formed at the interface with the insulating film containing oxygen, preventing Cu diffusion. preferable.

[0194] The conductive layer 530 may be made of indium tin oxide or indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide Add indium tin oxide, indium zinc oxide, and silicon oxide containing titanium oxide. A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the light-transmitting conductive material and the metal element may also be used.

[0195] <Gate insulating layer> The insulating layer 513 is formed of an insulating film having a single layer structure or a multilayer structure. Aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Contains one or more of tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. An insulating film can be used. The insulating layer 513 may be a stack of the above materials. The insulating layer 513 is doped with lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities. The insulating layer 511 may be formed in the same manner as the insulating layer 513. The insulating layer 513 contains, for example, oxygen, nitrogen, silicon, hafnium, etc. Preferably, the insulating layer includes hafnium oxide, and silicon oxide or silicon oxynitride.

[0196] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Since the thickness can be increased relative to silicon oxide, the leakage current due to tunnel current is reduced. That is, a transistor with low off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure has a higher melting point than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, It is preferable to use hafnium oxide having a crystalline structure. An example of the crystalline structure is monoclinic hafnium oxide. However, one embodiment of the present invention is not limited to these.

[0197] <Source electrode, drain electrode, backgate electrode> The conductive layers 541, 542, and 531 are prepared in the same manner as the conductive layer 530. The Cu-Mn alloy film has low electrical resistance and has no oxide matrix at the interface with the OS layer 520. Since the diffusion of Cu can be prevented by forming a junction, the conductive layer 541 and the conductive layer 542 can be formed. It is preferable that

[0198] <Protective insulating film> The insulating layer 514 is a blocking layer for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing such an insulating layer 514, the OS layer 52 Prevents the diffusion of oxygen from the outside and prevents hydrogen, water, etc. from entering the OS layer 520 from the outside. The insulating layer 514 may be, for example, a nitride insulating film. The nitride insulating film may be silicon nitride, silicon oxynitride, aluminum nitride, or silicon oxynitride. Aluminum, etc. In addition, oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of a nitride insulating film with a blocking effect, a material with a blocking effect against oxygen, hydrogen, water, etc. An oxide insulating film having an acid having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, and nitridium oxide. Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Nium, etc.

[0199] The aluminum oxide membrane is permeable to both impurities such as hydrogen and moisture, and oxygen. Therefore, aluminum oxide is preferable for use as the insulating layer 514 because it has a high blocking effect. The aluminum film improves the electrical characteristics of the transistor during and after the transistor manufacturing process. Preventing impurities such as hydrogen and moisture, which are factors that cause fluctuations in the properties, from entering the OS layer 520; Preventing the release of oxygen, which is the main component material constituting the oxide semiconductor, from the insulating layer 512 It is suitable for use as a protective film that has the effect of preventing unnecessary release of oxygen. Oxygen contained in the aluminum film can also be diffused into the oxide semiconductor.

[0200] <Interlayer insulating film> In addition, an insulating layer 515 is preferably formed over the insulating layer 514. The insulating film may be formed of a single-layer structure or a multi-layer structure. Nesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gas oxide Sodium oxide, Germanium oxide, Yttrium oxide, Zirconium oxide, Lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide can be used. do.

[0201] <<Film forming method>> Examples of methods for forming insulating films, conductive films, semiconductor films, and the like that constitute semiconductor devices include sputtering methods, The plasma CVD method is a typical example. It can also be formed by other methods, such as thermal CVD. As a thermal CVD method, for example, MOCVD (Metal Organic Chemical Vapor Deposition (ALD) and Atomic A layer deposition technique can be used.

[0202] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. The thermal CVD method has the advantage that the pressure in the chamber is not changed to atmospheric pressure or reduced pressure. The source gas and the oxidant are fed into the chamber at the same time and reacted near or on the substrate. Alternatively, the film may be formed by mixing the solution and depositing it on the substrate.

[0203] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching each switching valve (also called high-speed valve), two or more types of The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first single source gas. The second monoatomic layer is formed on the first monoatomic layer by reacting with the second source gas introduced later. A thin film is formed by stacking atomic layers. The order of gas introduction is controlled to obtain the desired thickness. By repeating this process several times until the thin film is completely removed, a thin film with excellent step coverage can be formed. The thickness can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing precise film thickness adjustment. This allows for fine tuning and is suitable for fabricating miniaturized FETs.

[0204] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. Conductive and semiconductive films can be formed. For example, InGaZnO X (X>0) Film deposition In this case, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula for trimethylindium is (CH3)3In. The chemical formula for gallium is (CH3)3Ga. The chemical formula for dimethylzinc is (CH 3) 2Zn. In addition, the combination is not limited to these, and trimethylgallium can be used instead. Triethylgallium (chemical formula (C2H5)3Ga) can also be used, and dimethylzinc Alternatively, diethylzinc (chemical formula (C2H5)2Zn) can be used.

[0205] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 Gas and H2 gas are introduced simultaneously to form a tungsten film. Note that instead of B2H6 gas, Alternatively, SiH4 gas may be used.

[0206] For example, an oxide semiconductor film, such as InGaZnO, can be formed by a film formation apparatus using ALD. X (X >0) film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly. After forming an InO2 layer, Ga(CH3)3 gas and O3 gas were introduced simultaneously to form GaO Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Mixed compounds such as O2 layers, InZnO2 layers, GaInO layers, ZnInO layers, and GaZnO layers A layer may be formed by bubbling an inert gas such as Ar instead of O3 gas. However, it is preferable to use O gas that does not contain H. Instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Ga(C2H5)3 gas may be used instead of Zn(CH3 )2 gas may also be used.

[0207] <<Example of semiconductor device configuration>> The device structure of a semiconductor device having an OS transistor will be described below. As described in the first embodiment, the p-type transistor included in the semiconductor device is a Si transistor. In this case, the n-type transistor can be an OS transistor. In one example, a semiconductor device is fabricated by stacking an OS transistor on a p-type transistor. With reference to Figs. 15 and 16, the above laminated structure can be realized. A configuration example of a semiconductor device will be described. Here, as an example of the semiconductor device, the semiconductor device shown in FIG. The device structure of the semiconductor device 102 will be described.

[0208] FIG. 15 is a plan view showing an example of the device structure of the semiconductor device 102, and FIG. For clarity of the drawing, FIG. 15 shows a circuit layout of the semiconductor device 102 in three dimensions. The figure is exploded into two plan views, with some of the components (insulating layers, plugs, etc.) omitted. FIG. 15C shows a plan view of the transistors Mp1 and Mp5, and FIG. The plan view of the wiring that supplies the power supply potential and the signal Fig. 16 shows a plan view of the input and output terminals of the signal. 1 is a cross-sectional view taken along a channel length direction of a transistor included in the semiconductor device 102. do.

[0209] In the example of FIG. 16, the semiconductor device 102 is formed on a single crystal silicon wafer 400 . The insulating layer 403 is a layer for isolating the transistors Mp1 and Mp5. Region 401 is an element region in which transistor Mp1 is formed, and region 402 is a This is the element region in which the transistor Mp5 is formed. 13. The OS transistor 502 has a device structure similar to that of the OS transistor 502 shown in FIG. It is possible to make it.

[0210] In FIG. 16, the insulating layers 404-410 are formed of insulating films having a single layer or a multilayer structure. This insulating film is made of aluminum oxide, aluminum nitride oxide, magnesium oxide, and oxide. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, acid The insulating material may be one or more selected from hafnium oxide, tantalum oxide, etc. In addition, the insulating film may be made of a material such as polyimide resin, polyamide resin, acrylic resin, or siloxane. An organic resin film such as resin, epoxy resin, or phenol resin can be used.

[0211] <Transistors Mp1 and Mp5> The semiconductor device 102 is formed on a single crystal silicon wafer 400. The insulating layer 403 is The region 401 is a layer for isolating the transistors Mp1 and Mp5. The region 402 is an element region in which the transistor Mp5 is formed. In the example of FIG. 16, the transistors Mp1 and Mp5 are formed in the plate Of course, the devices of the transistors Mp1 and Mp5 The structure is not limited to the example shown in FIG. 16. For example, a 3D transistor (fin type, Also, it is possible to use SOI type with a single crystal silicon layer. The transistors Mp1 and Mp5 may be fabricated from a semiconductor substrate.

[0212] The transistor Mp1 includes a conductive layer 411, a gate insulating layer 415, an impurity region 421, and an impurity The impurity regions include a region 422, an impurity region 425, and an impurity region 426. The element region 401 includes a channel region of the transistor Mp1. The impurity regions 421 and 422 function as a source region and a drain region. The object regions 425 and 426 are LDD (Lightly Doped Drain) regions and In this example, the impurity regions 421, 422, 425, and 42 The conductive layer 411 functions as the gate electrode of the transistor Mp1. An insulating layer 413 is formed on the side surface of the conductive layer 411. By this, impurity regions 421, 422, 425, and 426 are formed in the element region 401 in a self-aligned manner. It can be formed.

[0213] The transistor Mp5 includes a conductive layer 412, an insulating layer 414, a gate insulating layer 416, and an impurity region 423, impurity region 424, impurity region 427 and impurity region 428. The impurity region is formed in the element region 402 and has a p-type conductivity. The transistor Mp5 has a channel region similar to that of the transistor Mp1. The device has the following structure.

[0214] The transistors Mp1 and Mp5 are covered with an insulating layer 404. 405 is formed, and transistors Mos1, Mos3, and Mos5 are formed on an insulating layer 406. It has been done.

[0215] Hydrogen in the insulating layer 404 provided near the semiconductor film of the transistors Mp1 and Mp5 is converted into silicon. Terminates dangling bonds of capacitors and improves the reliability of transistors Mp1 and Mp5. On the other hand, this hydrogen has a detrimental effect on the oxide semiconductors of the transistors Mos1, Mos3, and Mos5. This causes carriers to be generated in the conductor film, and transistors Mos1, Mos3, and Mos5 Therefore, the transistors Mp1 and Mp5 and the transistor The insulating layer 405 between the transistors Mos1, Mos3, and Mos5 serves to prevent hydrogen diffusion. The insulating layer 405 confines hydrogen in the lower layer and prevents it from diffusing to the upper layer. By preventing this, the transistors Mp1, Mp5 and the transistors Mos1, Mos3, It can improve the reliability of Mos5.

[0216] The insulating layer 405 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used. 13, the insulating layer 406 has a function of supplying oxygen to the oxide semiconductor film. The insulating material may be used.

[0217] <Transistors Mos1, Mos3, Mos5> The transistors Mos1, Mos3, and Mos5 correspond to the OS transistor 502 shown in FIG. The device has a similar structure, and is an s-channel transistor with a three-layer OS layer. It is a ninja.

[0218] The insulating layer 407 constitutes the gate insulating layer of the transistors Mos1, Mos3, and Mos5. The transistors Mos1 and Mos3 share the OS layer 490 and the conductive layer 432 . The OS layer 490 has a three-layer structure including an OS layer 490a, an OS layer 490b, and an OS layer 490c. The conductive layer 431, the conductive layer 432, and the conductive layer 441 are the transistor Mo The conductive layer 432 serves as a source electrode, a drain electrode, and a gate electrode of the semiconductor substrate s1. The conductive layer 433 and the conductive layer 442 are the source electrode and drain electrode of the transistor Mos3, respectively. It functions as a drain electrode and a gate electrode.

[0219] The OS layer 491 of the transistor Mos5 includes an OS layer 491a, an OS layer 491b, and an OS layer 491c. The OS layer 490c is shared by the OS layer 490 and the OS layer 491. The conductive layer 434, the conductive layer 435, and the conductive layer 443 are the transistor M It functions as a source electrode, a drain electrode, and a gate electrode of os5.

[0220] <Wiring, electrode> An insulating layer 408 is formed covering the transistors Mos1, Mos3, and Mos5. An insulating layer 409 is formed to cover the edge layer 408. On the insulating layer, a wiring 451, a wiring 452, and a 52, electrodes 453-457 are formed. Wiring 451 is a power line for a high power supply potential VDD. The wiring 452 is a power supply line for the high power supply potential VSS.

[0221] The source (impurity region 421) of the transistor Mp1 is formed by a plug 471 and a plug 479. The source of the transistor Mp5 (impurity region 424) is electrically connected to wiring 451 by plug 474 and plug 483. The transistor Mos1 is electrically connected to the wiring 452 by a plug 478. The resistor Mos5 is electrically connected to the wiring 452 by a plug 482.

[0222] The gate electrode (conductive layer 441) of the transistor Mos1 and the gate electrode (conductive layer 442) of the transistor Mp1 The electrodes (conductive layers 411) are electrically connected to the electrodes 455 by plugs (not shown). The gate electrode (conductive layer 442) of the transistor Mos3 is connected to the The drain electrode (conductive layer 432) is electrically connected to the electrode 456 via a plug 479. The gate electrode (conductive The gate electrode (conductive layer 412) of the transistor Mp5 are not shown. It is electrically connected to the electrode 454 via a plug.

[0223] The drain (impurity region 422) of the transistor Mp1 and the source (impurity region 423) of the transistor Mos3 The source electrode (conductive layer 433) is electrically connected by plug 472 and plug 475. The source electrode (conductive layer 435) of the transistor Mos5 and the drain electrode (conductive layer 435) of the transistor Mp5 The impurity region 423 is electrically connected to the plug 473 and the plug 477. The conductive layer 435 is electrically connected to the electrode 457 via a plug 481.

[0224] An insulating layer 410 is formed to cover the wiring 451, the wiring 452, and the electrodes 454-457. Electrodes 461-463 are formed on an insulating layer 410. The electrode 461 is connected to the semiconductor device 102. Electrode 462 serves as an output terminal. Electrode 463 serves as an input terminal for a signal S It functions as an input terminal for LP. Electrode 461 is electrically connected to electrode 455 via a plug (not shown). The electrode 462 is electrically connected to the electrode 457 by a plug 484. The electrode 463 is electrically connected to the electrode 456 via a plug (not shown).

[0225] The wiring 452, the electrodes 454-457, the electrodes 461-463, and the plugs such as the plug 470 The tag can be made of a single or multi-layer conductive layer. The conductive layer can be copper ( Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al) , Manganese (Mn), Titanium (Ti), Tantalum (Ta), Nickel (Ni), Chromium ( Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru) , iridium (Ir), strontium (Sr), platinum (Pt) or It is preferable that the material is an alloy or a compound containing the alloy as a main component. It is preferable to use a high melting point material such as tungsten or molybdenum that is also electrically conductive. It is also preferable to form the capacitor from a low resistance conductive material such as aluminum or copper. When a u-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide The gun is preferable because it has the function of suppressing the diffusion of Cu.

[0226] (Embodiment 3) The logic circuits (logic cells) and clock trees described in the first embodiment can be incorporated into various integrated circuits. Here, a central processing unit (CPU) is used as an example of such an integrated circuit. This article explains CPU.

[0227] FIG. 17 is a block diagram showing an example of a CPU. The CPU 300 shown in FIG. The semiconductor memory device includes a semiconductor memory 301, a peripheral circuit 302, and a power management unit 303. The power management unit 303 includes a power supply control unit 331 and a clock control unit 332. The peripheral circuit 302 includes an instruction cache control unit 321, an instruction cache 323, data cache control unit 322, data cache 324, The CPU core 301 has a control unit 311, a feed The register file 313 includes a register and decode unit 312, an execution unit 314, and a register file 313. Yes.

[0228] The semiconductor device according to the first embodiment can be applied to a logic circuit included in the CPU 300. Therefore, the power supply control unit 331, the clock control unit 332, the instruction cache cache control unit 321, instruction cache 323, data cache control unit 322 , data cache 324, bus interface 325, control unit 311, The switch and decode unit 312, the execution unit 314, and / or the register file In addition, the clock tree for transferring the clock signal can be applied to the clock tree 313. This provides a compact, low-power CPU 300. It is possible to reduce the power consumption of electronic devices incorporating the CPU 300 as an electronic component. Therefore, the CPU 300 is suitable for, for example, battery-powered electrical devices.

[0229] The fetch and decode unit 312 retrieves instructions from the main memory and the instruction cache 323. The control unit 311 has a function of fetching instructions and decoding the instructions. Based on the received instructions, the fetch and decode unit 312, the execution unit 314, The timing of data transfer between the register file 313 and the outside of the CPU core 301 The execution unit 314 has a function of controlling the ALU (Arithmetic Logical Unit). It has a digital unit, a shifter, a multiplier, etc. It can perform various operations such as arithmetic operations and logical operations. It has the function of performing calculations.

[0230] The register file 313 has a plurality of registers including a general-purpose register. Data read from memory or data cache 324, or data output by execution unit 314 The instruction cache 323 temporarily stores frequently used instructions. The data cache 324 temporarily stores frequently used data. The instruction cache control unit 321 has a function of storing the instruction The data cache control unit 322 controls the operation of the data cache 3. It controls the operation of 24.

[0231] The bus interface 325 is connected to an external bus (External BUS) and It functions as a data path between the PU 300 and various devices external to the CPU 300. Possesses the ability.

[0232] The power management unit 303 controls the power of the CPU 300. The control unit 331 receives control signals from the CPU core 301 and interrupts from outside the CPU 300. An interrupt signal, etc. is input, and a signal for power control (P For example, the CPU300 outputs multiple Each power domain has a power switch between the power supply and the power supply. In such a case, the power control unit 331 controls the operation of the power switch. For example, if a voltage regulator is provided, The power supply control unit 331 may have a function of controlling a voltage regulator. The regulator may be provided inside the CPU 300 or outside the CPU 300. Alternatively, only a portion of the voltage regulator (e.g., the inductor coil) may be may be provided outside the CPU 300.

[0233] The clock control unit 332 receives control signals from the CPU core 301 and from outside the CPU 300. The clock signal, interrupt signal, etc. are input from For example, the CPU 300 outputs an internal clock. Coarse-grained clock control for each large block such as the CPU core 301 and the peripheral circuit 302 A configuration that performs clock gating at a fine grain may be used, or a configuration that uses fewer flip-flops may be used. This is a configuration that performs fine-grained clock gating to control the clock for each small block. When fine-grained clock gating is performed, the clock tree of the first embodiment is applied. By using this, it is possible to reduce power consumption in the clock tree during clock gating. In addition, the clock tree can store the state, allowing immediate return to normal operation mode. It is possible to do so.

[0234] The CPU 300 having the above configuration is capable of performing power gating. The flow of the gating operation will be described with an example.

[0235] Power gating is a process that reduces the power consumption of CPU 300 during periods when CPU 300 is not processing. This is a technology that stops the supply of power voltage to one or more of the various circuits in the 00. This technology reduces power consumption by reducing the DC power consumed when supplying power voltage. In power gating, when the power is turned off, the necessary data in the CPU 300 is When the power is turned on, the saved data is restored and the Resume execution of instructions.

[0236] First, the CPU core 301 sets a value in a register in the power supply control unit 331 in advance. The power gating mode is set by specifying the power gating mode. Power gating starts when For example, the process starts with an instruction to the CPU core 301. The CPU core 301 decodes the instruction. After the download, a control signal to turn off the power is sent to the power supply control unit 331. The power supply control unit 331 controls the registers and register file 3 included in the CPU 300. 13, data stored in the instruction cache 323, data cache 324, etc., or Then, the power supply control unit 331 controls the operation of the power switch. By this, the power supply voltage is supplied to one or more of the various circuits included in the CPU 300. On the other hand, the interrupt signal is input to the power management unit 303. Then, the supply of the power supply voltage to the circuit is started. The timing at which the supply of power voltage begins is determined by the relevant Next, the CPU 300 restores the saved data. Then, execution of instructions in the CPU core 301 is resumed.

[0237] The registers can be state retention registers. The data stored in the register is not saved to the outside of the CPU 300, but is stored in the status bar of the register. Data can be saved to the state retention section. The state retention unit may be configured not to stop supplying the power supply voltage during the off state. The circuit has an oxide semiconductor transistor and a capacitor, and can store data for a long period of time without power supply. A memory circuit capable of storing the register may be used. This saves power and time compared to saving data stored in a register to memory other than the register. can be reduced.

[0238] The register file 313, the instruction cache 323, and / or the data cache 32 4 is a memory cell including an oxide semiconductor transistor as exemplified in the above embodiment. For example, when a back-up SRAM cell is provided, the register file may be The cache 313, the instruction cache 323, and / or the data cache 324 may store The stored data can be saved in a backup memory circuit. The stack file 313, the instruction cache 323, and / or the data cache 324 A mode in which a power supply voltage low enough to retain data is supplied (called low power supply voltage mode). When power gating is performed, the register file 313, the instruction key The supply of power supply voltage to the data cache 323 and / or the data cache 324 is stopped. Instead, by switching to a low power supply voltage mode, power consumption can be reduced. By configuring in this way, the register file 313, the instruction cache 323, and / or Or, when the data stored in the data cache 324 is to be evacuated to the outside of the CPU 300, In comparison with the above, power and time can be reduced. The data stored in the instruction cache 323 and / or the data cache 324 is purged. After power-on, data and instructions are retrieved from memory outside the CPU 300 as necessary. This can reduce power and / or time compared to the case where a conventional method is used.

[0239] Here, a CPU has been described as an example of a processing unit. The embodiments can be applied to various processing units, e.g., RFID tags. , GPU (Graphics Processing Unit), PLD (Progr. ammable Logic Device), DSP(Digital Signal Processor), MCU (Microcontroller Unit), It can also be applied to Tam LSIs.

[0240] (Embodiment 4) In this embodiment, an electronic component and an electronic device including the electronic component are used as an example of a semiconductor device. The following describes the equipment, etc.

[0241] <Examples of how to manufacture electronic components> FIG. 18A is a flowchart showing an example of a method for manufacturing an electronic component. This electronic component is also called a package or IC package. There are multiple standards and names for each type of connector depending on its shape. I will explain about this.

[0242] Semiconductor devices made up of transistors are assembled into printed circuit boards through a post-assembly process. The assembly is completed by assembling several detachable parts. Specifically, the element substrate obtained in the previous process is After the substrate is formed (step S1), the back surface of the substrate is ground (step S2). By making the film thinner, it is possible to reduce warping of the board during pre-processing and to make the component smaller.

[0243] A dicing process is performed in which the back surface of the substrate is ground and the substrate is separated into a plurality of chips. The separated chips are individually picked up and mounted on a lead frame for bonding. In this die bonding process, the chip and the lead are The adhesive to the frame is made by resin adhesive, tape adhesive, etc., depending on the product. The die bonding process is performed by mounting the chip on an interposer and bonding it. Good too.

[0244] Next, the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. Wire bonding is performed to connect the wires to the board (step S4). Wire bonding can be used. Wire bonding can be used in combination with ball bonding and wafer bonding. Edge bonding can be used.

[0245] The wire-bonded chip is then sealed with epoxy resin or other materials in a molding process. (Step S5). The inside of the electronic component is filled with resin by the molding process. It is possible to reduce damage to the built-in circuitry and wires caused by external mechanical forces. It is also possible to reduce deterioration of characteristics due to moisture and dust.

[0246] The leads of the lead frame are then plated, and the leads are then cut and shaped. (Step S6). This plating process prevents the leads from rusting and allows them to be mounted on a printed circuit board later. This allows soldering to be performed more reliably.

[0247] Next, the surface of the package is printed (marked) (step S7). After passing through a general inspection process (step S8), the electronic components are completed (step S9).

[0248] The electronic components described above include the semiconductor devices described in the above embodiments. This makes it possible to realize electronic components that consume less power and are more compact. can.

[0249] <Example of electronic component configuration> A perspective schematic diagram of the completed electronic component is shown in FIG. 18B. In FIG. 18B, FIG. 18B shows a schematic perspective view of a QFP (Quad Flat Package). As shown in FIG. 7, the electronic component 700 includes leads 701 and a circuit section 703. The electronic component 700 is mounted on, for example, a printed circuit board 702. The components are combined and electrically connected on a printed circuit board 702 to form an electronic device. The completed circuit board 704 can be installed inside an electronic device, etc. For example, electronic component 700 may include a random access memory for storing data; A processor that performs various processes such as MCU (microcontroller unit) and RFID tags. It can be used as a processing unit.

[0250] Thus, the electronic component 700 can be used in a wide range of applications including digital signal processing, software radio, avionics (communications (Electrical equipment related to aviation, such as aircraft navigation systems, autopilots, and flight management systems) SIC prototyping, medical image processing, speech recognition, cryptography, bioinformatics (bioinformatics), emulators of mechanical devices, and radio telescopes in radio astronomy This technology can be applied to electronic components (IC chips) in a wide range of electronic devices. Such electronic devices include display devices, personal computers (PCs), and devices equipped with recording media. Image playback devices (typically DVD: Digital Versatile Disc, etc.) It can be used in a device having a display that can play back a recording medium and display the image. Other examples of electronic devices in which the semiconductor device according to one embodiment of the present invention can be used include Mobile phones, portable game consoles, portable data terminals, e-book terminals, cameras (video cameras) cameras, digital still cameras, etc.), wearable display devices or terminals (head-mounted type, goggle type, eyeglass type, armband type, bracelet type, necklace type, etc.), navigation Systems, audio playback devices (car audio, digital audio players, etc.), copiers , fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of such electronic devices are shown in Figure 19.

[0251] <Examples of electronic device configurations> 19A to 19F show examples of the configuration of a battery-powered electronic device having a display unit. The portable game machine 900 shown in FIG. 19A includes a housing 901, a housing 902, a display 903, a display unit 904, a microphone 905, a speaker 906, an operation key 907, etc. The display unit 903 is provided with a touch screen as an input device, and a stylus It can be operated using a device such as the 908.

[0252] An information terminal 910 shown in FIG. 19B includes a housing 911, a display unit 912, a microphone 917, a speaker, and the like. The device includes a touch panel 914, a camera 913, an external connection section 916, and an operation button 915. The display unit 912 is equipped with a display panel and a touch screen using a flexible substrate. The information terminal 910 may be, for example, a smartphone, a mobile phone, a tablet information terminal, It can be used as a tablet PC, e-book reader, etc.

[0253] The notebook PC 920 shown in FIG. 19C includes a housing 921, a display unit 922, a keyboard 923, and a pointing device 924.

[0254] The video camera 940 shown in FIG. 19D includes a housing 941, a housing 942, a display unit 943, and an operation key. The operation keys 944 and the lens 945 are connected to each other. The display unit 945 is provided in the housing 941, and the display unit 943 is provided in the housing 942. The body 941 and the housing 942 are connected by a connection portion 946. The angle between the housing 941 and the connecting portion 946 can be changed. Depending on the angle of the housing 942, the direction of the image displayed on the display unit 943 can be changed, and the image can be displayed in a different direction. You can toggle the display on and off.

[0255] An example of a bangle-type information terminal is shown in FIG. 19E. The information terminal 950 includes a housing 951 and The display unit 952 and the like are provided. The display unit 952 is supported by a housing 951 having a curved surface. The display unit 952 is equipped with a display panel using a flexible substrate, and therefore is flexible. Moreover, it is possible to provide an information terminal 950 that is light and easy to use.

[0256] FIG. 19F shows an example of a wristwatch-type information terminal. The information terminal 960 includes a housing 961, a display unit 9 62, a band 963, a buckle 964, an operation button 965, an input / output terminal 966, etc. The information terminal 960 can be used for mobile phone calls, e-mail, document viewing and creation, music playback, and internet. It can run various applications such as internet communication and computer games. .

[0257] The display surface of the display unit 962 is curved, and display can be performed along the curved display surface. The display unit 962 is also equipped with a touch sensor, and when you touch the screen with a finger or a stylus, For example, the user can touch the icon 967 displayed on the display unit 962. The operation button 965 can be used to set the time, Power on / off operation, wireless communication on / off operation, silent mode activation / deactivation, power saving For example, the information terminal 9 can have various functions such as enabling and disabling the power mode. The operating system built into the 60 allows the user to set the functions of the operation button 965. It is also possible.

[0258] Furthermore, the information terminal 960 is capable of performing standardized short-range wireless communication. For example, by communicating with a wireless headset, you can talk hands-free. The information terminal 960 also includes an input / output terminal 966, and can be connected to other information terminals. Data can be exchanged directly through the input / output terminal 966. The charging operation can be performed by wireless power supply without going through the input / output terminal 966. It is also acceptable to

[0259] FIG. 19G shows an electric refrigerator-freezer as an example of a household electrical appliance. The electric refrigerator-freezer 970 is The refrigerator has a housing 971, a door for a refrigerator compartment 972, and a door for a freezer compartment 973, etc.

[0260] FIG. 19H is an external view showing an example of the configuration of an automobile. The automobile 980 includes a body 981, It has a wheel 982, a dashboard 983, and lights 984, etc.

[0261] The electronic device shown in this embodiment includes an electronic component having the semiconductor device according to the above embodiment. Therefore, it is possible to provide an electronic device that consumes less power and is compact. It will be possible to do this. [Explanation of symbols]

[0262] 21-24 Circuit 101-108 Semiconductor devices 120-122 Clock Tree 150-153 Power switch 160-165 Wiring

Claims

[Claim 1] An output node; First and second nodes; First to third transistors, a function of performing arithmetic processing on one or a plurality of first signals and outputting a second signal from the output node; A first power supply potential is input to the first node, a second power supply potential is input to the second node; the first power supply potential is higher than the second power supply potential, the first transistor is a p-type transistor; the second and third transistors are n-type transistors; the semiconductor regions of the second and third transistors include an oxide semiconductor; the first transistor, the third transistor, and the second transistor are electrically connected in series in this order; the source of the first transistor is electrically connected to the first node; the drain of the second transistor is electrically connected to the output node; the source of the second transistor is electrically connected to the second node; the potentials of the gates of the first and second transistors are controlled by the one or more first signals; A third signal is input to the gate of the third transistor.

Images