Semiconductor device

Abstract

To provide a semiconductor device which can reduce a chip area by increasing the mounting efficiency of an output element on a main surface.SOLUTION: A semiconductor device 1 includes: a semiconductor chip 2; an output region 6 which is formed on a first main surface 3, and in which an output transistor 20 is disposed; an inner element region 8 which is surrounded by the output region 6, and in which a temperature sensor element 9 is disposed; a first wiring layer 12, including first source wiring 98A, which is formed on the first main surface 3 so as to cover the output region 6; and a second wiring layer 13, formed on the first wiring layer 12, and including second source wiring 98B and pieces of connection wiring 10A, 10B extending from the inner element region 8 to a control region 7 outside the output region 6, while traversing the output region 6. The output transistor 20 has a trench gate structure 70 which is disposed under the pieces of connection wiring 10A, 10B and overlaps the pieces of connection wiring 10A, 10B in a thickness direction Z of the semiconductor chip 2.SELECTED DRAWING: Figure 19A

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor chip having a main surface, an output region in which an output element is arranged, and a temperature sensitive diode structure arranged within the output region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-167338 A

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device that increases the packaging efficiency of output elements in an output region, thereby enabling a reduction in chip area.

[0005] An embodiment of the present disclosure provides a semiconductor device including: a semiconductor chip having a main surface; an output region formed on the main surface and in which an output element is arranged; an inner element region surrounded by the output region and insulated from the output region, in which a first element different from the output element is arranged; a first wiring layer formed on the main surface so as to cover the output region and including a first output wiring electrically connected to the output element; a second wiring layer formed on the first wiring layer, the second wiring layer including a second output wiring electrically connected to the first output wiring and a connection wiring insulated from the second output wiring and extending from the inner element region to an outer region outside the output region across the output region. The output element is arranged below the connection wiring and has a trench electrode structure overlapping the connection wiring in a thickness direction of the semiconductor chip. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. [Diagram 3] FIG. 3 is a plan view showing an example of a layout within the semiconductor chip shown in FIG. [Figure 4] FIG. 4 is a schematic circuit diagram showing the electrical configuration of the semiconductor device. [Diagram 5] FIG. 5 is a schematic circuit diagram showing a configuration of the output transistor shown in FIG. [Figure 6] FIG. 6 is a plan view showing the output region and the inner element region shown in FIG. [Figure 7] FIG. 7 is an enlarged view of region VII shown in FIG. [Figure 8] FIG. 8 is a further enlarged view of the region VII. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along the line XII-XII shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is a plan view showing the inner element region, and is an enlarged view of region XIV shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19A]FIG. 19A is a cross-sectional view taken along line XIXA-XIXA shown in FIG. [Figure 19B] FIG. 19B is a cross-sectional view taken along line XIXB-XIXB shown in FIG. [Figure 20] FIG. 20 is a plan view showing an example of a layout in a semiconductor chip shown in the reference embodiment. [Figure 21] FIG. 21 is a plan view showing the output region and the inner element region of the semiconductor device according to the second embodiment, and corresponds to FIG. [Figure 22] FIG. 22 is a plan view showing the inner element region, and is an enlarged view of region XXII shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. [Diagram 25] FIG. 25 is a cross-sectional view taken along the line XXV-XXV shown in FIG. [Figure 26A] FIG. 26A is a plan view showing an output region and an inner element region of a semiconductor device according to a third embodiment, and corresponds to FIG. [Figure 26B] FIG. 26B is a cross-sectional view taken along line XXVIB-XXVIB shown in FIG. 26A. [Figure 27] FIG. 27 is a plan view showing a first modified example of the connection wiring according to the second embodiment, and corresponds to FIG. [Figure 28] FIG. 28 is a cross-sectional view showing a second modification of the planar structure of the semiconductor device according to the first embodiment, and corresponds to FIG.

[0007] [Detailed Description] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. In addition, the same reference numerals are given to corresponding structures among the accompanying drawings, and duplicated descriptions are omitted or simplified.

[0008] Fig. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example of a layout within a semiconductor chip 2 shown in Fig. 1.

[0009] 1 to 3, the semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape. In this embodiment, the semiconductor chip 2 is a Si chip including a single crystal of Si. The semiconductor chip 2 may be a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). For example, the semiconductor chip 2 may be a SiC chip including a single crystal of SiC.

[0010] 2, the semiconductor chip 2 has a first main surface (principal surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from a normal direction Z thereto (hereinafter simply referred to as a "plan view"). The normal direction Z is also the thickness direction of the semiconductor chip 2.

[0011] The first main surface 3 is a circuit surface on which various circuit structures constituting an electronic circuit are formed. The second main surface 4 is a non-circuit surface that does not have any circuit structures. The first side surface 5A and the second side surface 5B extend in a second direction Y that intersects (specifically, is perpendicular to) the first direction X along the first main surface 3, and face (back to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the first direction X and face (back to) the second direction Y.

[0012] Referring to FIG. 3, the semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output region 6 is a region having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. In the output region 6, an output transistor 20 (see FIG. 6) is formed in substantially the entire region except for the inner peripheral portion and the outer peripheral portion. In this embodiment, the output region 6 is partitioned into a region on the first side surface 5A side on the first main surface 3. The output region 6 has four sides parallel to the periphery of the first main surface 3 in a plan view. The output region 6 is an annular (endless) region in a plan view. In this embodiment, the output region 6 is a substantially quadrangular annular region.

[0013] The position, size, planar shape, etc. of the output area 6 are arbitrary and are not limited to a specific layout. The output area 6 may have a planar area of ​​25% or more and 80% or less of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 30% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 40% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 50% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 75% or less of the planar area of ​​the first main surface 3.

[0014] 3, the semiconductor device 1 includes a control region 7 provided in a region different from the output region 6 on the first main surface 3. The control region 7 is an example of an outer region located outside the output region 6. The control region 7 is a region having a plurality of types of electronic circuits (circuit devices) configured to generate control signals for controlling the output region 6. In this embodiment, the control region 7 is defined in a region on the second side surface 5B side with respect to the output region 6, and faces the output region 6 in the first direction X. In this embodiment, the control region 7 is defined in a substantially rectangular shape having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0015] The position, size, planar shape, etc. of the control area 7 are arbitrary and are not limited to a specific layout. The planar area of ​​the control area 7 may be approximately equal to the planar area of ​​the output area 6. The planar area of ​​the control area 7 may be larger than the planar area of ​​the output area 6. The planar area of ​​the control area 7 may be smaller than the planar area of ​​the output area 6. The ratio of the planar area of ​​the control area 7 to the planar area of ​​the output area 6 may be 0.1 or more and 4 or less.

[0016] 3, the semiconductor device 1 includes an inner element region 8 surrounded by an output region 6 on the first main surface 3. The inner element region 8 is disposed in the center of the output region 6. The inner element region 8 is a region that is insulated and isolated from the output region 6. No unit transistors 22 (see FIG. 6) are formed in the inner element region 8.

[0017] The inner element region 8 is adjacent to the output region 6 in four directions in a plan view. In this embodiment, the inner element region 8 has a planar area smaller than the planar area of ​​the output region 6. The ratio of the planar area of ​​the inner element region 8 to the planar area of ​​the output region 6 may be 0.001 or more and 0.5 or less. The ratio of the planar area of ​​the inner element region 8 to the planar area of ​​the output region 6 may be 0.01 or more and 0.1 or less.

[0018] In this embodiment, the inner element region 8 is a region for arranging a temperature sensor element 9 as an example of a first element. The inner element region 8 is formed at a position corresponding to the center of the output region 6. Therefore, the temperature sensor element 9 arranged in the inner element region 8 is arranged at a position corresponding to the center of the output region 6. The temperature sensor element 9 is arranged adjacent to the output region 6. The temperature sensor element 9 detects the temperature of the output region 6.

[0019] 3, the output region 6 surrounds the entire periphery of the inner element region 8. The output region 6 is a quadrangular ring-shaped (endless) region. In other words, the output region 6 surrounds the inner element region 8 so as to separate it from the control region 7.

[0020] 2, the semiconductor device 1 includes an interlayer insulating layer 11 covering the first main surface 3. The interlayer insulating layer 11 collectively covers the output region 6, the control region 7, and the inner element region 8. In this embodiment, the interlayer insulating layer 11 has a stacked wiring structure having a stacked structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked. Each insulating layer includes at least one of a SiO2 film and a SiN film.

[0021] The interlayer insulating layer 11 includes a first wiring layer 12 disposed anywhere above the first main surface 3 via an insulating layer, and a second wiring layer 13 disposed above the first wiring layer 12 via an insulating layer. The first wiring layer 12 and the second wiring layer 13 each include a plurality of output wirings. The plurality of wirings included in the first wiring layer 12 all have the same height from the first main surface 3. The plurality of wirings included in the second wiring layer 13 all have the same height from the first main surface 3. The heights from the first main surface 3 of the first wiring layer 12 and the second wiring layer 13 are different from each other.

[0022] The multiple wirings included in the first wiring layer 12 and the second wiring layer 13 include gate wirings 16 .

[0023] The semiconductor device 1 includes n gate wirings 16. The n gate wirings 16 are electrically connected to n main gates of the output transistors 20 and a control circuit 23, which will be described later. Specifically, the n gate wirings 16 are electrically connected to the n main gates (n system gates) of the output transistors 20 in a one-to-one correspondence while being electrically independent from one another. As a result, the n gate wirings 16 individually transmit the n gate signals generated by the control circuit 23 to the n main gates of the output transistors 20. In other words, the n gate wirings 16 are electrically connected to the unit gates of one or more unit transistors 22 to be systematized as an individual control target from among a set of multiple unit transistors 22. The n gate wirings 16 may include one or more gate wirings 16 electrically connected to one unit transistor 22 to be systematized as an individual control target. The n gate wirings 16 may also include one or more gate wirings 16 that connect in parallel multiple unit transistors 22 to be systematized as an individual control target.

[0024] 3, a connection wiring 10 is connected to the temperature sensor element 9. The connection wiring 10 is one or more wires. The connection wiring 10 crosses the output region 6 and extends from the inner element region 8 to the control region 7 outside the output region 6. The connection wiring 10 connects the temperature sensor element 9 to the control circuit 23 of the control region 7. A first temperature detection signal from the temperature sensor element 9 is provided to an overheat protection circuit 27 of the control circuit 23 via the connection wiring 10. As will be described later, the connection wiring 10 is included in the second wiring layer 13.

[0025] 1 and 2, the semiconductor device 1 includes a plurality of terminals 17-19. In Fig. 1, the plurality of terminals 17-19 are indicated by hatching. The number, arrangement and planar shape of the plurality of terminals 17-19 may be adjusted to any form according to the specifications of the output transistor 20 and the specifications of the control circuit 23, and are not limited to the form shown in Fig. 1 and 2. In this form, the plurality of terminals 17-19 include a source terminal 17, a plurality of control terminals 18 and a drain terminal 19.

[0026] In this embodiment, the source terminal 17 is provided as an output terminal electrically connected to a load, and is disposed on a portion of the interlayer insulating layer 11 that covers the output region 6. The source terminal 17 may cover the entire output region 6 in a plan view. The source terminal 17 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0027] The multiple control terminals 18 are terminals electrically connected to various electronic circuits in the control region 7, and are arranged on a portion of the interlayer insulating layer 11 that covers the control region 7. The multiple control terminals 18 each have a planar area less than the planar area of ​​the source terminal 17, and are arranged at intervals along the periphery of the control region 7 (the periphery of the first main surface 3).

[0028] FIG. 4 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in FIG. 1. FIG. 5 is a schematic circuit diagram showing the configuration of the output transistor 20. In FIG. 4, in order to show an example of the operation of the semiconductor device 1, an example is shown in which an inductive load L as an example of a load is electrically connected to the source terminal 17. The inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be called an "inductive load driving device" or an "inductive load control device". Examples of the inductive load L include a relay, a solenoid, a lamp, a motor, and the like. The inductive load L may be an inductive load for an automobile. That is, the semiconductor device 1 may be an inductive load for an automobile.

[0029] 3 and 4, the semiconductor device 1 includes an output transistor 20 formed in the output region 6. In this embodiment, the output transistor 20 is a gate split transistor including one main drain, one main source, and a plurality of main gates. The main drain is electrically connected to the drain terminal 19 (see FIG. 2). The main source is electrically connected to the source terminal 17 (see FIG. 2).

[0030] 4, the multiple main gates of the output transistor 20 are configured to receive multiple electrically independent gate signals (gate potentials) individually. The output transistor 20 generates a single output current Io (output signal) in response to the multiple gate signals. In other words, the output transistor 20 is a multiple-input single-output switching device. The output current Io is a drain-source current that flows between the main drain and the main source. The output current Io is output to the outside of the semiconductor chip 2 (to an inductive load L) via the source terminal 17.

[0031] 4, the output transistor 20 includes a plurality of (two or more) system transistors 21 that are electrically controlled independently. In this embodiment, the plurality of system transistors 21 includes a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are formed in a concentrated manner in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are inputted individually, and are configured so that the system transistors 21 in the on state and the system transistors 21 in the off state coexist.

[0032] Each of the system transistors 21 includes a system drain, a system source, and a system gate. The system drains are electrically connected to a main drain (drain terminal 19). The system sources are electrically connected to a main source (source terminal 17). Each system gate is electrically connected to each main gate. In other words, each system gate constitutes each main gate.

[0033] The multiple system transistors 21 each generate a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between the system drain and the system source of each system transistor 21. The multiple system currents Is may have different values ​​or may have approximately equal values. The multiple system currents Is are added between the main drain and the main source. As a result, a single output current Io consisting of the added value of the multiple system currents Is is generated.

[0034] 5, the multiple system transistors 21 each include a single or multiple unit transistors 22 organized (grouped) as individual control targets. Specifically, the multiple system transistors 21 are formed of a single unit transistor 22 or a parallel circuit including multiple unit transistors 22. In this embodiment, each of the multiple unit transistors 22 is of a trench gate vertical type. The multiple system transistors 21 may be composed of the same number of unit transistors 22, or may be composed of different numbers of unit transistors 22.

[0035] 5, each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

[0036] 5, the multiple unit transistors 22 each generate a unit current Iu in response to a corresponding gate signal. Each unit current Iu is a drain-source current flowing between the unit drain and unit source of each unit transistor 22. The multiple unit currents Iu may have different values ​​or may have approximately equal values. The multiple unit currents Iu are added between the corresponding system drains and system sources. As a result, a system current Is consisting of the sum of the multiple unit currents Iu is generated.

[0037] In this way, the output transistor 20 is configured so that the first system transistor 21A and the second system transistor 21B are controlled to be on and off in a state where they are electrically independent of each other. That is, the output transistor 20 is configured so that both the first system transistor 21A and the second system transistor 21B are simultaneously in an on state. Also, the output transistor 20 is configured so that either the first system transistor 21A or the second system transistor 21B is in an on state and the other is in an off state.

[0038] 5, when both the first system transistor 21A and the second system transistor 21B are simultaneously turned on, the channel utilization rate of the output transistor 20 increases and the on-resistance decreases. When either the first system transistor 21A or the second system transistor 21B is turned on while the other is turned off, the channel utilization rate of the output transistor 20 decreases and the on-resistance increases. That is, the output transistor 20 is composed of an on-resistance variable switching device.

[0039] 3 and 4, the semiconductor device 1 includes a control circuit 23 formed in the control region 7 so as to be electrically connected to the output transistor 20. The control circuit 23 may be referred to as a "control IC." The control circuit 23 includes various functional circuits, and configures an IPD (Intelligent Power Device) together with the output transistor 20. The IPD may be referred to as an "IPM (Intelligent Power Module)," an "IPS (Intelligent Power Switch)," a "smart power driver," a "smart MISFET (smart MOSFET)," or a "protected MISFET (protected MOSFET)."

[0040] 3 and 4, in this embodiment, control circuit 23 includes a gate control circuit 24, a current monitor circuit 25, an overcurrent protection circuit 26, an overheat protection circuit 27, an undervoltage malfunction avoidance circuit 28, an open load detection circuit 29, an active clamp circuit 30, and a logic circuit 32. Control circuit 23 does not necessarily need to include all of these functional circuits at the same time, and it is sufficient if it includes at least one of these functional circuits.

[0041] The current monitor circuit 25 may be called a CS circuit (Current Sense circuit). The overcurrent protection circuit 26 may be called an OCP circuit (Over Current Protection circuit). The overheat protection circuit 27 may be called a TSD circuit (Thermal shut down circuit). The low voltage malfunction avoidance circuit 28 may be called a UVLO circuit (Under Voltage Lock Out circuit). The open load detection circuit 29 may be called an OLD circuit (Open Load Detection circuit).

[0042] The gate control circuit 24 is configured to generate gate signals that control the on / off of the output transistors 20. Specifically, the gate control circuit 24 generates a plurality of gate signals that individually control the on / off of the plurality of system transistors 21. That is, in this embodiment, the gate control circuit 24 generates a first gate signal that individually controls the on / off of the first system transistors 21A, and a second gate signal that individually controls the on / off of the second system transistors 21B electrically independent of the first system transistors 21A.

[0043] The current monitor circuit 25 generates a monitor current that monitors the output current Io (see FIG. 4) of the output transistor 20, and outputs the monitor current to another circuit. For example, the monitor circuit may include a transistor having a similar configuration to the output transistor 20, and be configured to generate a monitor current linked to the output current Io by being on / off controlled simultaneously with the output transistor 20. Of course, the current monitor circuit 25 may also be configured to generate a monitor current linked to one or more system currents Is.

[0044] The overcurrent protection circuit 26 generates an electric signal for controlling the gate control circuit 24 based on the monitor current from the current monitor circuit 25, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20. For example, the overcurrent protection circuit 26 may be configured to determine that the output transistor 20 is in an overcurrent state when the monitor current is equal to or greater than a predetermined threshold, and to control some or all of the output transistor 20 (the multiple system transistors 21) to an off state in cooperation with the gate control circuit 24. The overcurrent protection circuit 26 may also be configured to cooperate with the gate control circuit 24 to shift the output transistor 20 to a normal operation when the monitor current is less than a predetermined threshold.

[0045] As described above, the overheat protection circuit 27 is provided with a first temperature detection signal from the temperature sensor element 9 that detects the temperature of the output region 6. The overheat protection circuit 27 also includes a temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the control region 7. The overheat protection circuit 27 generates an electric signal that controls the gate control circuit 24 based on the first temperature detection signal from the temperature sensor element 9 and the second temperature detection signal from the temperature sensing device, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20.

[0046] For example, the overheat protection circuit 27 may be configured to determine that the output region 6 is in an overheated state when the difference value between the first temperature detection signal and the second temperature detection signal is equal to or greater than a predetermined threshold, and to control some or all of the output transistors 20 (the multiple system transistors 21) to an off state in cooperation with the gate control circuit 24. The overheat protection circuit 27 may also be configured to transition the output transistors 20 to normal operation in cooperation with the gate control circuit 24 when the difference value becomes less than a predetermined threshold.

[0047] Low voltage malfunction avoidance circuit 28 is configured to avoid malfunction of various functional circuits in control circuit 23 when the startup voltage for starting control circuit 23 is less than a predetermined value. For example, low voltage malfunction avoidance circuit 28 may be configured to start control circuit 23 when the startup voltage becomes equal to or greater than a predetermined threshold voltage, and to stop control circuit 23 when the startup voltage becomes less than the threshold voltage. The threshold voltage may have a hysteresis characteristic.

[0048] The open load detection circuit 29 determines the electrical connection state of the inductive load L. For example, the open load detection circuit 29 may be configured to monitor the voltage between the terminals of the output transistor 20 and determine that the inductive load L is in an open state when the voltage between the terminals becomes equal to or higher than a predetermined threshold. For example, the open load detection circuit 29 may be configured to determine that the inductive load L is in an open state when the monitor current becomes equal to or lower than a predetermined threshold.

[0049] The active clamp circuit 30 is electrically connected to the main drain and at least one main gate (for example, the system gate of the first system transistor 21A) of the output transistor 20. The active clamp circuit 30 includes a Zener diode and a pn junction diode connected in series with the Zener diode in a reverse bias state. The pn junction diode is a backflow prevention diode that prevents backflow from the output transistor 20.

[0050] The active clamp circuit 30 is configured to cooperate with the gate control circuit 24 to control a part or the whole of the output transistor 20 to an ON state when a back electromotive voltage caused by the inductive load L is applied to the output transistor 20. Specifically, the output transistor 20 is controlled in a plurality of operation modes including a normal operation, a first OFF operation, an active clamp operation, and a second OFF operation.

[0051] In normal operation, both the first system transistor 21A and the second system transistor 21B are controlled to be in the on state at the same time. This increases the channel utilization rate of the output transistor 20 and reduces the on-resistance. In the first off operation, both the first system transistor 21A and the second system transistor 21B are controlled to be changed from the on state to the off state at the same time. This causes the back electromotive voltage caused by the inductive load L to be applied to both the first system transistor 21A and the second system transistor 21B.

[0052] The active clamp operation is an operation in which the energy stored in the inductive load L is absorbed (consumed) by the output transistor 20, and is executed when the back electromotive voltage caused by the inductive load L becomes equal to or higher than a predetermined threshold voltage. In the active clamp operation, the first system transistor 21A is controlled to change from an OFF state to an ON state, and at the same time, the second system transistor 21B is controlled (maintained) in the OFF state.

[0053] The channel utilization rate of the output transistor 20 during active clamp operation is less than the channel utilization rate of the output transistor 20 during normal operation. The on-resistance of the output transistor 20 during active clamp operation is greater than the on-resistance of the output transistor 20 during normal operation. This suppresses a sudden temperature rise of the output transistor 20 during active clamp operation, improving the active clamp withstand capability.

[0054] The second off operation is executed when the back electromotive voltage becomes less than a predetermined threshold voltage. In the second off operation, the first system transistor 21A is controlled from the on state to the off state, and at the same time, the second system transistor 21B is controlled (maintained) in the off state. In this way, the back electromotive voltage (energy) of the inductive load L is absorbed by a part of the output transistor 20 (here, the first system transistor 21A). Of course, during the active clamp operation, the first system transistor 21A may be controlled (maintained) in the off state, and at the same time, the second system transistor 21B may be controlled to the on state.

[0055] Hereinafter, the configuration of the output region 6 will be described with reference to Figs. 6 to 13. Fig. 6 is a plan view showing the output region 6 and the inner element region 8. Fig. 7 is an enlarged view of region VII shown in Fig. 6. Fig. 8 is a further enlarged view of region VII. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 7. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 7. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 7. Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 7. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 7.

[0056] The semiconductor device 1 includes a first semiconductor region 51 of n-type (first conductivity type) formed in a surface layer portion of the second main surface 4 of the semiconductor chip 2. The first semiconductor region 51 forms a main drain of the output transistor 20 and a system drain of the system transistor 21. The first semiconductor region 51 may be referred to as a "drain region." The first semiconductor region 51 is formed over the entire surface layer portion of the second main surface 4 and is exposed from the second main surface 4 and first to fourth side surfaces 5A to 5D (see FIG. 1, etc.).

[0057] The n-type impurity concentration of the first semiconductor region 51 is 1×10 18 cm -3 More than 1×10 21 cm -3 The thickness of the first semiconductor region 51 may be 10 μm or more and 450 μm or less. The thickness of the first semiconductor region 51 is preferably 50 μm or more and 150 μm or less. In this embodiment, the first semiconductor region 51 is formed of an n-type semiconductor substrate (Si substrate).

[0058] The semiconductor device 1 includes an n-type second semiconductor region 52 formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. The second semiconductor region 52, together with the first semiconductor region 51, forms a main drain of the output transistor 20 and a system drain of the system transistor 21. The second semiconductor region 52 may be referred to as a "drift region." The second semiconductor region 52 is formed over the entire surface layer portion of the first main surface 3 so as to be electrically connected to the first semiconductor region 51, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D (see FIG. 1, etc.).

[0059] The second semiconductor region 52 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 51. The n-type impurity concentration of the second semiconductor region 52 is 1×10 15 cm -3 More than 1×10 18 cm -3The second semiconductor region 52 may have a thickness less than that of the first semiconductor region 51. The second semiconductor region 52 may have a thickness of 1 μm or more and 25 μm or less. The second semiconductor region 52 preferably has a thickness of 5 μm or more and 15 μm or less. In this embodiment, the second semiconductor region 52 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0060] The semiconductor device 1 includes a first trench isolation structure 60 as an example of a region isolation structure that defines the outer edge of the output region 6 on the first main surface 3. The first trench isolation structure 60 may be referred to as a "DTI (deep trench isolation) structure." The first trench isolation structure 60 may be referred to as an "outer isolation structure."

[0061] 6, the first trench isolation structure 60 is formed in a ring shape surrounding the outer periphery of the output region 6 in a plan view. In this embodiment, the first trench isolation structure 60 is formed in a substantially quadrangular ring shape having four sides parallel to the periphery of the first main surface 3 in a plan view. Strictly speaking, the first trench isolation structure 60 has a protrusion 60a that protrudes toward the inner element region 8 in the first direction X in a region facing the inner element region 8 across the output region 6 (a region facing a protrusion 8a described below in the first direction X). The first trench isolation structure 60 may have any planar shape, and may be formed in a polygonal ring shape.

[0062] 9 to 13, the first trench isolation structure 60 includes a first isolation trench 61, a first isolation insulating film 62, and a first isolation electrode 63. That is, the first trench isolation structure 60 has a single electrode structure including a single electrode (first isolation electrode 63) embedded in the first isolation trench 61 with an insulator (first isolation insulating film 62) sandwiched therebetween.

[0063] The first isolation trench 61 is dug down from the first main surface 3 toward the second main surface 4. The first isolation trench 61 is formed at a distance from the bottom of the second semiconductor region 52 toward the first main surface 3. The first isolation insulating film 62 covers the wall surface of the first isolation trench 61. The first isolation insulating film 62 may include a silicon oxide film. The first isolation insulating film 62 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method. The first isolation electrode 63 is embedded in the first isolation trench 61 with the first isolation insulating film 62 sandwiched therebetween. The first isolation electrode 63 may include conductive polysilicon.

[0064] 7 and 9 to 11, first trench isolation structure 60 has a first isolation width W1 and a first isolation depth D1. First isolation width W1 is a width in a direction perpendicular to the direction in which first trench isolation structure 60 extends in a plan view. First isolation width W1 may be 0.5 μm or more and 2.5 μm or less. First isolation width W1 is preferably 1.2 μm or more and 2 μm or less. First isolation depth D1 may be 1 μm or more and 10 μm or less. First isolation depth D1 is preferably 2 μm or more and 6 μm or less.

[0065] The aspect ratio D1 / W1 of the first trench isolation structure 60 may be greater than 1 and less than or equal to 5. The aspect ratio D1 / W1 is the ratio of the first isolation depth D1 to the first isolation width W1. The aspect ratio D1 / W1 is preferably greater than or equal to 2. The bottom wall of the first trench isolation structure 60 is preferably spaced from the bottom of the second semiconductor region 52 by a distance greater than or equal to 1 μm and less than or equal to 5 μm.

[0066] 6 and 7, the first trench isolation structure 60 has corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (curved shape). In this embodiment, the four corners of the first trench isolation structure 60 are formed in an arc shape. In other words, the output region 6 is partitioned into a quadrangle having four corners that each extend in an arc shape. The corners of the first trench isolation structure 60 preferably have a constant first isolation width W1 along the arc direction.

[0067] 9 to 13, the first isolation trench 61 includes a sidewall and a bottom wall. The angle that the sidewall of the first isolation trench 61 makes with the first main surface 3 in the semiconductor chip 2 may be equal to or greater than 90° and equal to or less than 92°. The first isolation trench 61 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the first isolation trench 61 are preferably formed in a curved shape. The entire bottom wall of the first isolation trench 61 may be formed in a curved shape toward the second main surface 4.

[0068] The first isolation insulating film 62 is formed on the wall surface of the first isolation trench 61. Specifically, the first isolation insulating film 62 is formed in the form of a film on the entire wall surface of the first isolation trench 61, and defines a recess space in the first isolation trench 61. The first isolation insulating film 62 preferably includes a silicon oxide film. It is particularly preferable that the first isolation insulating film 62 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0069] The first isolated electrode 63 is embedded in the first isolation trench 61 as an integrated member with the first isolation insulating film 62 sandwiched therebetween. In this embodiment, the first isolated electrode 63 includes conductive polysilicon. A source potential is applied to the first isolated electrode 63. The first isolated electrode 63 has an electrode surface (isolated electrode surface) exposed from the first isolation trench 61. The electrode surface of the first isolated electrode 63 may be recessed in a curved shape toward the bottom wall of the first isolation trench 61. It is preferable that the electrode surface of the first isolated electrode 63 is spaced from the first main surface 3 to the bottom wall of the first isolation trench 61 in the depth direction of the first isolation trench 61.

[0070] 7 to 13, semiconductor device 1 includes a p-type (second conductivity type) first body region 67 formed in a surface layer portion of first main surface 3 in output region 6. The p-type impurity concentration of first body region 67 is 1×10 16 cm -3 More than 1×10 18 cm -3The first body region 67 is formed in the entire surface layer portion of the first main surface 3 in the output region 6, and is in contact with the side wall of the first trench isolation structure 60. The first body region 67 is formed in a region on the first main surface 3 side with respect to the bottom wall of the first trench isolation structure 60. The first body region 67 is preferably formed in a region on the first main surface 3 side with respect to the intermediate portion of the first trench isolation structure 60.

[0071] 6, as described above, the semiconductor device 1 includes an output transistor 20 formed on the first main surface 3 in the output region 6. The output transistor 20 is arranged in a ring shape surrounding the inner element region 8. The output transistor 20 includes a plurality of unit transistors 22 (see FIG. 8) formed collectively on the first main surface 3 of the output region 6. The number of unit transistors 22 is arbitrary. It is preferable that the number of unit transistors 22 is an even number. The plurality of unit transistors 22 are arranged in a line in the second direction Y in a plan view, and are each formed in a band shape extending in the first direction X. The plurality of unit transistors 22 are formed in a stripe shape extending in the first direction X in a plan view.

[0072] 8, each unit transistor 22 includes one trench gate structure (trench electrode structure) 70, and a channel cell 78 controlled by the trench gate structure 70. Each trench gate structure 70 constitutes a unit gate of the unit transistor 22. The channel cell 78 is a region where the opening and closing of a current path is controlled by the trench gate structure 70. In this embodiment, the unit transistor 22 includes a pair of channel cells 78 formed on both sides of one trench gate structure 70.

[0073] 7 and 8, the multiple trench gate structures 70 are arranged at intervals in the second direction Y in a plan view, and are each formed in a band shape extending in the first direction X. That is, the multiple trench gate structures 70 are formed in a stripe shape extending in the first direction X in a plan view.

[0074] Referring to FIGS. 7 to 10, the plurality of trench gate structures 70 have a trench width W2 and a trench depth D2. The trench width W2 is the width in a direction (second direction Y) orthogonal to the direction in which the trench gate structure 70 extends. The trench width W2 is preferably less than the first separation width W1 of the first trench separation structure 60 (W2 < W1). The trench width W2 may be 0.5 μm or more and 2 μm or less. The trench width W2 is preferably 0.5 μm or more and 1.5 μm or less. Of course, the trench width W2 may be approximately equal to the first separation width W1 (W2 ≒ W1).

[0075] The trench depth D2 is preferably less than the first separation depth D1 of the first trench separation structure 60 (D2 < D1). The trench depth D2 may be 1 μm or more and 10 μm or less. The trench depth D2 is preferably 2 μm or more and 6 μm or less. Of course, the trench depth D2 may be approximately equal to the first separation depth D1 (D2 ≒ D1). The aspect ratio D2 / W2 of the trench gate structure 70 may be more than 1 and 5 or less. The aspect ratio D2 / W2 is the ratio of the trench depth D2 to the trench width W2. The aspect ratio D2 / W2 is particularly preferably 2 or more. The bottom wall of the trench gate structure 70 is preferably spaced 1 μm or more and 5 μm or less from the bottom of the second semiconductor region 52.

[0076] Referring to FIGS. 7 to 10, the plurality of trench gate structures 70 are arranged with a first interval I1 in the second direction Y. The first interval I1 is also the mesa width of the mesa portion partitioned in the region between two adjacent trench gate structures 70. The first interval I1 is preferably less than or equal to the first separation width W1 of the first trench separation structure 60. The first interval I1 is preferably less than or equal to the trench width W2. The first interval I1 is particularly preferably less than the trench width W2. The first interval I1 may be 0.5 μm or more and 2 μm or less.

[0077] Hereinafter, a description will be given of the internal configuration of one trench gate structure 70. With reference to Fig. 9 to Fig. 13, the trench gate structure 70 includes a gate trench 71, an insulating film 72, an upper electrode 73, a lower electrode 74, and an intermediate insulating film 75. In other words, the trench gate structure 70 has a multi-electrode structure including a plurality of electrodes (upper electrode 73 and lower electrode 74) vertically embedded in the gate trench 71 with an insulator (insulating film 72 and intermediate insulating film 75) sandwiched therebetween.

[0078] The gate trench 71 is dug down from the first main surface 3 toward the second main surface 4. The gate trench 71 penetrates the first body region 67 and is formed at an interval from the bottom of the second semiconductor region 52 toward the first main surface 3. The gate trench 71 includes a side wall and a bottom wall. The angle that the side wall of the gate trench 71 makes with the first main surface 3 in the semiconductor chip 2 may be 90° or more and 92° or less. The gate trench 71 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The bottom wall corners of the gate trench 71 are preferably formed in a curved shape. The entire bottom wall of the gate trench 71 may be formed in a curved shape toward the second main surface 4. The insulating film 72 covers the wall surface of the gate trench 71. The insulating film 72 includes an upper insulating film 76 and a lower insulating film 77. The upper insulating film 76 covers the wall surface of the gate trench 71 on the opening side relative to the bottom of the first body region 67 .

[0079] The upper insulating film 76 partially covers the wall surface of the gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The upper insulating film 76 is thinner than the first isolation insulating film 62. The upper insulating film 76 is formed as a gate insulating film. The upper insulating film 76 may include a silicon oxide film. The upper insulating film 76 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0080] The lower insulating film 77 covers the wall surface on the bottom wall side of the gate trench 71 relative to the bottom of the first body region 67. The lower insulating film 77 is thicker than the upper insulating film 76. The thickness of the lower insulating film 77 may be approximately equal to the thickness of the first isolation insulating film 62. The lower insulating film 77 may include a silicon oxide film. The lower insulating film 77 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0081] The upper electrode 73 is embedded in the opening side of the gate trench 71 with an insulating film 72 interposed therebetween. Specifically, the upper electrode 73 is embedded in the opening side of the gate trench 71 with an upper insulating film 76 interposed therebetween, and faces the first body region 67 with the upper insulating film 76 interposed therebetween. The upper electrode 73 may include conductive polysilicon.

[0082] The lower electrode 74 is embedded in the bottom wall side of the gate trench 71 with the insulating film 72 sandwiched therebetween. The lower electrode 74 has an upper end portion that protrudes from the lower insulating film 77 toward the upper electrode 73 so as to engage with the bottom portion of the upper electrode 73. The upper end portion of the lower electrode 74 faces the upper insulating film 76 with the lower end portion of the upper electrode 73 sandwiched therebetween in the lateral direction along the first main surface 3. The lower electrode 74 may include conductive polysilicon.

[0083] The intermediate insulating film 75 is interposed between the upper electrode 73 and the lower electrode 74, and electrically insulates the upper electrode 73 and the lower electrode 74 in the gate trench 71. The intermediate insulating film 75 is continuous with the upper insulating film 76 and the lower insulating film 77. The intermediate insulating film 75 is thinner than the lower insulating film 77. The intermediate insulating film 75 may include a silicon oxide film. The intermediate insulating film 75 preferably includes a silicon oxide film made of an oxide of the lower electrode 74.

[0084] As described above, each unit transistor 22 includes a channel cell 78 controlled by a trench gate structure 70. In this embodiment, the two channel cells 78 arranged on either side of one trench gate structure 70 are controlled by that one trench gate structure 70 and are not subject to control by the other trench gate structure 70.

[0085] 8, the channel cells 78 are formed in a region along the inner portion of the trench gate structure 70 at intervals from both ends in the longitudinal direction (first direction X) of the trench gate structure 70. The channel cells 78 expose the first body region 67 from a region of the first main surface 3 between both ends of the trench gate structures 70.

[0086] 8, each channel cell 78 includes a plurality of n-type source regions 79 and a plurality of p-type contact regions 80. In FIG. 8, the source regions 79 are hatched for clarity. The contact regions 80 may be referred to as "back gate regions." The n-type impurity concentration of each source region 79 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following.

[0087] 8 and 9, the multiple source regions 79 are arranged at intervals along each trench gate structure 70. The multiple source regions 79 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and face the upper electrode 73 with the insulating film 72 (upper insulating film 76) between them. All of the source regions 79 included in each unit transistor 22 form a unit source of that unit transistor 22.

[0088] 8 and 9, each contact region 80 has a higher p-type impurity concentration than the first body region 67. The p-type impurity concentration of each contact region 80 is 1×10 18 cm -3 More than 1×10 21 cm -3 The plurality of contact regions 80 are arranged alternately with the plurality of source regions 79 along each trench gate structure 70. The plurality of contact regions 80 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and face the upper electrode 73 with the insulating film 72 (upper insulating film 76) interposed therebetween.

[0089] 8, with respect to two channel cells 78 formed on both sides of one trench gate structure 70, a plurality of source regions 79 in one channel cell 78 face a plurality of source regions 79 in the other channel cell 78 across the trench gate structure 70. Also, a plurality of contact regions 80 in one channel cell 78 face a plurality of contact regions 80 in the other channel cell 78 across the trench gate structure 70.

[0090] Of course, the multiple source regions 79 in one channel cell 78 may face the multiple contact regions 80 in the other channel cell 78 across the trench gate structure 70. Also, the multiple contact regions 80 in one channel cell 78 may face the multiple source regions 79 in the other channel cell 78 across the trench gate structure 70.

[0091] With respect to the two channel cells 78 interposed between the two trench gate structures 70, the source regions 79 in one channel cell 78 are connected to the contact regions 80 in the other channel cell 78 in the second direction Y. Also, the contact regions 80 in one channel cell 78 are connected to the source regions 79 in the other channel cell 78 in the second direction Y.

[0092] Of course, a plurality of source regions 79 in one channel cell 78 may be connected to a plurality of source regions 79 in the other channel cell 78 in the second direction Y. Also, a plurality of contact regions 80 in one channel cell 78 may be connected to a plurality of contact regions 80 in the other channel cell 78 in the second direction Y.

[0093] Of the two channel cells 78 formed on both sides of the outermost trench gate structure 70, the channel cell 78 located on the inner side faces the second semiconductor region 52 across a part of the first body region 67 in the thickness direction. On the other hand, the channel cell 78 located on the outer side does not include a source region 79, but only a contact region 80. This suppresses the formation of a current path in the region between the first trench isolation structure 60 and the outermost trench gate structure 70.

[0094] 7 and 8, the output transistor 20 includes a plurality of unit transistors 22. Each of the plurality of unit transistors 22 includes one trench gate structure 70 and two channel cells 78 formed on both sides of the one trench gate structure 70. For each unit transistor 22, the one trench gate structure 70 constitutes a unit gate, the plurality of source regions 79 (two channel cells 78) constitute a unit source, and the first semiconductor region 51 constitutes a unit drain.

[0095] As described above, the output transistors 20 include first system transistors 21A (see FIG. 5) and second system transistors 21B (see FIG. 5). The first system transistors 21A include a plurality of unit transistors 22 organized (grouped) as targets of individual control from a plurality of unit transistors 22. The second system transistors 21B include a plurality of unit transistors 22 organized (grouped) as targets of individual control from a plurality of unit transistors 22 other than the first system transistors 21A.

[0096] 7 and 8, the output transistor 20 in this embodiment includes a plurality of block regions 81 provided in the output region 6. The plurality of block regions 81 include a plurality of first block regions 81A and a plurality of second block regions 81B. The plurality of first block regions 81A are regions in which one or more (a plurality in this embodiment) unit transistors 22 (see FIG. 5) for the first system transistors 21A (see FIG. 5) are respectively arranged. The plurality of second block regions 81B are regions in which one or more (a plurality in this embodiment) unit transistors 22 (see FIG. 5) for the second system transistors 21B (see FIG. 5) are arranged.

[0097] The multiple first block regions 81A are arranged at intervals in the second direction Y. The number of unit transistors 22 in each first block region 81A is arbitrary. In this embodiment, two unit transistors 22 are arranged in each first block region 81A. As the number of unit transistors 22 in each first block region 81A increases, the amount of heat generated in each first block region 81A increases. Therefore, it is preferable that the number of unit transistors 22 in each first block region 81A be between two and five.

[0098] The second block regions 81B are arranged alternately with the first block regions 81A in the second direction Y so as to sandwich one first block region 81A therebetween. This allows heat generation locations caused by the first block regions 81A to be thinned out by the second block regions 81B, and at the same time, heat generation locations caused by the second block regions 81B to be thinned out by the first block regions 81A.

[0099] Each second block region 81B may have any number of unit transistors 22. In this embodiment, two unit transistors 22 are arranged in each second block region 81B. As the number of unit transistors 22 in each second block region 81B increases, the amount of heat generated in each second block region 81B increases.

[0100] Therefore, the number of unit transistors 22 in each second block region 81B is preferably between 2 and 5. In consideration of in-plane temperature variations in the output region 6, the number of unit transistors 22 in the second block region 81B is preferably the same as the number of unit transistors 22 in the first block region 81A.

[0101] 6 and 7, the semiconductor device 1 includes a pair of trench connection structures 90 that connect both ends of a plurality of (two in this embodiment) trench gate structures 70 to be organized (grouped) in each block region 81. That is, the pair of trench connection structures 90 connect both ends of the plurality of trench gate structures 70 to be organized as system transistors 21, respectively.

[0102] 6, the trench connection structure 90 on one side connects, in an arch shape, first ends of a plurality of (two in this embodiment) corresponding trench gate structures 70 in a plan view. The trench connection structure 90 on the other side connects, in an arch shape, second ends of a plurality of (two in this embodiment) corresponding trench gate structures 70 in a plan view.

[0103] Specifically, the trench connection structure 90 on one side has a first portion extending in the second direction Y and a plurality of (two in this embodiment) second portions extending in the first direction X. The first portion faces first ends of the plurality of trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

[0104] The trench connection structure 90 on the other side has a first portion extending in the second direction Y and a plurality of (two in this embodiment) second portions extending in the first direction X. The first portion faces the second ends of the plurality of trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of trench connection structures 90 and the plurality of trench gate structures 70 in each block region 81 form a ring-shaped or ladder-shaped trench structure.

[0105] 6, a plurality of trench connection structures 90 are formed at intervals from the bottom of the first semiconductor region 51 toward the first main surface 3, and face the first semiconductor region 51 with a part of the second semiconductor region 52 interposed therebetween.

[0106] 7, the trench connection structures 90 may be formed with approximately the same width and depth as the trench gate structure 70. Of course, the first and second parts of the trench connection structure 90 may have different widths. For example, the second part of the trench connection structure 90 may be formed narrower than the first part of the trench connection structure 90.

[0107] In this case, the first portion may have a width approximately equal to the width of the first trench isolation structure 60, and the second portion may have a width approximately equal to the width of the trench gate structure 70. Further, in this case, the first portion may have a depth approximately equal to the depth of the first trench isolation structure 60, and the second portion may have a depth approximately equal to the depth of the trench gate structure 70.

[0108] 6, the trench connection structure 90 on the other side has a structure similar to that of the trench connection structure 90 on one side, except that the trench connection structure 90 on the other side is connected to the second end of the trench gate structure 70. Hereinafter, the configuration of the trench connection structure 90 on one side will be described, and a description of the configuration of the trench connection structure 90 on the other side will be omitted.

[0109] 7 and 11 to 13, trench connection structure 90 includes a connection trench 91, a connection insulating film 92, and a connection electrode 93. Connection trench 91 is formed in first main surface 3 and defines a wall surface of trench connection structure 90. Connection trench 91 is connected to a plurality of gate trenches 71.

[0110] The connection insulating film 92 covers the wall surface of the connection trench 91. The connection insulating film 92 is connected to the upper insulating film 76, the lower insulating film 77, and the intermediate insulating film 75 at the communicating portion between the connection trench 91 and the gate trench 71. The connection insulating film 92 is thicker than the upper insulating film 76. The thickness of the connection insulating film 92 may be approximately equal to the thickness of the lower insulating film 77. The connection insulating film 92 may include a silicon oxide film. The connection insulating film 92 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0111] The connection electrode 93 is embedded in the connection trench 91 with a connection insulating film 92 interposed therebetween, and faces the second semiconductor region 52 and the first body region 67 with the connection insulating film 92 interposed therebetween. The connection electrode 93 is connected to the lower electrode 74 at the communicating portion between the connection trench 91 and the gate trench 71, and is electrically insulated from the upper electrode 73 by the intermediate insulating film 75. The connection electrode 93 is formed of an extension portion where the lower electrode 74 is extended from inside the gate trench 71 into the connection trench 91. The connection electrode 93 may include conductive polysilicon.

[0112] 9 and 10, semiconductor device 1 includes a main surface insulating film 94 that selectively covers first main surface 3 in output region 6. Main surface insulating film 94 is connected to insulating film 72 (upper insulating film 76) and connection insulating film 92, and exposes first separated electrode 63, upper electrode 73, and connection electrode 93.

[0113] 9 and 10, the main surface insulating film 94 is thinner than the first isolation insulating film 62. The main surface insulating film 94 is thinner than the lower insulating film 77. The main surface insulating film 94 is thinner than the connection insulating film 92. The main surface insulating film 94 may have a thickness approximately equal to that of the upper insulating film 76. The main surface insulating film 94 may include a silicon oxide film. The main surface insulating film 94 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0114] 10 to 13, the semiconductor device 1 includes a field insulating film 95 selectively covering the first main surface 3 inside and outside the output region 6. The field insulating film 95 is thicker than the main surface insulating film 94. The field insulating film 95 is thicker than the upper insulating film 76. The field insulating film 95 may have a thickness substantially equal to that of the first isolation insulating film 62. The field insulating film 95 may include a silicon oxide film. The field insulating film 95 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0115] The field insulating film 95 covers the first main surface 3 along the inner wall of the first trench isolation structure 60 and the outer wall of the second trench isolation structure 100 (see FIG. 15, etc.) in the output region 6, and is connected to the first isolation insulating film 62, the connection insulating film 92, the main surface insulating film 94, and the second isolation insulating film 102 (see FIG. 15, etc.). The field insulating film 95 covers the first main surface 3 along the outer wall of the first trench isolation structure 60 outside the output region 6, and is connected to the first isolation insulating film 62.

[0116] 9 to 13, the above-mentioned interlayer insulating layer 11 covers the first trench isolation structure 60, the trench gate structure 70, the trench connection structure 90, the main surface insulating film 94 and the field insulating film 95 in the output region 6.

[0117] 6, in this embodiment, a plurality of block regions 81 are formed in the output region 6 on both sides in the first direction X of the inner element region 8. The plurality of block regions 81 formed on one side in the first direction X of the inner element region 8 face in the first direction X to the plurality of block regions 81 formed on the other side in the first direction X of the inner element region 8, with the inner element region 8 sandwiched therebetween. The block regions 81 facing in the first direction X are electrically connected to each other.

[0118] 6, as described above, the semiconductor device 1 includes a plurality of gate wirings 16 arranged in the interlayer insulating layer 11. The plurality of gate wirings 16 are routed to the output region 6 and the control region 7, electrically connected to the output transistor 20 in the output region 6, and electrically connected to the control circuit 23 (see FIG. 4; gate control circuit 24) in the control region 7. The plurality of gate wirings 16 individually transmit a plurality of gate signals generated by the control circuit 23 (see FIG. 4; gate control circuit 24) to the output transistor 20.

[0119] The multiple gate wirings 16 include first system gate wirings 16A and second system gate wirings 16B. The first system gate wirings 16A individually transmit gate signals to the first system transistors 21A. The first system gate wirings 16A are electrically connected to the multiple trench gate structures 70 for the first system transistors 21A through multiple via electrodes 97 arranged in the interlayer insulating layer 11. Specifically, the first system gate wirings 16A are electrically connected to the multiple upper electrodes 73 and the multiple connection electrodes 93 corresponding thereto through the multiple via electrodes 97.

[0120] That is, the upper electrode 73 and the lower electrode 74 for the first system transistor 21A are simultaneously controlled to be turned on and off by the same gate signal. This suppresses the voltage drop between the upper electrode 73 and the lower electrode 74, and suppresses undesirable electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0121] The second system gate wiring 16B transmits gate signals to the second system transistors 21B individually, electrically independent from the first system gate wiring 16A. The second system gate wiring 16B is electrically connected to the trench gate structures 70 for the second system transistors 21B through the via electrodes 97 arranged in the interlayer insulating layer 11. Specifically, the second system gate wiring 16B is electrically connected to the corresponding upper electrodes 73 and connection electrodes 93 through the via electrodes 97.

[0122] That is, the upper electrode 73 and the lower electrode 74 for the second system transistor 21B are simultaneously controlled to be turned on and off by the same gate signal. This suppresses the voltage drop between the upper electrode 73 and the lower electrode 74, and suppresses undesirable electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0123] 10 to 13, the gate wiring 16 includes a first gate wiring 161 included in the first wiring layer 12 and a second gate wiring 162 included in the second wiring layer 13. The first gate wiring 161 may include a first system gate wiring 16A and a second system gate wiring 16B. The second gate wiring 162 may include the first system gate wiring 16A and the second system gate wiring 16B.

[0124] 9 to 13, the semiconductor device 1 includes a source wiring 98 disposed in the interlayer insulating layer 11. The source wiring 98 is electrically connected to the source terminal 17, the first trench isolation structure 60, and the plurality of channel cells 78. Specifically, the source wiring 98 is electrically connected to the first trench isolation structure 60 and the plurality of channel cells 78 through a plurality of via electrodes 97 disposed in the interlayer insulating layer 11.

[0125] 7, the via electrode 97 for each channel cell 78 is disposed so as to straddle two adjacent channel cells 78, and is formed in a strip shape extending along each channel cell 78 in a plan view. As a result, the source terminal 17 is electrically connected to the system sources of all the system transistors 21 (the unit sources of the unit transistors 22).

[0126] 9 to 13, the source wiring 98 includes a first source wiring (first output wiring) 98A included in the first wiring layer 12 and a second source wiring (second output wiring) 98B included in the second wiring layer 13. The first source wiring 98A and the second source wiring 98B are electrically connected through a via electrode (not shown). The first source wiring 98A and the second source wiring 98B are formed in plurality so as to overlap substantially the entire region in which the output transistor 20 is formed on the first main surface 3 in a plan view.

[0127] Fig. 14 is a plan view showing the inner element region 8 and an enlarged view of region XIV shown in Fig. 6. Fig. 15 is a cross-sectional view taken along line XV-XV shown in Fig. 14. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 14. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 14. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 14.

[0128] As described above, on the first main surface 3, the inner element region 8 is formed in the center of the output region 6 and is surrounded by the output region 6. Hereinafter, the configuration of the inner element region 8 will be described with reference to FIGS. 6, 14, 15 and 17.

[0129] 6 and 14, the inner element region 8 is a region insulated and separated from the output region 6. In this embodiment, the inner element region 8 is partitioned into a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view. In the example of FIG. 6 and FIG. 14, the inner element region 8 is substantially rectangular. The inner element region 8 has a protrusion 8a that protrudes outward in the first direction X in a region facing the control region 7 across the output region 6.

[0130] 14, the semiconductor device 1 includes a second trench isolation structure (isolation structure) 100 as an example of a region isolation structure that defines the periphery of the inner element region 8 on the first main surface 3. The second trench isolation structure 100 may be referred to as a "DTI (deep trench isolation) structure." The second trench isolation structure 100 may be referred to as an "inner isolation structure."

[0131] 14, the second trench isolation structure 100 is formed in a ring shape surrounding the outer periphery of the inner element region 8 in a plan view. In this embodiment, the second trench isolation structure 100 is formed in a substantially quadrangular ring shape having four sides parallel to the periphery of the first main surface 3 in a plan view. The second trench isolation structure 100 has a protrusion 100a that protrudes outward in the first direction X in a region facing the control region 7 with the output region 6 in between. The second trench isolation structure 100 may have any planar shape and may be formed in a polygonal ring shape.

[0132] 15 and 17, the second trench isolation structure 100 includes a second isolation trench (isolation trench) 101, a second isolation insulating film (isolation insulator) 102, and a second isolation electrode (isolation electrode) 103. That is, the second trench isolation structure 100 has a single electrode structure including a single electrode (second isolation electrode 103) embedded in the second isolation trench 101 with an insulator (second isolation insulating film 102) sandwiched therebetween.

[0133] 15 and 17, the second isolation trench 101 is dug down from the first main surface 3 toward the second main surface 4. The second isolation trench 101 is formed at an interval from the bottom of the second semiconductor region 52 toward the first main surface 3. The second isolation insulating film 102 covers the wall surface of the second isolation trench 101. The second isolation insulating film 102 may include a silicon oxide film. The second isolation insulating film 102 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method. The second isolation electrode 103 is embedded in the second isolation trench 101 with the second isolation insulating film 102 sandwiched therebetween. The second isolation electrode 103 may include conductive polysilicon.

[0134] 15 and 17, the second trench isolation structure 100 has a second isolation width W3 and a second isolation depth D3. The second isolation depth D3 may be the same as the first isolation depth D1 (D3=D1). The second isolation depth D3 is preferably greater than the trench depth D2 (D3>D2). The second isolation width W3 is a width in a direction perpendicular to the direction in which the second trench isolation structure 100 extends in a plan view. The second isolation width W3 may be the same as the first isolation width W1 (W3=W1).

[0135] The aspect ratio D3 / W3 of the second trench isolation structure 100 may be greater than 1 and less than or equal to 5. The aspect ratio D3 / W3 is the ratio of the second isolation depth D3 to the second isolation width W3. The aspect ratio D3 / W3 is preferably greater than or equal to 2. The bottom wall of the second trench isolation structure 100 is preferably spaced from the bottom of the second semiconductor region 52 by a distance of greater than or equal to 1 μm and less than or equal to 5 μm.

[0136] 14, the second trench isolation structure 100 has corners that connect the portions extending in the first direction X and the second direction Y in an arc shape (curved shape). In this embodiment, the four corners of the second trench isolation structure 100 are formed in an arc shape. That is, the inner element region 8 is partitioned into a substantially rectangular shape having four corners that each extend in an arc shape. The corners of the second trench isolation structure 100 preferably have a constant second isolation width W3 along the arc direction.

[0137] 15 and 17, second isolation trench 101 includes a sidewall and a bottom wall. The angle that the sidewall of second isolation trench 101 makes with first main surface 3 in semiconductor chip 2 may be 90° or more and 92° or less. Second isolation trench 101 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. Bottom wall corners of second isolation trench 101 are preferably formed in a curved shape. The entire bottom wall of second isolation trench 101 may be formed in a curved shape toward second main surface 4.

[0138] 15 and 17, the second isolation insulating film 102 is formed on the wall surface of the second isolation trench 101. Specifically, the second isolation insulating film 102 is formed in the form of a film on the entire wall surface of the second isolation trench 101, and defines a recess space in the second isolation trench 101. The second isolation insulating film 102 preferably includes a silicon oxide film. It is particularly preferable that the second isolation insulating film 102 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0139] 15 and 17, the second isolated electrode 103 is embedded in the second isolation trench 101 as an integrated member with the second isolation insulating film 102 interposed therebetween. In this embodiment, the second isolated electrode 103 includes conductive polysilicon. A source potential is applied to the second isolated electrode 103. The second isolated electrode 103 has an electrode surface (isolated electrode surface) exposed from the second isolation trench 101. The electrode surface of the second isolated electrode 103 may be recessed in a curved shape toward the bottom wall of the second isolation trench 101. It is preferable that the electrode surface of the second isolated electrode 103 is spaced from the first main surface 3 to the bottom wall of the second isolation trench 101 in the depth direction of the second isolation trench 101.

[0140] 15 and 17, a field insulating film 95 covers the first main surface 3 in the inner element region 8. The field insulating film 95 covers the first main surface 3 along the inner wall of the second trench isolation structure 100 in the inner element region 8, and is connected to a second isolation insulating film 102.

[0141] As described above, the temperature sensor element 9 is disposed in the inner element region 8. The configuration of the temperature sensor element 9 will be described below with reference to Figs.

[0142] 14 and 15, in this embodiment, the temperature sensor element 9 is a temperature sensing diode 110. The temperature sensing diode 110 is, for example, a polysilicon diode. The temperature sensing diode 110 includes a plurality of temperature sensing diode elements 111. The temperature sensing diode 110 is in the form of a diode string in which a plurality of temperature sensing diode elements 111 are connected in series in the forward direction. Although not shown, the temperature sensing diode 110 may have a plurality of temperature sensing diode elements 111 connected in parallel. The number (plurality) of the temperature sensing diode elements 111 included in the temperature sensing diode 110 may be, for example, two to four (three in the example of FIG. 14). The number of the temperature sensing diode elements 111 included in the temperature sensing diode 110 is not limited to a plurality, and may be one.

[0143] 15, each of the temperature sensitive diode elements 111 includes a polysilicon layer 113 formed on the first main surface 3 in the inner element region 8. More specifically, the polysilicon layer 113 is formed on the field insulating film 95. The polysilicon layer 113 is electrically insulated from the first main surface 3 by the field insulating film 95. The thickness of the polysilicon layer 113 may be 0.2 μm or more and 1.0 μm or less. The temperature sensitive diode element 111 is formed by selectively introducing n-type impurities and p-type impurities into the polysilicon layer 113. The temperature sensitive diode element 111 includes an anode region 114 formed in the polysilicon layer 113 and a cathode region 115 formed in the polysilicon layer 113. The temperature sensitive diode element 111 is a diode element in which the anode region 114 serves as an anode and the cathode region 115 serves as a cathode.

[0144] 14, each polysilicon layer 113 is set to have a quadrangular shape in a plan view. The multiple polysilicon layers 113 are aligned in a first direction X. The cathode region 115 is formed in the center of each polysilicon layer 113. In this embodiment, the cathode region 115 is exposed from a first surface 113a and a second surface 113b of the polysilicon layer 113.

[0145] Referring to FIG. 14, the anode region 114 is formed along the periphery of the cathode region 115. In this embodiment, the anode region 114 is formed in a C-shape or U-shape surrounding the cathode region 115 in a plan view. The anode region 114 may be formed in a ring shape surrounding the entire circumference of the cathode region 115. The anode region 114 is electrically connected to the cathode region 115. In this embodiment, the anode region 114 is exposed from the first surface 113a and the second surface 113b of the polysilicon layer 113. The anode region 114 is connected to the cathode region 115 over the entire thickness direction of the polysilicon layer 113. The anode region 114 forms a pn junction at the interface with the cathode region 115. In this embodiment, the anode region 114 surrounds the cathode region 115 in a C-shape or U-shape, so that the pn junction is also C-shaped or U-shaped in a plan view. The anode region 114 may annularly surround the cathode region 115. In this case, the pn junction is annular in plan view.

[0146] 14 and 16, the temperature sensitive diode 110 includes a diode wiring 116. The diode wiring 116 has one end 116a and the other end 116b. The first connection wiring 10A is electrically connected to the one end 116a of the diode wiring 116 through a via electrode 117. The second connection wiring 10B is electrically connected to the other end 116b of the diode wiring 116 through the via electrode 117. Therefore, the temperature sensor element 9 (temperature sensitive diode 110) is connected to the control circuit 23 (see FIG. 4) of the control region 7 through the first connection wiring 10A and the second connection wiring 10B.

[0147] 14, a pair of block regions 81 facing each other in the first direction X with the inner element region 8 therebetween are electrically connected to each other. Connection electrodes 93 (see FIGS. 17 and 18) of the block regions 81 are connected by a gate connection wiring 120. The gate connection wiring 120 includes a first gate connection wiring 121 and a second gate connection wiring 122 facing each other in the first direction X.

[0148] 14, the first gate connection wiring 121 has a strip shape extending in the second direction Y. The first gate connection wiring 121 is formed so as to overlap, in plan view, with the block region 81 on one side in the first direction X (the upper side in FIG. 14).

[0149] 17, the first gate connection wiring 121 is electrically connected to the connection electrode 93 in the block region 81 through a via electrode 121A.

[0150] 14, the second gate connection wiring 122 has a strip shape extending in the second direction Y. The second gate connection wiring 122 is formed so as to overlap, in plan view, with the block region 81 on the other side in the first direction X (the lower side in FIG. 14).

[0151] 18, the second gate connection wiring 122 is electrically connected to the connection electrode 93 in the block region 81 through a via electrode 122A.

[0152] As described above, in this embodiment, the convex portion 8a is formed in the inner element region 8. Referring to FIG. 14, in order to avoid interference with the convex portion 8a, on the first main surface 3, the trench connection structure 90 facing the convex portion 8a in the first direction X is retreated further outward (toward the control region 7) in the first direction X than the other trench connection structures 90. The second gate connection wiring 122 is disposed so as to overlap all the connection electrodes 93 (trench connection structures 90) of the block region 81 on the other side in the normal direction Z. The second gate connection wiring 122 crosses the convex portion 8a of the inner element region 8 in the second direction Y in a plan view.

[0153] 14, the gate connection wiring 120 further includes a third gate connection wiring 123. The third gate connection wiring 123 electrically connects the first gate connection wiring 121 and the second gate connection wiring 122. The third gate connection wiring 123 is in a strip shape extending in the first direction X. In this embodiment, the third gate connection wiring 123 has a pair of third gate connection wirings 123 facing each other in the second direction Y. The third gate connection wiring 123 crosses the inner element region 8 in the first direction X in a plan view. The pair of third gate connection wirings 123 sandwich the temperature sensor element 9 in the second direction Y in a plan view. The number of third gate connection wirings 123 is not limited to a pair (two) and may be one.

[0154] 17 and 18, the gate connection wiring 120 includes a lower wiring included in the first wiring layer 12 and an upper wiring included in the second wiring layer 13. Specifically, the first gate connection wiring 121 (see FIG. 17) includes a first gate connection wiring 121 included in the first wiring layer 12 and a first gate connection wiring 121 included in the second wiring layer 13. The second gate connection wiring 122 (see FIG. 18) includes a second gate connection wiring 122 included in the first wiring layer 12 and a second gate connection wiring 122 included in the second wiring layer 13. The third gate connection wiring 123 (see FIG. 17 and 18) includes a third gate connection wiring 123 included in the first wiring layer 12 and a third gate connection wiring 123 included in the second wiring layer 13. The first gate connection wiring 121, the second gate connection wiring 122 and the third gate connection wiring 123 included in the first wiring layer 12 are electrically connected to the first gate connection wiring 121, the second gate connection wiring 122 and the third gate connection wiring 123 included in the second wiring layer 13, respectively, via vias (not shown).

[0155] Fig. 19A is a cross-sectional view taken along line XIXA-XIXA shown in Fig. 14. Fig. 19B is a cross-sectional view taken along line XIXB-XIXB shown in Fig. 6.

[0156] 19A, in a region between the control region 7 and the inner element region 8 in the output region 6, a first source wiring 98A and a second source wiring 98B are arranged above the first main surface 3. As described above, the first source wiring 98A is included in the first wiring layer 12, and the second source wiring 98B is included in the second wiring layer 13. In this region, the second wiring layer 13 includes the first connection wiring 10A and the second connection wiring 10B together with the second source wiring 98B. In this region, the first connection wiring 10A and the second connection wiring 10B extend along the first direction X. The first connection wiring 10A and the second connection wiring 10B are sandwiched in the second direction Y by a plurality of second source wirings 98B. The first source wiring 98A overlaps the first connection wiring 10A and the second connection wiring 10B in the normal direction Z.

[0157] The first connection wiring 10A and the second connection wiring 10B are not included in the first wiring layer 12. The first connection wiring 10A and the second connection wiring 10B are insulated and separated from each other. The first connection wiring 10A and the second connection wiring 10B are insulated and separated from the second source wiring 98B. The first connection wiring 10A and the second connection wiring 10B are also insulated and separated from the first source wiring 98A included in the first wiring layer 12.

[0158] The first source wiring 98A is formed so as to overlap the entire area of ​​the arrangement region of the output transistor 20 on the first main surface 3 in a plan view. The second source wiring 98B is formed so as to overlap the entire area of ​​the formation region of the output transistor 20 on the first main surface 3 in a plan view, except for the area where the connection wiring 10 (first connection wiring 10A, second connection wiring 10B) is arranged.

[0159] A trench gate structure 70 is disposed below the first connection wiring 10A and the second connection wiring 10B. That is, the trench gate structure 70 is formed below the first connection wiring 10A and the second connection wiring 10B so as to overlap with the first connection wiring 10A and the second connection wiring 10B in a plan view.

[0160] In this embodiment, the first connection wiring 10A and the second connection wiring 10B are included in the wiring layer (second wiring layer 13). Therefore, even if the output transistor 20 is arranged so as to overlap the first connection wiring 10A and the second connection wiring 10B in a plan view, the output transistor 20 is not electrically connected to the connection wirings 10A and 10B. In this case, since the first connection wiring 10A and the second connection wiring 10B can be arranged above the trench gate structure 70, the output transistor 20 can be arranged in approximately the entire circumferential area of ​​the rectangular ring-shaped output region 6 that surrounds the entire periphery of the inner element region 8.

[0161] 19B, in a region between the control region 7 and the inner element region 8 in the output region 6, a first gate wiring 161 and a second gate wiring 162 are arranged above the first main surface 3. As described above, the first gate wiring 161 is included in the first wiring layer 12, and the second gate wiring 162 is included in the second wiring layer 13. In this region, the second wiring layer 13 includes the first connection wiring 10A and the second connection wiring 10B together with the second gate wiring 162. The first connection wiring 10A and the second connection wiring 10B are not included in the first wiring layer 12. In this region, the first connection wiring 10A and the second connection wiring 10B extend along the first direction X, similar to the first gate wiring 161 and the second gate wiring 162.

[0162] The first connection wiring 10A and the second connection wiring 10B are insulated and separated from each other. The first connection wiring 10A and the second connection wiring 10B are insulated and separated from the second gate wiring 162. The first connection wiring 10A and the second connection wiring 10B are also insulated and separated from the first gate wiring 161 included in the first wiring layer 12.

[0163] 3, 4, 19A and 19B, a first temperature detection signal from the temperature sensor element 9 is provided to the overheat protection circuit 27 via the first connection wiring 10A and the second connection wiring 10B. The overheat protection circuit 27 controls the on / off of the output transistor 20 based on the first temperature detection signal from the temperature sensor element 9. When the overheat protection circuit 27 determines that the output region 6 is in an overheated state, it controls a part or all of the output transistor 20 to an off state. This prevents the semiconductor device 1 from being destroyed.

[0164] Fig. 20 is a plan view showing an example of the layout in the semiconductor chip 2 of a semiconductor device 191 shown in a reference embodiment. In Fig. 20, the output region 6 is formed so as to surround the inner element region 8. However, in the reference embodiment shown in Fig. 20, the output transistor 20 is not arranged in a region 192 between the control region 7 and the inner element region 8 in the output region 6. That is, in the reference embodiment shown in Fig. 20, the output transistor 20 is not arranged in a region of the output region 6 that overlaps with the connection wiring 10 in a plan view (a region of the output region 6 below the connection wiring 10).

[0165] In the semiconductor device 1 according to the first embodiment, as shown in Fig. 19A, the output transistors 20 are also formed in the region of the output region 6 between the control region 7 and the inner element region 8 over the entire area in the second direction Y. That is, the output transistors 20 are also formed in the region of the output region 6 that overlaps with the connection wiring 10 in a planar view. By effectively utilizing this region as an arrangement region for the output transistors 20, the semiconductor device 1 can improve the mounting efficiency of the output transistors 20 on the first main surface 3 compared to the reference embodiment shown in Fig. 20. This makes it possible to reduce the chip area in the semiconductor device 1.

[0166] Furthermore, the first connection wiring 10A and the second connection wiring 10B included in the first wiring layer 12 are not included in the first wiring layer 12 but in the second wiring layer 13 formed on the first wiring layer 12. This does not affect the routing of the first source wiring 98A in the first wiring layer 12. This allows the source potential to be applied satisfactorily to the output transistor 20 (unit transistor 22). This allows the mounting efficiency of the output transistor 20 to be improved while allowing the source potential to be applied satisfactorily to the output transistor 20.

[0167] FIG. 21 is a plan view showing the output region 6 and the inner element region 208 of the semiconductor device 201 according to the second embodiment, and corresponds to FIG. 6. FIG. 22 is a plan view showing the inner element region 208, and is an enlarged view of the region XXII shown in FIG. 21. FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. 22. FIG. 24 is a cross-sectional view taken along the line XXIV-XXIV shown in FIG. 22. FIG. 25 is a cross-sectional view taken along the line XXV-XXV shown in FIG. 22. In the second embodiment, only the parts different from the first embodiment will be mainly described, and the same reference symbols will be used for the same configurations as those described so far, and the description thereof will be omitted.

[0168] The second embodiment differs from the first embodiment in that not only a temperature sensor element 9 as a first element, but also a current monitor element 209 as a second element are arranged in the inner element region 208. The second embodiment also differs from the first embodiment in that a third trench isolation structure 140 (see FIG. 22) is formed inside the inner element region 208.

[0169] 21 and 22, the size of the inner element region 208 in the second direction Y is larger than that of the inner element region 8 (see FIGS. 6 and 14). Except for this, the inner element region 208 has the same configuration as the inner element region 8. The periphery of the inner element region 208 is defined by the second trench isolation structure 100, similar to the inner element region 8.

[0170] As described above, the temperature sensor element 9 and the current monitor element 209, which is an example of a second element, are arranged in the inner element region 208. The inner element region 208 is arranged alongside the temperature sensor element 9 in the second direction Y.

[0171] In the semiconductor device 201 according to the second embodiment, the current monitor element 209 generates a monitor current that monitors the output current Io (see FIG. 4) of the output transistor 20. The current monitor element 209 includes a transistor having a similar configuration to the output transistor 20, and is on / off controlled simultaneously with the output transistor 20 to generate a monitor current linked to the output current Io.

[0172] The current monitor element 209 is used in place of the current monitor circuit 25 (see FIG. 4) of the control circuit 23 of the first embodiment. The overcurrent protection circuit 26 (see FIG. 4) generates an electric signal for controlling the gate control circuit 24 based on the monitor current from the current monitor element 209, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20.

[0173] The configuration of the current monitoring element 209 will be described below with reference to FIGS.

[0174] 22, the third trench isolation structure 140 defines a current detection region 209A in which the current monitor element 209 is disposed in the inner element region 208. The third trench isolation structure 140 may be referred to as a "DTI structure." In this embodiment, the third trench isolation structure 140 is formed in a quadrangular ring shape having four sides parallel to the periphery of the first main surface 3 in a plan view, and defines a quadrangular current detection region 209A. The current detection region 209A may be defined in a polygonal shape according to the planar shape of the third trench isolation structure 140. In this case, the planar shape of the third trench isolation structure 140 may be formed in a polygonal ring shape.

[0175] 23, the third trench isolation structure 140 includes a third isolation trench 141, a third isolation insulating film 142, and a third isolation electrode 143. That is, the third trench isolation structure 140 has a single electrode structure including a single electrode (third isolation electrode 143) embedded in the third isolation trench 141 with an insulator (third isolation insulating film 142) sandwiched therebetween.

[0176] The third isolation trench 141 is dug down from the first main surface 3 toward the second main surface 4. The third isolation trench 141 is formed at an interval from the bottom of the second semiconductor region 52 toward the first main surface 3. The third isolation insulating film 142 covers the wall surface of the third isolation trench 141. The third isolation insulating film 142 may include a silicon oxide film. The third isolation insulating film 142 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method. The third isolation electrode 143 is embedded in the third isolation trench 141 with the third isolation insulating film 142 sandwiched therebetween. The third isolation electrode 143 may include conductive polysilicon.

[0177] The aspect ratio D4 / W4 of the third trench isolation structure 140 may be greater than 1 and less than or equal to 5. The aspect ratio D4 / W4 is the ratio of the third isolation depth D4 to the third isolation width W4. The aspect ratio D4 / W4 is preferably greater than or equal to 2. The bottom wall of the third trench isolation structure 140 is preferably spaced from the bottom of the second semiconductor region 52 by a distance greater than or equal to 1 μm and less than or equal to 5 μm.

[0178] 23, the third isolation trench 141 includes a sidewall and a bottom wall. The angle that the sidewall of the third isolation trench 141 makes with the first main surface 3 in the semiconductor chip 2 may be equal to or greater than 90° and equal to or less than 92°. The third isolation trench 141 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the third isolation trench 141 are preferably formed in a curved shape. The entire bottom wall of the third isolation trench 141 may be formed in a curved shape toward the second main surface 4.

[0179] 23, the third isolation insulating film 142 is formed on the wall surface of the third isolation trench 141. Specifically, the third isolation insulating film 142 is formed in the form of a film on the entire wall surface of the third isolation trench 141, and defines a recess space in the third isolation trench 141. The third isolation insulating film 142 preferably includes a silicon oxide film. It is particularly preferable that the third isolation insulating film 142 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0180] 23, the third isolated electrode 143 is embedded in the third isolation trench 141 as an integrated member with the third isolation insulating film 142 interposed therebetween. In this embodiment, the third isolated electrode 143 includes conductive polysilicon. A source potential is applied to the third isolated electrode 143. The third isolated electrode 143 has an electrode surface (isolated electrode surface) exposed from the third isolation trench 141. The electrode surface of the third isolated electrode 143 may be recessed in a curved shape toward the bottom wall of the third isolation trench 141. It is preferable that the electrode surface of the third isolated electrode 143 is spaced from the first main surface 3 to the bottom wall of the third isolation trench 141 in the depth direction of the third isolation trench 141.

[0181] 23, semiconductor device 201 includes second body region 167 formed in a surface layer portion of first main surface 3 in current detection region 209A. The p-type impurity concentration of second body region 167 is 1×10 16 cm -3 More than 1×10 18 cm -3 or less. The p-type impurity concentration of the second body region 167 is preferably approximately equal to the p-type impurity concentration of the first body region 67 (see FIG. 7, etc.). The second body region 167 preferably has approximately the same thickness (depth) as the first body region 67. With this structure, the second body region 167 can be formed simultaneously with the first body region 67.

[0182] The second body region 167 is formed in the current detection region 209A over the entire surface portion of the first main surface 3. The second body region 167 is in contact with the inner circumferential wall of the third isolation trench 141, but is not in contact with the inner circumferential wall of the second isolation trench 101.

[0183] 22, semiconductor device 201 includes a monitor transistor 220 formed on first main surface 3 in current detection region 209A. Monitor transistor 220 includes a plurality of unit transistors 222 formed collectively on first main surface 3 in current detection region 209A. The plurality of unit transistors 222 are formed in stripes extending in first direction X in plan view. In monitor transistor 220, a monitor current corresponding to output current Io (see FIG. 4) is generated in second body region 167.

[0184] 23, each unit transistor 222 includes one trench gate structure 170 and a channel cell controlled by the trench gate structure 170. In this embodiment, the unit transistor 222 includes a pair of channel cells formed on both sides of one trench gate structure 170. Each channel cell includes a number of n-type source regions 179 and a number of p-type contact regions 180.

[0185] The multiple trench gate structures 170 are arranged at intervals in the second direction Y in a plan view, and are each formed in a belt shape extending in the first direction X. That is, the multiple trench gate structures 170 are formed in a stripe shape extending in the first direction X in a plan view.

[0186] 23, the trench gate structures 170 have a trench width W5 and a trench depth D5. The trench width W5 may be approximately equal to the trench width W2 (W5≈W2). The trench depth D5 may be approximately equal to the trench depth D2 (D5≈D2). The aspect ratio D5 / W5 of the trench gate structure 170 may be equivalent to the aspect ratio D2 / W2 of the trench gate structure 70.

[0187] The trench gate structure 170 includes a gate trench 171, an insulating film 172, an upper electrode 173, a lower electrode 174, and an intermediate insulating film 175. That is, the trench gate structure 170 has a multi-electrode structure including a plurality of electrodes (upper electrode 173 and lower electrode 174) vertically embedded in the gate trench 171 with an insulator (insulating film 172 and intermediate insulating film 175) sandwiched therebetween. The insulating film 172 includes an upper insulating film 176 and a lower insulating film 177. The gate trench 171, the insulating film 172, the upper electrode 173, the lower electrode 174, the intermediate insulating film 175, the upper insulating film 176, and the lower insulating film 177 may have the same configuration as the gate trench 71, the insulating film 72, the upper electrode 73, the lower electrode 74, the intermediate insulating film 75, the upper insulating film 76, and the lower insulating film 77 shown in FIG. 9 and the like, respectively.

[0188] First and second ends of the multiple trench gate structures 170 are respectively connected by a trench connection structure 190. The configuration of the trench connection structure 190 is the same as that of the trench connection structure 90 (see FIG. 7, etc.), and therefore a description thereof will be omitted.

[0189] 23, the semiconductor device 201 includes a field insulating film 155 selectively covering the first main surface 3 inside and outside the current detection region 209A. The thickness of the field insulating film 155 may be the same as that of the field insulating film 95 (see FIG. 9, etc.). The field insulating film 155 may include a silicon oxide film. The field insulating film 155 may include a silicon oxide film made of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0190] The monitor transistor 220 is on / off controlled at the same timing as the output transistor 20. The monitor transistor 220 generates a monitor current that increases and decreases in conjunction with the output current Io (see FIG. 4) of the output transistor 20. The monitor current generated by the monitor transistor 220 is provided to an overcurrent protection circuit 26 (see FIG. 4) of the control circuit 23 in the control region 7 via the connection wiring 210.

[0191] The monitor transistor 220 may include a first system monitor transistor and a second system monitor transistor corresponding to the first system transistor 21A and the second system transistor 21B, respectively. Each system monitor transistor may be on / off controlled at the same timing as the corresponding system transistor 21A, 21B, and may generate a system monitor current that increases or decreases in conjunction with an increase or decrease in the system current Is (see FIG. 4) of the corresponding system transistor 21A, 21B.

[0192] 22, one end of a connection wiring 210 is connected to the current monitor element 209. The connection wiring 210 is, for example, a single wire. The other end of the connection wiring 210 extends across the output region 6 from the inner element region 208 to the control region 7 located outside the output region 6. The connection wiring 210 connects the current monitor element 209 to the control circuit 23 (see FIG. 4) of the control region 7.

[0193] 23 and 24, the connection wiring 210 is included in the second wiring layer 13. A current signal from the current monitoring element 209 is provided via the connection wiring 210 to the overcurrent protection circuit 26 (see FIG. 4) of the control circuit 23.

[0194] 25, in a region between the control region 7 and the inner element region 208 in the output region 6, a first source wiring 98A and a second source wiring 98B are arranged above the first main surface 3. As described above, the first source wiring 98A is included in the first wiring layer 12, and the second source wiring 98B is included in the second wiring layer 13. In this region, the second wiring layer 13 includes a connection wiring 210 together with the second source wiring 98B, the first connection wiring 10A, and the second connection wiring 10B. In this region, the connection wiring 210 extends along the first direction X. The connection wiring 210 is sandwiched in the second direction Y by a plurality of second source wirings 98B. The wiring width WC1 of the connection wiring 210 is the same as the wiring width WA of each of the first connection wiring 10A and the second connection wiring 10B. The first source wiring 98A overlaps the connection wiring 210 in the normal direction Z.

[0195] The connection wiring 210 is not included in the first wiring layer 12. The connection wiring 210 is insulated and separated from the first connection wiring 10A and the second connection wiring 10B. The connection wiring 210 is also insulated and separated from the second source wiring 98B. The connection wiring 210 is also insulated and separated from the first source wiring 98A included in the first wiring layer 12.

[0196] A current signal from the current monitor element 209 (see FIG. 22) is provided to the overcurrent protection circuit 26 (see FIG. 4) of the control circuit 23 via the connection wiring 210. The overcurrent protection circuit 26 controls the on / off of the output transistor 20 based on the current signal from the current monitor element 209. When the overcurrent protection circuit 26 determines that the output region 6 is in an overcurrent state, it controls a part or all of the output transistor 20 to an off state. This prevents the semiconductor device 201 from being destroyed.

[0197] Fig. 26A is a plan view showing the output region 6 and the inner element region 308 of the semiconductor device 301 according to the third embodiment, and corresponds to Fig. 6. Fig. 26B is a cross-sectional view taken along the line XXVIB-XXVIB shown in Fig. 26A. In the third embodiment, only the parts different from the first embodiment will be mainly described, and the same reference symbols will be used for the same configurations as those described so far, and the description thereof will be omitted.

[0198] The third embodiment differs from the first embodiment in that a current monitoring element 309 as a first element is disposed in the inner element region 308. In addition, the inner element region 308 is not formed in a substantially rectangular shape but in a polygonal shape (a hexagonal shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0199] The current monitor element 309 according to the third embodiment has the same configuration as the current monitor element 209 according to the second embodiment. Therefore, a description of the current monitor element 309 will be omitted. The current monitor element 309 and the control circuit 23 (see FIG. 4) of the control region 7 are connected by a connection wiring 210.

[0200] 26B, the connection wiring 210 is sandwiched between a plurality of second source wirings 98B in the second direction Y. The connection wiring 210 has a wiring width WC2. The first source wiring 98A overlaps with the connection wiring 210 in the normal direction Z.

[0201] Although several embodiments of the present disclosure have been described above, the present disclosure can be embodied in other forms.

[0202] A modified example of the second embodiment is shown in Fig. 27. Fig. 27 is a diagram corresponding to Fig. 25. A semiconductor device 401 shown in Fig. 27 differs from the second embodiment in that the wiring width WC2 of the connection wiring 210 is wider than each of the wiring widths WA of the first connection wiring 10A and the second connection wiring 10B.

[0203] A modified example of the first embodiment is shown in Fig. 28. Fig. 28 is a view corresponding to Fig. 6. The semiconductor device 501 shown in Fig. 28 differs from the first embodiment in that no protruding portion 8a (see Fig. 6a) is formed in the inner element region 8. In this modified example, all of the trench connection structures 90 that face each other in the first direction X in the inner element region 8 are aligned in the first direction X. In this case, the first trench isolation structure 60 does not need to have the protruding portion 60a (see Fig. 6).

[0204] Moreover, the modification shown in FIG. 28 may be combined not only with the semiconductor device 1 of the first embodiment, but also with the semiconductor devices 201 and 301 of the second and third embodiments.

[0205] In the first and second embodiments, other types of temperature sensor elements may be used instead of the temperature sensor element 9. For example, a temperature sensor element may be used in which a p-type diffusion region isolated from the surroundings by a ring-shaped isolation structure equivalent to the third trench isolation structure 140 (see FIG. 22) is formed inside the inner element region 8, 208, and a trench gate structure is formed in this diffusion region.

[0206] Furthermore, the temperature sensor element 9, the current monitor element 209 and the current monitor element 309 have been given as examples of elements (first element, second element) to be placed in the inner element regions 8, 208, 308, but elements other than the temperature sensor element and the current monitor element may also be placed in the inner element regions 8, 208, 308.

[0207] In addition, although an example has been given in which the connection wirings 10A, 10B, and 210 connect the elements (first element, second element) arranged in the inner element regions 8, 208, and 308 to the control region 7, the connection wirings 10A, 10B, and 210 may be connected to regions other than the control region 7.

[0208] In addition, in each of the above-mentioned embodiments, an example was described in which a wiring structure having a first wiring layer 12 and a second wiring layer 13 was adopted, but the wiring structure is not limited to a two-layer structure and may be a three-layer structure or a multi-layer structure in which four or more layers are stacked.

[0209] In addition, in each of the above-described embodiments, an example has been described in which the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the above description and the accompanying drawings.

[0210] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects.

[0211] The following characteristics can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiment, but are not intended to limit the scope of each clause to the embodiment.

[0212] [Appendix 1-1] A semiconductor chip (2) having a main surface (3); an output region (6) formed on the main surface (3) and having output elements disposed therein; an inner element region (8, 208, 308) surrounded by the output region (6) and insulated and isolated from the output region (6), the inner element region (8, 208, 308) including a first element (9, 309) different from the output element (20); a first wiring layer (12) formed on the main surface (3) so as to cover the output region (6) and including a first output wiring (98A) electrically connected to the output element (20); a second wiring layer (13) formed on the first wiring layer (12), the second wiring layer (13) including a second output wiring (98B) electrically connected to the first output wiring (98A), and a connection wiring (10, 210) insulated and isolated from the second output wiring (98B), crossing the output region (6), and extending from the inner element region (8, 208, 308) to an outer region (7) outside the output region (6); The output element (20) is disposed below the connection wiring (10, 210), and has a trench electrode structure (70) that overlaps with the connection wiring (10, 210) in the thickness direction (Z) of the semiconductor chip (2).

[0213] According to this configuration, the connection wiring (10, 210) is included in the second wiring layer (13). Therefore, the first element (9, 309) can be arranged in the area below the connection wiring (10, 210) on the main surface (3). By arranging the first element (9, 309) below the connection wiring (10, 210), it is possible to increase the mounting efficiency of the first element (9, 309) on the main surface. This makes it possible to reduce the chip area.

[0214] [Appendix 1-2] The semiconductor device (1, 201, 301, 401, 501) described in Appendix 1-1, wherein the connection wiring (10, 210) is sandwiched by a plurality of the second output wirings (98B) in a second direction (Y) intersecting a first direction (X) in which the trench electrode structure (70) extends.

[0215] [Appendix 1-3] A semiconductor device (1, 201, 301, 401, 501) according to Appendix 1-1 or Appendix 1-2, wherein the first output wiring (98A) included in the first wiring layer (12) overlaps the connection wiring (10, 210) in the thickness direction (Z) of the semiconductor chip (2).

[0216] [Appendix 1-4] The output element (20) includes an output transistor (20) formed on the main surface (3), Further comprising an interlayer insulating layer (11) covering the main surface (3), the first wiring layer (12) and the second wiring layer (13) are formed in the interlayer insulating layer (11); The semiconductor device (1, 201, 301, 401, 501) according to any one of Supplementary Notes 1-1 to 1-3, wherein the first output wiring (98A) and the second output wiring (98B) include a source wiring (98A, 98B) connected to the output transistor (20).

[0217] [Appendix 1-5] The semiconductor device (1, 201, 301, 401, 501) according to any one of Supplementary Notes 1-1 to 1-4, wherein the trench electrode structure (70) is arranged across the entire area of ​​a second direction (Y) intersecting with the first direction (X) in a region of the output region (6) sandwiched between the outer region (7) and the inner element region (8, 208, 308) in a first direction (X) in which the trench electrode structure (70) extends.

[0218] [Appendix 1-6] the output region (6) is annular and surrounds the inner element region (8, 208, 308); The semiconductor device (1, 201, 301, 401, 501) according to appendix 1-5, wherein the output element (20) is arranged in a ring shape surrounding the inner element region (8, 208, 308).

[0219] [Appendix 1-7] The semiconductor device (1, 201, 301, 401, 501) according to any one of Supplementary Notes 1-1 to 1-6, further including an annular isolation structure (100) that surrounds the inner element region (8, 208, 308) and insulates and isolates the inner element region (8, 208, 308) from the output region (6).

[0220] [Appendix 1-8] The semiconductor device (1, 201, 301, 401, 501) according to any one of claims 1 to 7, wherein the isolation structure (100) includes an isolation electrode (103) embedded in the isolation trench (101) with an isolation insulator (102) therebetween.

[0221] [Appendix 1-9] the connection wiring (10, 210) includes a plurality of the connection wirings (10, 210), The semiconductor device (201, 301, 401) according to any one of Supplementary Notes 1-1 to 1-8, wherein a width (WC2) of at least one of the plurality of connection wirings (10, 210) is different from a width (WA) of the other connection wirings (10).

[0222] [Appendix 1-10] The semiconductor device (1, 201, 401, 501) according to any one of Supplementary Notes 1-1 to 1-9, wherein the first element (9) includes a temperature sensor element (9) that detects a temperature of the output region (6).

[0223] [Appendix 1-11] the temperature sensor element (9) includes a temperature sensing diode (110) and a diode wiring (116) that connects the temperature sensing diode (110) and a connection wiring (10); The semiconductor device (1, 201, 401, 501) according to appendix 1-10, wherein the diode wiring (116) is included in the first wiring layer (12).

[0224] [Appendix 1-12] The semiconductor device (201, 401, 501) according to any one of Supplementary Notes 1-1 to 1-11, wherein a second element (209) different from the first element (9) is further disposed in the inner element region (208).

[0225] [Appendix 1-13] The semiconductor device (201, 401, 501) according to appendix 1-12, wherein the second element (209) includes a current monitor element (209) that detects an output current (Io) generated by the output element (20).

[0226] [Appendix 1-14] The semiconductor device (301, 401, 501) according to any one of Supplementary Notes 1-1 to 1-9, wherein the first element (309) includes a current monitoring element (309) that detects an output current (Io) generated by the output element (20).

[0227] [Appendix 1-15] The semiconductor device (1, 201, 301, 401, 501) according to any one of Supplementary Notes 1-1 to 1-14, wherein the outer region (7) includes a control region (7) that generates a control signal. [Explanation of symbols]

[0228] 1: Semiconductor device 2: Semiconductor chips 3: First main surface (main surface) 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: Output area 7: Control area (outer area) 8: Inner element region 8a: Convex part 9: Temperature sensor element (first element) 10: Connection wiring 10A: First connection wire 10B: Second connection wiring 11: Interlayer insulation layer 12: 1st wiring layer 13: 2nd wiring layer 16: Gate wiring 16A: First system gate wiring 16B: Second system gate wiring 17: Source terminal 18: Control terminal 19: Drain terminal 20: Output transistor 21: System transistor 21A: First system transistor 21B: Second system transistor 22: Unit transistor 23: Control circuit 24: Gate control circuit 25: Current monitor circuit 26: Overcurrent protection circuit 27: Overheat protection circuit 28: Low voltage malfunction prevention circuit 29: Load open detection circuit 30: Active clamp circuit 32: Logic circuit 51: First semiconductor region 52: Second semiconductor region 60: First trench isolation structure 60a: Convex part 61: First isolation trench 62: First isolation insulating film 63: 1st separation electrode 67: First body region 70: Trench gate structure (trench electrode structure) 71: Gate trench 72: Insulating film 73: Upper electrode 74: Lower electrode 75: Intermediate insulating film 76: Upper insulating film 77: Lower insulating film 78: Channel cell 79: Source area 80: Contact area 81: Block area 81A: First block area 81B: Second block area 90: Trench connection structure 91: Connection trench 92: Connection insulating film 93: Connection electrode 94: Main surface insulating film 95: Field insulating film 97: Via electrode 98: Source wiring 98A: 1st source wiring (1st output wiring) 98B: Second source wiring (second output wiring) 100: Second trench isolation structure (isolation structure) 100a: Convex part 101: Second isolation trench (isolation trench) 102: Second isolation insulating film (isolation insulator) 103:Second separation electrode (separation electrode) 110: Temperature sensing diode 111: Temperature-sensitive diode element 113: Polysilicon layer 113a: 1st page 113b: 2nd side 114: Anode region 115: Cathode region 116: Diode wiring 116b: Other end 117: Via electrode 120: Gate connection wiring 121: First gate connection wiring 121A: Via electrode 122: Second gate connection wiring 122A: Via electrode 123: Third gate connection wiring 140: Third trench isolation structure 141: Third isolation trench 142: Third isolation insulating film 143:Third separation electrode 155: Field insulating film 161: First gate wiring 162: Second gate wiring 167: Second body region 170: Trench gate structure 171: Gate trench 172: Insulating film 173: Upper electrode 174: Lower electrode 175: Intermediate insulating film 176: Upper insulating film 177: Lower insulating film 179: Source area 180: Contact area 190: Trench connection structure 191: Semiconductor devices 192: area 201: Semiconductor device 208: Inner element region 209: Current monitor element (second element) 209A: Current detection area 210: Connection wiring 301: Semiconductor device 308: Inner element region 309: Current monitor element (first element) 401: Semiconductor device 501: Semiconductor device D1: First separation depth D2: Trench depth D3: Second separation depth D4: Third separation depth D5: Trench depth I1: First interval Io: Output current Is: Grid current Iu: unit current L: Inductive load W1: 1st separation width W2: Trench width W3: 2nd separation width W4: 3rd separation width W5: Trench width WA: Wiring width WC1: Wiring width WC2: Wiring width X: 1st direction Y: Second direction Z: Normal direction (thickness direction)

Claims

1. a semiconductor chip having a major surface; an output region formed on the main surface and having output elements disposed therein; an inner element region surrounded by the output region and insulated and separated from the output region, the inner element region including a first element different from the output element; a first wiring layer formed on the main surface so as to cover the output region and including first output wiring electrically connected to the output element; a second wiring layer formed on the first wiring layer, the second wiring layer including a second output wiring electrically connected to the first output wiring, and a connection wiring insulated and separated from the second output wiring, crossing the output region, and extending from the inner element region to an outer region outside the output region; The output element is disposed below the connection wiring and has a trench electrode structure overlapping the connection wiring in a thickness direction of the semiconductor chip.

2. 2 . The semiconductor device according to claim 1 , wherein said connection wiring is sandwiched between a plurality of said second output wirings in a second direction intersecting with a first direction in which said trench electrode structure extends.

3. 3 . The semiconductor device according to claim 1 , wherein the first output wiring included in the first wiring layer overlaps the connection wiring in the thickness direction of the semiconductor chip.

4. the output element includes an output transistor formed on the main surface, Further comprising an interlayer insulating layer covering the main surface, the first wiring layer and the second wiring layer are formed in the interlayer insulating layer; 3. The semiconductor device according to claim 1, wherein the first output wiring and the second output wiring include a source wiring connected to the output transistor.

5. 3. The semiconductor device according to claim 1, wherein the trench electrode structure is arranged across an entire area of ​​a second direction intersecting the first direction in a region of the output region sandwiched between the outer region and the inner element region in a first direction in which the trench electrode structure extends.

6. the output region is annular and surrounds the inner element region; The semiconductor device according to claim 5 , wherein said output elements are arranged in a ring shape surrounding said inner element region.

7. 3. The semiconductor device according to claim 1, further comprising an annular isolation structure surrounding said inner element region and insulating and isolating said inner element region from said output region.

8. 8. The semiconductor device of claim 7, wherein the isolation structure includes an isolation electrode embedded in an isolation trench with an isolation insulator therebetween.

9. the connection wiring includes a plurality of the connection wirings, 3. The semiconductor device according to claim 1, wherein a width of at least one of said plurality of connection wirings is different from a width of the other connection wirings.

10. 3. The semiconductor device according to claim 1, wherein the first element includes a temperature sensor element that detects a temperature of the output region.

11. the temperature sensor element includes a temperature sensing diode and a diode wiring that connects the temperature sensing diode and the connection wiring, The semiconductor device according to claim 10 , wherein the diode wiring is included in the first wiring layer.

12. The semiconductor device according to claim 1 , further comprising a second element different from the first element, disposed in the inner element region.

13. 13. The semiconductor device according to claim 12, wherein said second element includes a current monitor element that detects an output current generated by said output element.

14. 3. The semiconductor device according to claim 1, wherein said first element includes a current monitor element that detects an output current generated by said output element.

15. The semiconductor device according to claim 1 , wherein the outer region includes a control region for generating a control signal.

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