Silicon carbide semiconductor device and method for manufacturing the same

Abstract

To reduce the ON-resistance of a silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device includes: a semiconductor substrate SB made of 4H-SiC; a collector region CR formed within the semiconductor substrate SB; a contact layer CL that is in contact with the collector region CR and includes a silicide region SCR and a non-silicide region NSCR; and a collector electrode CE that is in contact with the contact layer CL. In the silicide region SCR, a silicide layer SC that has an upper surface and a lower surface is formed. An altered layer AL made of 3C-SiC is interposed between the upper surface of the silicide layer SC and the collector region CR. The lower surface of the silicide layer SC is in contact with the collector electrode CE.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing the same, and in particular to an IGBT. [Background technology]

[0002] In an IGBT (Insulated Gate Bipolar Transistor), a silicide layer is interposed between a collector region and a collector electrode in order to form a low-resistance ohmic electrode for a p-type silicon carbide semiconductor layer.

[0003] For example, Patent Document 1 discloses an ohmic electrode including an aluminum-containing silicon alloy layer deposited on the back surface of a p-type silicon carbide epitaxial layer (the aforementioned "collector region"), and an aluminum-containing titanium alloy layer deposited on the silicon alloy layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-154174 A Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, an aluminum electrode layer and a titanium electrode layer are sequentially deposited on the back side of a p-type silicon carbide epitaxial layer, and then the titanium electrode layer and the aluminum electrode layer are irradiated with laser light to form an ohmic electrode. However, according to the study by the present inventors, it was found that the crystalline state between the p-type silicon carbide epitaxial layer, the ohmic electrode (silicide layer), and the collector electrode affects the contact resistance. In other words, there is a problem that the ON resistance of the IGBT element increases depending on the crystalline state.

[0006] For this reason, it is desirable to reduce the ON resistance of silicon carbide semiconductor devices such as IGBT elements.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief outline of a representative embodiment of the present invention will be described below.

[0009] A silicon carbide semiconductor device according to one embodiment includes a semiconductor substrate having a first main surface and a second main surface located opposite to each other in a thickness direction thereof and made of 4H-SiC, a semiconductor layer formed in the semiconductor substrate at the second main surface of the semiconductor substrate, a contact layer in contact with the second main surface of the semiconductor substrate and including a silicide region and a non-silicide region, and an electrode in contact with the contact layer and formed on the opposite side of the semiconductor substrate with respect to the contact layer. A silicide layer having an upper surface and a lower surface is formed in the silicide region, an altered layer made of 3C-SiC is interposed between the upper surface of the silicide layer and the semiconductor layer, and the lower surface of the silicide layer is in contact with the electrode.

[0010] A method for manufacturing a silicon carbide semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate made of 4H-SiC and having a first main surface and a second main surface located opposite each other in a thickness direction of the semiconductor substrate, (b) forming a metal layer on the second main surface of the semiconductor substrate so as to contact a semiconductor layer formed in the semiconductor substrate, (c) selectively irradiating the metal layer with a laser beam to form a contact layer including a silicide region and a non-silicide region, and (d) forming an electrode on the contact layer. In the step (c), a silicide layer including the metal layer is formed in the silicide region where the metal layer is irradiated with the laser beam, and the metal layer is left in the non-silicide region where the metal layer is not irradiated with the laser beam, and an altered layer made of 3C-SiC is formed at the boundary between the semiconductor layer and the silicide layer in the silicide region. Effect of the Invention

[0011] According to one embodiment, the ON resistance of a silicon carbide semiconductor device can be reduced. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view of an IGBT according to an embodiment. [Diagram 2] 2 is a cross-sectional view illustrating the operation (on state) of the IGBT according to the embodiment. FIG. [Diagram 3] 2 is a plan view of a contact layer of the IGBT according to the embodiment. [Figure 4] 1 is a diagram showing the relationship between the area ratio of a non-silicide region in a contact layer of an IGBT and an increase in on-state voltage in an embodiment. [Diagram 5] 2 is an image diagram of a band diagram from a collector region to a collector electrode of an IGBT according to an embodiment. FIG. [Figure 6] 3A to 3C are cross-sectional views of an IGBT during a manufacturing process in the embodiment. [Figure 7] 7 is a cross-sectional view of the IGBT during the manufacturing process, following FIG. 6. [Figure 8] 8 is a cross-sectional view of the IGBT during the manufacturing process, following FIG. 7. [Figure 9] 9 is a cross-sectional view of the IGBT during the manufacturing process, following FIG. 8. [Figure 10] 10 is a cross-sectional view of the IGBT during the manufacturing process, following FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view of an IGBT according to a first modified example. [Figure 12] FIG. 11 is a cross-sectional view of an IGBT according to a second modified example. [Figure 13] FIG. 11 is a cross-sectional view of a power MOSFET according to a third modification. [Figure 14] FIG. 11 is a cross-sectional view of a power MOSFET according to a fourth modified example. [Figure 15] FIG. 13 is a cross-sectional view of a power MOSFET according to a fifth modified example. [Figure 16] FIG. 13 is a cross-sectional view of a PN diode in Modification 6. [Figure 17] FIG. 13 is a cross-sectional view of a JBS diode according to Modification 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, the same reference numerals are used for components having the same functions, and repeated explanations are omitted. In the following embodiments, explanations of the same or similar parts will not be repeated in principle, unless otherwise necessary.

[0014] In addition, in the drawings used in the embodiments, hatching may be omitted or may be added in order to make the drawings easier to understand.

[0015] In addition, although the embodiments are described in sufficient detail for a person skilled in the art to implement the present disclosure, other implementations and forms are possible. It should be understood that configuration and structure changes and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0016] Silicon carbide (SiC) has many crystal polytypes such as 3C-SiC, 4H-SiC, and 6H-SiC due to differences in overlapping of the Si plane and the C plane. In the following embodiments, a silicon carbide layer (silicon carbide substrate) having a 3C-SiC crystal structure is referred to as 3C-SiC, and a silicon carbide layer (silicon carbide substrate) having a 4H-SiC crystal structure is referred to as 4H-SiC.

[0017] In addition, the expression "a layer consisting of..." means "a layer containing... as a main material", and includes cases where other impurities are contained in the layer.

[0018] Also, "p-type" means "p-type conductivity" and "n-type" means "n-type conductivity."

[0019] In addition, in the drawings of the embodiments and modifications, the first main surface side of the semiconductor substrate (the upper side of the drawings) is expressed as "upper", and the second main surface side (the lower side of the drawings) is expressed as "lower".

[0020] (Embodiment) <Structure of the IGBT according to this embodiment> A silicon carbide semiconductor device (particularly an IGBT) according to an embodiment will be described with reference to Figs. 1 to 5. Fig. 1 is a cross-sectional view of an IGBT. Fig. 2 is a cross-sectional view explaining the operation (on state) of the IGBT. Fig. 3 is a plan view of a contact layer of the IGBT. Fig. 4 is a diagram showing the relationship between the area ratio of a non-silicide region in a contact layer of an IGBT and an increase in on-voltage. Fig. 5 is an image diagram of a band diagram from the collector region to the collector electrode of an IGBT.

[0021] As shown in FIG. 1, the IGBT has a semiconductor substrate SB made of 4H-SiC. The semiconductor substrate SB is an epitaxial substrate having a desired film thickness, and has a first main surface SBa and a second main surface SBb located opposite to each other in the film thickness direction. Here, the side on which the emitter electrode EE is formed is referred to as the first main surface SBa, and the side on which the collector electrode CE is formed is referred to as the second main surface SBb. However, the side on which the emitter electrode EE is formed can also be referred to as the second main surface SBa, and the side on which the collector electrode CE is formed can also be referred to as the first main surface SBb. The semiconductor substrate SB has, from the second main surface SBb side to the first main surface side, a p-type collector region CR (sometimes referred to as a semiconductor layer SL), an n-type buffer layer BL (sometimes referred to as a semiconductor layer SL), and an n-type drift layer DL (sometimes referred to as a semiconductor layer SL), in that order. The drift layer DL is formed from an end of the buffer layer BL to the first main surface SBa. The p-type collector region CR is a p-type semiconductor region containing, for example, aluminum (Al) or boron (B) as a dopant. The n-type buffer layer BL and the n-type drift layer DL are n-type semiconductor regions containing, for example, nitrogen (N) or phosphorus (P) as a dopant. The impurity concentration of the drift layer DL is lower than the impurity concentration of the buffer layer BL. Although it depends on the element rating of the IGBT, the impurity concentration of the drift layer DL is, for example, 1×10 14 cm -3 Greater than or equal to 1×10 17 cm -3 The thickness of the drift layer DL is preferably, for example, 30 μm or more and 150 μm or less.

[0022] In the drift layer DL, a plurality of p-type body regions PBR (sometimes called semiconductor layers SL) are formed apart from each other from the first main surface SBa of the semiconductor substrate SB to the intermediate depth of the drift layer DL. In the p-type body region PBR, an n-type emitter region ER (sometimes called semiconductor layer SL) and a p-type body contact region PBC (sometimes called semiconductor layer SL) are formed. The n-type emitter region ER and the p-type body contact region PBC are formed from the first main surface SBa of the semiconductor substrate SB to the intermediate depth of the body region PBR. In the film thickness direction of the semiconductor substrate SB and the direction along the first main surface SBa, the emitter region ER is separated from the drift layer DL, and the body region PBR is interposed between the emitter region ER and the drift layer DL. The body region PBR and the body contact region PBC are p-type semiconductor regions containing, for example, aluminum (Al) or boron (B) as a dopant. The impurity concentration of the body contact region PBC is higher than the impurity concentration of the body region PBR. The emitter region ER is an n-type semiconductor region containing, for example, nitrogen (N) or phosphorus (P) as a dopant. The impurity concentration of the emitter region ER is higher than the impurity concentration of the drift layer DL.

[0023] A gate electrode GE is formed on the first main surface SBa of the semiconductor substrate SB via a gate insulating film GI so as to cover the body region PBR between the emitter region ER and the drift layer DL in a direction along the first main surface SBa. The gate electrode GE is formed across the emitter region ER, the body region PBR, and the drift layer DL. The gate insulating film GI includes, for example, a silicon oxide film, and the thickness thereof is preferably, for example, 0.05 μm or more and 0.15 μm or less. The gate electrode GE includes, for example, a polysilicon film, and the thickness thereof is preferably, for example, 0.2 μm or more and 0.5 μm or less. An interlayer insulating film IF is formed on the gate electrode GE. The interlayer insulating film IF covers the upper surface and sidewalls of the gate electrode GE.

[0024] A silicide layer SCU is formed in a region exposed from the interlayer insulating film IF in the first main surface SBa of the semiconductor substrate SB. The silicide layer SCU is in contact with the emitter region ER and the body contact region PBC. An emitter electrode EE is formed on the first main surface SBa of the semiconductor substrate SB so as to cover the gate electrode GE, the emitter region ER, and the body contact region PBC. The emitter electrode EE is electrically isolated from the gate electrode GE by the interlayer insulating film IF. The emitter electrode EE is connected to the emitter region ER and the body contact region PBC via the silicide layer SCU. The silicide layer SCU is formed so as to cover both the emitter region ER and the body contact region PBC, but may be formed so as to cover only one of the emitter region ER or the body contact region PBC. In other words, the silicide layer SCU may be structured so as to be in contact with only one of the emitter region ER or the body contact region PBC. The silicide layer SCU is, for example, nickel silicide (NiSi). The emitter electrode EE is a laminated film including, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film in this order from the silicide layer SCU side. In order to reduce the resistance of the emitter electrode EE, it is preferable to set the thickness of the aluminum film to 1.0 μm or more.

[0025] A contact layer CL is formed below the second main surface SBb of the semiconductor substrate SB so as to be in contact with the second main surface SBb, and a collector electrode CE is formed below the contact layer CL so as to be in contact with the contact layer CL. In the direction along the second main surface SBb, for example, the contact layer CL covers the entire area of ​​the second main surface SBb, and the collector electrode CE covers the entire area of ​​the contact layer CL.

[0026] In a direction along the second main surface SBb, the contact layer CL includes a silicide region SCR and a non-silicide region NSCR. A silicide layer SC is formed in the silicide region SCR, and a metal layer ML is formed in the non-silicide region NSCR. In addition, an altered layer AL, which is an n-type semiconductor layer, is formed in the collector region CR corresponding to the silicide region SCR. The altered layer AL is included in the collector region CR.

[0027] The silicide layer SC formed in the silicide region SCR, which is a part of the contact layer CL, is an alloy layer containing aluminum (Al), titanium (Ti), silicon (Si), carbon (C) and oxygen (O). As described later, the silicide layer SC is an alloy layer between a metal layer containing aluminum (Al) and titanium (Ti) and a semiconductor substrate SB made of 4H-SiC, in other words, a collector region CR (semiconductor layer SL) made of 4H-SiC. In the silicide region SCR, the silicide layer SC is sandwiched between the collector region CR (semiconductor layer SL) and the collector electrode CE, and is in contact with the collector region CR and the collector electrode CE. The metal layer ML formed in the non-silicide region NSCR, which is a part of the contact layer CL, contains, for example, aluminum (Al) and titanium (Ti). The metal layer ML may be a laminated film of an aluminum (Al) film and a titanium (Ti) film, or may be an alloy layer containing aluminum (Al) and titanium (Ti). In the non-silicide region NSCR, the metal layer ML is sandwiched between the collector region CR (semiconductor layer SL) and the collector electrode CE, and is in contact with the collector region CR and the collector electrode CE.

[0028] The altered layer AL is a part of the p-type collector region CR (semiconductor layer SL) made of 4H-SiC, and is a p-type semiconductor layer SL made of 3C-SiC. The altered layer AL is a p-type semiconductor layer SL in which the crystal polytype of the p-type collector region CR (semiconductor layer SL) made of 4H-SiC has been altered to 3C-SiC.

[0029] The collector electrode CE includes, for example, a laminated metal film of an aluminum (Al) film and a gold (Au) film. The aluminum (Al) film is in contact with the contact layer CL and is formed below the contact layer CL. The aluminum (Al) film is formed, for example, to cover the entire area of ​​the contact layer CL in the direction along the second main surface SBb. The gold (Au) film is in contact with the aluminum (Al) film and is formed below the aluminum (Al) film. The gold (Au) film is formed, for example, to cover the entire area of ​​the aluminum (Al) film in the direction along the second main surface SBb.

[0030] That is, the IGBT has a stacked structure in the silicide region SCR, which includes a collector region CR (semiconductor layer SL) made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a collector electrode CE. In the silicide region SCR, the collector electrode CE is ohmically connected to the collector region CR (semiconductor layer SL) via the silicide layer SC. In other words, in the silicide region SCR, the collector electrode CE is ohmically connected to the collector region CR (semiconductor layer SL) including the altered layer AL made of 3C-SiC via the silicide layer SC. In the silicide region SCR, the collector region CR and the collector electrode CE are connected with low resistance by interposing the silicide layer SC between them. Also, in the non-silicide region NSCR, the IGBT has a stacked structure in the collector region CR (semiconductor layer SL) made of 4H-SiC, a metal layer ML, and a collector electrode CE. In the non-silicide region NSCR, a metal layer ML is interposed between the collector region CR and the collector electrode CE, and a silicide layer SC is not interposed, so that the collector region CR and the collector electrode CE are connected with a higher resistance than in the silicide region SCR.

[0031] In addition, since the silicide layer SC is an alloy layer consisting of the collector region CR (semiconductor layer SL) made of 4H—SiC and a metal film containing aluminum (Al) and titanium (Ti), the upper surface of the silicide layer SC may extend beyond the second main surface SBb and extend into the collector region CR (semiconductor layer SL).

[0032] <Operation of IGBT> Using FIG. 2, the operation (on state) of the IGBT will be described. Although not shown, in the on state of the IGBT, for example, 0V is applied to the emitter electrode EE, Vge (>Vth>0V) is applied to the gate electrode GE, and Vce (>>0V) is applied to the collector electrode CE. Vge represents the voltage of the gate electrode GE with respect to the emitter electrode EE, and Vce represents the voltage of the collector electrode CE with respect to the emitter electrode EE. Vth is the threshold voltage of the MOSFET (field effect transistor) composed of the gate electrode GE, the n-type emitter region ER, the n-type drift layer DL, and the p-type body region PBR. That is, a voltage higher than the threshold voltage Vth of the MOSFET is applied to the gate electrode GE, and a positive high voltage is applied to the collector electrode CE.

[0033] When Vge (>Vth) is applied to the gate electrode GE, an inversion layer is formed on the surface (the first main surface SBa side) of the p-type body region PBR, and a large amount of electrons (e) flow from the n-type emitter region ER to the n-type drift layer DL. A part of the electrons (e) flowing into the drift layer DL flows into the p-type collector region CR. Simultaneously with the flow of these electrons (e), the PN junction composed of the p-type collector region CR, the n-type buffer layer BL, and the n-type drift layer DL becomes forward-biased, and a large amount of holes (h) are injected from the collector region CR into the drift layer DL. This corresponds to the current flowing from the collector electrode CE to the emitter electrode EE. Since a large amount of electrons (e) and holes (h) are injected into the drift layer DL, the concentrations of electrons (e) and holes (h) in the n-type drift layer DL increase dramatically, and conductivity modulation of the n-type drift layer DL occurs. Therefore, since the on-resistance with respect to the current flowing from the collector electrode CE to the emitter electrode EE becomes low, the current driving ability of the IGBT is significantly improved.

[0034] As described above, when a large amount of holes (h) are injected from the collector region CR to the drift layer DL, the concentration of holes (h) in the collector region CR decreases. Then, in order to replenish the holes (h) in the collector region CR, holes (h) are injected from the collector electrode CE to the collector region CR through the contact layer CL. Here, holes (h) are injected from the collector electrode CE to the collector region CR through the silicide region SCR of the contact layer CL. In the non-silicide region NSCR of the contact layer CL, holes (h) are not injected from the collector electrode CE to the collector region CR. This is because, as described above, in the silicide region SCR, the collector region CR and the collector electrode CE are connected with a low resistance, and in the non-silicide region NSCR, the collector region CR and the collector electrode CE are connected with a high resistance.

[0035] <About the contact layer CL> The contact layer CL will be described with reference to Figs. 3 and 4. Fig. 3 is a plan view of the contact layer CL. As shown in Fig. 3, the contact layer CL includes a silicide region SCR and a non-silicide region NSCR. The silicide region SCR is composed of a collection of a plurality of units. The shape of each unit is, for example, an ellipse in a plan view. The silicide region SCR is composed of a plurality of units arranged in a matrix. However, the shape and arrangement of the units are not limited to this.

[0036] Here, it is essential that the contact layer CL includes both the silicide region SCR and the non-silicide region NSCR. In plan view, if the entire area of ​​the contact layer CL (in other words, the entire area of ​​the second main surface SBb of the semiconductor substrate SB) is made into the silicide region SCR, the holes (h) injected from the collector electrode CE into the collector region CR will be excessive. Therefore, by limiting the area of ​​the silicide region SCR into which the holes (h) can be injected, the amount of holes (h) injected from the collector electrode CE into the collector region CR (in other words, the amount of holes (h) injected into the drift layer DL) is limited. In other words, limiting the area of ​​the silicide region SCR leads to securing a predetermined area of ​​the non-silicide region NSCR with respect to the entire area of ​​the contact layer CL (in other words, the entire area of ​​the second main surface SBb of the semiconductor substrate SB). According to the study by the present inventor, it was found that the area ratio of the non-silicide region NSCR needs to be 10% or more. Here, the area ratio of the non-silicide region NSCR is the ratio of the area of ​​the non-silicide region NSCR to the area of ​​the second main surface SBb of the semiconductor substrate SB.

[0037] Next, the reason why the non-silicide region NSCR is necessary in the contact layer CL will be explained. The semiconductor substrate SB made of silicon carbide described above is generally formed by using an epitaxial growth method. The semiconductor substrate SB made of silicon carbide has defects called basal plane dislocations (BPDs). For example, when the BPD defects exist in the drift layer DL shown in FIG. 2, a large amount of holes (h) are supplied to the drift layer DL, and the BPD defects become the starting point to generate planar stacking faults. The phenomenon in which the on-voltage of the IGBT increases due to planar stacking faults is called bipolar degradation. Note that bipolar degradation is a phenomenon specific to bipolar devices formed on silicon carbide substrates. In the IGBT of this embodiment, the area ratio of the non-silicide region NSCR of the contact layer CL is set to 10% or more, thereby limiting the injection of holes (h) into the drift layer DL and suppressing bipolar degradation.

[0038] 4 is a diagram showing the relationship between the area ratio of the non-silicide region NSCR of the contact layer CL and the increase in the on-voltage of the IGBT. According to the study by the inventors of the present application, it has been confirmed that when the area ratio of the non-silicide region NSCR exceeds 60%, the on-voltage of the IGBT increases significantly. In other words, it is essential to set the area ratio of the non-silicide region NSCR to 60% or less. Therefore, in order to suppress the above-mentioned bipolar deterioration and reduce the on-voltage of the IGBT, it is essential to set the area ratio of the non-silicide region NSCR to 10% or more and 60% or less.

[0039] <About the altered AL layer> As shown in Fig. 1, the IGBT of this embodiment has a laminated structure in the silicide region SCR, which is made of a collector region CR made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a collector electrode CE. Fig. 5 is an image of a band diagram from the collector region CR to the collector electrode CE of the IGBT. In other words, it corresponds to a band diagram of the laminated structure formed in the silicide region SCR. Fig. 5 shows the conduction band minimum E in the p-type collector region CR made of 4H-SiC, the p-type collector region CR made of 3C-SiC (corresponding to the altered layer AL in Fig. 1), the silicide layer SC, and the collector electrode CE. C , Fermi level E F and the upper limit of the valence band E V The conduction band minimum E C and the upper limit of the valence band E V The width between the valence band and the collector electrode CE is the band gap. The band gap (2.4 eV) of the p-type collector region CR made of 3C-SiC is smaller than the band gap (3.3 eV) of the p-type collector region CR made of 4H-SiC. By interposing the collector region CR made of 3C-SiC (corresponding to the altered layer AL in Fig. 1) with a small band gap between the collector region CR made of 4H-SiC and the silicide layer SC, the band diagram (here, the upper end E V ) becomes stepped, and the resistance between the collector region CR made of 4H—SiC and the collector electrode CE can be made low.

[0040] <Features of the IGBT of this embodiment> As shown in Fig. 1, the IGBT of this embodiment has a stacked structure in the silicide region SCR, which includes a collector region CR (semiconductor layer SL) made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a collector electrode CE. Therefore, in the silicide region SCR, the collector electrode CE is ohmically connected to the collector region CR (semiconductor layer SL) via the silicide layer SC. In addition, by interposing the collector region CR (corresponding to the altered layer AL in Fig. 1) made of 3C-SiC with a small band gap between the collector region CR made of 4H-SiC and the silicide layer SC, the resistance between the p-type collector region CR made of 4H-SiC and the collector electrode CE can be reduced. In other words, the ON resistance of the IGBT can be reduced.

[0041] As shown in Fig. 1, the IGBT of this embodiment includes a contact layer CL between a collector region CR and a collector electrode CE. The contact layer CL includes a silicide region SCR and a non-silicide region NSCR, and the area ratio of the non-silicide region NSCR is set to 10% or more and 60% or less. Therefore, it is possible to suppress bipolar deterioration and reduce the on-voltage of the IGBT.

[0042] <Method of manufacturing IGBT according to this embodiment> A method for manufacturing the IGBT of this embodiment will be described with reference to Figures 6 to 10. Figures 6 to 10 are cross-sectional views of the IGBT during the manufacturing process.

[0043] First, as shown in Fig. 6, a base substrate BSB is prepared. The base substrate BSB is a silicon carbide substrate made of 4H-SiC and contains n-type impurities (for example, nitrogen (N)). The impurity concentration of the n-type impurity is 1 x 10 18 cm -3 Greater than or equal to 1×10 21 cm -3The range is as follows. The surface of the silicon carbide substrate may be either the Si surface or the C surface. Next, a p-type collector region CR, an n-type buffer layer BL, and an n-type drift layer DL are formed in this order on the base substrate BSB by epitaxial growth. The p-type collector region CR, the n-type buffer layer BL, and the n-type drift layer DL constitute a semiconductor substrate SB, which is an epitaxial substrate and is a silicon carbide substrate made of 4H-SiC. The p-type collector region CR, the n-type buffer layer BL, and the n-type drift layer DL are each a silicon carbide layer (semiconductor layer SL) made of 4H-SiC.

[0044] Next, as shown in Fig. 7, a p-type body region PBR, an n-type emitter region ER, and a p-type body contact region PBC are formed in the drift layer DL. The body region PBR, the emitter region ER, and the body contact region PBC are formed by using an ion implantation method. The locations where they are formed are as described with reference to Fig. 1.

[0045] Next, as shown in FIG. 8, a gate electrode GE is formed on the first main surface via a gate insulating film GI. The gate insulating film GI is, for example, a thermal oxide film (silicon oxide film) or a CVD oxide film (silicon oxide film) formed by using a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. The gate insulating film GI may be a laminated film of a thermal oxide film and a CVD oxide film formed on the thermal oxide film. The gate electrode GE is formed by patterning a polysilicon film deposited on the gate insulating film GI. Note that photolithography and etching are used for patterning the polysilicon film. The polysilicon film constituting the gate electrode GE contains n-type or p-type impurities. The thickness of the gate insulating film GI is, for example, 0.05 μm or more and 0.15 μm or less. The thickness of the gate electrode GE is, for example, 0.2 μm or more and 0.5 μm or less.

[0046] Next, as shown in FIG. 8, an interlayer insulating film IF is formed. The interlayer insulating film IF covers an upper surface of the gate electrode GE and side surfaces of the gate electrode GE and the gate insulating film GI. The interlayer insulating film IF is formed by, for example, a plasma CVD method so as to cover the first main surface SBa and the gate electrode GE. Next, the interlayer insulating film IF is processed using a photolithography technique and an etching method to expose the emitter region ER and the body contact region PBC on the first main surface SBa.

[0047] 8, a silicide layer SCU is formed on the exposed surfaces of the emitter region ER and the body contact region PBC. The silicide layer SCU is, for example, nickel silicide (NiSi). After depositing a nickel (Ni) film with a thickness of, for example, about 0.05 μm on the first main surface SBa, a heat treatment at 600° C. or more and 1000° C. or less is performed to form the silicide layer SCU on the surfaces of the emitter region ER and the body contact region PBC.

[0048] Next, as shown in Fig. 8, an emitter electrode EE is formed on the interlayer insulating film IF and the silicide layer SCU. The emitter electrode EE is made of a laminated film in which a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film are laminated in this order on the first main surface SBa. The emitter electrode EE is electrically connected to the emitter region ER and the body contact region PBC via the silicide layer SCU.

[0049] Next, the base substrate BSB shown in FIG. 8 is removed using a grinding technique to expose the second main surface SBb of the semiconductor substrate SB. Here, the gate electrode GE, the emitter electrode EE, and the like are formed on the semiconductor substrate SB, and then the base substrate BSB is removed. However, if the semiconductor substrate SB has sufficient strength, the gate electrode GE, the emitter electrode EE, and the like may be formed on the semiconductor substrate SB after removing the base substrate BSB. Furthermore, if a p-type silicon carbide substrate is used as the base substrate BSB, it is not necessary to completely remove the base substrate BSB. Furthermore, the grinding step of the base substrate BSB may be omitted.

[0050] Next, as shown in FIG. 9, a metal layer ML is formed below the second main surface SBb. For example, the metal layer ML is a laminated film (two-layer film) of an aluminum (Al) film in contact with the collector region CR on the second main surface SBb, and a titanium (Ti) film in contact with the aluminum (Al) film below the aluminum (Al) film. The laminated film may be a three-layer film. For example, a nickel (Ni) film, a molybdenum (Mo) film, a cobalt (Co) film, a titanium nitride (TiN) film, a gold (Au) film, a germanium (Ge) film, or a tungsten (W) film may be further provided below the titanium (Ti) film in contact with the lower side of the aluminum (Al) film. The total thickness of the laminated film is preferably 50 nm or more and 300 nm or less. The metal layer ML may also be an alloy layer containing aluminum (Al) and titanium (Ti).

[0051] Next, as shown in FIG. 9, a laser annealing process is performed on the IGBT by a laser device LE. That is, the metal layer ML is selectively irradiated with laser light from the metal layer ML side toward the collector region CR. The laser light is irradiated to the silicide region SCR shown in FIG. 3. The unit described in FIG. 3 indicates the irradiation region of the laser light per one time. Then, as shown in FIG. 10, a contact layer CL having the silicide region SCR and the non-silicide region NSCR and an altered layer AL made of 3C-SiC are formed. In the silicide region SCR irradiated with the laser light, the silicide layer SC and the altered layer AL are formed. In the non-silicide region NSCR not irradiated with the laser light, the silicide layer SC and the altered layer AL are not formed, and the metal layer ML remains. Therefore, the laser irradiation conditions need to be energy equivalent to or greater than the band gap of 4H-SiC in order to form the altered layer AL made of 3C-SiC. The wavelength of the laser light is preferably, for example, 290 nm or more and 600 nm or less. The irradiation intensity of the laser light was 3.0 J / cm 2 Above 3.5 J / cm 2It is preferable that the irradiation intensity is set to 10% or less. If the irradiation intensity is too weak, the aluminum (Al) of the metal layer ML does not react with the SiC of the collector region CR, and if the irradiation intensity is too strong, the silicide layer SC may disappear from the SiC of the collector region CR. As described above, the area ratio of the non-silicide region NSCR that is not irradiated with the laser light is set to 10% or more and 60% or less.

[0052] In the laser annealing process, it is essential to irradiate the titanium (Ti) film, nickel (Ni) film, molybdenum (Mo) film, cobalt (Co) film, titanium nitride (TiN) film, gold (Au) film, germanium (Ge) film, or tungsten (W) film with the laser light, without directly irradiating the aluminum (Al) film contained in the metal layer ML with the laser light, because the aluminum (Al) film has a high reflectance to the laser light, which weakens the effect of the laser irradiation.

[0053] Next, as shown in FIG. 1, a collector electrode CE is formed below the contact layer CL.

[0054] <Features of the IGBT manufacturing method according to this embodiment> As described in FIG. 9 and FIG. 10, the metal layer ML is selectively irradiated with laser light to form a silicide layer SC in the silicide region SCR of the contact layer CL, and also form an altered layer AL made of 3C-SiC in a part of the collector region CR made of 4H-SiC. The IGBT thus manufactured has a stacked structure in the silicide region SCR made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a collector electrode CE. Therefore, in the silicide region SCR, the collector electrode CE is ohmically connected to the collector region CR via the silicide layer SC. In addition, since the altered layer AL made of 3C-SiC is interposed between the p-type collector region CR made of 4H-SiC and the silicide layer SC, the resistance between the p-type collector region CR and the collector electrode CE can be reduced. In other words, the on-resistance of the IGBT can be reduced.

[0055] Furthermore, in the laser annealing process, the efficiency of laser annealing can be improved by irradiating laser light to a titanium (Ti) film, nickel (Ni) film, molybdenum (Mo) film, cobalt (Co) film, titanium nitride (TiN) film, gold (Au) film, germanium (Ge) film or tungsten (W) film covering the aluminum (Al) film, without irradiating the laser light directly to the aluminum (Al) film contained in the metal layer ML.

[0056] By setting the area ratio of the non-silicide region NSCR to 10% or more and 60% or less, bipolar degradation can be suppressed and the on-voltage of the IGBT can be reduced.

[0057] <IGBT structure of modification example 1> The structure of an IGBT, which is a silicon carbide semiconductor device of Modification 1, will be described. Fig. 11 is a cross-sectional view of the IGBT in Modification 1. The structure of the IGBT of Modification 1 is obtained by adding an altered layer AL1 to the IGBT of the above embodiment. As shown in Fig. 11, the IGBT of Modification 1 has an altered layer AL1 made of 3C-SiC between the emitter region ER and the body contact region PBC and the silicide layer SCU.

[0058] The IGBT in the first modification has a layered structure including a p-type body contact region PBC, an altered layer AL1 made of 3C-SiC, a silicide layer SCU, and an emitter electrode EE. By interposing the altered layer AL1 made of 3C-SiC with a small band gap between the p-type body contact region PBC made of 4H-SiC and the silicide layer SCU, it is possible to reduce the resistance between the p-type body contact region PBC made of 4H-SiC and the emitter electrode EE.

[0059] The IGBT in the first modification has a layered structure made of an n-type emitter region ER, an altered layer AL1 made of 3C-SiC, a silicide layer SCU, and an emitter electrode EE. By interposing the altered layer AL1 made of 3C-SiC with a small band gap between the n-type emitter region ER made of 4H-SiC and the silicide layer SCU, it is possible to reduce the resistance between the n-type emitter region ER made of 4H-SiC and the emitter electrode EE. In the explanation of FIG. 5, if the collector region CR is replaced with the n-type emitter region ER and the collector electrode CE is replaced with the emitter electrode EE, the band diagram between the n-type emitter region ER made of 4H-SiC and the emitter electrode EE (here, the conduction band lower limit E C ) is seen to have a stepped shape.

[0060] In the first modification, an altered layer AL1 made of 3C-SiC is provided between the emitter region ER and the body contact region PBC and the silicide layer SCU, but a structure in which an altered layer AL1 is provided between either the emitter region ER or the body contact region PBC and the emitter electrode EE may also be used.

[0061] <IGBT structure of modified example 2> The structure of a trench-gate IGBT, which is a silicon carbide semiconductor device of the second modification, will be described. FIG. 12 is a cross-sectional view of the IGBT of the second modification. In the IGBT of the second modification, the gate electrode GE of the IGBT of the above embodiment is disposed in a groove TR provided in the first main surface SBa. The groove TR extends from the first main surface SBa toward the second main surface SBb, and reaches the drift layer DL through the body region PBR. The gate electrode GE is formed in the groove TR via a gate insulating film GI. The IGBT of the second modification is similar to the IGBT of the above embodiment except for the structure of the gate electrode GE, and therefore has the same effect as the IGBT of the above embodiment. The altered layer AL1 of the first modification may be added to the trench-gate IGBT of the second modification.

[0062] <Structure of power MOSFET of modification 3> In the third modification, the contact layer CL and the altered layer AL, which are features of the above embodiment, are applied to a power MOSFET. Fig. 13 is a cross-sectional view of the power MOSFET in the third modification. The power MOSFET of the third modification has a structure in which the p-type collector region CR, collector electrode CE, n-type emitter region ER, and emitter electrode EE of the IGBT of the above embodiment are replaced with an n-type substrate region NSB, drain electrode DE, n-type source region SR, and source electrode SE. The n-type substrate region NSB and the n-type source region SR are n-type semiconductor regions. The material of the drain electrode DE is the same as the material of the collector electrode CE, and the material of the source electrode SE is the same as the material of the emitter electrode EE.

[0063] The power MOSFET of the third modification has a stacked structure in the silicide region SCR, which includes an n-type substrate region NSB (semiconductor layer SL) made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a drain electrode DE. By interposing the altered layer AL made of 3C-SiC having a small band gap between the n-type substrate region NSB made of 4H-SiC and the silicide layer SC, the resistance between the n-type substrate region NSB made of 4H-SiC and the drain electrode DE can be reduced.

[0064] <Structure of power MOSFET of modification 4> Modification 4 is a modification of Modification 3, and has a structure in which an altered layer AL1 is added to the power MOSFET of Modification 3. FIG.

[0065] The power MOSFET in the fourth modification has a layered structure including a p-type body contact region PBC, an altered layer AL1 made of 3C-SiC, a silicide layer SCU, and a source electrode SE. By interposing the altered layer AL1 made of 3C-SiC with a small band gap between the p-type body contact region PBC made of 4H-SiC and the silicide layer SCU, it is possible to reduce the resistance between the p-type body contact region PBC made of 4H-SiC and the source electrode SE.

[0066] The power MOSFET in the fourth modification has a layered structure including an n-type source region SR, an altered layer AL1 made of 3C-SiC, a silicide layer SCU, and a source electrode SE. By interposing the altered layer AL1 made of 3C-SiC with a small band gap between the n-type source region SR made of 4H-SiC and the silicide layer SCU, it is possible to reduce the resistance between the n-type source region SR made of 4H-SiC and the source electrode SE.

[0067] In the fourth modification, an altered layer AL1 made of 3C-SiC is provided between the source region SR and the body contact region PBC and the silicide layer SCU, but a structure in which an altered layer AL1 is provided between either the source region SR or the body contact region PBC and the source electrode SE may also be used.

[0068] <Structure of power MOSFET of modification 5> The fifth modification is a modification of the third modification, and is a trench-gate type power MOSFET. The gate electrode GE of the power MOSFET of the third modification is disposed in a groove TR provided in the first main surface SBa. FIG. 15 is a cross-sectional view of the power MOSFET in the fifth modification. The groove TR extends from the first main surface SBa toward the second main surface SBb, and penetrates the body region PBR to reach the drift layer DL. The gate electrode GE is formed in the groove TR via the gate insulating film GI. The power MOSFET in the fifth modification is similar to the third modification except for the structure of the gate electrode GE, and therefore has the same effect as the power MOSFET in the third modification.

[0069] <Structure of PN diode of modification 6> In the sixth modification, the contact layer CL and the altered layer AL, which are features of the above-mentioned embodiment, are applied to a PN diode. FIG. 16 is a cross-sectional view of the PN diode in the sixth modification. The PN diode in the sixth modification is provided with a contact layer CL1 and an altered layer AL1 also on the anode electrode AE ​​side. However, the PN diode may have a structure in which the contact layer CL and the altered layer AL are provided only on the cathode electrode CTE side. Also, the contact layer CL1 and the altered layer AL1 may be provided only on the anode electrode AE ​​side.

[0070] The PN diode has a semiconductor substrate SB, contact layers CL and CL1, a cathode electrode CTE, and an anode electrode AE. The semiconductor substrate SB made of 4H-SiC has a first main surface SBa and a second main surface SBb. The semiconductor substrate SB further includes, in a direction from the second main surface SBb toward the first main surface SBa, an n-type substrate region NSB (sometimes referred to as a semiconductor layer SL), an n-type buffer layer BL (sometimes referred to as a semiconductor layer SL), an n-type drift layer DL (sometimes referred to as a semiconductor layer SL), and a p-type semiconductor region PR (sometimes referred to as a semiconductor layer SL). A contact layer CL is formed below the n-type substrate region NSB, and a cathode electrode CTE is formed below the contact layer CL. The contact layer CL includes a silicide region SCR and a non-silicide region NSCR, and a silicide layer SC is formed in the silicide region SCR, and a metal layer ML is formed in the non-silicide region NSCR. The area ratio of the non-silicide region NSCR is 10% or more and 60% or less. Furthermore, in a region corresponding to the silicide region SCR, an altered layer AL made of 3C-SiC is formed in the n-type substrate region NSB, and the altered layer AL is in contact with the silicide layer SC.

[0071] The PN diode of the sixth modification has a laminated structure in the silicide region SCR on the cathode electrode CTE side, which includes an n-type substrate region NSB (semiconductor layer SL) made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a cathode electrode CTE. By interposing the altered layer AL made of 3C-SiC with a small band gap between the n-type substrate region NSB made of 4H-SiC and the silicide layer SC, the resistance between the n-type substrate region NSB made of 4H-SiC and the cathode electrode CTE can be made low.

[0072] Moreover, a contact layer CL1 is formed on the upper side of the p-type semiconductor region PR, and an anode electrode AE ​​is formed on the upper side of the contact layer CL1. The contact layer CL1 includes a silicide region SCR and a non-silicide region NSCR, and a silicide layer SC is formed in the silicide region SCR, and a metal layer ML is formed in the non-silicide region NSCR. The area ratio of the non-silicide region NSCR is 10% or more and 60% or less. Here, the area ratio of the non-silicide region NSCR is the ratio of the area of ​​the non-silicide region NSCR to the area of ​​the first main surface SBa of the semiconductor substrate SB. Furthermore, in a region corresponding to the silicide region SCR, an altered layer AL1 made of 3C-SiC is formed in the p-type semiconductor region PR. The material of the cathode electrode CTE is the same as the material of the collector electrode CE (see FIG. 1), and the material of the anode electrode AE ​​is the same as the material of the emitter electrode EE (see FIG. 1).

[0073] The PN diode of the sixth modification has a stacked structure including a p-type semiconductor region PR (semiconductor layer SL) made of 4H-SiC, an altered layer AL1 made of 3C-SiC, a silicide layer SC, and an anode electrode AE ​​in the silicide region SCR on the anode electrode AE ​​side. Therefore, in the silicide region SCR, the anode electrode AE ​​is ohmically connected to the p-type semiconductor region PR (semiconductor layer SL) via the silicide layer SC. In addition, by interposing the altered layer AL1 made of 3C-SiC having a small band gap between the p-type semiconductor region PR made of 4H-SiC and the silicide layer SC, the resistance between the p-type semiconductor region PR made of 4H-SiC and the anode electrode AE ​​can be made low. In addition, in the contact layer CL1, the area ratio of the non-silicide region NSCR is set to 10% or more and 60% or less. Therefore, in the PN diode, bipolar deterioration can be suppressed. Since the PN diode of the sixth modification is a bipolar device, limiting the area ratio of the non-silicide region NSCR leads to suppression of bipolar deterioration.

[0074] Alternatively, a structure may be provided in the first main surface SBa such that a plurality of grooves shallower than the depth of the p-type semiconductor region PR are provided in the first main surface SBa, and the contact layer CL1 and the anode electrode AE ​​are provided on the first main surface SBa including the recesses and protrusions.

[0075] <Structure of JBS diode of modification example 7> In the seventh modification, the contact layer CL and the altered layer AL, which are features of the above-mentioned embodiment, are applied to a JBS (Junction Barrier Schottky) diode. FIG. 17 is a cross-sectional view of the JBS diode in the seventh modification. The structure of the JBS diode is similar to the structure of the PN diode in the sixth modification, so the differences between the two will be described. In the JBS diode, a plurality of p-type semiconductor regions PR are formed at a distance from each other on the first main surface SBa of the semiconductor substrate SB, and an n-type drift layer DL is exposed between the plurality of p-type semiconductor regions PR on the first main surface SBa. A barrier metal layer BM is formed on the first main surface SBa, and an anode electrode AE ​​is formed on the barrier metal layer BM. The barrier metal layer BM is made of, for example, molybdenum (Mo), titanium (Ti), or vanadium (V).

[0076] The JBS diode of the seventh modification has a laminated structure in the silicide region SCR on the cathode electrode CTE side, which includes an n-type substrate region NSB (semiconductor layer SL) made of 4H-SiC, an altered layer AL made of 3C-SiC, a silicide layer SC, and a cathode electrode CTE. By interposing the altered layer AL made of 3C-SiC with a small band gap between the n-type substrate region NSB made of 4H-SiC and the silicide layer SC, the resistance between the n-type substrate region NSB made of 4H-SiC and the cathode electrode CTE can be reduced.

[0077] Alternatively, a structure may be provided in the first main surface SBa such that a plurality of grooves shallower than the depth of the p-type semiconductor region PR are provided, and a barrier metal layer BM and an anode electrode AE ​​are formed on the first main surface SBa including the recesses and protrusions.

[0078] Although not shown, in a JBS diode according to a further modification of the seventh modification, the barrier metal layer BM may be provided only on the n-type drift layer DL, and the silicide layer SC may be provided on the p-type semiconductor region PR. That is, the JBS diode includes a first stacked structure including the n-type drift layer DL, the barrier metal layer BM, and the anode electrode AE, and a second stacked structure including the p-type semiconductor region PR, the silicide layer SC, and the anode electrode AE. Furthermore, in the second stacked structure, an altered layer AL1 may be interposed between the p-type semiconductor region PR and the silicide layer SC.

[0079] In addition, a structure may be provided in the first main surface SBa, the depth of which is shallower than the depth of the p-type semiconductor region PR, and in the first main surface SBa including the recesses and protrusions, a barrier metal layer BM is provided on the protrusions and a silicide layer SC is provided in the recesses.

[0080] Furthermore, if a metal having a Schottky barrier between the n-type drift layer DL and the metal layer of the anode electrode AE ​​is selected, the barrier metal layer BM may be omitted.

[0081] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above-mentioned embodiments or modified examples, and can be modified in various ways without departing from the gist of the invention.

[0082] In addition, some of the contents described in the above embodiment will be described below.

[0083] [Note] (Appendix 1) (a) preparing a base substrate made of 4H—SiC; (b) forming a semiconductor layer on the base substrate; (c) forming an element structure of a silicon carbide semiconductor device including a gate electrode and an emitter electrode on the semiconductor layer; (d) grinding the base substrate to expose the semiconductor layer; (e) forming a metal layer on the exposed semiconductor layer; (f) selectively irradiating the metal layer with laser light to form a contact layer including a silicide region and a non-silicide region; (g) forming an electrode on the contact layer; Equipped with a silicide layer including a metal layer is formed in the silicide region where the metal layer is irradiated with the laser light in the step (f), the metal layer is left in the non-silicide region where the metal layer is not irradiated with the laser light, and an altered layer made of 3C-SiC is formed at the boundary between the semiconductor layer and the silicide layer in the silicide region. [Explanation of symbols]

[0084] AE anode electrode AL, AL1 Deteriorated layer BL Buffer layer BM Barrier metal layer BSB Base Board CE collector electrode CL, CL1 contact layer CR Collector Area CTE cathode electrode DE Drain electrode DL Drift Layer DR Drain region EE emitter electrode ER emitter area GE gate electrode GI Gate Insulator IF Interlayer Insulating Film LE Laser Equipment ML metal layer NSB n-type substrate area NSCR Non-silicide region PBC Body Contact Area PBR Body Region PR p-type semiconductor region SB Semiconductor Substrate SBa 1st main surface SBb Second principal surface SC, SCU silicide layer SCa top surface SCb bottom surface SCR silicide area SE source electrode SL Semiconductor layer SR Source Region TR groove

Claims

1. a semiconductor substrate made of 4H—SiC and having a first main surface and a second main surface located opposite to each other in a thickness direction of the semiconductor substrate; a first semiconductor layer formed in the semiconductor substrate at the second major surface of the semiconductor substrate; a contact layer in contact with the second main surface of the semiconductor substrate and including a silicide region and a non-silicide region; a first electrode in contact with the contact layer and formed on a side of the contact layer opposite to the semiconductor substrate; Equipped with a first silicide layer having an upper surface and a lower surface is formed in the silicide region; a first affected layer made of 3C-SiC is interposed between the upper surface of the first silicide layer and the first semiconductor layer; the lower surface of the first silicide layer is in contact with the first electrode.

2. 2. The silicon carbide semiconductor device according to claim 1, In the silicon carbide semiconductor device, in the contact layer, the first silicide layer is an alloy layer containing aluminum, titanium, silicon and carbon.

3. The silicon carbide semiconductor device according to claim 2 , A silicon carbide semiconductor device, wherein in the contact layer, the non-silicide region is a metal layer containing aluminum and titanium.

4. The silicon carbide semiconductor device according to claim 3 , The first electrode includes an aluminum film.

5. 2. The silicon carbide semiconductor device according to claim 1, a non-silicide region having an area that is equal to or greater than 10% and equal to or less than 60% of an area of ​​the second main surface of the semiconductor substrate in a plan view;

6. 2. The silicon carbide semiconductor device according to claim 1, the silicon carbide semiconductor device includes an insulated gate bipolar transistor having a collector electrode, an emitter electrode, and a gate electrode; the first semiconductor layer is of a first conductivity type; the first electrode is the collector electrode, moreover, a second semiconductor layer having a second conductivity type different from the first conductivity type, the second semiconductor layer being formed in the semiconductor substrate at the first main surface of the semiconductor substrate; a third semiconductor layer of the second conductivity type formed on the first semiconductor layer in the semiconductor substrate; a fourth semiconductor layer of the first conductivity type formed from the first main surface of the semiconductor substrate to a depth of the third semiconductor layer so as to include the second semiconductor layer; the gate electrode formed on the first major surface via a gate insulating film so as to cover the fourth semiconductor layer between the second semiconductor layer and the third semiconductor layer; a second electrode formed on the first main surface and serving as the emitter electrode; a second silicide layer located between the second semiconductor layer and the second electrode; A silicon carbide semiconductor device comprising:

7. 7. The silicon carbide semiconductor device according to claim 6, the second semiconductor layer is made of 4H—SiC; the second silicide layer is in contact with the second semiconductor layer and the second electrode.

8. 7. The silicon carbide semiconductor device according to claim 6, the second semiconductor layer is made of 4H—SiC; the second silicide layer is in contact with the second electrode; a second altered layer made of 3C-SiC is interposed between the second silicide layer and the second semiconductor layer.

9. 7. The silicon carbide semiconductor device according to claim 6, the semiconductor substrate includes a trench formed from the first main surface toward the second main surface, penetrating the fourth semiconductor layer, and reaching the third semiconductor layer; the gate insulating film and the gate electrode are formed in the trench.

10. 2. The silicon carbide semiconductor device according to claim 1, the silicon carbide semiconductor device includes a power transistor having a source electrode, a drain electrode, and a gate electrode; the first semiconductor layer is of a first conductivity type; the first electrode is the drain electrode, moreover, a second semiconductor layer of the first conductivity type formed in the semiconductor substrate at the first main surface of the semiconductor substrate; a third semiconductor layer of the first conductivity type formed on the first semiconductor layer in the semiconductor substrate; a fourth semiconductor layer of a second conductivity type different from the first conductivity type formed from the first main surface of the semiconductor substrate to a depth of the third semiconductor layer so as to include the second semiconductor layer; a gate electrode formed on the first main surface via a gate insulating film so as to cover the fourth semiconductor layer between the second semiconductor layer and the third semiconductor layer.

11. 2. The silicon carbide semiconductor device according to claim 1, the silicon carbide semiconductor device includes a diode element having an anode electrode and a cathode electrode, the first semiconductor layer is of a first conductivity type; the first electrode is the cathode electrode, moreover, a second electrode formed on the first main surface, the second electrode being the anode electrode; a second semiconductor layer having a second conductivity type different from the first conductivity type, the second semiconductor layer being formed in the semiconductor substrate at the first main surface of the semiconductor substrate; a third semiconductor layer of the first conductivity type formed on the first semiconductor layer in the semiconductor substrate and having an impurity concentration lower than that of the first semiconductor layer; Equipped with the second semiconductor layer and the third semiconductor layer form a PN junction.

12. 2. The silicon carbide semiconductor device according to claim 1, the silicon carbide semiconductor device includes a diode element having an anode electrode and a cathode electrode, the first semiconductor layer is of a first conductivity type; the first electrode is the cathode electrode, moreover, a second electrode formed on the first main surface, the second electrode being the anode electrode; a second semiconductor layer of a second conductivity type different from the first conductivity type, the second semiconductor layer being selectively formed in the semiconductor substrate at the first main surface of the semiconductor substrate; a third semiconductor layer of the first conductivity type formed on the first semiconductor layer in the semiconductor substrate so as to include the second semiconductor layer; a barrier metal layer covering the second semiconductor layer and the third semiconductor layer and interposed between the second semiconductor layer and the second electrode; Equipped with the second semiconductor layer and the third semiconductor layer form a PN junction.

13. (a) preparing a semiconductor substrate made of 4H—SiC and having a first main surface and a second main surface positioned opposite to each other in a thickness direction of the semiconductor substrate; (b) forming a first metal layer on the second main surface of the semiconductor substrate so as to contact a first semiconductor layer formed in the semiconductor substrate at the second main surface of the semiconductor substrate; (c) selectively irradiating the first metal layer with laser light to form a contact layer including a silicide region and a non-silicide region; (d) forming a first electrode in contact with the contact layer; Equipped with In the step (c), forming a first silicide layer including the first metal layer in the silicide region where the first metal layer is irradiated with the laser light; the first metal layer is left in a non-silicide region where the laser light is not irradiated to the first metal layer; forming an altered layer made of 3C-SiC at a boundary between the first semiconductor layer and the first silicide layer in the silicide region.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, the first metal layer includes an aluminum film in contact with the first semiconductor layer, and a titanium film located on the opposite side of the first semiconductor layer with respect to the aluminum film; The method for manufacturing a silicon carbide semiconductor device, wherein in the step (c), the laser light is irradiated from the titanium film side.

15. The method for manufacturing a silicon carbide semiconductor device according to claim 13, In the step (c), a non-silicide region that is not irradiated with the laser light has an area that is 10% or more and 60% or less of an area of ​​the second main surface of the semiconductor substrate in a plan view.

Images