Semiconductor integrated circuit device and motor system

Abstract

To reduce heat generation inside a semiconductor integrated circuit device.SOLUTION: A semiconductor integrated circuit device (11) includes a first terminal (VB) configured to receive a first voltage, a portion (Q1, Q2) of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal, at least a portion (Q3, R1, R2, REF1, AMP1) of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit, an internal circuit (1) configured to use the third voltage received from the linear power supply circuit as a power supply, a second terminal (CPA) configured to be connected to a first end of an external resistor (31) included in the charge pump circuit, and a third terminal (CPB) configured to be connected to a second end of the external resistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor integrated circuit device and a motor system. [Background technology]

[0002] In the motor drive device (semiconductor integrated circuit device) disclosed in Patent Document 1, an internal power supply circuit generates an internal power supply voltage from a power supply voltage, and supplies this to each section (logic circuit, etc.) of the motor drive device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-102658 A

[0004] [overview] However, when the difference between the power supply voltage and the internal power supply voltage becomes large and the circuit current of the circuit to which the internal power supply voltage is supplied becomes large, the heat generated by the semiconductor integrated circuit device increases. Possible solutions include using a linear power supply circuit as the internal power supply circuit and using an output transistor of the linear power supply circuit as an external component, or using a switching regulator as the internal power supply circuit, but when these solutions are implemented, problems such as increased costs and increased mounting area arise.

[0005] The semiconductor integrated circuit device disclosed in this specification comprises a first terminal configured to receive a first voltage, a part of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal, at least a part of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit, an internal circuit configured to use the third voltage received from the linear power supply circuit as a power supply, a second terminal configured to be connected to a first end of an external resistor included in the charge pump circuit, and a third terminal configured to be connected to a second end of the external resistor.

[0006] The motor system disclosed in this specification includes a motor and the semiconductor integrated circuit device having the above-described configuration that is configured to drive the motor. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a motor system according to a first embodiment. [Diagram 2] FIG. 2 is a perspective view of the appearance of the semiconductor integrated circuit device. [Diagram 3] FIG. 3 is a timing chart for explaining the operation of the semiconductor integrated circuit device according to the first embodiment. [Figure 4] FIG. 4 is a timing chart for explaining another operation of the semiconductor integrated circuit device according to the first embodiment. [Diagram 5] FIG. 5 is a timing chart for explaining still another operation of the semiconductor integrated circuit device according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing the relationship between the voltage applied to the terminal VB and the power consumption of the semiconductor integrated circuit device. [Figure 7] FIG. 7 is a diagram showing a schematic configuration of a motor system according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing a schematic configuration of a motor system according to the third embodiment. [Figure 9] FIG. 9 is a diagram showing a schematic configuration of a motor system according to a fourth embodiment.

[0008] [Detailed Description] In this specification, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0009] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0010] First Embodiment 1 is a diagram showing a schematic configuration of a motor system according to a first embodiment. The motor system SYS1 shown in FIG.

[0011] 2 is an external perspective view of the semiconductor integrated circuit device 11. The semiconductor integrated circuit device 11 is an electronic component formed by encapsulating a semiconductor integrated circuit chip in a housing (package) made of resin. A plurality of external terminals are exposed on the housing of the semiconductor integrated circuit device 11, and the plurality of external terminals include terminals VB, CPA, CPB, VREG, OUT1A, OUT1B, OUT2A, OUT2B, PGND, and GND shown in FIG. 1. Note that the number of external terminals of the semiconductor integrated circuit device 11 and the external appearance of the semiconductor integrated circuit device 11 shown in FIG. 2 are merely examples.

[0012] The semiconductor integrated circuit device 11 includes a control circuit 1, a pre-driver 2, a driver 3, and terminals VB, OUT1A, OUT1B, OUT2A, OUT2B, PGND, and GND.

[0013] The control circuit 1 includes a control logic circuit and an analog circuit, and controls the driver 3 via the pre-driver 2 .

[0014] The pre-driver 2 performs predetermined signal processing (level shift processing, waveform shaping processing, simultaneous on prohibition processing, etc.) on the upper / lower pre-driver drive signals of each phase supplied from the control circuit 1 to generate upper / lower driver drive signals of each phase and output them to the driver 3.

[0015] The driver 3 generates a motor drive voltage for each phase based on the upper / lower driver drive signals for each phase supplied from the pre-driver 2, and outputs the generated motor drive voltage to the motor 21. The motor 21 is a two-phase stepping motor. The motor 21 includes a rotor RT1 and stator coils L1 and L2 corresponding to the two phases. The driver 3 is connected to a first end of the stator coil L1 via a terminal OUT1A, connected to a second end of the stator coil L1 via a terminal OUT1B, connected to a first end of the stator coil L2 via a terminal OUT2A, and connected to a second end of the stator coil L2 via a terminal OUT2B.

[0016] A voltage Vb is applied to the terminal VB from a voltage source B1. The pre-driver 2 and the driver 3 are configured to use the voltage Vb received from the terminal VB as a power supply.

[0017] A ground potential is applied to the terminal PGND. The driver 3 is configured to use the ground potential received from the terminal PGND as a reference potential.

[0018] A ground potential is applied to the terminal GND. The ground potential applied to the terminal GND is used as a reference potential in each portion within the semiconductor integrated circuit device 11.

[0019] The semiconductor integrated circuit device 11 further includes transistors Q1 to Q3 which are P-channel MOSFETs, resistors R1 and R2, an amplifier AMP1, a reference voltage source REF1, a charge / discharge control circuit 4, a switching control circuit 5, a monitor circuit 6, and terminals CPA, CPB, and VREG.

[0020] The source of the transistor Q1 is connected to the terminal VB. The drain of the transistor Q1 is connected to the terminal CPA and the source of the transistor Q2. The drain of the transistor Q2 is connected to the terminal CPB and the source of the transistor Q3. The voltage Vreg, which is the drain of the transistor Q3, is supplied to the terminal VREG, a voltage divider circuit including resistors R1 and R2, and the control circuit 1.

[0021] The charge / discharge control circuit 4 controls the transistor Q1. The switching control circuit 5 controls the transistor Q2. The monitor circuit 6 monitors the voltage Vcpb of the terminal CPB, and outputs the monitoring result to the charge / discharge control circuit 4 and the switching control circuit 5.

[0022] AMP1 controls the transistor Q3 in accordance with the difference between a reference voltage Vref output from a reference voltage source REF1 and the voltage Vreg.

[0023] Outside the semiconductor integrated circuit device 11, a first end of resistor 31 is connected to terminal CPA, a second end of resistor 31 and a first end of capacitor 32 are connected to terminal CPB, a first end of capacitor 33 is connected to terminal VREG, and a second end of capacitor 32 and a second end of capacitor 33 are connected to ground potential.

[0024] A charge pump circuit including transistors Q1 and Q2, a resistor 31, and a capacitor 32 is configured to output a voltage Vcpb obtained by stepping down Vb received from a terminal VB.

[0025] A linear power supply circuit including a transistor Q3, resistors R1 and R2, an amplifier AMP1, and a capacitor 33 is configured to output a voltage Vreg obtained by stepping down the voltage Vcpb.

[0026] Fig. 3 is a timing chart for explaining the operation of the semiconductor integrated circuit device 11. In Fig. 3, voltage Vb, voltage Vcpb, voltage Vreg, the state of transistor Q1, and the state of transistor Q2 are depicted from the top. Note that the voltage values ​​depicted in Fig. 3 are merely examples and are not limited to these.

[0027] The charge / discharge control circuit 4 turns on the transistor Q1 when the voltage Vcpb drops to a first threshold (eg, 6.8 V), and turns off the transistor Q1 when the voltage Vcpb rises to a second threshold (eg, 7 V) that is higher than the first threshold.

[0028] When the transistor Q1 is on, the capacitor 32 is charged and the voltage Vcpb rises, and when the transistor Q1 is off, the capacitor 32 is discharged and the voltage Vcpb falls. In the timing chart shown in FIG. 3, since the transistor Q2 is off, the power supplied to the terminal VB is distributed and consumed inside the semiconductor integrated circuit device 11 and the resistor 31. This reduces the power consumption inside the semiconductor integrated circuit device 11 and makes it possible to suppress heat generation inside the semiconductor integrated circuit device 11. In this way, the semiconductor integrated circuit device 11 can suppress heat generation inside the semiconductor integrated circuit device 11, and therefore the output current capacity of the driver 3 can be improved.

[0029] Fig. 4 is a timing chart for explaining another operation of the semiconductor integrated circuit device 11. In Fig. 4, from the top, voltage Vb, voltage Vcpb, voltage Vreg, state of transistor Q1, state of transistor Q2, and current I_load flowing through transistor Q1 are depicted. Note that the voltage values ​​depicted in Fig. 4 are merely examples and are not limited to these.

[0030] In Fig. 4, the transition is made in the order of period P1, period P2, and period P3. Periods P1 and P3 are periods in which the load driven by the power output from the linear power supply circuit including the transistor Q3, resistors R1 and R2, amplifier AMP1, and capacitor 33 is light. Period P2 is a period in which the load driven by the power output from the linear power supply circuit including the transistor Q3, resistors R1 and R2, amplifier AMP1, and capacitor 33 is heavy. For example, when a variable load is externally connected to the terminal VREG, the semiconductor integrated circuit device 11 may perform an operation as shown in Fig. 4.

[0031] The operation of the semiconductor integrated circuit device 11 during the period P1 is similar to that in FIG.

[0032] In period P2, even if the transistor Q1 is turned on, the voltage Vcpb continues to drop. When the voltage Vcpb drops to a third threshold (e.g., 5.8 V) that is lower than the first threshold, the switching control circuit 5 turns on the transistor Q2. As a result, the terminals CPA and CPB are shorted and the resistance value between the terminals CPA and CPB decreases, so that the charging capability of the charge pump circuit is improved compared to a state in which the terminals CPA and CPB are not shorted, and it becomes possible to increase the voltage Vcpb.

[0033] When the voltage Vcpb rises to a fourth threshold (for example, 6 V) that is greater than the third threshold and less than the first threshold, the switching control circuit 5 turns off the transistor Q2. As a result, the charging ability of the charge pump circuit decreases compared to when the terminals CPA and CPB are shorted, so that the voltage Vcpb drops during the period P2 but rises during the period P3.

[0034] That is, by providing a switching circuit (transistor Q2 in this embodiment) configured to switch between short-circuiting and non-shorting the terminals CPA and CPB, the charge pump circuit can handle a larger load. Note that in cases where the charge pump circuit does not need to handle a larger load, the charge pump circuit may not be provided with a switching circuit (transistor Q2 in this embodiment) configured to switch between short-circuiting and non-shorting the terminals CPA and CPB.

[0035] Fig. 5 is a timing chart for explaining still another operation of the semiconductor integrated circuit device 11. In Fig. 5, voltage Vb, voltage Vcpb, voltage Vreg, the state of transistor Q1, the state of transistor Q2, and current I_load flowing through transistor Q1 are depicted in this order from the top. Note that the voltage values ​​depicted in Fig. 5 are merely examples and are not limited to these.

[0036] In FIG. 5, the voltage Vb gradually decreases (decreases in voltage). When the voltage Vb decreases below a first threshold (e.g., 6.8V), the voltage Vcpb does not increase even if the transistor Q1 is turned on. When the voltage Vcpb decreases to a third threshold (e.g., 5.8V) that is smaller than the first threshold, the switching control circuit 5 turns on the transistor Q2. As a result, the terminals CPA and CPB are short-circuited, and the resistance value between the terminals CPA and CPB decreases. This improves the charging ability of the charge pump circuit compared to a state in which the terminals CPA and CPB are not short-circuited, making it possible to suppress the decrease in the voltage Vcpb.

[0037] Furthermore, when the voltage Vb falls below the target output voltage (e.g., 5 V) of the linear power supply circuit including the transistor Q3, the resistors R1 and R2, the amplifier AMP1, and the capacitor 33, the output voltage Vreg of the linear power supply circuit including the transistor Q3, the resistors R1 and R2, the amplifier AMP1, and the capacitor 33 becomes lower than the target output voltage.

[0038] By providing a switching circuit (transistor Q2 in this embodiment) configured to switch between short-circuiting and non-shorting the terminals CPA and CPB, it is possible to improve the resistance of the voltage Vb to a voltage reduction.

[0039] Fig. 6 is a diagram showing the relationship between the voltage Vb applied to the terminal VB and the power consumption of the semiconductor integrated circuit device 11. In Fig. 6, the horizontal axis represents the voltage Vb applied to the terminal VB, and the vertical axis represents the power consumption.

[0040] 6 indicates the power supplied to the terminal VB, that is, the power consumption of the semiconductor integrated circuit device 11 and the resistor 31. The thick solid line W2 in FIG.

[0041] When transistor Q2 is on, the thin solid line W1 in FIG. 6 and the thick solid line W2 in FIG. 6 coincide with each other.

[0042] When transistor Q2 is off, the power consumption of semiconductor integrated circuit device 11 is smaller than the power supplied to terminal VB, and the difference between thin solid line W1 in FIG. 6 and thick solid line W2 in FIG. 6 is the power consumed by resistor 31.

[0043] <Second embodiment> 7 is a diagram showing a schematic configuration of a motor system according to the second embodiment. The motor system SYS2 shown in Fig. 7 includes a semiconductor integrated circuit device 12, a motor 21, a resistor 31, and capacitors 32 and 33.

[0044] The semiconductor integrated circuit device 12 has a configuration in which a transistor Q4 which is a P-channel type MOSFET, a switch SW1 controlled by the charge / discharge control circuit 4, and a current source CS1 are added to the semiconductor integrated circuit device 11. The transistors Q1 and Q4 form a current mirror circuit. When the switch SW1 is on, the current mirror circuit formed by the transistors Q1 and Q4 supplies a mirror current which is a mirror of the output current of the current source CS1 to the terminal CPA.

[0045] In this embodiment, the transistor Q1 functions as a current source. That is, in this embodiment, the current source is connected to the terminal CPA. This makes the voltage change at the terminal CPA less steep, and the ripple of the voltage Vreg can be reduced. Note that in Figs. 3 to 5 in the first embodiment described above, the waveform of the voltage Vreg is simplified and the ripple of the voltage Vreg is not shown.

[0046] Similar to the semiconductor integrated circuit device 11, the semiconductor integrated circuit device 12 can suppress heat generation inside the semiconductor integrated circuit device 12.

[0047] <Third embodiment> 8 is a diagram showing a schematic configuration of a motor system according to the third embodiment. The motor system SYS3 shown in Fig. 8 includes a semiconductor integrated circuit device 13, a motor 21, a resistor 31, and capacitors 32 and 33.

[0048] The semiconductor integrated circuit device 13 differs from the semiconductor integrated circuit device 11 in that the pre-driver 2 is configured to use the voltage Vreg as a power supply, but is similar to the semiconductor integrated circuit device 11 in other respects.

[0049] Similar to the semiconductor integrated circuit device 11, the semiconductor integrated circuit device 13 can suppress heat generation inside the semiconductor integrated circuit device 13.

[0050] <Fourth embodiment> Fig. 9 is a diagram showing a schematic configuration of a motor system according to the fourth embodiment. The motor system SYS4 shown in Fig. 9 includes a semiconductor integrated circuit device 14, a motor 21, a resistor 31, capacitors 32 and 33, and a driver 3.

[0051] The semiconductor integrated circuit device 14 differs from the semiconductor integrated circuit device 13 in that the driver 3 is externally connected, but is otherwise similar to the semiconductor integrated circuit device 13.

[0052] Similar to the semiconductor integrated circuit device 11, the semiconductor integrated circuit device 14 can suppress heat generation inside the semiconductor integrated circuit device 14.

[0053] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0054] For example, in the various embodiments described above, the motor is a two-phase motor, but the motor may be a three-phase motor.

[0055] For example, in the various embodiments described above, the pre-driver 2 uses the voltage Vb applied to the terminal VB as a power supply, but a boost circuit configured to boost the voltage Vb applied to the terminal VB of the semiconductor integrated circuit device may be provided in the semiconductor integrated circuit device, and the voltage boosted by the pre-driver 2 from the voltage Vb may be used as a power supply.

[0056] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0057] A semiconductor integrated circuit device (11 to 15) of the present disclosure has a configuration (first configuration) including a first terminal (VB) configured to receive a first voltage, a part (Q1, Q2) of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal, at least a part (Q3, R1, R2, REF1, AMP1) of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit, an internal circuit (1) configured to use the third voltage received from the linear power supply circuit as a power supply, a second terminal (CPA) configured to be connected to a first end of an external resistor included in the charge pump circuit, and a third terminal (CPB) configured to be connected to the second end of the external resistor.

[0058] According to the semiconductor integrated circuit device having the first configuration, the power supplied to the first terminal is distributed and consumed inside the semiconductor integrated circuit device and in the external resistor, thereby reducing the power consumption inside the semiconductor integrated circuit device and suppressing heat generation inside the semiconductor integrated circuit device.

[0059] The semiconductor integrated circuit device of the first configuration may have a configuration (second configuration) including an output stage (2, 3) configured to use the first voltage received from the first terminal as a power supply.

[0060] In the semiconductor integrated circuit device of the above first or second configuration, the charge pump circuit may be configured (third configuration) to include a switching circuit (Q2) configured to switch between a short circuit and a non-shorting between the second terminal and the third terminal.

[0061] The semiconductor integrated circuit device of the third configuration may further include a switching control circuit (5) configured to control the switching circuit based on the second voltage (fourth configuration).

[0062] In the semiconductor integrated circuit device of the above fourth configuration, the switching control circuit may be configured to switch the connection between the second terminal and the third terminal from non-shorted to shorted when the second voltage falls below a predetermined value (fifth configuration).

[0063] The semiconductor integrated circuit device of any of the first to fifth configurations may have a configuration (sixth configuration) including a charge / discharge control circuit (4) configured to control charging / discharging of a capacitor (32) included in the charge pump circuit based on the second voltage.

[0064] The semiconductor integrated circuit device of any one of the first to sixth configurations may further include a current source (Q1) connected to the second terminal (seventh configuration).

[0065] In the semiconductor integrated circuit device of the second configuration, the internal circuit may be configured (eighth configuration) to include a control circuit (1) configured to directly or indirectly control the output stage.

[0066] In the semiconductor integrated circuit device of the eighth configuration, a pre-driver (2) may be provided, and the control circuit is configured to indirectly control the output stage via the pre-driver, and the pre-driver is configured to use the first voltage received from the first terminal or a voltage obtained by boosting the first voltage as a power supply (ninth configuration).

[0067] In the semiconductor integrated circuit device of the second configuration, a control circuit (1) configured to indirectly control the output stage via a pre-driver (2) may be provided, and the internal circuit may be configured to include the pre-driver (10th configuration).

[0068] In the semiconductor integrated circuit device of the tenth configuration, the internal circuit may include the control circuit (eleventh configuration).

[0069] A motor system (SYS1 to SYS5) of the present disclosure has a configuration (twelfth configuration) including a motor (21) and a semiconductor integrated circuit device of any of the first to eleventh configurations configured to drive the motor. [Explanation of symbols]

[0070] 1 Control circuit 2 Pre-driver 3 Driver 4. Charge / discharge control circuit 5. Switching control circuit 6 Monitor Circuit 11~15 Semiconductor integrated circuit device 21 Motor 31 Resistance 32, 33 Capacitor AMP B1 Voltage source CS1 current source L1, L2 stator coil Q1~Q4 Transistors R1, R2 resistance REF1 Reference voltage source RT1 rotor SW1 Switch SYS1~SYS5 Motor systems VB, CPA, CPB, VREG, OUT1A, OUT1B, OUT2A, OUT2B, PGND, GND terminal

Claims

1. a first terminal configured to receive a first voltage; a part of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal; at least a part of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit; an internal circuit configured to use the third voltage received from the linear power supply circuit as a power source; a second terminal configured to be connected to a first end of an external resistor included in the charge pump circuit; and a third terminal configured to be connected to the second end of the external resistor.

2. 2. The semiconductor integrated circuit device according to claim 1, further comprising an output stage configured to use said first voltage received from said first terminal as a power supply.

3. 2. The semiconductor integrated circuit device according to claim 1, wherein the charge pump circuit includes a switching circuit configured to switch between a short circuit and an unshorted circuit between the second terminal and the third terminal.

4. 4. The semiconductor integrated circuit device according to claim 3, further comprising a switching control circuit configured to control said switching circuit based on said second voltage.

5. 5. The semiconductor integrated circuit device according to claim 4, wherein the switching control circuit is configured to switch the connection between the second terminal and the third terminal from a non-shorted state to a shorted state when the second voltage falls below a predetermined value.

6. 2. The semiconductor integrated circuit device according to claim 1, further comprising a charge / discharge control circuit configured to control charging and discharging of a capacitor included in said charge pump circuit based on said second voltage.

7. The semiconductor integrated circuit device according to claim 1 , further comprising a current source connected to said second terminal.

8. 3. The semiconductor integrated circuit device according to claim 2, wherein the internal circuitry includes a control circuit configured to directly or indirectly control the output stage.

9. Equipped with a pre-driver, the control circuit is configured to indirectly control the output stage via the pre-driver; 9. The semiconductor integrated circuit device according to claim 8, wherein the pre-driver is configured to use the first voltage received from the first terminal or a voltage obtained by boosting the first voltage as a power supply.

10. a control circuit configured to indirectly control the output stage via a pre-driver; 3. The semiconductor integrated circuit device according to claim 2, wherein said internal circuitry includes said pre-driver.

11. 11. The semiconductor integrated circuit device according to claim 10, wherein said internal circuitry includes said control circuit.

12. A motor; A motor system comprising: the semiconductor integrated circuit device according to any one of claims 1 to 11 configured to drive the motor.

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