Methods for improving passivation layer durability
Patent Information
- Application Number
- JP2024108747
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-08-01
- Filing Date
- 2024-07-05
- Publication Date
- 2025-02-19
Smart Images
Figure 2025023889000001_ABST
Abstract
Description
[Technical field]
[0001] FIELD OF THE DISCLOSURE Exemplary embodiments of the present disclosure relate generally to semiconductor devices and fabrication techniques. More specifically, the present disclosure relates to a method for improving the durability of a passivation layer. [Background technology]
[0002] Some semiconductor devices may include layers of various materials formed in a stack on a semiconductor substrate. Such semiconductor devices may be formed using various techniques, such as photolithography, etching, deposition, doping, and other techniques. Such techniques may be utilized to form the various materials into patterns and configurations that enable the operation of the semiconductor device. In some cases, the semiconductor devices may include various structures for coupling with other devices, such as other semiconductor devices. For example, a semiconductor device may include one or more layers formed in such a manner that the semiconductor device may be coupled with another semiconductor device (e.g., via soldering, via flip-chip bonding). In some cases, the semiconductor devices may include dissimilar materials having geometric discontinuities, including interfaces, corners, and edges. Such semiconductor devices may be exposed to non-uniform thermal cycles during fabrication, testing, storage, and operation. Due to the differences in thermochemical properties of each material and the geometric discontinuities, the interfaces between the materials may be prone to various types of failures, such as delamination. Summary of the Invention
[0003] Various embodiments described herein relate to methods, devices, and systems for improving the durability of a passivation layer. In one aspect, the device includes a semiconductor substrate extending along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate, one or more layers formed on the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate, at least a region of the one or more layers including a circuit, and a passivation layer formed on the one or more layers in the third direction, the passivation layer including a plurality of cavities each extending through the passivation layer, the plurality of cavities and the circuit do not overlap in the first direction and the second direction.
[0004] In some embodiments, the one or more layers may include an insulating layer formed between the circuitry and the passivation layer, and each cavity of the plurality of cavities exposes a surface of the insulating layer. In some embodiments, each cavity of the plurality of cavities is formed in the shape of an elliptical cylinder with a height axis parallel to a third direction. In some embodiments, the ratio of the major axis to the minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern with uniform spacing between each cavity of the plurality of cavities. In some cases, all four sides of the rectangular pattern may have equal lengths (e.g., the rectangular pattern may be a square). In some other cases, the sides of the rectangular pattern may have different lengths (e.g., the rectangular pattern may be a rectangle).
[0005] In some embodiments, the semiconductor substrate comprises a silicon carbide material. In some embodiments, the one or more layers comprise a silicon carbide layer formed in contact with the semiconductor substrate, a metal layer formed in at least partial contact with the silicon carbide layer, and a silicon nitride layer formed in at least partial contact with the metal layer. In some embodiments, the circuit may comprise a transistor circuit. Other technical features may be readily apparent to one skilled in the art from the following drawings, description, and claims.
[0006] In one aspect, a method may include forming a semiconductor substrate extending along a first direction and a second direction, where the first direction is parallel to a width of the semiconductor substrate and the second direction is parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes a circuit; and forming a passivation layer on the one or more layers in the third direction, where the passivation layer includes a plurality of cavities each extending through the passivation layer, and where the plurality of cavities and the circuit do not overlap in the first direction and the second direction.
[0007] The method may also include forming one or more layers including an insulating layer between the circuitry and the passivation layer, each cavity of the plurality of cavities exposing a surface of the insulating layer. In some embodiments, forming each cavity of the plurality of cavities may include forming a cavity in the shape of an elliptical cylinder including a height axis parallel to a third direction. In some embodiments, a ratio of a major axis to a minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities. The method may also include forming the semiconductor substrate using a silicon carbide material.
[0008] In some embodiments, forming one or more layers may include forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer in at least partial contact with the silicon carbide layer, and forming a silicon nitride layer in at least partial contact with the metal layer. Other technical features may be readily apparent to those skilled in the art from the following drawings, descriptions, and claims.
[0009] In one aspect, a method for forming a product may include forming a semiconductor substrate extending along a first direction and a second direction, where the first direction is parallel to a width of the semiconductor substrate and the second direction is parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes a circuit; and forming a passivation layer formed on the one or more layers in the third direction, where the passivation layer includes a plurality of cavities each extending through the passivation layer, where the plurality of cavities and the circuit do not overlap in the first direction and the second direction.
[0010] In some embodiments, forming the one or more layers may include forming an insulating layer between the circuitry and the passivation layer, and each cavity of the plurality of cavities exposes a surface of the insulating layer. In some embodiments, forming each cavity of the plurality of cavities may include forming a cavity in the shape of an elliptical cylinder including a height axis parallel to a third direction. In some embodiments, a ratio of a major axis to a minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities. Other technical features may be readily apparent to one skilled in the art from the following drawings, descriptions, and claims.
[0011] In some embodiments, a non-transitory computer-readable storage medium may include instructions that, when executed by a computer, cause the computer to: form a semiconductor substrate extending along a first direction and a second direction, where the first direction is parallel to a width of the semiconductor substrate and the second direction is parallel to a depth of the semiconductor substrate; form one or more layers on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes a circuit; and form a passivation layer formed on the one or more layers relative to the third direction, where the passivation layer includes a plurality of cavities each extending through the passivation layer, where the plurality of cavities and the circuitry do not overlap relative to the first direction and the second direction.
[0012] In some cases, forming the one or more layers may include forming an insulating layer between the circuitry and the passivation layer, with each cavity of the plurality of cavities exposing a surface of the insulating layer. In some cases, forming each cavity of the plurality of cavities includes forming a cavity in the shape of an elliptical cylinder that includes a height axis parallel to a third direction. In some cases, the plurality of cavities are arranged in a rectangular pattern that includes uniform spaces between each cavity of the plurality of cavities. In some cases, forming the semiconductor substrate includes forming the semiconductor substrate using a silicon carbide material.
[0013] In some cases, forming the one or more layers includes forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer in at least partial contact with the silicon carbide layer, and forming a silicon nitride layer in at least partial contact with the metal layer. In some cases, the ratio of the major axis to the minor axis of each elliptical cylinder is 3 to 1. Other technical features may be readily apparent to one skilled in the art from the following drawings, description, and claims.
[0014] In some embodiments, the apparatus includes a processor, and the apparatus also includes a memory storing instructions that, when executed by the processor, configure the apparatus to: form a semiconductor substrate extending along a first direction and a second direction, where the first direction is parallel to a width of the semiconductor substrate and the second direction is parallel to a depth of the semiconductor substrate, form one or more layers on the semiconductor substrate relative to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes a circuit, and form a passivation layer formed on the one or more layers relative to the third direction, where the passivation layer includes a plurality of cavities each extending through the passivation layer, where the plurality of cavities and the circuit do not overlap relative to the first direction and the second direction.
[0015] The apparatus may also be configured to form one or more layers, including forming an insulating layer between the circuitry and the passivation layer, each cavity of the plurality of cavities exposing a surface of the insulating layer. The apparatus may also be configured to form each cavity of the plurality of cavities, including forming a cavity in the shape of an elliptical cylinder including a height axis parallel to a third direction. The apparatus may also be configured to arrange the plurality of cavities in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities. In some cases, forming the semiconductor substrate includes forming the semiconductor substrate using a silicon carbide material.
[0016] In some cases, forming one or more layers includes forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer in at least partial contact with the silicon carbide layer, and forming a silicon nitride layer in at least partial contact with the metal layer. Other technical features may be readily apparent to those skilled in the art from the following drawings, description, and claims. In some cases, the ratio of the major axis to the minor axis of each elliptical cylinder is 3 to 1. Other technical features may be readily apparent to those skilled in the art from the following drawings, description, and claims.
[0017] The foregoing exemplary summary, as well as other exemplary objects and / or advantages of the present disclosure, and the manner in which they are accomplished, are further described in the following detailed description and its accompanying drawings. [Brief description of the drawings]
[0018] The description of the exemplary embodiments may be read in conjunction with the accompanying drawings. It will be understood that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale unless otherwise noted. For example, dimensions of some of the elements may be exaggerated relative to other elements unless otherwise noted. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the figures presented herein. [Figure 1] Illustrates example material configurations that support methods for improving the durability of passivation layers. [Diagram 2] Illustrates example material configurations that support methods for improving the durability of passivation layers. [Diagram 3] Illustrates example material configurations that support methods for improving the durability of passivation layers. [Figure 4] 1 illustrates an example of a flow diagram supporting a method for improving the durability of a passivation layer. [Diagram 5] 1 illustrates an example of a flow diagram supporting a method for improving the durability of a passivation layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] Some embodiments of the present disclosure are described more fully below with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. However, these disclosures may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.
[0020] As used herein, terms such as "front," "rear," "top," and the like are used for illustrative purposes in the examples provided below to describe the relative locations of particular components or portions of components. Additionally, as would be apparent to one of ordinary skill in the art in light of this disclosure, the terms "substantially" and "approximately" indicate that the referenced component or associated description is accurate to within applicable engineering tolerances.
[0021] As used herein, the term "comprising" means including but not limited to and should be interpreted in the manner typically used in the patent context. The use of broader terms such as comprises, includes, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting substantially of.
[0022] Phrases such as "in one embodiment," "according to one embodiment," and the like generally mean that the particular feature, structure, or characteristic that follows the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).
[0023] The words "exemplary" or "exemplary" are used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
[0024] When the specification describes a component or feature as "may include," "can include," "could include," "should include," "will include," "preferably include," "possibly include," "typically include," "optionally include," "for example include," "often include," or "may include" (or other such language) or as having a certain characteristic, that particular component or feature is not required to be included or to have that characteristic. Such components or features may be optionally included or excluded in some embodiments.
[0025] FIG. 1 illustrates an example of a material configuration 100 that supports a method for improving the durability of a passivation layer. In some cases, the material configuration 100 may illustrate one or more portions of a semiconductor device or any other electronic device. For example, the material configuration 100 may illustrate multiple portions of a silicon carbide power device, such as a diode or a transistor. The material configuration 100 may be an example of a device or one or more portions of a device used in various applications, such as power electronics applications. The material configuration 100 may illustrate one or more sections of a semiconductor device, and some portions of the semiconductor device may be cut away or may not be shown. For example, the material configuration 100 may illustrate six portions of a semiconductor device, and the portions may be shown separately to illustrate that an intervening material 110 or layer 105 may be included between the portions. However, in some cases, the six portions may not include an intervening material 110 or layer 105 and may instead be formed in contact with one another. As described herein, each layer 105 of the material configuration 100 may correspond to a respective material 110. Additionally, layer 105-d may include implanted regions 115, which may be portions of layer 105-d that have been implanted or doped according to a particular implantation or doping recipe. Although several examples of particular materials 110 or material compounds are described herein, material configuration 100 may include any combination of materials 110.
[0026] The material configuration 100 may include a layer 105-a. The layer 105-a may be an example of a passivation layer that may insulate or otherwise protect one or more layers 105 of the material configuration 100 (e.g., a layer 105 positioned below the layer 105-a in the y-direction). In some cases, the layer 105-a may electrically insulate one or more layers of the material configuration 100 or may otherwise prevent the transmission of radio waves (e.g., electromagnetic fields) or electrical signals through the layer 105-a. The layer 105-a may also serve to protect the material configuration 100 from suffering damage due to weathering or mechanical stress. The layer 105-a may be formed using a material 110-a (e.g., a passivation material, an insulating material). In some cases, the material 110-a may be an example of polyimide, silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. Layer 105-a may be formed in contact with layer 105-b.
[0027] The material configuration 100 may include layer 105-b. Layer 105-b may be an example of an insulating layer (e.g., a second insulating layer) that may be included in the material configuration 100 (e.g., in addition to layer 105-a) to improve adhesion of layer 105-a. For example, layer 105-a may adhere more easily to layer 105-b than to layer 105-c. Layer 105-b may insulate or otherwise protect one or more layers 105 of the material configuration 100 (e.g., one or more layers 105 positioned below layer 105-b in the y-direction). In some cases, layer 105-b may electrically insulate one or more layers 105 of the material configuration 100 or otherwise prevent transmission of radio waves (e.g., electromagnetic fields) or electrical signals through layer 105-b. Layer 105-b may be formed using material 110-b, which may be an example of an insulating material such as polyimide, silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. In one illustrative example, material 110-a may be polyimide and material 110-b may be silicon nitride. However, in some other examples, layer 105-a and layer 105-b may be formed using the same material (e.g., polyimide). As described herein, layer 105-b may be formed in contact with layer 105-c, layer 105-a, layer 105-g, and layer 105-d.
[0028] Material configuration 100 may include layer 105-c. Layer 105-c may be an example of a metal layer that may be utilized to route electrical signals. Layer 105-c may be an example of a redistribution layer or any other type of conductive layer or trace. Layer 105-c may be formed using material 110-c. Material 110-c may be an example of copper, tungsten, aluminum, titanium, silver, or any other conductive material. As described herein, layer 105-c may be formed in contact with any combination of layers 105-b, 105-d, and 105-g.
[0029] Material configuration 100 may include layer 105-d. Layer 105-d may be an example of a semiconductor layer that may be utilized to form a circuit. Layer 105-d may include implanted regions 115 (e.g., implanted region 115-a, implanted region 115-b, implanted region 115-c). Implanted region 115 may be an example of a doped region of layer 105-d and a depletion region of layer 105-d. For example, implanted region 115-a may be an example of a ring implanted region, which may be a region of layer 105-d that is doped according to a particular process (e.g., n-type doping). Implanted region 115-b may be an example of an anode implanted region, which may be doped differently than implanted region 115-a (e.g., using p-type doping). Implanted region 115-b may be an example of an anode or positive terminal (e.g., for a diode) for material configuration 100. Layer 105-d may include implanted region 115-c, which may be an example of a depletion zone. Layer 105-d may be formed using material 110-e (e.g., a semiconductor material), which may be silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, germanium, or any other example semiconductor material. As described herein, layer 105-d may be formed in contact with layer 105-e, layer 105-c, layer 105-g, and layer 105-b.
[0030] Material configuration 100 may include layer 105-g. Layer 105-g may be an example of an oxide layer that may provide electrical insulation. In some cases, layer 105-g may be an example of an interlayer dielectric (ILD) or a gate dielectric. Layer 105-g may be formed using material 110-d. Material 110-d may be an example of an oxide material, such as silicon dioxide, aluminum oxide, or any other dielectric material. As described herein, layer 105-g may be formed in contact with layer 105-b, layer 105-c, and layer 105-d.
[0031] Material configuration 100 may include layer 105-e. Layer 105-e may be an example of a semiconductor substrate. In some cases, layer 105-c may be formed using material 110-f. Material 110-f may be an example of any semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, germanium, etc. In some cases, material 110-f and material 110-e may be different. However, in some other cases, material 110-f and material 110-e may be the same material, such as silicon carbide. As described herein, layer 105-e may be formed in contact with layer 105-d and layer 105-f.
[0032] Material configuration 100 may include layer 105-f. Layer 105-f may be an example of a solder alloy layer. Although layer 105-f is shown in FIG. 1 as a single material (e.g., material 110-g), layer 105-f may be formed using a combination of materials 110. For example, material 110-g may be an example of an alloy including titanium, nickel, vanadium, and silver. Layer 105-f may be used to interconnect or bond material configuration 100 with semiconductor packaging (e.g., via soldering). As described herein, layer 105-f may be formed in contact with layer 105-e.
[0033] In some cases, material configuration 100 may be formed using one or more processes, such as lithography, etching, deposition, doping, metallization, soldering, or any other type of process. In some cases, layer 105-e may be deposited on layer 105-f, layer 105-d may be deposited on layer 105-e, layer 105-g may be deposited on layer 105-d, and so on. In some cases, material configuration 100 may include one or more layers 105 for coupling layer 105-d, regions of layer 105-d, or layer 105-e (e.g., a redistribution layer) with the circuitry of one or more other devices, such as another semiconductor device (not shown).
[0034] As described herein, the material configuration 100 may include various dissimilar materials having geometric discontinuities, including interfaces, corners, and edges. The material configuration 100 may be subjected to non-uniform thermal cycles during manufacturing, testing, storage, and operation. Due to the differences in thermochemical properties and geometric discontinuities of each material 110, the interfaces between the materials 110 (e.g., layers 105) may be susceptible to failure. In some cases, a layer 105-a (e.g., a passivation layer) that electrically insulates the stack of materials may be particularly susceptible to mechanical failure (e.g., delamination). An additional layer 105, such as layer 105-b (e.g., silicon nitride), may be formed in contact with layer 105-a to improve adhesion (e.g., between layer 105-a and layer 105-b). However, if a crack forms in layer 105-b and the delamination of layer 105-a extends to layer 105-c (eg, a metal layer), an electrical discharge can occur, as described below.
[0035] The present disclosure provides techniques for improving the durability of layer 105-a by forming stress relief cavities through layer 105-a. The cavities may be located along the periphery of material configuration 100. For example, the cavities may be positioned such that they do not overlap (e.g., in the xz plane) with layer 105-c, implanted region 115-a, implanted region 115-b, or implanted region 115-c. For example, the location of the cavities may be selected such that the location of the cavities in the xz plane does not overlap with a region of material configuration 100 that includes active circuitry. As described herein, positioning the cavities in a region of material configuration 100 that does not overlap with active circuitry may ensure that the active circuitry is effectively insulated by layer 105-c (e.g., electromagnetic fields do not escape through the cavities). Additionally, each cavity may be formed in the shape of an ellipse (e.g., an elliptical cylinder) and may extend downward (e.g., in the negative y direction) through the passivation layer. Although the examples described herein generally refer to cavities formed in the shape of an ellipse, any cavity shape or geometry may be used. Similarly, the relative distance between the cavities or the relative positions of the cavities may be modified based on one or more properties of the material configuration 100.
[0036] 2 illustrates an example of a material configuration 200 supporting a method for improving the durability of a passivation layer. For example, material configuration 200-a may illustrate a layer 205-a (e.g., a passivation layer) without a cavity 215, and material configuration 200-b may illustrate a layer 205-a with a cavity 215. Material configuration 200-a and material configuration 200-b may be examples of material configuration 100 described with reference to FIG. 1, or a portion of material configuration 100. Material configuration 200-b may illustrate a portion of material configuration 100 after one or more steps have been performed (e.g., to form cavity 215).
[0037] Material configuration 200-a may include one or more layers 205. For example, material configuration 200-a may include layer 205-a (e.g., a passivation layer) and layer 205-b. Layer 205-b may be an example of layer 205 located below layer 205-a in the y-direction. Layer 205-b may be formed using material 210-b. Material 210-b may be an insulating material such as silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. In some other cases, material 210-b may be a conductive material such as aluminum. Layer 205-a may be formed using material 210-a, which may be an example of an insulating material (e.g., different from material 210-b). For example, material 210-a may be an example of polyimide.
[0038] Layer 205-a may be formed around the periphery of a semiconductor device (e.g., around the periphery of material configuration 200). In some cases, layer 205-a may be formed by first depositing (e.g., uniformly) material 210-a onto layer 205-b. A central portion of layer 205-a may then be removed to form a void that exposes a top surface (e.g., in the y-direction) of layer 205-b (as shown in FIG. 2). In some cases, the void formed through layer 205-a may be an example of a bolt pad opening. The bolt pad opening may allow material configuration 200-a to be secured to another device via one or more bolts or fasteners that connect to layer 205-b.
[0039] As shown, layer 205-a of material configuration 200-a may not include a cavity 215 (e.g., a surrounding cavity). Thus, non-uniform thermal cycling during manufacturing, testing, storage, and operation may result in mechanical stresses within layer 205-a or between layers 205-a and 205-b. For example, increasing the temperature may cause layers 205-a and 205-b to expand. However, material 210-a may have a different coefficient of thermal expansion than material 210-b, which may result in stresses between layers 205-a and 205-b. Such stresses may increase the likelihood of delamination between layers 205-a and 205-b, which may lead to failure of material configuration 200-a.
[0040] According to one or more aspects of the present disclosure, as illustrated by material configuration 200-b, one or more cavities 215 may be formed in layer 205-a, which may relieve stress (e.g., mechanical stress) in layer 205-a or between layer 205-a and layer 205-b. As illustrated, material configuration 200-b may include multiple cavities 215 (e.g., cavities 215-a through 215-jj). Each cavity 215 may expose a surface of layer 205-b. Additionally or alternatively, each cavity 215 may be formed in a location that avoids overlap with circuitry (e.g., active circuitry). For example, the circuitry may be located in region 220 (e.g., under layer 205-b). Thus, cavity 215 may be formed outside region 220 (e.g., along the perimeter of material configuration 200-b).
[0041] FIG. 3 illustrates an example of a material configuration 300 supporting a method for improving the durability of a passivation layer. The material configuration 300 may be an example of a portion of the material configuration 200-b, as described with reference to FIG. 2. For example, the region 325 of the material configuration 200 may be an example of a magnified view of a portion of the material configuration 300-b. The material configuration 300 may include a layer 305-a (e.g., a passivation layer) and a layer 305-b, which may be examples of the layers 205-a and 205-b, respectively, as described with reference to FIG. 2. Thus, the layer 305-a may be formed using the material 310-a, and the layer 305-b may be formed using the material 310-b. The materials 310-a and 310-b may be examples of the materials 210-a and 210-b, respectively, as described with reference to FIG. 2. Additionally, material configuration 300 may include a number of cavities 315, which may be examples of cavities 215, as described with reference to FIG.
[0042] According to one or more aspects of the present disclosure, each cavity 315 may be formed in the shape of an elliptical cylinder. For example, each cavity 315 may have a dimension 320-b (e.g., inner diameter, minor axis) and a dimension 320-c (e.g., outer diameter, major axis). For one or more cavities 315 (e.g., cavity 315-a, cavity 315-b), dimension 320-b may be parallel to the z-direction and dimension 320-c may be parallel to the x-direction. However, the orientation of the dimension 320 of each cavity 315 may correspond to the orientation of each cavity 315. For example, cavity 315-e may be oriented differently than cavity 315-a. Thus, dimension 320-b of cavity 315-e may be parallel to the x-direction and dimension 320-c of cavity 315-e may be parallel to the z-direction.
[0043] Additionally, each cavity 315 may have a height dimension (not shown). The height dimension of each cavity 315 may be parallel to the y-direction. As described herein, each cavity 315 may extend (e.g., completely) through the layer 305-a. Additionally or alternatively, the cavities 315 may be spaced apart or positioned according to a dimension 320-a and a dimension 320-d. For example, the dimension 320-a may be an example of a distance between a respective cavity 315 (e.g., cavity 315-a) and an extent of the layer 305-a. The dimension 320-a may be selected based on the location of the circuit. For example, the dimension 320-a may be selected such that each cavity 315 is positioned sufficiently away from the circuit. Although not shown, the dimension 320-a may be the same for each cavity 315. That is, each cavity 315 may be positioned the same distance away from the extent of the layer 305-a. The dimension 320-d may represent the distance or spacing between each of the cavities 315. In some cases, the dimension 320-d may be uniform for multiple cavities 315, i.e., the spacing between each of the cavities 315 may be the same.
[0044] The dimension 320 may be determined based on a mathematical relationship, an algorithm, modeling, or test results. For example, a modeling process may be performed to determine the stresses present in layer 305-a. The modeling process may output various stress values for a given dimension 320. Thus, the modeling process may select the dimension 320 such that one or more stresses in layer 305 are minimized. In some cases, a particular ratio of dimension 320-c to dimension 320-b may be utilized. For example, dimension 320-c may be approximately three times larger than dimension 320-b. Such a ratio of dimension 320-c to dimension 320-b may be selected based on one or more stress values output by the modeling process. For example, selecting dimension 320-c to be approximately three times larger than dimension 320-b may substantially reduce or eliminate stresses in layer 305-a.
[0045] Although some examples described herein refer to cavities 315, some other examples may include forming (e.g., depositing) different materials 310 within cavities 315. For example, each cavity 315 may be filled (e.g., partially or completely) with a material 310 different from material 310-a. For example, material 310 may be configured for stress relief applications, or more generally, may have one or more properties that allow for stress reduction in layer 305-a. Material 310 may have a lower hardness or stiffness than material 310-a, which may allow material 310 to relieve or eliminate stress. For example, material 310 may be relatively flexible when compared to material 310-a. In some cases, one or more dimensions 320 may be selected or otherwise altered based on one or more dimensions of material configuration 300. For example, dimension 320 may be selected to match the size of material configuration 300. In some cases, one or more of the dimensions 320 may be selected or otherwise varied based on the material 310 selected for the material configuration 300. For example, one or more of the dimensions 320 may be selected based on one or more attributes of the material 310-a, the material 310-b, or both.
[0046] FIG. 4 illustrates an example flow diagram illustrating a method 400 that supports improving the durability of a passivation layer. The steps of method 400 may be performed by a manufacturing system or machine configured to perform one or more steps described herein. For example, a machine or manufacturing system configured to perform one or more deposition, etching, or any other material formation or removal steps may perform the steps of method 400. In some cases, the manufacturing system or machine may execute instructions to control one or more functional elements to perform the described steps. Additionally or alternatively, the machine or manufacturing system may perform aspects of the described steps using dedicated hardware.
[0047] At 405, the method 400 may include forming a semiconductor substrate extending along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate. The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0048] At 410, the method 400 may include forming one or more layers over the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate. In some cases, at least a region of the one or more layers includes circuitry (e.g., active circuitry). The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0049] At 415, the method 400 may include forming a passivation layer over the one or more layers in a third direction. The passivation layer may include a plurality of cavities each extending through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping in the first and second directions. The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0050] FIG. 5 illustrates an example flow diagram illustrating a method 500 for improving the durability of a passivation layer. The steps of method 500 may be performed by a manufacturing system or machine configured to perform one or more steps described herein. For example, a machine or manufacturing system configured to perform one or more material removal steps or one or more material formation steps may perform the steps of method 500. In some cases, the manufacturing system or machine may execute instructions to control one or more functional elements to perform the described steps. Additionally or alternatively, the machine or manufacturing system may perform aspects of the described steps using dedicated hardware.
[0051] At 505, the method 500 may include forming a semiconductor substrate extending along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate. The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0052] At 510, the method 500 may include forming one or more layers over the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate. In some cases, at least a region of the one or more layers includes circuitry (e.g., active circuitry). The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0053] At 515, the method 500 may include forming an insulating layer between the circuitry and the passivation layer. Each cavity of the plurality of cavities may expose a surface of the insulating layer. In some cases, forming the one or more layers may include forming an insulating layer between the circuitry and the passivation layer. The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0054] At 520, the method 500 may include forming a passivation layer over the one or more layers in a third direction. The passivation layer may include a plurality of cavities each extending through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping in the first and second directions. The process may be performed according to examples as described herein. In some examples, aspects of the process may be performed using a dedicated machine or manufacturing system.
[0055] Although this detailed description has described several embodiments of the present invention, the appended claims also cover other embodiments of the present invention that may differ from the described embodiments, according to various modifications and improvements. Within the appended claims, it is not intended that a claim be interpreted under 35 USC 112, paragraph 6, unless the specific term "means for" or "step for" is used in a given claim.
Claims
1. a semiconductor substrate extending along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; one or more layers formed on the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate, at least a region of the one or more layers including a circuit; a passivation layer formed on the one or more layers in the third direction, the passivation layer comprising a plurality of cavities each extending through the passivation layer, the plurality of cavities and the circuitry not overlapping in the first direction and the second direction; An apparatus comprising:
2. The one or more layers are 2. The apparatus of claim 1, further comprising an insulating layer formed between said circuitry and said passivation layer, each cavity of said plurality of cavities exposing a surface of said insulating layer.
3. The apparatus of claim 1 , wherein each cavity of the plurality of cavities is formed in the shape of an elliptical cylinder that includes a height axis parallel to the third direction.
4. 4. The apparatus of claim 3, wherein the ratio of the major axis to the minor axis of each elliptical cylinder is 3:
1.
5. The apparatus of claim 1 , wherein the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities.
6. The apparatus of claim 1 , wherein the semiconductor substrate comprises a silicon carbide material.
7. The one or more layers are a silicon carbide layer formed in contact with the semiconductor substrate; a metal layer formed in at least partial contact with the silicon carbide layer; 10. The apparatus of claim 1, further comprising: a silicon nitride layer formed at least partially in contact with the metal layer.
8. The apparatus of claim 1 , wherein the circuitry comprises a transistor circuit.
9. forming a semiconductor substrate extending along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate, at least a region of the one or more layers including a circuit; forming a passivation layer over the one or more layers in the third direction, the passivation layer comprising a plurality of cavities each extending through the passivation layer, the plurality of cavities and the circuitry not overlapping in the first direction and the second direction; A method comprising:
10. forming the one or more layers 10. The method of claim 9, further comprising forming an insulating layer between the circuitry and the passivation layer, each cavity of the plurality of cavities exposing a surface of the insulating layer.
11. forming each cavity of the plurality of cavities, The method of claim 9 , comprising forming a cavity in the shape of an elliptical cylinder with a height axis parallel to the third direction.
12. The method of claim 11 , wherein the ratio of the major axis to the minor axis of each elliptical cylinder is 3:
1.
13. The method of claim 9 , wherein the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities.
14. forming the semiconductor substrate, The method of claim 9 comprising forming the semiconductor substrate using a silicon carbide material.
15. forming the one or more layers forming a silicon carbide layer in contact with the semiconductor substrate; forming a metal layer in at least partial contact with the silicon carbide layer; and forming a silicon nitride layer in at least partial contact with the metal layer.
16. 1. A product formed by a method, the method comprising: forming a semiconductor substrate extending along a first direction and a second direction, the first direction being parallel to a width of the semiconductor substrate and the second direction being parallel to a depth of the semiconductor substrate; forming one or more layers on the semiconductor substrate in a third direction parallel to a height of the semiconductor substrate, at least a region of the one or more layers including a circuit; forming a passivation layer over the one or more layers in the third direction, the passivation layer comprising a plurality of cavities each extending through the passivation layer, the plurality of cavities and the circuitry not overlapping in the first direction and the second direction; Including the product.
17. forming the one or more layers 17. The product formed by the method of claim 16, further comprising forming an insulating layer between said circuitry and said passivation layer, each cavity of said plurality of cavities exposing a surface of said insulating layer.
18. forming each cavity of the plurality of cavities, 17. The product formed by the method of claim 16, including forming a cavity in the shape of an elliptical cylinder with a height axis parallel to the third direction.
19. 20. The product formed by the method of claim 18, wherein the ratio of the major axis to the minor axis of each elliptical cylinder is 3 to 1.
20. 17. The product formed by the method of claim 16, wherein the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities.
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US12408635B2