Semiconductor device

Abstract

To provide a logic circuit that prevents wrong operation or reduces consumption power, and a semiconductor device including the logic circuit.SOLUTION: A logic circuit includes a thin film transistor 14 whose channel formation region is formed of an oxide semiconductor, and a capacitor element 15 in which the potential of one terminal is floated by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019(atoms / cm3) or less, and functions as an insulator substantially when an electric field is not generated. Therefore, the off current of the thin film transistor can be reduced. Thus, the leak of charges accumulated in the capacitor element through the thin film transistor can be suppressed and the wrong operation of the logic circuit can be prevented. In addition, by reducing the off current of the thin film transistor, the waste current flowing in the logic circuit can be reduced, so that the consumption power of the logic circuit can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a logic circuit including a field-effect transistor using an oxide semiconductor. The present invention also relates to a semiconductor device having the logic circuit.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, and electro-optical devices, semiconductor circuits, and electrical equipment are all classified as semiconductor devices. [Background technology]

[0003] Thin film transistors (TFTs) are made using semiconductor thin films formed on substrates with insulating surfaces. Thin-film transistors are used in displays such as LCD televisions. Silicon-based semiconductor thin films that can be used in thin-film transistors are Conductive materials are well known, but oxide semiconductors have also attracted attention as other materials.

[0004] Zinc oxide or materials containing zinc oxide are known as oxide semiconductor materials. And the electron carrier density is 10 18 / cm 3 Amorphous oxide (oxide semiconductor) ) are disclosed in Patent Documents 1 to 3. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165527 A [Patent Document 2] JP 2006-165528 A [Patent Document 3] JP 2006-165529 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the composition of oxide semiconductors deviates from the stoichiometric value during the thin film formation process. For example, the electrical conductivity of an oxide semiconductor changes depending on whether there is an excess or deficiency of oxygen. In addition, hydrogen that is mixed in during the formation of the oxide semiconductor thin film forms oxygen (O)-hydrogen (H) bonds. In addition, OH is a polar molecule, so it becomes an electron donor and causes a change in electrical conductivity. It is particularly useful for active devices such as thin film transistors made of oxide semiconductors. This is a factor that can affect gender.

[0007] The electron carrier density is 10 18 / cm 3 Even if the oxide semiconductor has a is an n-type thin-film transistor, and the on / off ratio of the thin-film transistor disclosed in the above-mentioned patent document is 10 3 deer The reason for the low on-off ratio of such thin-film transistors is that the off-current is high. This is due to the fact that

[0008] The on-off ratio is an index that indicates the characteristics of a switch. In circuits that are composed of transistors, the circuit operation becomes unstable. Also, the off-current is high. This causes a problem of unnecessary current flow and increased power consumption.

[0009] In view of the above-described problems, one embodiment of the present invention provides a thin film transistor formed using an oxide semiconductor. One object of the present invention is to reduce malfunctions of logic circuits constituted by resistors.

[0010] Another embodiment of the present invention is a thin film transistor formed using an oxide semiconductor. One object is to reduce power consumption of a logic circuit configured. [Means for solving the problem]

[0011] One embodiment of the present invention is to provide an oxide semiconductor having an impurity (hydrogen or By removing the water, etc., an intrinsic or substantially intrinsic semiconductor, such as a silicon semiconductor, A thin film transistor in which a channel formation region is formed using an oxide semiconductor with a larger energy gap than that of the A logic circuit is formed using transistors.

[0012] Specifically, the hydrogen contained in the oxide semiconductor is 5×10 19 / cm 3 Less than or equal to 5, preferably ×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The following oxide semiconductors are Remove hydrogen or OH bonds from the body and reduce the carrier density to 5×10 14 / cm 3 below , preferably 5 x 10 12 / cm 3 A channel formation region is formed using an oxide semiconductor having the following structure: The thin film transistors form a logic circuit.

[0013] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, it is set to 3 eV or more, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier Rear density 1×10 14 / cm 3 Less than or equal to 1×10 12 / cm 3 The following should be true: to.

[0014] Such a highly purified oxide semiconductor is used for the channel formation region of a thin film transistor. Even when the channel width is 10 mm, the drain voltage is 1 V and 10 V. In this case, the drain current is 1×10 -13 [A] Acts so as to:

[0015] That is, one embodiment of the present invention is a thin film transistor and a thin film transistor that is turned off. A capacitor element in which the potential of a node to which one terminal is electrically connected is in a floating state by the The channel formation region of the thin film transistor has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) A logic circuit including the following oxide semiconductors:

[0016] In this specification, the concentration is measured by secondary ion mass spectrometry. Mass Spectrometry (hereinafter referred to as SIMS) However, this does not apply if other measurement methods are listed or if otherwise specified. do not have.

[0017] A semiconductor device including the above-described logic circuit is also one embodiment of the present invention. Effect of the Invention

[0018] A logic circuit according to one embodiment of the present invention includes a thin-film transistor in which a channel formation region is formed using an oxide semiconductor. When the thin film transistor is turned off, the potential of one terminal of the thin film transistor floats. The oxide semiconductor has a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / c m 3 In addition, the oxide semiconductor is an insulator or an insulator in the absence of an electric field. Therefore, the thin film transistor functions as a semiconductor (effectively an insulator) close to the This reduces the off-current of the charge stored in the capacitor. This can suppress leakage through the thin film transistor, thereby preventing malfunction of the logic circuit. In addition, the potential of one terminal of the capacitance element can be prevented from being in a floating state. In other words, the time required for rewriting (refreshing) information to the capacitive element can be increased. This can reduce the frequency of noise (also called "flash" noise).

[0019] In addition, by reducing the off-current of the thin film transistor, It is possible to reduce unnecessary current, thereby reducing the power consumption of the logic circuit. This can be done. [Brief description of the drawings]

[0020] [Figure 1] (A) and (C) are circuit diagrams, and (B) and (D) are timing charts showing an example of an inverter. [Diagram 2] 3A to 3D are circuit diagrams showing an example of an inverter. [Diagram 3] FIG. 1A is a circuit diagram showing an example of a shift register, and FIG. [Figure 4] FIG. 1A is a circuit diagram showing an example of a shift register, and FIG. [Diagram 5] 1A and 1B are a plan view and a cross-sectional view, respectively, illustrating an example of a thin film transistor. [Figure 6] 1A to 1E are cross-sectional views illustrating an example of a method for manufacturing a thin film transistor. [Figure 7] 1A and 1B are a plan view and a cross-sectional view, respectively, illustrating an example of a thin film transistor. [Figure 8]1A to 1E are cross-sectional views illustrating an example of a method for manufacturing a thin film transistor. [Figure 9] 1A and 1B are cross-sectional views showing an example of a thin film transistor. [Figure 10] 1A to 1E are cross-sectional views illustrating an example of a method for manufacturing a thin film transistor. [Figure 11] 1A to 1E are cross-sectional views illustrating an example of a method for manufacturing a thin film transistor. [Figure 12] 1A to 1D are cross-sectional views illustrating an example of a method for manufacturing a thin film transistor. [Figure 13] 1A to 1D are cross-sectional views illustrating an example of a method for manufacturing a thin film transistor. [Figure 14] FIG. 1 is a cross-sectional view illustrating an example of a thin film transistor. [Figure 15] 1A and 1B are plan views and a cross-sectional view, respectively, illustrating an example of a semiconductor device. [Figure 16] FIG. 1 illustrates an example of a pixel equivalent circuit of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views showing an example of a semiconductor device. [Figure 18] 1A and 1B are a plan view and a cross-sectional view, respectively, illustrating an example of a semiconductor device. [Figure 19] FIG. 1 is a cross-sectional view showing an example of a semiconductor device. [Figure 20] 1A and 1B are diagrams showing an example of a semiconductor device. [Figure 21] 1A and 1B are diagrams showing an example of a semiconductor device. [Figure 22] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Diagram 23] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Figure 24] FIG. 1 is a diagram showing a band structure between a source and a drain of a MOS transistor using an oxide semiconductor. [Diagram 25] 25 is a diagram showing a state in which a positive voltage is applied to the drain side in FIG. 24. [Figure 26] 1A and 1B are energy band diagrams of a MOS structure of a MOS transistor using an oxide semiconductor, showing a case where the gate voltage is positive and a case where the gate voltage is negative. [Figure 27] FIG. 1 shows the band structure between the source and drain of a silicon MOS transistor. [Figure 28] FIG. 13 is a graph showing initial characteristics of an example of a thin film transistor. [Figure 29] 1A and 1B are top views of an evaluation element of an example of a thin-film transistor. [Diagram 30] 1A and 1B are graphs showing the Vg-Id characteristics of an evaluation element of an example of a thin-film transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0022] The source and drain terminals of a transistor depend on the structure and operating conditions of the transistor. It is difficult to identify which is the source terminal and which is the drain terminal. Therefore, in this specification, one of the source terminal and the drain terminal is referred to as a first terminal. The other of the source terminal and drain terminal will be referred to as a second terminal to distinguish it from the other.

[0023] In addition, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may differ from the actual size, layer thickness, or area shown in the drawings of each embodiment. In some cases, the figures are exaggerated for clarity. Therefore, the figures are not necessarily limited to the scale. In addition, ordinal numbers such as "first," "second," and "third" used in this specification are not limited to the structure. It is added to avoid confusion of the constituent elements, and is not a numerical limitation. do.

[0024] (Embodiment 1) In this embodiment, an example of a logic circuit will be described. Regarding an example of an inverter having a thin film transistor formed of an oxide semiconductor This will be explained with reference to FIG. 1 and FIG.

[0025] FIG. 1(A) is a circuit diagram showing an example of an inverter according to the present embodiment. The inverter includes thin film transistors 11 to 14, a capacitor element 15, and Here, the thin film transistor 11 is a depletion type transistor, The thin film transistors 12 to 14 are enhancement type transistors. In this specification, the case where the transistor is an n-channel type and the threshold voltage is positive is assumed. is called an enhancement type transistor, which is an n-channel type and has a negative threshold voltage. In this case, it is called a depletion type transistor.

[0026] The thin film transistor 11 has a first terminal connected to a line for supplying a high power supply potential (VDD) (hereinafter, The power supply line is electrically connected to the

[0027] The thin film transistor 12 has a gate terminal connected to a wiring that supplies an input signal (IN) (hereinafter, The first terminal is electrically connected to the gate terminal of the thin film transistor 11. and the second terminal.

[0028] The thin film transistor 13 has a gate terminal connected to a line for supplying a pulse signal (PS) (hereinafter, The first terminal is electrically connected to the second terminal of the thin film transistor 12. The second terminal is electrically connected to the low power supply potential (VSS) The resistors are electrically connected to the power supply (also called the power supply line).

[0029] The thin film transistor 14 has a gate terminal electrically connected to the pulse signal line and a first terminal A gate terminal and a second terminal of the thin film transistor 11 and a first terminal of the thin film transistor 12 and a wiring through which the second terminal outputs an output signal (hereinafter also referred to as an output signal line). is electrically connected to

[0030] The capacitance element 15 has one terminal electrically connected to the second terminal of the thin film transistor 14 and the output signal line. The other terminal is electrically connected to a low power supply potential line.

[0031] The thin film transistor 11 has a first terminal electrically connected to a high power supply potential line and a gate The first terminal is electrically connected to the second terminal. The thin film transistor 11 maintains the on state regardless of the period. The capacitor 11 is used as a resistive element.

[0032] In this specification, the high power supply potential (VDD) and the low power supply potential (VSS) When comparing the two, if the high power supply potential (VDD) is higher than the low power supply potential (VSS), For example, the low power supply potential (VSS) may be a ground potential or 0V. For example, any positive potential can be applied as the high power supply potential (VDD).

[0033] Next, the operation of the circuit shown in FIG. 1(A) will be described with reference to the timing chart shown in FIG. 1(B). For convenience, the gate of the thin film transistor 11 is shown in FIG. the first terminal and the second terminal of the thin film transistor 12 and the second terminal of the thin film transistor 14 The node to which the first terminal is electrically connected will be referred to as node A in the following description.

[0034] In the period T1, the potential of the input signal (IN) and the pulse signal (PS) increases to a high level. Therefore, the thin film transistor 12, the thin film transistor 13, and the thin film transistor 1 4 is turned on. As a result, node A and one terminal of the capacitance element are electrically connected to the low power supply line. That is, the potential of node A and the output signal (OUT) of the inverter are at the low level. Moreover, no charge is stored in the capacitance element 15.

[0035] In the period T2, the potential of the pulse signal (PS) falls to a low level. The thin film transistor 13 and the thin film transistor 14 are turned off. Accordingly, the potential of the node A increases to a high level. As a result, the potential of one terminal of the capacitance element 15 is in a floating state. The signal (OUT) is maintained at a low level.

[0036] In a period T3, the potential of the input signal (IN) falls to a low level, and the pulse signal (PS ) increases to a high level. As a result, the thin film transistor 12 is turned off. This causes the node A and the capacitive element 13 and the thin film transistor 14 to turn on. One terminal of 15 is electrically connected to a high power supply potential line via a thin film transistor 11 . That is, the potential of the node A and the output signal (OUT) of the inverter increase to a high level. Moreover, a positive charge is stored in one terminal of the capacitance element 15 .

[0037] The inverter of this embodiment has a plurality of thin film transistors each having a channel forming region formed of an oxide. The oxide semiconductor is an oxide semiconductor having a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, and in the absence of an electric field, it is an insulator or a semiconductor close to an insulator (effectively an insulator Therefore, a channel formation region is formed of the oxide semiconductor. It is possible to reduce the off-current of the thin film transistor. This makes it possible to suppress leakage of electric charges through the sta.

[0038] For example, the channel formation region of the thin film transistor 14 is made of the oxide semiconductor. As a result, the potential of one terminal of the capacitance element 15 is in a floating state (period T2). The amount of change in potential during period T1 (such as an increase in potential during period T2) can be reduced. This makes it possible to prevent the inverter from malfunctioning. In other words, the period during which the potential of the terminal of the capacitance element 15 is in a floating state can be extended. This reduces the frequency with which information needs to be rewritten (also called refreshed) to the memory.

[0039] In addition, the channel formation region of the thin film transistor 13 is formed of the oxide semiconductor. By this, when the potential of the input signal (IN) is at a high level and the potential of the pulse signal (PS) is at a low level, Penetration current that flows from the high power supply line to the low power supply line during the period when the potential is at a low level (period T2) This allows the current to be reduced, thereby reducing the power consumption of the inverter. can.

[0040] The inverter of this embodiment is not limited to the inverter shown in FIG. In the following, referring to Fig. 1(C), we will introduce an inverter different from the inverter shown in Fig. 1(A). An example of the above will be described.

[0041] The inverter shown in FIG. 1C includes thin film transistors 21 to 24, The thin film transistor 21 is a depletion type transistor. The thin film transistors 22 to 24 are enhancement type transistors. It is assumed that the transistor.

[0042] The thin film transistor 21 has a first terminal electrically connected to a high power supply potential line.

[0043] The thin film transistor 22 has a gate terminal electrically connected to the pulse signal line and a first terminal The gate terminal and the second terminal of the thin film transistor 21 are electrically connected.

[0044] The thin film transistor 23 has a gate terminal electrically connected to the input signal line and a first terminal The second terminal of the membrane transistor 22 is electrically connected to the low power supply potential line. Connected.

[0045] The thin film transistor 24 has a gate terminal electrically connected to the pulse signal line and a first terminal A second terminal of the thin film transistor 22 and a first terminal of the thin film transistor 23 are electrically connected to each other. The second terminal is electrically connected to the output signal line.

[0046] The capacitance element 25 has one terminal electrically connected to the second terminal of the thin film transistor 24 and the output signal line. The other terminal is electrically connected to a low power supply potential line.

[0047] In short, the inverter shown in Fig. 1(C) is a thin-film transistor (TFT) 13 is replaced with a thin film transistor 22.

[0048] Next, the operation of the circuit shown in FIG. 1C will be described with reference to the timing chart shown in FIG. 1D. For convenience, the first thin film transistor 22 is shown in FIG. The second terminal, the first terminal of the thin film transistor 23, and the first terminal of the thin film transistor 24 are electrically The node connected to is described as node B.

[0049] In the period T4, the potential of the input signal (IN) and the pulse signal (PS) increases to a high level. Therefore, the thin film transistor 22, the thin film transistor 23, and the thin film transistor 2 As a result, node B and one terminal of the capacitance element 25 are connected to the low power supply potential line. In other words, the potential of node B and the output signal (OUT) of the inverter are electrically connected. Furthermore, no charge is stored in the capacitance element 25.

[0050] In the period T5, the potential of the pulse signal (PS) falls to a low level. The thin film transistor 22 and the thin film transistor 24 are turned off. As a result, the potential of one terminal of the capacitance element 25 becomes floating. The output signal (OUT) is maintained at a low level. Note that the potential of node B is at a low level. do.

[0051] In a period T6, the potential of the input signal (IN) falls to a low level, and the pulse signal (PS ) increases to a high level. As a result, the thin film transistor 23 turns off. This causes the node B and the capacitive element One terminal of 25 is electrically connected to a high power supply potential line via a thin film transistor 21 . That is, the potential of the node B and the output signal (OUT) of the inverter increase to a high level. Moreover, a positive charge is accumulated at one terminal of the capacitance element 25.

[0052] The inverter shown in FIG. 1C has a plurality of thin film transistors each having a channel forming region. The oxide semiconductor is an oxide semiconductor having a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, and in the absence of an electric field, it is an insulator or a semiconductor close to an insulator (effectively Therefore, the channel formation region is formed by the oxide semiconductor. This can reduce the off-state current of the thin film transistor. This makes it possible to suppress leakage of electric charges via the transistor.

[0053] For example, the channel formation region of the thin film transistor 24 is made of the oxide semiconductor. As a result, the potential of one terminal of the capacitance element 25 during the period in which the potential is in a floating state This can reduce the amount of change in the inverter. It is also possible to extend the period during which node B is in a floating state. This can reduce the frequency of rewriting (also called refreshing) information to the capacitance element 25. Cut.

[0054] In addition, the channel formation region of the thin film transistor 22 is formed of the oxide semiconductor. By this, when the potential of the input signal (IN) is at a high level and the potential of the pulse signal (PS) is at a low level, Through current that flows from the high power supply line to the low power supply line during the period when the potential is at a low level (period T5) This allows the current to be reduced, thereby reducing the power consumption of the inverter. can.

[0055] In the above-mentioned inverter, the thin film transistor electrically connected to the high power supply potential line has A depletion type transistor is applied, but the thin film transistor is changed to an enhancement type The inverter shown in FIG. 1A can be used as a transistor. The thin film transistor 11 is an enhancement type transistor. Similarly, FIG. 2(B) shows the inverter shown in FIG. 1(C) The thin film transistor 21 is replaced with an enhancement type thin film transistor 41. In addition, the thin film transistor 31 and the thin film transistor 41 have a gate The terminal and the first terminal are electrically connected to a high power supply potential line.

[0056] In addition, the inverter described above has a configuration including a capacitive element. The inverter can function even without the transistors. FIG. 2(D) shows the same as FIG. 2(B) except that the capacitive element 15 is removed. 13 shows an inverter in which the capacitive element 25 is removed.

[0057] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0058] (Embodiment 2) In this embodiment, an example of a logic circuit will be described. An example of a shift register having such an inverter will be described with reference to FIGS. 3 and 4. .

[0059] The shift register of the present embodiment includes a plurality of pulse output circuits, The odd-numbered wiring that supplies the first clock signal (CK1) is (also referred to as a first clock signal line) and the even-numbered ones of the plurality of pulse output circuits are electrically connected to The wiring that supplies the second clock signal (CK2) (hereinafter, the second clock signal line) Furthermore, the input terminal of each pulse output circuit receives a start pulse signal (SP) supply wiring (hereinafter also called start pulse line) or the previous stage pulse output circuit The output terminal of the power supply 1 is electrically connected to the power supply 2.

[0060] A specific example of the circuit configuration of the pulse output circuit will be described with reference to FIG. In FIG. 3A, pulse output circuits 110, 120, and 130 are shown.

[0061] The pulse output circuit 110 includes thin film transistors 101 to 104 and a capacitor. Here, the thin film transistor 101 is a depletion type transistor. The thin film transistors 102 to 104 are enhancement Assume that the transistor is a MOSFET.

[0062] The thin film transistor 101 has a first terminal electrically connected to a high power supply potential line.

[0063] The thin film transistor 102 has a gate terminal electrically connected to the start pulse line, and The terminal is electrically connected to the gate terminal and the second terminal of the thin film transistor 101 .

[0064] The thin film transistor 103 has a gate terminal electrically connected to a first clock signal line, The first terminal is electrically connected to the second terminal of the thin film transistor 102, and the second terminal is connected to a low power supply voltage The sensor is electrically connected to the position line.

[0065] The thin film transistor 104 has a gate terminal electrically connected to a first clock signal line, The first terminal is the gate terminal of the thin film transistor 101, the second terminal of the thin film transistor 1 02.

[0066] The capacitor 105 has one terminal electrically connected to the second terminal of the thin film transistor 104. The other terminal is electrically connected to a low power supply potential line.

[0067] That is, the pulse output circuit 110 shown in FIG. 3A is the inverter circuit shown in FIG. It is composed of

[0068] In addition, when simply referring to an input terminal or an output terminal of the pulse output circuit 110, the input terminal is The terminal to which the start pulse signal (SP) or the output signal of the previous stage pulse output circuit is input. The output terminal refers to a terminal that outputs a signal to a pulse input terminal in the subsequent stage. That is, in this case, the gate terminal of the thin film transistor 102 is the input terminal of the pulse output circuit. The second terminal of the thin film transistor 104 and one of the terminals of the capacitor 105 are electrically connected to the The terminal is electrically connected to the output terminal. When there is no input terminal, the gate terminal of the thin film transistor 102 is connected to the input terminal of the pulse output circuit. A second terminal of the thin film transistor 104 and one terminal of the capacitor element 105 are an output terminal. It can be described as a child.

[0069] The specific circuit configuration of the pulse output circuit 120 is the same as that of the pulse output circuit 110. The above description is used here. However, in the pulse output circuit 120, 1, the input terminal is electrically connected to the output terminal of the pulse output circuit 110 and the pulse output circuit In the circuit 110, the second clock signal (CK1) is input to the terminal to which the first clock signal (CK1) is input. It differs from the pulse output circuit 110 in that a signal (CK2) is input.

[0070] The circuit configuration of the pulse output circuits provided after the pulse output circuit 120 is the same as that of the pulse output circuit 1. 10 and the pulse output circuit 120. Therefore, the above description is incorporated herein. As described above, the odd-numbered pulse output circuits are the first clocks. The pulse output circuits electrically connected to the clock signal line and provided at the even positions are the second clock signal lines. The signal line is electrically connected to the latch signal line.

[0071] Next, the operation of the circuit shown in FIG. 3(A) will be described with reference to the timing chart shown in FIG. 3(B). For convenience, the circuit shown in FIG. 3(B) is a specific circuit shown in FIG. The nodes are labeled C to G, and the description will be given with reference to the changes in potential at each of the nodes.

[0072] During the period t1, the potential of the start pulse signal (SP) increases to a high level. Therefore, the thin film transistor 102 is turned on. The first terminal is electrically connected to the second terminal. The transistor 101 maintains an on state regardless of the period. In other words, the thin-film transistor The capacitor 101 is used as a resistive element.

[0073] During the period t2, the potential of the start pulse signal (SP) is maintained at a high level. Therefore, the thin film transistor 102 maintains the on state.

[0074] In a period t3, the potential of the first clock signal (CK1) increases to a high level. Therefore, the thin film transistor 103 and the thin film transistor 104 are turned on. The potential of the pulse signal (SP) is maintained at a high level. 2 remains on. This causes the nodes C and D to be electrically connected to the low power supply line. That is, the potentials of the nodes C and D drop to the low level.

[0075] In a period t4, the potential of the first clock signal (CK1) falls to a low level. Therefore, the thin film transistor 103 and the thin film transistor 104 are turned off. The node C is electrically connected to the high power supply potential line via the thin film transistor 101. That is, the potential of node C increases to a high level, and the potential of node D increases to a high level. The ranking will remain at a low level.

[0076] In period t5, the potential of the start pulse signal (SP) falls to a low level. Therefore, the thin film transistor 102 is turned off. Also, the potential of the second clock signal (CK2) As a result, the thin film transistor 113 and the thin film transistor 11 4 is turned on. As a result, the node F is connected to the high power supply potential via the thin film transistor 111. That is, the potential of the node F increases to a high level. , the thin film transistor 122 is turned on.

[0077] In a period t6, the potential of the second clock signal (CK2) falls to a low level. Therefore, the thin film transistor 113 and the thin film transistor 114 are turned off. The node F is in a floating state. In other words, the potentials of the nodes E and F are maintained at a high level. Hold.

[0078] In a period t7, the potential of the first clock signal (CK1) increases to a high level. Therefore, the thin film transistor 103, the thin film transistor 104, the thin film transistor 123, and As the thin film transistor 104 turns on, the node D is electrically connected to the high power supply potential line via the thin film transistor 101. The potential of node D increases to a high level. This turns on the thin film transistor 112. In addition, the potential of the node F is maintained at a high level. The ON state is maintained. As a result, the node G is electrically connected to the low power supply potential line. As a result, the potential of the node G drops to a low level.

[0079] In a period t8, the potential of the first clock signal (CK1) falls to a low level. Therefore, the thin film transistor 103, the thin film transistor 104, the thin film transistor 123, and As the thin film transistor 104 turns off, the node C is electrically connected to the high power supply potential line via the thin film transistor 101, and the node D is Therefore, the potentials of the nodes C and D are maintained at a high level. When the thin film transistor 123 is turned off, the node G is , electrically connected to the high power supply potential line. That is, the potential of the node G increases to a high level. .

[0080] In a period t9, the potential of the second clock signal (CK2) increases to a high level. Therefore, the thin film transistor 113 and the thin film transistor 114 are turned on. The potential of D is maintained at a high level. Therefore, the thin film transistor 112 is in an on state. As a result, the nodes E and F are electrically connected to the low power supply potential line. That is, the potentials of the nodes E and F drop to a low level. The potential of the start pulse (SP) increases to a high level again. Note that the operation associated with the increase in the potential of the start pulse (SP) after this period is as expected. The operation is the same as that in the period t1 and after. Therefore, the above description is applicable here. Let us assume that.

[0081] In a period t10, the potential of the second clock signal (CK2) falls to a low level. As a result, the thin film transistor 113 and the thin film transistor 114 are turned off. Therefore, the node F is in a floating state. In other words, the potential of the node F is maintained at a low level. , the node E is electrically connected to the high power supply potential line via a thin film transistor 111 . That is, the potential of the node E increases to a high level.

[0082] The operations after the period t10 are the same as those described above. The above explanation is incorporated herein by reference.

[0083] The capacitance elements (capacitance elements 105, 115, 125, etc.) of each pulse output circuit are , each of which is provided to hold an output signal of the pulse output circuit.

[0084] The shift register of this embodiment has a plurality of thin film transistors each having a channel forming region. The oxide semiconductor is an oxide semiconductor having a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, and in the absence of an electric field, it is an insulator or a semiconductor close to an insulator (effectively Therefore, the channel formation region is formed by the oxide semiconductor. This can reduce the off-state current of the thin film transistor. This makes it possible to suppress leakage of electric charges via the transistor.

[0085] For example, the channel formation region of the thin film transistor 104 is formed of the oxide semiconductor. By this, during the period when node D is in a floating state (such as the period t4 to the period t6), By reducing the amount of change in the potential of node D (such as the increase in the potential during periods t4 to t6), This makes it possible to prevent malfunction of the shift register. The period during which the node D is in a floating state can be increased. In other words, the capacitance element 105 This reduces the frequency of rewriting (also called refreshing) information.

[0086] In addition, a channel formation region of the thin film transistor 103 is formed of the oxide semiconductor. By this, the potential of the start pulse (SP) is at a high level and the first clock The period during which the potential of the clock signal (CK1) is at a low level (period t1, period t2, period t4, etc.) This can reduce the through current that flows from the high power supply potential line to the low power supply potential line. Therefore, the power consumption of the shift register can be reduced.

[0087] The shift register of this embodiment is not limited to the shift register shown in FIG. In the following, with reference to FIG. 4, a shift register different from that in FIG. 3 will be described. An example will be described.

[0088] The shift register shown in FIG. 4A includes pulse output circuits 210 to 230. The pulse output circuit 210 includes thin film transistors 201 to 20 4 and a capacitor element 205. Here, the thin film transistor 201 is a depletion The thin film transistors 202 to 204 are enhancement type transistors. It is assumed that the transistor is a stimulation type transistor.

[0089] A first terminal of the thin film transistor 201 is electrically connected to a high power supply potential line.

[0090] The thin film transistor 202 has a gate terminal electrically connected to the first clock signal line, The first terminal is electrically connected to the gate terminal and the second terminal of the thin film transistor 201 .

[0091] The thin film transistor 203 has a gate terminal electrically connected to the start pulse line and a first The terminal is electrically connected to the second terminal of the thin film transistor 202, and the second terminal is connected to a low power supply potential line is electrically connected to

[0092] The thin film transistor 204 has a gate terminal electrically connected to the first clock signal line, The first terminal is connected to the second terminal of the thin film transistor 202 and the first terminal of the thin film transistor 203. are electrically connected.

[0093] The capacitor element 205 has one terminal electrically connected to the second terminal of the thin film transistor 204. The other terminal is electrically connected to a low power supply potential line.

[0094] In short, the pulse output circuit 210 shown in FIG. 4A outputs the pulse A circuit in which the thin film transistor 103 in the output circuit 110 is replaced with a thin film transistor 202. It is a road.

[0095] FIG. 4B shows a timing chart illustrating the operation of the circuit shown in FIG. In FIG. 4B, for convenience, specific nodes of the circuit in FIG. 4A are labeled with symbols H to L. , the change in potential of each node will be described.

[0096] In a period t11, the potential of the start pulse signal (SP) increases to a high level. Therefore, the thin film transistor 203 is turned on. As a result, the node H is connected to the low power supply line. That is, the potential of the node H drops to a low level.

[0097] During a period t12, the potential of the start pulse signal (SP) is maintained at a high level. Therefore, the potential of the node H remains at the low level.

[0098] In period t13, the potential of the first clock signal (CK1) increases to a high level. Therefore, the thin film transistor 202 and the thin film transistor 204 are turned on. The potential of the gate pulse signal (SP) is maintained at a high level. 03 remains on, so that node I is electrically connected to the low power supply line. That is, the potential of the node I drops to a low level.

[0099] In a period t14, the potential of the first clock signal (CK1) falls to a low level. As a result, the thin film transistor 202 and the thin film transistor 204 are turned off. Therefore, the potential of the node I is maintained at a low level.

[0100] In a period t15, the potential of the start pulse signal (SP) falls to a low level. Therefore, the thin film transistor 203 is turned off. As a result, the node H is in a floating state. Therefore, the potential of the node H is maintained at a low level. 2) increases to a high level. As a result, the nodes J and K are connected to the thin-film transistors 211 and 214. 1, the potentials of the nodes J and K are electrically connected to the high power supply potential line. increases to a high level. As a result, the thin film transistor 223 turns on. The node L is electrically connected to the low power supply line. That is, the potential of the node L is at a low level. It decreases to.

[0101] In period t16, the potential of the second clock signal (CK2) falls to a low level. As a result, the thin film transistor 212 and the thin film transistor 214 are turned off. Therefore, the potentials of the nodes J and K are , maintains a high level, and the potential of node L maintains a low level.

[0102] In period t17, the potential of the first clock signal (CK1) increases to a high level. Therefore, the thin film transistor 202, the thin film transistor 204, the thin film transistor 222 The thin film transistor 202 and the thin film transistor 224 are turned on. When 204 is turned on, the nodes H and I are supplied with a high voltage through the thin film transistor 201. That is, the potentials of the nodes H and I are increased to a high level. Therefore, the thin film transistor 213 is turned on. As a result, the node J is The node J is electrically connected to the power supply line, that is, the potential of the node J drops to a low level.

[0103] In a period t18, the potential of the first clock signal (CK1) falls to a low level. Therefore, the thin film transistor 202, the thin film transistor 204, the thin film transistor 222 And the thin film transistor 224 is turned off. When 204 is turned off, the nodes H and I are in a floating state. The potential of node I remains at a high level.

[0104] In period t19, the potential of the second clock signal (CK2) increases to a high level. Therefore, the thin film transistor 212 and the thin film transistor 214 are turned on. The potential of the gate I is maintained at a high level. Therefore, the thin film transistor 213 is in an on state. As a result, the nodes J and K are electrically connected to the low power supply potential line. That is, the potential of the node J is maintained at a low level, and the potential of the node K drops to a low level. Therefore, the thin film transistor 223 is turned off. As a result, the node L is set to the low power supply potential. That is, the potential of the node L is maintained at a low level. The potential of the stop pulse (SP) is increased to a high level again. The operation associated with the increase in the potential of the start pulse (SP) is the same as that from period t11 onwards. Therefore, the above explanation will be used here.

[0105] In a period t20, the potential of the second clock signal (CK2) falls to a low level. As a result, the thin film transistor 212 and the thin film transistor 214 are turned off. As a result, the potentials of the nodes J and K are Maintain a low level.

[0106] The operations after the period t20 are the same as those described above. The above explanation is incorporated herein by reference.

[0107] The capacitance elements (capacitance elements 205, 215, 225, etc.) of each pulse output circuit are , each of which is provided to hold an output signal of the pulse output circuit.

[0108] The shift register shown in FIG. 4 has a plurality of thin film transistors each having a channel forming region. The oxide semiconductor is an oxide semiconductor having a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / c m 3 ) or less, and in the absence of an electric field, it is an insulator or a semiconductor close to an insulator (effectively an insulator Therefore, a channel formation region is formed of the oxide semiconductor. It is possible to reduce the off-current of the thin film transistor. This makes it possible to suppress leakage of electric charge through the transistor.

[0109] For example, the channel formation region of the thin film transistor 204 is formed of the oxide semiconductor. By this, the period during which node I is in a floating state (period t11, period t12, period t The amount of change in potential during periods t11, t14 to t16, t18 to t20, etc. (reduction in potential during periods t12, t19, t20, etc.) can be reduced. This makes it possible to prevent the shift register from malfunctioning. The period in which the capacitor element 205 is in the floating state can be extended. The frequency of writing (also called refreshing) can be reduced.

[0110] In addition, the channel formation region of the thin film transistor 202 is formed of the oxide semiconductor. By this, the potential of the start pulse (SP) is at a high level and the first clock The period during which the potential of the clock signal (CK1) is at a low level (period t11, period t12, period t14) During periods t16, t18, t20, etc., the current flows from the high power supply line to the low power supply line. This reduces the through current, thereby reducing the power consumption of the shift register. It is possible.

[0111] In the above-mentioned shift register, the thin-film transistor electrically connected to the high power supply potential line A depletion type transistor was applied to the thin film transistor, but the thin film transistor was changed to an enhancement type. That is, the transistor shown in FIG. 2(A) and FIG. 2(B) can be a transistor of the same structure. It is possible to apply a pulse output circuit such as a MOSFET to the pulse output circuit of this embodiment.

[0112] In the above-mentioned shift register, each pulse output circuit has a capacitance element. However, the shift register can function without the capacitance element. The inverters shown in Figs. 2(C) and 2(D) are applied as the pulse output circuit of this embodiment. It is possible to do so.

[0113] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0114] (Embodiment 3) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is An example is given below.

[0115] One mode of a thin film transistor and a manufacturing method thereof according to this embodiment will be described with reference to FIGS. explain.

[0116] 5(A) and (B) show an example of a planar and cross-sectional structure of a thin film transistor. The thin film transistor 410 shown in (B) is one of the thin film transistors having a top gate structure. It is.

[0117] FIG. 5A is a plan view of a thin film transistor 410 having a top gate structure, and FIG. FIG. 5(A) is a cross-sectional view taken along line C1-C2 of FIG.

[0118] The thin film transistor 410 is formed by forming an insulating layer 407, an oxide The semiconductor layer 412, the source or drain electrode layer 415a, and the source or drain electrode layer The gate electrode layer 415b, the gate insulating layer 402, and the gate electrode layer 411 are The drain electrode layer 415a and the source or drain electrode layer 415b are wiring layers. The wiring layer 414a and the wiring layer 414b are provided in contact with each other and are electrically connected.

[0119] In addition, the thin film transistor 410 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A star can also be formed.

[0120] Hereinafter, a thin film transistor 410 will be fabricated on a substrate 400 using FIGS. The process will be explained.

[0121] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as a borosilicate glass or an aluminoborosilicate glass substrate can be used.

[0122] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The above is recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. Generally, the content of barium oxide (BaO) is higher than that of boron oxide (B2O3). This results in a more practical heat-resistant glass. It is preferable to use a glass substrate.

[0123] Instead of the above glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used. Alternatively, crystallized glass may be used. In addition, a plastic substrate or the like can also be used as appropriate.

[0124] First, an insulating layer 407 is formed as a base film over a substrate 400 having an insulating surface. The insulating layer 407 in contact with the semiconductor layer is a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or the like. It is preferable to use an oxide insulating layer such as an aluminum layer or an aluminum oxynitride layer. The film formation method of 407 can be a plasma CVD method or a sputtering method. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, sputtering is preferably used. It is preferable to form the insulating layer 407 by a deposition method.

[0125] In this embodiment, a silicon oxide layer is formed by a sputtering method as the insulating layer 407. The substrate 400 is transferred to a processing chamber, and a spa containing high-purity oxygen from which hydrogen and moisture have been removed is used. A target gas is introduced and a silicon semiconductor is used to deposit an insulating layer 407 on the substrate 400. The silicon oxide layer is formed by the above-mentioned method. The substrate 400 may be at room temperature or may be heated. stomach.

[0126] For example, quartz (preferably synthetic quartz) is used as a target, the substrate temperature is 108° C., and the substrate The distance between the plate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high-frequency power Power 1.5kW, oxygen and argon (oxygen flow rate 25sccm: argon flow rate 25sccm A silicon oxide layer is formed by RF sputtering in a 1000 MPa (1:1) atmosphere. In addition, a silicon target is used instead of quartz (preferably synthetic quartz). It can be used as a target for forming a silicon layer. Oxygen or a mixture of oxygen and argon gas is used as the gas.

[0127] In this case, it is preferable to form the insulating layer 407 while removing residual moisture in the processing chamber. This is to prevent the insulating layer 407 from containing hydrogen, a hydroxyl group, or moisture.

[0128] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. As for the exhaust means, a turbo pump equipped with a cold trap is preferable. The deposition chamber evacuated by the cryopump may be filled with, for example, hydrogen atoms or water. Since compounds containing hydrogen atoms such as (H2O) are exhausted, the insulating layer 4 formed in the film formation chamber is The concentration of impurities contained in 07 can be reduced.

[0129] The sputtering gas used in forming the insulating layer 407 is hydrogen, water, a hydroxyl group, a hydride, or the like. It is possible to use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. preferable.

[0130] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and direct sputtering. The DC sputtering method uses a current source, and the pulsed DC sputtering method uses a pulsed bias. There is a sputtering method. The RF sputtering method is mainly used to deposit insulating films. The DC sputtering method is mainly used for forming metal films.

[0131] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0132] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. ECR using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0133] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering agent are interposed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting with gas components. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0134] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer from the substrate 400 side, A nitride insulating layer, such as a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer A laminated structure of an insulating layer and the oxide insulating layer may be used.

[0135] For example, a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced to the silicon tubing. Using the target, a silicon nitride layer is formed between the silicon oxide layer and the substrate. In the same manner as for the silicon oxide layer, the silicon nitride layer is also formed while removing the residual moisture in the processing chamber. It is preferable to form a film of

[0136] When forming a silicon nitride layer, the substrate may be heated during film formation.

[0137] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 407, the silicon nitride The silicon oxide layer and the silicon nitride layer are formed in the same processing chamber using a common silicon target. A nitrogen-containing sputtering gas is first introduced to the silicon wafer mounted in the processing chamber. The target is used to form a silicon nitride layer, and then the sputtering gas is changed to a sputtering gas containing oxygen. The silicon nitride layer is then deposited using the same silicon target. Since the silicon nitride layer and the silicon oxide layer can be formed in succession without exposure to the atmosphere, This can prevent impurities such as hydrogen and moisture from being adsorbed on the surface of the silicon layer.

[0138] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the insulating layer 407. do.

[0139] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor layer as much as possible, As a pretreatment for the film formation, the substrate on which the insulating layer 407 is formed is heated in a preheating chamber of the sputtering device. The plate 400 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 400 are desorbed and exhausted. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. This pre-heating process can be omitted. This may be performed on the substrate 400 before the formation of the source insulating layer 402, or after the source electrode layer or A substrate on which the drain electrode layer 415a and the source or drain electrode layer 415b have been formed You can do the same for 400.

[0140] Before the oxide semiconductor layer was formed by a sputtering method, argon gas was introduced. In this state, plasma is generated to perform reverse sputtering, and the metal adhering to the surface of the insulating layer 407 is removed. It is preferable to remove aluminum by reverse sputtering without applying voltage to the target side. A voltage is applied to the substrate side using a high-frequency power supply in a nitrogen atmosphere to form plasma on the substrate. This is a method for modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. It may be used.

[0141] The oxide semiconductor layer is formed by a sputtering method. Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn -O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based oxide semiconductor layers are used. In this embodiment, the oxide semiconductor layer is formed using an In-Ga-Zn-O based metal oxide target. The oxide semiconductor layer is formed by a sputtering method using a rare gas (typically In the case of a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of rare gas (typically argon) and oxygen, The film can be formed by sputtering in an atmosphere. When using a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less, the film is formed. It is also possible.

[0142] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, or a hydride. By using high-purity gas in which impurities such as is preferred.

[0143] Zinc oxide is mainly used as a target for producing an oxide semiconductor layer by sputtering. A target of a metal oxide having a metal component can be used. Another example of the target is a metal oxide target containing In, Ga, and Zn (composition ratio: , In2O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn=1:1 :0.5[atom]) can be used. Metals including In, Ga, and Zn can also be used. As an oxide target, In:Ga:Zn=1:1:1[atom] or In:Ga A target having a composition ratio of Zn=1:1:2 [atom] can also be used. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high filling rate, the oxide semiconductor film formed The body layer becomes a dense membrane.

[0144] The oxide semiconductor layer is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual water in the treatment chamber. A sputtering gas from which hydrogen and moisture have been removed while removing the molybdenum is introduced, and a metal oxide is deposited on the target. As a starting material, an oxide semiconductor layer is formed on a substrate 400. For this purpose, it is preferable to use an adsorption type vacuum pump. It is preferable to use a vacuum pump or a titanium sublimation pump. Alternatively, a turbo pump with a cold trap may be used. The deposition chamber that has been evacuated contains, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) (more Preferably, the oxide film formed in the film formation chamber is exhausted, since the oxide film formed in the film formation chamber is exhausted. The concentration of impurities in the semiconductor layer can be reduced. May be heated.

[0145] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, Pressure 0.4 Pa, direct current (DC) power supply power 0.5 kW, oxygen and argon (oxygen flow rate 15 s ccm: Argon flow rate 30sccm) atmosphere is applied. When a DC power supply is used, the powdery substances (also called particles or dust) generated during film formation are lightly The oxide semiconductor layer is preferably 5 nm or more. The thickness is set to 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0146] Next, the oxide semiconductor layer is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer. In order to form the island-shaped oxide semiconductor layer 412, The resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the injection method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0147] The etching of the oxide semiconductor layer may be performed by either dry etching or wet etching. Alternatively, either one may be used, or both may be used.

[0148] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C Cl4) etc.) are preferred.

[0149] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur fluoride (S F6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HB r), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing , etc. can be used.

[0150] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0151] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0152] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials such as these, we can make effective use of resources and reduce costs. do.

[0153] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0154] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 412 by a thermal etching method.

[0155] In this embodiment, the oxide semiconductor layer 412 is subjected to first heat treatment. The temperature is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is After performing heat treatment at 450°C for 1 hour in a nitrogen atmosphere, the substrate was exposed to the air. The first heat treatment can prevent water and hydrogen from entering the oxide semiconductor layer. The semiconductor layer 412 can be dehydrated or dehydrogenated.

[0156] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. A device that heats the workpiece by thermal radiation may be used. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. As the gas, a rare gas such as argon or nitrogen is used, which is almost completely absorbed by the object to be treated by the heat treatment. An inert gas that is minimally reactive is used.

[0157] For example, the first heat treatment is performed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved out and heated to a high temperature inert gas. You can also use GRTA, which is a method of removing the food from inside the container. Using GRTA, high-temperature heat treatment can be performed in a short time. It becomes.

[0158] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0159] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 412, In some cases, the semiconductor layer crystallizes to become a microcrystalline or polycrystalline film. In some cases, the oxide semiconductor layer is 0% or more, or 80% or more of a microcrystalline oxide semiconductor layer. Depending on the conditions of the heat treatment or the material of the oxide semiconductor layer 412, a non-crystalline oxide semiconductor layer containing no crystalline components may be formed. In some cases, the oxide semiconductor layer is crystalline. In other cases, a microcrystalline part ( Oxide semi-conductors with grain sizes of 1 nm to 20 nm (typically 2 nm to 4 nm) It may also be a conductive layer.

[0160] In addition, the first heat treatment is performed on the oxide semiconductor layer 412 before it is processed into the island-shaped oxide semiconductor layer 412. In that case, after the first heat treatment, the substrate is taken out of the heating device and Then, a photolithography process is performed.

[0161] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the deposition, a source electrode layer and a drain electrode layer were stacked over the oxide semiconductor layer 412. After forming a gate insulating layer on the source electrode layer and the drain electrode layer, .

[0162] Next, a conductive layer is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive layer can be formed by sputtering or vacuum deposition. An element selected from U, Ta, Ti, Mo, and W, or an alloy containing the above elements Manganese, magnesium, zirconium, beryllium, thorium, etc. The conductive layer may be formed of a single layer structure. However, it may be a laminated structure of two or more layers. For example, a single layer of aluminum containing silicon Structure: A two-layer structure with a titanium layer laminated on an aluminum layer, a Ti layer and a layer Examples include a three-layer structure in which an aluminum layer is laminated on top of the aluminum layer and a Ti layer is formed on top of that. In addition, titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum are added to Al. An element selected from Mo, chromium, neodymium, and scandium. A single or multiple combination layers of these, or alloy layers or nitride layers thereof may be used.

[0163] A resist mask is formed on the conductive layer by a second photolithography process, and selectively etched. The source or drain electrode layer 415a is then etched. After the electrode layer 415b is formed, the resist mask is removed (see FIG. 6B). When the ends of the formed source electrode layer and drain electrode layer are tapered, the gate electrode layer laminated thereon can be easily formed. This is preferable because it improves the coverage of the insulating layer.

[0164] In this embodiment, the source or drain electrode layer 415a A titanium layer having a thickness of 150 nm is formed as the electrode layer 415b by sputtering.

[0165] Note that when the conductive film is etched, the oxide semiconductor layer 412 is removed and the insulating film therebelow is removed. The materials and etching conditions are appropriately adjusted so that the layer 407 is not exposed.

[0166] In this embodiment, a Ti layer is used as the conductive film, and an In-GaAs layer is used as the oxide semiconductor layer 412. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0167] Note that in the second photolithography step, the oxide semiconductor layer 412 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). To form the drain electrode layer 415a and the source or drain electrode layer 415b, The resist mask may be formed by an ink-jet method. When the film is formed by the photolithography method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0168] The exposure to light during the formation of the resist mask in the second photolithography process uses ultraviolet light and KrF The source electrode layers adjacent to each other on the oxide semiconductor layer 412 are irradiated with laser light or ArF laser light. The width of the gap between the lower end of the drain electrode layer and the lower end of the thin film transistor to be formed later The channel length L is determined. Note that when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of several nm to several tens of nm. et) is used for exposure when forming a resist mask in the second photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the thin film transistor to 10 nm or more and 1000 nm or less. This allows the operating speed of the circuit to be increased and the off-current value to be made extremely small. This also contributes to reducing power consumption.

[0169] Next, the insulating layer 407, the oxide semiconductor layer 412, the source or drain electrode layer 41 5a, a gate insulating layer 402 is formed over the source or drain electrode layer 415b (FIG. 6(C)).

[0170] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. A single layer or a stacked layer of a silicon layer can be used. In order to prevent the amount of the gate insulating layer 402 from being included in the amount of the gate insulating layer 402, the gate insulating layer 402 is formed by a sputtering method. In the case where the silicon oxide layer is formed by a sputtering method, the target A silicon target or a quartz target is used as the sputtering gas, and oxygen or A mixture of oxygen and argon gas is used.

[0171] The gate insulating layer 402 is a source or drain electrode layer 415a, A silicon oxide layer and a silicon nitride layer are laminated from the drain electrode layer 415b side. For example, the first gate insulating layer may be an oxide film having a thickness of 5 nm to 300 nm. The silicon layer (SiO x (x>0) and forming a second gate insulating layer on the first gate insulating layer. A silicon nitride layer (Si) having a thickness of 50 nm to 200 nm is formed by sputtering. N y (y>0) may be laminated to form a gate insulating layer having a thickness of 100 nm. In this condition, the pressure was 0.4 Pa, the high-frequency power supply power was 1.5 kW, and oxygen and argon (oxygen flow rate 25 The deposition was performed by RF sputtering under an atmosphere of argon (25 sccm: argon flow rate 1:1). A silicon oxide layer is formed to a thickness of 100 nm.

[0172] Next, a resist mask is formed by a third photolithography process, and selectively etched. A part of the gate insulating layer 402 is removed by etching to form a source electrode layer or a drain electrode layer. The openings 421a and 421b reach the source electrode layer 415a and the drain electrode layer 415b. (See FIG. 6(D)).

[0173] Next, a conductive layer is formed over the gate insulating layer 402 and the openings 421a and 421b. A gate electrode layer 411 and wiring layers 414a and 414b are formed by the photolithography process of 4. The resist mask may be formed by an ink-jet method. When formed using the inkjet method, no photomask is used, reducing manufacturing costs. .

[0174] The gate electrode layer 411 and the wiring layers 414a and 414b are made of molybdenum, titanium, chromium, etc. Metallic materials such as titanium, tantalum, tungsten, aluminum, copper, neodymium, and scandium Alternatively, it can be formed in a single layer or a laminated layer using an alloy material mainly composed of these. .

[0175] For example, a two-layer laminate structure of a gate electrode layer 411 and wiring layers 414a and 414b may be as follows: Two-layer structure with molybdenum layer on aluminum layer or molybdenum on copper layer A two-layer structure with a copper layer laminated on top, or a titanium nitride layer or tantalum nitride layer laminated on a copper layer A two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. The three-layer laminate structure is a tungsten layer or a tungsten nitride layer, and an aluminum layer. A silicon alloy layer or an aluminum-titanium alloy layer and a titanium nitride layer or a titanium layer It is preferable that the gate electrode is a laminate of the above-mentioned conductive layer and the above-mentioned conductive layer. A transparent conductive layer may be formed using a transparent conductive oxide or the like. This can be cited as an example.

[0176] In this embodiment, the gate electrode layer 411 and the wiring layers 414a and 414b are formed by sputtering. A titanium layer with a thickness of 150 nm is formed by the etching method.

[0177] Then, a second heat treatment (preferably The heating temperature is 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 410 .

[0178] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature, or by heating from room temperature for 1 The temperature is raised to 00°C or higher and lowered to room temperature several times. This heating treatment may be carried out under reduced pressure. By carrying out this treatment, the heating time can be shortened.

[0179] Through the above steps, the oxide semiconductor layer 4 is obtained, in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced. A thin film transistor 410 having a thickness of 12 can be fabricated (see FIG. 6(E)). The transistor 410 is a thin-film transistor constituting the logic circuit shown in the first and second embodiments. It can be applied as a data.

[0180] In addition, a protective insulating layer and a planarizing insulating layer for planarization are provided on the thin film transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like may be used as the protective insulating layer. Applying a single layer or a stack of layers of silicon, silicon oxide, or aluminum oxide. can be done.

[0181] Although not shown, the planarizing insulating layer may be made of polyimide, acrylic resin, or benzocyclohexyl. Use heat-resistant organic materials such as arylbutene resins, polyamides, and epoxy resins. In addition to the above organic materials, low-k materials and siloxane resins are also available. Examples of usable materials include polysilicon, polysilicon glass (PSG), and boron phosphorus glass (BPSG). In addition, a planarized insulating layer is formed by stacking multiple insulating layers made of these materials. Good too.

[0182] The siloxane-based resin is a Si-O compound formed using a siloxane-based material as a starting material. The siloxane resin corresponds to a resin containing -Si bonds. The organic group may have a fluoro group. It's fine if it is.

[0183] The method for forming the flattening insulating layer is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A fukota or the like can be used.

[0184] When forming the oxide semiconductor layer as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor layer can be reduced. The oxide semiconductor layer can be stabilized.

[0185] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0186] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0187] (Embodiment 4) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is In addition, the same parts as those in the third embodiment or parts having similar functions and processes are shown. The process may be the same as that of the third embodiment, and the repeated explanation will be omitted. A detailed description of is also omitted.

[0188] One mode of a thin film transistor and a manufacturing method thereof according to this embodiment will be described with reference to FIGS. explain.

[0189] 7A and 7B show an example of a planar and cross-sectional structure of a thin film transistor. The thin film transistor 460 shown in (B) is one of the thin film transistors having a top gate structure. It is.

[0190] FIG. 7A is a plan view of a thin film transistor 460 having a top gate structure, and FIG. 7(A) is a cross-sectional view taken along line D1-D2 of FIG.

[0191] The thin film transistor 460 is formed by forming an insulating layer 457, a source The electrode layer or drain electrode layer 465a (465a1, 465a2), the oxide semiconductor layer 462 , a source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, a gate The source electrode layer 461 (461a, 461b) and the source or drain electrode layer 465 a (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also a gate insulating layer. The layer 452 is electrically connected to the wiring layer through an opening provided therein.

[0192] Hereinafter, a thin film transistor 460 will be fabricated on a substrate 450 using FIGS. The process will be explained.

[0193] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0194] In this embodiment, the insulating layer 457 is a silicon oxide layer formed by a sputtering method. The substrate 450 is transferred to a processing chamber, and a spa containing high-purity oxygen from which hydrogen and moisture have been removed is used. A target gas is introduced, and a silicon target or quartz (preferably synthetic quartz) is used to heat the substrate 4. A silicon oxide layer is formed as an insulating layer 457 on the substrate 50. Note that oxygen is used as a sputtering gas. Alternatively, a mixed gas of oxygen and argon is used.

[0195] For example, the purity of the sputtering gas is 6N, quartz (preferably synthetic quartz) is used, and the substrate The temperature was 108°C, the distance between the substrate and the target (TS distance) was 60 mm, and the pressure was 0.4 Pa, high frequency power supply power 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon A silicon oxide layer was formed by RF sputtering under a 25 sccm (1:1) atmosphere. The thickness of the film is 100 nm. Note that silicon is used instead of quartz (preferably synthetic quartz). The target can be used as a target for depositing a silicon oxide layer.

[0196] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl, or moisture. The deposition chamber evacuated using an ion pump contains hydrogen atoms, water (H2O), and other hydrogen atoms. Since compounds containing impurities are exhausted, the impurities contained in the insulating layer 457 formed in the deposition chamber are The concentration can be reduced.

[0197] The sputtering gas used in forming the insulating layer 457 is hydrogen, water, a hydroxyl group, a hydride, or the like. It is possible to use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. preferable.

[0198] The insulating layer 457 may have a laminated structure, for example, a silicon nitride layer from the substrate 450 side, Nitride insulating layers such as silicon oxynitride layers, aluminum nitride layers, and aluminum oxynitride layers The insulating layer may have a stacked structure of the oxide insulating layer and the oxide insulating layer.

[0199] For example, a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced to the silicon tubing. Using the target, a silicon nitride layer is formed between the silicon oxide layer and the substrate. In the same manner as for the silicon oxide layer, the silicon nitride layer is also formed while removing the residual moisture in the processing chamber. It is preferable to form a film of

[0200] Next, a conductive layer is formed on the insulating layer 457, and a conductive layer is formed by a first photolithography process. A resist mask is formed on the electrode layer, and selective etching is performed to form a source electrode layer or a drain electrode layer. After forming the electrode layers 465a1 and 465a2, the resist mask is removed (FIG. 8(A)). The source and drain electrode layers 465a1 and 465a2 are divided in the cross-sectional view. Although the source electrode layer and the drain electrode layer are shown as a single layer, they are continuous layers. The end of the gate insulating layer is preferably tapered to improve coverage with the gate insulating layer to be laminated thereon. stomach.

[0201] The material of the source electrode layer or the drain electrode layer 465a1, 465a2 is Al, Cr , Cu, Ta, Ti, Mo, W, or a material containing the above elements In addition, manganese, magnesium, zirconium, beryllium, tritium, etc. The metal conductive layer may be a single layer structure. For example, a single layer of aluminum containing silicon may be used. A two-layer structure with a titanium layer on an aluminum layer, a Ti layer and a layer on the Ti layer Examples include a three-layer structure in which an aluminum layer is laminated on top of the aluminum layer and a Ti layer is then formed on top of that. In addition, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo) and Elements selected from Mo, Cr, Nd, and Sc A single or combination of elements, alloy layers, or nitride layers may be used.

[0202] In this embodiment, the source and drain electrode layers 465a1 and 465a2 are A titanium layer having a thickness of 150 nm is formed by a varistor deposition method.

[0203] Next, the insulating layer 457 and the source and drain electrode layers 465a1 and 465a2 are An oxide semiconductor layer having a thickness of 2 nm to 200 nm is formed on the insulating film.

[0204] Next, the oxide semiconductor layer is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 46. 2 (see FIG. 8B). In this embodiment, the oxide semiconductor layer is The film is formed by sputtering using an nO-based metal oxide target.

[0205] The oxide semiconductor layer is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual water in the treatment chamber. A sputtering gas from which hydrogen and moisture have been removed while removing the molybdenum is introduced, and a metal oxide is deposited on the target. As a starting material, an oxide semiconductor layer is formed over a substrate 450. For this purpose, it is preferable to use an adsorption type vacuum pump. It is preferable to use a vacuum pump or a titanium sublimation pump. Alternatively, a turbo pump with a cold trap may be used. The deposition chamber that has been evacuated contains, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) (more Preferably, the oxide film formed in the film formation chamber is exhausted, since the oxide film formed in the film formation chamber is exhausted. The concentration of impurities in the semiconductor layer can be reduced. May be heated.

[0206] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, or a hydride. By using high-purity gas in which impurities such as is preferred.

[0207] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, Pressure 0.4 Pa, direct current (DC) power supply power 0.5 kW, oxygen and argon (oxygen flow rate 15 s ccm: Argon flow rate 30sccm) atmosphere is applied. When a DC power supply is used, the powdery substances (also called particles or dust) generated during film formation are lightly The oxide semiconductor layer is preferably 5 nm or more. The thickness is set to 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0208] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 462 by a thermal etching method.

[0209] In this embodiment, the oxide semiconductor layer 462 is subjected to first heat treatment. The temperature is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the specimen was placed in an oxygen-free environment without exposure to air. This first heat treatment prevents water and hydrogen from entering the oxide semiconductor layer and obtains an oxide semiconductor layer. Thus, the oxide semiconductor layer 462 can be dehydrated or dehydrogenated.

[0210] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment For example, the first heat treatment may be performed at a temperature of 650° C. to 7 The substrate is moved into an inert gas atmosphere heated to a high temperature of 00°C and heated for several minutes. Alternatively, GRTA can be performed by moving the container and releasing it from the inert gas heated to a high temperature. When used, high-temperature heat treatment can be performed in a short period of time.

[0211] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0212] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases the layer may crystallize to become a microcrystalline or polycrystalline layer.

[0213] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, the substrate may be removed from the heating device after the first heat treatment. Then, the substrate is taken out and subjected to a photolithography process.

[0214] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the deposition, a source electrode layer and a drain electrode layer are further stacked on the oxide semiconductor layer. After forming a gate insulating layer on the source electrode layer and the drain electrode layer, .

[0215] Next, a conductive layer is formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive layer by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask is The source / drain electrode layer 465b and the wiring layer 465 are removed (see FIG. 8C). The source electrode layer 68 is formed by the same material and process as the source electrode layer 465a1 and the drain electrode layer 465a2. It is sufficient to form it.

[0216] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are A titanium layer having a thickness of 150 nm is formed by a dipping method. and the source or drain electrode layer 465a1 and 465a2. For the example in which the same titanium layer is used for the source electrode layer 465a1 and the drain electrode layer 46b, The source or drain electrode layer 465b and the source electrode layer 5a2 have a selectivity in etching. Therefore, the source electrode layer or the drain electrode layer 465a1 and 465a2 are not The oxide semiconductor layer 465b is not etched during etching of the drain electrode layer 465b. A wiring layer 468 is formed on the source electrode layer or drain electrode layer 465a2 that is not covered with the dielectric layer 462. The source and drain electrode layers 465a1 and 465a2 are provided. The drain electrode layer 465b is made of a different material having a high selectivity in an etching process. When used, the source or drain electrode layer 465a2 is protected during etching. The wiring layer 468 does not necessarily have to be provided.

[0217] Note that the conductive film is etched so that the oxide semiconductor layer 462 is not removed. The materials and etching conditions are adjusted appropriately.

[0218] In this embodiment, a Ti layer is used as the conductive film, and an In-GaAs layer is used as the oxide semiconductor layer 462. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0219] Note that in the third photolithography step, part of the oxide semiconductor layer 462 is etched. In some cases, the source electrode layer or the oxide semiconductor layer may have a groove (a recess). A resist mask for forming the drain electrode layer 465b and the wiring layer 468 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing costs can be reduced.

[0220] Next, the insulating layer 457, the oxide semiconductor layer 462, and the source or drain electrode layer 46 5a1, 465a2, the source or drain electrode layer 465b, and the wiring layer 468. A gate insulating layer 452 is formed.

[0221] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. Note that if the gate insulating layer 452 contains a large amount of hydrogen, a single layer or a stacked layer of hydrogen may be used. In order to prevent the amount of the gate insulating layer 452 from being included in the amount of the gate insulating layer 452, the gate insulating layer 452 is formed by a sputtering method. In the case where the silicon oxide layer is formed by a sputtering method, the target A silicon target or a quartz target is used as the sputtering gas, and oxygen or A mixture of oxygen and argon gas is used.

[0222] The gate insulating layer 452 is a source or drain electrode layer 465a1, 465a2, A silicon oxide layer and a silicon nitride layer are laminated from the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, the power of the high frequency power source is 1.5 kW, oxygen and argon (oxygen flow rate 25sccm:argon flow rate 25sccm=1:1) The oxide film was deposited to a thickness of 100 nm by RF sputtering in a 1000 MPa atmosphere. A recon layer is formed.

[0223] Next, a resist mask is formed by a fourth photolithography process, and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 that reaches the wiring layer 468. Although not shown, when the opening 423 is formed, a source electrode layer or a drain electrode layer is formed. An opening may be formed that reaches the source electrode layer 465b. Alternatively, the opening to the drain electrode layer 465b is formed after laminating an interlayer insulating layer. In this example, a wiring layer to be connected to the semiconductor device is formed in the opening.

[0224] Next, a conductive layer is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a lithography process. The resist mask may be formed by an ink-jet method. When the ink jet method is used, no photomask is used, which reduces manufacturing costs.

[0225] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum, titanium, Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. A single layer or a laminate of the above metallic materials or alloy materials containing these as main components can be applied.

[0226] In this embodiment, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are A titanium layer having a thickness of 150 nm is formed by a sputtering method.

[0227] Then, a second heat treatment (preferably The heating temperature is 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 460 .

[0228] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature, or by heating from room temperature for 1 The temperature is raised to 00°C or higher and lowered to room temperature several times. This heating treatment may be carried out under reduced pressure. By carrying out this treatment, the heating time can be shortened.

[0229] Through the above steps, the oxide semiconductor layer 4 is obtained, in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced. A thin film transistor 460 having a layer 62 can be formed (see FIG. 8E).

[0230] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, a solenoid may be formed on the gate insulating layer 452, the protective insulating layer, and the planarizing insulating layer. An opening is formed so as to reach the source electrode layer or drain electrode layer 465b, and the source electrode layer Alternatively, a wiring layer electrically connected to the drain electrode layer 465b is formed.

[0231] When forming the oxide semiconductor film as described above, it is necessary to remove the residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0232] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0233] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0234] (Embodiment 5) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is Here, an example will be shown. Note that the same parts as those in the third or fourth embodiment or parts having similar functions, The steps may be similar to those in the third or fourth embodiment, and a repeated explanation thereof will be omitted. Further, detailed explanations of the same parts will be omitted.

[0235] The thin film transistor of this embodiment will be described with reference to FIG.

[0236] 9(A) and (B) show an example of a cross-sectional structure of a thin film transistor. In the thin film transistors 425 and 426 shown in FIG. It is one of the thin film transistors with a sandwich structure.

[0237] In addition, in FIGS. 9(A) and 9(B), a silicon substrate is used. Thin film transistors 425 and 426 are provided on an insulating layer 422 provided on a substrate 420. It is being done.

[0238] In FIG. 9A, an insulating layer 422 and an insulating layer 407 are provided on a silicon substrate 420. A conductive layer 427 is provided between the oxide semiconductor layer 412 and the insulating layer 424 so as to overlap with at least the entire oxide semiconductor layer 412. do.

[0239] In FIG. 9B, the conductive layer between the insulating layer 422 and the insulating layer 407 is the conductive layer 424. At least the channel formation region of the oxide semiconductor layer 412 is processed by etching in this manner. This is an example where it overlaps with a part including.

[0240] The conductive layers 427 and 424 are made of a metal material that can withstand the heat treatment temperature in the subsequent process. Commonly, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), Elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc), or Use alloys containing the above elements or nitrides containing the above elements. In addition, the structure may be a single layer or a multilayer structure. For example, a single layer of tungsten or a nitride layer may be used. A stacked structure of a tungsten layer and a tungsten layer can be used.

[0241] The conductive layers 427 and 424 are connected to the gate electrodes of the thin film transistors 425 and 426. This may be the same as or different from layer 411 and serves as a second gate electrode layer. In addition, the potentials of the conductive layers 427 and 424 may be fixed potentials of GND and 0V. This is also fine.

[0242] The conductive layers 427 and 424 control the electrical characteristics of the thin film transistors 425 and 426. It is possible.

[0243] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0244] (Embodiment 6) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is An example is given below.

[0245] One mode of a thin film transistor and a manufacturing method thereof will be described with reference to FIGS. do.

[0246] FIG. 10(E) shows an example of a cross-sectional structure of a thin film transistor. The transistor 390 is a type of bottom gate structure, also called an inverted staggered thin film transistor. cormorant.

[0247] In addition, the thin film transistor 390 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A star can also be formed.

[0248] 10(A) to (E), a thin film transistor 390 is fabricated on a substrate 394. The process for doing so will be described.

[0249] First, a conductive layer is formed on a substrate 394 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 391 is formed by a deposition process. The end of the gate electrode layer 391 is A perforated shape is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The resist mask may be formed by an inkjet method. When the method is used for formation, no photomask is used, and therefore the manufacturing cost can be reduced.

[0250] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least At the very least, it is necessary for the material to have heat resistance sufficient to withstand subsequent heat treatment. For example, The substrate 394 is a glass substrate such as barium borosilicate glass or aluminoborosilicate glass. A plate can be used.

[0251] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The above is recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. Generally, it contains more barium oxide (BaO) than boron oxide (B2O3). By mixing BaO with B2O3, a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing a large amount of fluorine.

[0252] Instead of the above glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used. Additionally, plastic substrates and the like can also be used as appropriate.

[0253] An insulating layer serving as a base layer may be provided between the substrate 394 and the gate electrode layer 391. The function of the silicon nitride layer is to prevent the diffusion of impurity elements from the substrate 394. A silicon layer, a silicon oxide nitride layer, or a silicon oxynitride layer is formed on one or more films. The laminated structure can be formed by the above.

[0254] The gate electrode layer 391 may be made of any of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as aluminum, copper, neodymium, and scandium, or alloys containing these as the main components. A single layer or multiple layers of gold material can be applied.

[0255] For example, the gate electrode layer 391 may have a two-layer laminate structure of molybdenum on an aluminum layer. Two-layer structure with a molybdenum layer laminated on a copper layer, two-layer structure with a molybdenum layer laminated on a copper layer, A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on the titanium nitride layer, and a molybdenum layer and a A two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated, or a tungsten nitride layer and a tungsten layer are laminated. A two-layer structure is preferable. A three-layer structure is preferably a tungsten layer or a tungsten nitride layer. A layer of tin and an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium. It is preferable that the transparent insulating film is a laminate of a titanium nitride layer and a titanium layer. A gate electrode layer can also be formed using a conductive layer having a light-transmitting property. An example of such a material is a transparent conductive oxide.

[0256] Then, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0257] The gate insulating layer 397 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. A single layer or a stacked layer of a silicon layer can be used. In order to prevent the amount of the gate insulating layer 397 from being included in the amount of the gate insulating layer 397, the gate insulating layer 397 is formed by a sputtering method. In the case where the silicon oxide layer is formed by a sputtering method, the target A silicon target or a quartz target is used as the sputtering gas, and oxygen or This is carried out using a mixture of oxygen and argon gas.

[0258] The gate insulating layer 397 is a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. For example, the first gate insulating layer may be formed by sputtering. The silicon nitride layer (SiN y (y>0) A second gate insulating layer having a thickness of 5 nm to 300 nm is formed on the first gate insulating layer. Silicon oxide layer (SiO x (x>0)) is laminated to form a gate insulating layer with a thickness of 100 nm. do.

[0259] In addition, hydrogen, a hydroxyl group, and water are added to the gate insulating layer 397 and the oxide semiconductor layer 393 to be formed later. In order to minimize the inclusion of foreign matter, the sputtering equipment is used as a pretreatment for film formation. In the preheating chamber, the gate electrode layer 391 is formed on the substrate 394, or the gate insulating layer 397 is formed. The substrate 394 on which the SiO 2 is formed is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 394. It is preferable to desorb and exhaust the gas. The preheating temperature is 100°C to 400°C. The temperature is preferably 150° C. or higher and 300° C. or lower. A cryopump is preferable. This preheating process can be omitted. The preheating may be performed before the formation of the oxide insulating layer 396 to be formed later, or after the formation of the oxide insulating layer 396 to be formed later. The substrate 394 on which the source electrode layer 395a and the drain electrode layer 395b are formed is also similarly You may go.

[0260] Next, an oxide semiconductor layer 3 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 397. 93 is formed (see FIG. 10(A)).

[0261] Note that before the oxide semiconductor layer 393 was formed by a sputtering method, argon gas was With the electrodes introduced, plasma is generated to perform reverse sputtering, and the electrodes are attached to the surface of the gate insulating layer 397. It is preferable to remove the dust adhering to the target. In an argon atmosphere, a voltage was applied to the substrate side using an RF power source to generate plasma on the substrate. This is a method of forming a silicon substrate and modifying the surface. Note that nitrogen, helium, or oxygen can be used instead of argon. Elements such as fluorine may also be used.

[0262] The oxide semiconductor layer 393 is formed by a sputtering method. In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxides In this embodiment, the oxide semiconductor layer 393 is made of an In-Ga-Zn-O based metal. The oxide semiconductor layer 3 is formed by a sputtering method using a metal oxide target. 93 is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically The film can be formed by sputtering in a mixed atmosphere of argon and oxygen. In addition, when the sputtering method is used, the SiO2 content is 2% by weight or more and 10% by weight or less. The film may be formed using a target.

[0263] As a target for depositing the oxide semiconductor layer 393 by a sputtering method, A metal oxide target mainly composed of lead can be used. Another example of a target is an oxide semiconductor target containing In, Ga, and Zn (composition: The ratio is In2O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn =1:1:0.5 [atom]). In, Ga, and Zn can be used. Metal oxide targets containing In:Ga:Zn=1:1:1[atom] or I It is also possible to use a target with a composition ratio of n:Ga:Zn=1:1:2 [atom]. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. By using a metal oxide target with a high filling rate, the oxide film formed is The compound semiconductor layer becomes a dense film.

[0264] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to room temperature or a temperature less than 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering process in which hydrogen and moisture have been removed is completed. A gas is introduced, and an oxide semiconductor layer 393 is formed on a substrate 394 using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump is used. As an exhaust means, a turbo pump with a cold trap is preferably used. The deposition chamber evacuated using a cryopump may be filled with, for example, hydrogen atoms, water, etc. Compounds containing hydrogen atoms such as (H2O) (and more preferably compounds containing carbon atoms) are excluded. Therefore, the concentration of impurities in the oxide semiconductor layer formed in the deposition chamber can be reduced. In addition, the sputtering process is performed while removing the moisture remaining in the processing chamber using a cryopump. By performing the above-mentioned process, the substrate temperature during the formation of the oxide semiconductor layer 393 is set to be from room temperature to lower than 400° C. It is possible.

[0265] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 P. a, DC power supply power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere conditions In addition, when a pulsed direct current (DC) power supply is used, the powdery material (pulse) generated during film formation is This is preferable because it can reduce the amount of oxide particles (also called "tickles" or "dust") and make the film thickness distribution uniform. The thickness of the semiconductor layer is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material, and an appropriate thickness may be selected depending on the material.

[0266] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and direct sputtering. The DC sputtering method uses a current source, and the pulsed DC sputtering method uses a pulsed bias. There is a sputtering method. The RF sputtering method is mainly used to deposit insulating films. The DC sputtering method is mainly used for forming metal films.

[0267] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0268] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. ECR using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0269] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering agent are interposed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting with gas components. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0270] Next, the oxide semiconductor layer 393 is divided into island-shaped oxide semiconductor layers by a second photolithography process. The insulating film is processed into a conductor layer 399 (see FIG. 10B). A resist mask for forming the resist film may be formed by an ink-jet method. When the ink jet method is used, no photomask is used, which reduces manufacturing costs.

[0271] Also, when forming a contact hole in the gate insulating layer 397, the process is performed using an oxide semiconductor. This can be done when forming the coating layer 399 .

[0272] Note that the etching of the oxide semiconductor layer 393 here can be performed by dry etching or wet etching. Etching may be used, or both may be used.

[0273] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C Cl4) etc.) are preferred.

[0274] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur fluoride (S F6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HB r), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing , etc. can be used.

[0275] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0276] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0277] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials such as these, we can make effective use of resources and reduce costs. do.

[0278] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0279] Note that reverse sputtering is performed before the conductive layer is formed in the next step, and the oxide semiconductor layer 399 and the gate It is preferable to remove resist residues and the like adhering to the surface of the gate insulating layer 397.

[0280] Next, a conductive layer is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive layer can be formed by sputtering or vacuum deposition. , Cr, Cu, Ta, Ti, Mo, W, or the above elements are included In addition, alloys of manganese, magnesium, zirconium, beryllium, etc. Alternatively, a material selected from one or more of the following metal conductors may be used: The layer may be a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single-layer structure of a titanium layer, a two-layer structure of a titanium layer on an aluminum layer, a Ti layer and A three-layer structure is formed by laminating an aluminum layer on a Ti layer, and then forming a Ti layer on top of that. In addition, titanium (Ti), tantalum (Ta), tungsten (W ), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc) A layer of a single or multiple combinations of elements selected from the above, an alloy layer, or a nitride layer may be used. stomach.

[0281] A resist mask is formed on the conductive layer by a third photolithography process, and selectively etched. After etching to form a source electrode layer 395a and a drain electrode layer 395b, The mask is then removed (see FIG. 10(C)).

[0282] The third photolithography process uses ultraviolet light and KrF for exposure when forming the resist mask. The source electrode layers adjacent to each other on the oxide semiconductor layer 399 are irradiated with a laser beam or an ArF laser beam. The width of the gap between the lower end of the drain electrode layer and the lower end of the thin film transistor to be formed later The channel length L is determined. Note that when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of several nm to several tens of nm. et) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the thin film transistor to 10 nm or more and 1000 nm or less. This allows the operating speed of the circuit to be increased and the off-current value to be made extremely small. This also contributes to reducing power consumption.

[0283] Note that the oxide semiconductor layer 399 is not removed when the conductive layer is etched. The materials and etching conditions are adjusted appropriately.

[0284] In this embodiment, a Ti layer is used as the conductive film, and an In-GaAs layer is used as the oxide semiconductor layer 399. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0285] Note that in the third photolithography step, the oxide semiconductor layer 399 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). A resist mask for forming the drain electrode layer 395a and the drain electrode layer 395b is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0286] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0287] Plasma treatment with gases such as N2O, N2, or Ar removes exposed oxide. Water adsorbed on the surface of the semiconductor layer may be removed. A plasma treatment may be performed using the gas.

[0288] When the plasma treatment is performed, the oxide semiconductor layer is protected from contact with the air. An oxide insulating layer 396 is formed as a protective insulating layer (see FIG. 10D). In this embodiment, The oxide semiconductor layer 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b. In this region, the oxide semiconductor layer 399 and the oxide insulating layer 396 are formed in contact with each other.

[0289] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399, a source The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated at room temperature or 100° C. A sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. A silicon target is used to deposit a defective silicon oxide layer.

[0290] For example, the purity of the sputtering gas is 6N and the silicon target is doped with boron. (resistance value 0.01Ω·cm) and the distance between the substrate and the target (TS distance) 89mm, pressure 0.4Pa, direct current (DC) power supply power 6kW, oxygen (oxygen flow rate 100% A silicon oxide layer is formed by pulse DC sputtering in a 300 MPa (100 MPa) atmosphere. In addition, quartz (preferably synthetic quartz) is used instead of the silicon target. It can be used as a target for forming a silicon layer. The reaction is carried out using oxygen or a mixed gas of oxygen and argon.

[0291] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 399 and the oxide insulating layer 396. This is to ensure that it is not included.

[0292] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H Since compounds containing hydrogen atoms such as 2O) are exhausted, the film formed in the film formation chamber In addition, the concentration of impurities in the oxide insulating layer 396 can be reduced.

[0293] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide Alternatively, an aluminum nitride layer, an aluminum oxynitride layer, or the like can be used.

[0294] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 4 Heat treatment may be performed at 00° C. In this embodiment, the oxide insulating layer 396 has many defects. Therefore, hydrogen, moisture, and hydroxide contained in the oxide semiconductor layer 399 are removed by this heat treatment. Impurities such as bases or hydrides are diffused into the oxide insulating layer 396, and the oxide semiconductor layer 399 is The impurities contained in the above can be further reduced.

[0295] The oxide semiconductor layer 3 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced by the above steps is obtained. A thin film transistor 390 having the structure 92 can be formed (see FIG. 10(E)).

[0296] When forming the oxide semiconductor layer as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor layer can be reduced. This can stabilize the oxide semiconductor layer.

[0297] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is The protective insulating layer 398 is formed on the oxide insulating layer 396. The protective insulating layer 398 may be a silicon nitride layer, a nitride oxide layer, or the like. A silicon oxide layer, an aluminum nitride layer, an aluminum nitride oxide layer, or the like is used.

[0298] The substrate 394 on which the oxide insulating layer 396 has been formed is heated to 100° C. The sputtering gas was heated to 400°C and contained high-purity nitrogen from which hydrogen and moisture had been removed. In this case, the silicon nitride layer is formed using a silicon target. As with the protective insulating layer 396, a protective insulating layer 398 is formed while removing residual moisture in the processing chamber. It is preferable.

[0299] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the film formation of the protective insulating layer 398. By heating the substrate 394, hydrogen or moisture contained in the oxide semiconductor layer is oxidized to an oxide insulating layer. In this case, a heat treatment is performed after the formation of the oxide insulating layer 396. This does not have to be done.

[0300] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and the silicon nitride layer are placed in the same processing chamber and a common A silicon target can be used for deposition. First, oxygen-containing sputtering gas is introduced. Then, a silicon oxide layer is formed using a silicon target mounted in the processing chamber, and then The sputtering gas was changed to one containing nitrogen, and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are successively formed without exposure to the atmosphere. Therefore, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396. A silicon nitride layer is then laminated as a protective insulating layer 398, and then the oxide semiconductor layer is Heat treatment (temperature 100°C to 40°C) to diffuse hydrogen or moisture into the oxide insulating layer. 0℃).

[0301] After the protective insulation layer is formed, it is further left in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment may be performed at a constant temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. This heat treatment may be repeated several times to lower the temperature to 100° C. Before the formation, the heating treatment may be performed under reduced pressure. By performing the heating treatment under reduced pressure, the heating time can be shortened. This heat treatment makes it possible to obtain a normally-off thin film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0302] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, By removing residual moisture in the reaction atmosphere, the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced. can be reduced.

[0303] The above process is applicable to LCD panels, electroluminescent display panels, and electronic ink displays. Used in the manufacture of backplanes (substrates on which thin-film transistors are formed) for display devices, etc. The above process is carried out at a temperature of 400°C or less, so the thickness is 1 mm or less. It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 400°C, making it ideal for manufacturing display panels. This means that you don't have to consume a lot of energy to do so.

[0304] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0305] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0306] (Embodiment 7) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is An example is given below.

[0307] A thin film transistor and a manufacturing method thereof according to this embodiment will be described with reference to FIGS. .

[0308] FIG. 11 shows an example of a cross-sectional structure of a thin film transistor. The transistor 310 has a bottom gate structure and is also called an inverted staggered thin film transistor.

[0309] In addition, the thin film transistor 310 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A star can also be formed.

[0310] 11A to 11E, a thin film transistor 310 is formed on a substrate 300. The process for doing so will be described.

[0311] First, a conductive layer is formed on a substrate 300 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 311 is formed by a deposition process. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0312] There is no significant limitation on the substrate that can be used for the substrate 300 having an insulating surface. At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as a borosilicate glass or an aluminoborosilicate glass substrate can be used.

[0313] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The above is recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. Generally, it contains more barium oxide (BaO) than boron oxide (B2O3). By mixing BaO with B2O3, a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing

[0314] Instead of the above glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used. .

[0315] An insulating layer serving as a base layer may be provided between the substrate 300 and the gate electrode layer 311. The silicon nitride layer and the silicon oxide layer have a function of preventing the diffusion of impurity elements from the substrate 300. A silicon nitride oxide layer, a silicon oxynitride layer, or a silicon nitride layer. It can be formed.

[0316] The gate electrode layer 311 may be made of molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as aluminum, copper, neodymium, and scandium, or alloys containing these as the main components. A single layer or multiple layers of gold material can be applied.

[0317] For example, the gate electrode layer 311 may have a two-layer laminate structure of molybdenum on an aluminum layer. two-layer laminated structure with a molybdenum layer on a copper layer; two-layer laminated structure with a molybdenum layer on a copper layer; A two-layer laminate structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, a titanium nitride layer and a molybdenum layer, or a tungsten nitride layer and a tungsten layer. The three-layer structure is preferably a tungsten layer or a nitride layer. tungsten, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium; It is preferable to form a laminate including a titanium nitride layer or a titanium layer.

[0318] Next, the gate insulating layer 302 is formed on the gate electrode layer 311 .

[0319] The gate insulating layer 302 is formed by depositing silicon oxide by plasma CVD, sputtering, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer; For example, a deposition gas of SiH4, oxygen and nitrogen is used. The silicon oxynitride layer may be formed by plasma CVD. In the case of a multilayer structure, the thickness is, for example, 50 nm to 20 nm. A first gate insulating layer having a thickness of 0 nm or less, and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer. The second gate insulating layer has the following laminate structure:

[0320] In this embodiment, the gate insulating layer 302 is formed to a thickness of 100 nm by plasma CVD. The following silicon oxynitride layers are formed:

[0321] Next, an oxide semiconductor layer 3 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 302. Form 30.

[0322] Before the oxide semiconductor layer 330 was formed by sputtering, argon gas was introduced. In this state, plasma is generated to perform reverse sputtering, and the silicon oxide is attached to the surface of the gate insulating layer 302. It is preferable to remove the dust that is present in the argon atmosphere. Elements such as fluorine may also be used.

[0323] The oxide semiconductor layer 330 may be an In-Ga-Zn-O-based, In-Sn-Zn-O-based, or In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn In this embodiment, the oxide semiconductor layer 330 is made of a Zn-O-based or Zn-O-based oxide semiconductor. The film is formed by sputtering using an In-Ga-Zn-O metal oxide target as the The cross-sectional view at this stage corresponds to FIG. 11(A). Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The film can be formed by sputtering in a mixed atmosphere of SiO and oxygen. When using the ring method, a target containing 2% to 10% by weight of SiO2 is used. Film formation may also be performed.

[0324] As a target for forming the oxide semiconductor layer 330 by a sputtering method, nitrogen oxide was used. A metal oxide target mainly composed of lead can be used. Another example of a target is a metal oxide target containing In, Ga, and Zn (composition ratio: As such, In2O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn= 1:1:0.5 [atom]) can be used. In, Ga, and Zn are also included. Metal oxide targets including In:Ga:Zn=1:1:1[atom] or In A target having a composition ratio of Ga:Zn=1:1:2 [atom] can also be used. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 96% or less. The metal oxide target with a high filling rate was used, and the oxide film was The semiconductor layer becomes a dense film.

[0325] The oxide semiconductor layer 330 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or water. Uses high-purity gas in which impurities such as chlorine have been removed to concentrations of ppm or ppb. It is preferable that

[0326] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is maintained at 100°C to 600°C. The temperature is preferably 200° C. or higher and 400° C. or lower. By forming the film while heating the substrate, The concentration of impurities contained in the formed oxide semiconductor layer can be reduced. Damage caused by the ring is reduced. Also, hydrogen and moisture are removed while removing residual moisture in the processing chamber. A sputtering gas from which the metal oxide has been removed is introduced, and an oxide film is formed on the substrate 300 using the metal oxide as a target. In order to remove the residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump as the exhaust means. The deposition chamber is evacuated using a cryopump. For example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Since the impurities contained in the oxide semiconductor layer formed in the deposition chamber are exhausted, The concentration of pure substances can be reduced.

[0327] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 P. a, DC power supply power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere conditions In addition, when a pulsed direct current (DC) power supply is used, the powdery material (pulse) generated during film formation is This is preferable because it can reduce the amount of oxide particles (also called "tickles" or "dust") and make the film thickness distribution uniform. The thickness of the semiconductor layer is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material, and an appropriate thickness may be selected depending on the material.

[0328] Next, the oxide semiconductor layer 330 is divided into islands of oxide semiconductor by a second photolithography process. The oxide semiconductor layer is then processed into a conductor layer. A resist mask for forming an island-shaped oxide semiconductor layer is then applied to the insulator. If the resist mask is formed by the inkjet method, the photoresist mask may be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0329] Next, the oxide semiconductor layer is subjected to a first heat treatment. The semiconductor layer can be dehydrated or dehydrogenated. The heating temperature is from 400° C. to 750° C., preferably from 400° C. to the distortion point of the substrate. The substrate is introduced into an electric furnace, which is one of the processing apparatuses, and the oxide semiconductor layer is heated to 45 After performing heat treatment at 0° C. for 1 hour, the oxide semiconductor layer was The inclusion of water or hydrogen is prevented, and an oxide semiconductor layer 331 is obtained (see FIG. 11B).

[0330] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0331] For example, the first heat treatment is performed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved out and heated to a high temperature inert gas. You can also use GRTA, which is a method of removing the food from inside the container. Using GRTA, high-temperature heat treatment can be performed in a short time. It becomes.

[0332] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0333] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, The layer may crystallize and become microcrystalline or polycrystalline. For example, the crystallinity is 90% or more. Alternatively, the oxide semiconductor layer may be 80% or more microcrystalline. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. In addition, there are cases where microcrystals (grain size 1 nm or more, 2 nm or more) are present in the amorphous oxide semiconductor. In the case where the oxide semiconductor layer is a mixture of 0 nm or less (typically 2 nm or more and 4 nm or less), There are also.

[0334] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, the second heat treatment can be performed on the semiconductor layer 330. The substrate is then removed and subjected to a photolithography process.

[0335] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the deposition, a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer. The deposition may be performed either before or after a protective insulating layer is formed over the electrode layer and the drain electrode layer.

[0336] In addition, when a contact hole is formed in the gate insulating layer 302, the process is performed using an oxide semiconductor. This may be carried out before or after the layer is subjected to a dehydration or dehydrogenation treatment.

[0337] Note that the etching of the oxide semiconductor film here is not limited to wet etching, but may be dry etching. Etching may also be used.

[0338] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0339] Next, a conductive layer is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive layer can be formed by sputtering or vacuum deposition. , Cr, Cu, Ta, Ti, Mo, W, or the above elements are included The alloy layer may be a combination of the above elements. One or more of magnesium, zirconium, beryllium, and thorium are selected from the group consisting of The conductive layer may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum layer containing silicon, a titanium layer on an aluminum layer, A two-layer structure, a Ti layer, an aluminum layer on top of the Ti layer, and A three-layer structure is also possible, with a titanium layer formed on top of the aluminum. , Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Sc (Scandium) , an alloy layer, or a nitride layer may also be used.

[0340] When a heat treatment is performed after the conductive layer is formed, the conductive layer must have heat resistance to withstand the heat treatment. It is preferable to do so.

[0341] A resist mask is formed on the conductive layer by a third photolithography process, and selectively etched. After etching to form the source electrode layer 315a and the drain electrode layer 315b, The mask is then removed (see FIG. 11(C)).

[0342] The third photolithography process uses ultraviolet light and KrF for exposure when forming the resist mask. The source electrode layers adjacent to each other on the oxide semiconductor layer 331 are irradiated with a laser beam or an ArF laser beam. The width of the gap between the lower end of the drain electrode layer and the lower end of the thin film transistor to be formed later The channel length L is determined. Note that when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of several nm to several tens of nm. et) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the thin film transistor to 10 nm or more and 1000 nm or less. This allows the operating speed of the circuit to be increased and the off-current value to be made extremely small. This also contributes to reducing power consumption.

[0343] Note that the oxide semiconductor layer 331 is not removed when the conductive layer is etched. The materials and etching conditions are adjusted appropriately.

[0344] In this embodiment, a Ti layer is used as the conductive layer, and an In-GaAs layer is used as the oxide semiconductor layer 331. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0345] Note that in the third photolithography step, the oxide semiconductor layer 331 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). A resist mask for forming the drain electrode layer 315a and the drain electrode layer 315b is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0346] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer and the metal layer for forming the source electrode layer and the drain electrode layer may be The oxide conductive layer can function as a source region and a drain region. .

[0347] The oxide conductive layer is connected to the oxide semiconductor layer and the source electrode layer as the source region and the drain region. By providing the source and drain electrode layers between the source and drain regions, the resistance of the source and drain regions can be reduced. This allows the transistor to operate at high speed.

[0348] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of masks can be reduced. The corresponding photolithography process can also be eliminated, making it possible to simplify the process.

[0349] Then, a plasma treatment is performed using gas such as N2O, N2, or Ar. The Zuma treatment removes adsorbed water and the like attached to the exposed surface of the oxide semiconductor layer. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0350] After the plasma treatment, a protective film is placed in contact with a part of the oxide semiconductor layer without being exposed to the air. An oxide insulating layer 316 that serves as an insulating layer is formed.

[0351] The oxide insulating layer 316 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The edge layer 316 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the edge layer 316. When hydrogen is contained in the oxide insulating layer 316, the hydrogen may enter the oxide semiconductor layer or the hydrogen may be released from the oxide semiconductor layer. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, and the back channel of the oxide semiconductor layer is formed. The resistance becomes low (N-type), and a parasitic channel may be formed. The insulating layer 316 is formed without using hydrogen so that the layer contains as little hydrogen as possible. It is important that:

[0352] In this embodiment, a silicon oxide layer having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 316. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The silicon oxide layer is formed by sputtering using a rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen atmosphere. The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. A silicon oxide layer can be formed by sputtering in an atmosphere. The oxide insulating layer 316 formed in contact with the oxide semiconductor layer that has been made to be N-type is resistant to moisture, water, and the like. Elementary ion, OH - It does not contain impurities such as nicotinamide, and blocks them from entering from the outside. An inorganic insulating layer is used, typically a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. A layer, an aluminum oxynitride layer, or the like is used.

[0353] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 331 and the oxide insulating layer 316. This is to ensure that it is not included.

[0354] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, so the oxide insulating film formed in the film formation chamber The concentration of impurities contained in layer 316 can be reduced.

[0355] The sputtering gas used in forming the oxide insulating layer 316 is hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferable.

[0356] Then, a second heat treatment (preferably 200°C to 400°C (e.g., 250°C to 350°C) is performed. For example, The second heat treatment is performed at 250° C. for 1 hour under atmospheric conditions. A part of the conductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 316 .

[0357] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. At the same time as the heat treatment for the oxidation is performed, the oxide semiconductor layer is made to have a low resistance, i.e., to become an N-type oxide semiconductor layer. By forming an oxide insulating layer in contact with the oxide semiconductor layer, a part of the oxide semiconductor layer is selected. As a result, the channel formation region overlapping with the gate electrode layer 311 is At this time, the carrier density is at least higher than that of the channel formation region 313. A high-resistance source region 314a overlapping a source electrode layer 315a and a channel region 315b are formed. The high-resistance region 315b overlaps the drain electrode layer 315b and has a higher carrier density than the drain electrode region 313. Through the above steps, the thin film transistor 31 is formed in a self-aligned manner. 0 is formed (see FIG. 11(D)).

[0358] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. By performing the heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer to obtain a normally-off thin film transistor. Therefore, the reliability of the semiconductor device can be improved. When a silicon oxide layer containing hydrogen is used, hydrogen, Impurities such as moisture, a hydroxyl group, or hydride are diffused into the oxide insulating layer, and the oxide semiconductor layer is This has the effect of further reducing the amount of impurities contained therein.

[0359] Note that the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a) By forming a high-resistance drain region 314b (and a high-resistance source region 314a) in the As a result, the reliability of the thin film transistor can be improved. By forming the drain region 314b, a high resistance drain region is formed from the drain electrode layer 315b. 314b, a structure capable of gradually changing the conductivity toward the channel forming region 313; Therefore, a high power supply potential VDD is supplied to the drain electrode layer 315b. When the transistor is connected to a wiring for operation, a gate electrode layer 311 and a drain electrode layer 315b are Even when a high voltage is applied, the high-resistance drain region acts as a buffer to prevent localized electric field concentration. In addition, a structure in which the withstand voltage of the transistor is improved can be obtained.

[0360] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably made of an oxide semiconductor. When the thickness of the conductor layer is thin, 15 nm or less, oxide is formed throughout the thickness direction. When the thickness of the semiconductor layer is thicker, ie, 30 nm or more and 50 nm or less, a part of the oxide semiconductor layer, The resistance of the region in contact with the source electrode layer or the drain electrode layer and its vicinity is reduced, forming a high-resistance source region. a high-resistance drain region or a high-resistance drain region is formed in the oxide semiconductor layer, and the region is close to the gate insulating film can also be of type I.

[0361] A protective insulating layer may be further formed on the oxide insulating layer 316. For example, the protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is suitable for forming a protective insulating layer. It is preferable as a membrane method. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - Does not contain impurities such as The inorganic insulating layer blocks these substances from entering from the outside. An aluminum nitride layer, a silicon nitride oxide layer, an aluminum nitride oxide layer, or the like is used. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride layer as the protective insulating layer. See Figure 11(E).

[0362] In this embodiment, the substrate 300 on which the oxide insulating layer 316 has been formed is heated at 100° C. to 400° C. The temperature was heated to 100°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture had been removed was introduced. A silicon nitride layer is formed as the protective insulating layer 303 using a silicon target. In this case, similarly to the oxide insulating layer 316, the protective insulating layer is formed while removing residual moisture in the treatment chamber. Preferably, layer 303 is deposited.

[0363] Although not shown, a planarization insulating layer for planarization may be provided over the protective insulating layer 303 .

[0364] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0365] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0366] (Embodiment 8) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is An example is given below.

[0367] One mode of a thin film transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS. do.

[0368] FIG. 12(D) shows an example of a cross-sectional structure of a thin film transistor. The transistor 360 is a bottom-type transistor called a channel protection type (also called a channel stop type). This is one of the gate structures and is also called an inverted staggered thin film transistor.

[0369] In addition, the thin film transistor 360 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A star can also be formed.

[0370] 12(A) to 12(D), a thin film transistor 360 is fabricated on a substrate 320. The process for doing so will be described.

[0371] First, a conductive layer is formed on a substrate 320 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 361 is formed by a deposition process. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0372] The gate electrode layer 361 may be made of molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as aluminum, copper, neodymium, and scandium, or alloys containing these as the main components. A single layer or multiple layers of gold material can be applied.

[0373] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0374] In this embodiment, the gate insulating layer 322 is formed to a thickness of 100 nm by plasma CVD. The following silicon oxynitride layers are formed:

[0375] Next, an oxide semiconductor layer having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 322. The oxide semiconductor layer is then processed into an island shape by a second photolithography process. In this embodiment, the oxide semiconductor layer is spun using an In-Ga-Zn-O metal oxide target. The film is formed by sputtering.

[0376] In this case, the oxide semiconductor layer can be formed while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor layer.

[0377] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H Since compounds containing hydrogen atoms such as 2O) are exhausted, the oxide semiconductor film formed in the film formation chamber is The concentration of impurities contained in the body layer can be reduced.

[0378] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, or a hydride. By using high-purity gas in which impurities such as is preferred.

[0379] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. The oxide semiconductor layer 332 is obtained without any heat treatment and without any heat treatment. See Figure 12(A).

[0380] Then, a plasma treatment is performed using gas such as N2O, N2, or Ar. The Zuma treatment removes adsorbed water and the like attached to the exposed surface of the oxide semiconductor layer. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0381] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. Then, a resist mask is formed by a third photolithography process, and selective etching is performed. After etching is performed to form the oxide insulating layer 366, the resist mask is removed.

[0382] In this embodiment, a silicon oxide layer having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The silicon oxide layer is formed by sputtering using a rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen mixture The reaction can be carried out in an atmosphere. The target is a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and nitrogen. Silicon oxide can be formed by sputtering in a nitrogen atmosphere.

[0383] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 332 and the oxide insulating layer 366. This is to ensure that it is not included.

[0384] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, so the oxide insulating film formed in the film formation chamber The concentration of impurities contained in layer 366 can be reduced.

[0385] The sputtering gas used in forming the oxide insulating layer 366 is hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferable.

[0386] Then, a second heat treatment (preferably The heating may be performed at 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer is heated while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366. can be.

[0387] In this embodiment, an oxide insulating layer 366 is further provided, and a part of the oxide semiconductor is exposed. The oxide insulating layer 332 is subjected to a heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed areas of the oxide semiconductor layer 332 that are not covered by 366 are etched with nitrogen, an inert gas. The resistance can be reduced by performing a heat treatment in a gas atmosphere or under reduced pressure. For example, Then, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0388] The oxide semiconductor layer 332 provided with the oxide insulating layer 366 is subjected to heat treatment in a nitrogen atmosphere. Due to this phenomenon, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 12 In FIG. 1B, the oxide semiconductor layer 362 has a portion (indicated by a hatched area and a white area).

[0389] Next, a semiconductor layer 362, a gate insulating layer 322, and an oxide insulating layer 366 are formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After the conductive layer is formed, a resist mask is formed by a fourth photolithography process. After selective etching to form the source electrode layer 365a and the drain electrode layer 365b, Then, the resist mask is removed (see FIG. 12(C)).

[0390] The source electrode layer 365a and the drain electrode layer 365b are made of materials such as Al, Cr, Cu, An element selected from Ta, Ti, Mo, and W, or an alloy containing the above elements, etc. The metal conductive layer may have a single layer structure or a laminated structure of two or more layers.

[0391] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. When the heat treatment for oxidation is performed, the material becomes oxygen deficient and the resistance becomes low, i.e., it becomes N-type. Then, an oxide insulating layer is formed in contact with the oxide semiconductor layer, so that a part of the oxide semiconductor layer is As a result, a channel is formed overlapping with the gate electrode layer 361. The region 363 becomes an I-type. At this time, the carrier is larger than that of the channel forming region 363. A high-resistance source region 364a having a high density and overlapping a source electrode layer 365a; The carrier density is higher than that of the channel formation region 363 and overlaps with the drain electrode layer 365b. The high resistance drain region 364b is formed in a self-aligned manner. A 360 is created.

[0392] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. By performing the heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer to obtain a normally-off thin film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0393] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) By forming a high-resistance drain region 364b (and a high-resistance source region 364a) in the As a result, the reliability of the thin film transistor can be improved. By forming the drain region 364b, the high resistance drain region 364b is formed from the drain electrode layer. The conductivity of the semiconductor layer 361 can be changed stepwise from the first region 361 to the channel forming region 363. Therefore, the drain electrode layer 365b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated continuously, a high voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if a high voltage is applied, the high-resistance drain region acts as a buffer to prevent localized electric field concentration. It is possible to provide a configuration in which the breakdown voltage of the transistor is improved.

[0394] A protective insulating layer is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride layer. (See FIG. 12(D)).

[0395] Note that a thin film is further provided on the source electrode layer 365 a, the drain electrode layer 365 b, and the oxide insulating layer 366. An oxide insulating layer may be formed over the insulating film 324 and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0396] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0397] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0398] (Embodiment 9) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is An example is given below.

[0399] One mode of a thin film transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS. do.

[0400] The thin film transistor 350 shown in FIG. 13(D) is a thin film transistor having a single gate structure. However, if necessary, a multi-gate structure thin film having multiple channel formation regions can be used. A transistor can also be formed.

[0401] 13A to 13D, a thin film transistor 350 is fabricated on a substrate 340. The process for doing so will be described.

[0402] First, a conductive layer is formed on a substrate 340 having an insulating surface, and then a first photolithography process is performed. In this embodiment, the gate electrode layer 351 is formed by a deposition process. Then, a tungsten layer having a thickness of 150 nm is formed by sputtering.

[0403] Next, the gate insulating layer 342 is formed over the gate electrode layer 351. A silicon oxynitride layer having a thickness of 100 nm or less is formed as the gate insulating layer 342 by the plasma CVD method. A film is formed.

[0404] Next, a conductive layer is formed on the gate insulating layer 342 and then subjected to a second photolithography process. A resist mask is formed on the conductive layer, and selective etching is performed to form the source electrode layer 35. 5a, after forming the drain electrode layer 355b, the resist mask is removed (FIG. 13(A) reference).

[0405] Next, an oxide semiconductor layer 345 is formed (see FIG. 13B). The compound semiconductor layer 345 is formed by sputtering using an In-Ga-Zn-O metal oxide target. The oxide semiconductor layer 345 is formed into an island-shaped oxide film by a third photolithography process. The resulting semiconductor layer is then processed into a compound semiconductor layer.

[0406] In this case, the oxide semiconductor layer 345 is formed while removing moisture remaining in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture not be contained in the oxide semiconductor layer 345. This is why.

[0407] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H Since compounds containing hydrogen atoms such as 2O) are exhausted, the oxide semiconductor film formed in the film formation chamber is The concentration of impurities contained in the body layer 345 can be reduced.

[0408] The sputtering gas used in forming the oxide semiconductor layer 345 is hydrogen, water, a hydroxyl group, or a hydrogen atom. Uses high-purity gas in which impurities such as chlorine and fluorine have been removed to concentrations of ppm or ppb. It is preferable that

[0409] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. The oxide semiconductor layer 346 is obtained without any heat treatment and without any heat treatment. See Figure 13(C).

[0410] In the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. Using GRTA, high-temperature heat treatment can be performed in a short time. become.

[0411] Next, an oxide insulating layer 356 serving as a protective insulating layer in contact with the oxide semiconductor layer 346 is formed. do.

[0412] The oxide insulating layer 356 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The edge layer 356 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the edge layer 356. When hydrogen is contained in the oxide insulating layer 356, the hydrogen may enter the oxide semiconductor layer or may be released from the oxide semiconductor layer. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, and the back channel of the oxide semiconductor layer is formed. The resistance becomes low (N-type), and a parasitic channel may be formed. The insulating layer 356 is formed without using hydrogen so that the layer contains as little hydrogen as possible. It is important that:

[0413] In this embodiment, a silicon oxide layer having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 356. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The silicon oxide layer is formed by sputtering using a rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen mixture The reaction can be carried out in an atmosphere. The target is a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and nitrogen. A silicon oxide layer can be formed by sputtering in an oxygen atmosphere. The oxide insulating layer 356 formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture, hydrogen ions, and the like. , O.H. - Inorganic insulation that does not contain impurities such as these and blocks their intrusion from the outside A layer is typically used, such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or An aluminum oxynitride layer or the like is used.

[0414] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 346 and the oxide insulating layer 356. This is to ensure that it is not included.

[0415] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, so the oxide insulating film formed in the film formation chamber The concentration of impurities contained in the layer 356 can be reduced.

[0416] The sputtering gas used in forming the oxide insulating layer 356 is hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferable.

[0417] Then, a second heat treatment (preferably 200°C to 400°C (e.g., 250°C to 350°C) is performed. For example, The second heat treatment is performed at 250° C. for 1 hour under atmospheric conditions. A part of the conductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 356 .

[0418] Through the above process, oxygen deficiency occurs simultaneously with dehydration or dehydrogenation, resulting in low The oxide semiconductor layer that has been made resistive is made into an oxygen-excess state. As a result, a highly resistive I-type oxide semiconductor layer is formed. Thus, a compound semiconductor layer 352 is formed. Through the above steps, a thin film transistor 350 is formed.

[0419] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be carried out under reduced pressure. When the heat treatment is carried out under reduced pressure, the heating time is shortened. By this heat treatment, hydrogen is removed from the oxide semiconductor layer into the oxide insulating layer. Thus, a normally-off thin film transistor can be obtained. This can improve the reliability of the system.

[0420] A protective insulating layer 343 may be further formed on the oxide insulating layer 356. For example, In this embodiment, a silicon nitride layer is formed as the protective insulating layer 343 by a deposition method. A silicon nitride layer is used (see FIG. 13(D)).

[0421] Although not shown, a planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0422] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0423] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0424] (Embodiment 10) In this embodiment mode, the thin film transistor included in the logic circuit shown in Embodiment 1 or 2 is An example is given below.

[0425] In this embodiment mode, an example in which a part of a manufacturing process of a thin film transistor is different from that in Embodiment Mode 7 is shown. Figure 14 is the same as Figure 11 except for some differences in the process, so the same parts are used. The same reference numerals are used, and detailed explanations of the same parts will be omitted.

[0426] According to the seventh embodiment, a gate electrode layer 381 is formed on a substrate 370, and a first gate insulating layer 382 is formed on the substrate 370. An edge layer 372a and a second gate insulating layer 372b are laminated. In this embodiment, the gate insulating layer The layer has a two-layer structure, with a nitride insulating layer as the first gate insulating layer 372a and a nitride insulating layer as the second gate insulating layer An oxide insulating layer is used for 372b.

[0427] The oxide insulating layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. As the nitride insulating layer, a nitride layer, an aluminum oxynitride layer, or the like can be used. , a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer. A rubber layer or the like can be used.

[0428] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. The first gate insulating layer 372a is formed by sputtering to a thickness of 50 A silicon nitride layer (SiN y (y >0) is deposited on the first gate insulating layer 372a as a second gate insulating layer 372b. A silicon oxide layer (Si O x (x>0) is laminated to form the gate insulating layer.

[0429] Next, an oxide semiconductor layer is formed, and the oxide semiconductor layer is The oxide semiconductor layer is processed into an island shape. In this embodiment, the oxide semiconductor layer is The film is formed by sputtering using an nO-based metal oxide target.

[0430] In this case, the oxide semiconductor layer can be formed while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor layer.

[0431] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H Since compounds containing hydrogen atoms such as 2O) are exhausted, the oxide semiconductor film formed in the film formation chamber is The concentration of impurities contained in the body layer can be reduced.

[0432] The sputtering gas used in forming the oxide semiconductor layer is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0433] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or higher and 750° C. or lower, preferably 425° C. or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. The heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to a heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is prevented from being exposed to the air, preventing water and hydrogen from entering the oxide semiconductor layer. After that, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air is added to the same furnace. Cooling is performed by introducing oxygen gas (dew point is -40℃ or less, preferably -60℃ or less). It is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or NO gas to be fed is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably 0.1 ppm or less).

[0434] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid T thermal annealing) equipment, LRTA (Lamp Rapid Thermal) RTA (Rapid Thermal Anneal) equipment such as The LRTA device can be used with halogen lamps, metal halide lamps, xenon lamps, etc. Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. Heat is generated by heat conduction or radiation from heating elements such as RTA devices, lamps, and resistance heating elements. A GRTA is a device that uses high-temperature gas to heat the object to be treated. The gas used is a rare gas such as argon, or nitrogen, which is suitable for heat treatment. Inert gas that hardly reacts with the workpiece is used. Heat treatment may be performed at 00° C. to 750° C. for several minutes.

[0435] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Preferably, heating is performed at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. Processing may be carried out.

[0436] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, the substrate may be removed from the heating device after the first heat treatment. Then, the substrate is taken out and subjected to a photolithography process.

[0437] By going through the above steps, the entire oxide semiconductor layer is made into an oxygen-excess state, and I As a result, the oxide semiconductor layer 382 is entirely i-type.

[0438] Next, a conductive layer is formed over the oxide semiconductor layer 382. A resist mask is formed by a lithography process, and selective etching is performed to form the source electrode. A layer 385a and a drain electrode layer 385b are formed, and an oxide insulating layer 386 is formed by a sputtering method. do.

[0439] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 382 and the oxide insulating layer 386. This is to ensure that it is not included.

[0440] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, so the oxide insulating film formed in the film formation chamber The concentration of impurities contained in layer 386 can be reduced.

[0441] The sputtering gas used in forming the oxide insulating layer 386 is hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferable.

[0442] Through the above steps, a thin film transistor 380 can be manufactured.

[0443] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, Heat treatment (preferably at 150°C or higher and lower than 350°C) is performed under a nitrogen gas atmosphere. For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0444] In addition, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be carried out under reduced pressure. When the heat treatment is carried out under reduced pressure, the heating time is shortened. By this heat treatment, hydrogen is removed from the oxide semiconductor layer into the oxide insulating layer. Thus, a normally-off thin film transistor can be obtained. This can improve the reliability of the system.

[0445] A protective insulating layer 373 is formed over the oxide insulating layer 386. In this embodiment, the protective insulating layer As the layer 373, a silicon nitride layer is formed to a thickness of 100 nm by using a sputtering method.

[0446] The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer are resistant to moisture and It does not contain impurities such as hydrogen, hydrides, or hydroxides, and prevents these from entering from the outside. It has a locking effect.

[0447] Therefore, in the manufacturing process after the protective insulating layer 373 is formed, impurities such as moisture from the outside In addition, the device can be used as a semiconductor device, for example, a liquid crystal display device. Even after completion, the device can be protected from the intrusion of impurities such as moisture from the outside for a long period of time. The long-term reliability of the device can be improved.

[0448] In addition, between the protective insulating layer 373 made of a nitride insulating layer and the first gate insulating layer 372a The insulating layer provided on the first gate insulating layer 372a is removed, and the protective insulating layer 373 and the first gate insulating layer 372a are bonded to each other. The structure may be such that:

[0449] Therefore, impurities such as moisture, hydrogen, hydrides, and hydroxides in the oxide semiconductor layer can be eliminated. and preventing the inclusion of the impurities, thereby maintaining the impurity concentration in the oxide semiconductor layer low. It is possible.

[0450] Although not shown, a planarization insulating layer for planarization may be provided over the protective insulating layer 373.

[0451] By applying the above-mentioned thin film transistor to the logic circuits shown in the first and second embodiments, As a result, it is possible to provide a logic circuit having stable electrical characteristics and high reliability.

[0452] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0453] (Embodiment 11) In this embodiment, an example of a semiconductor device including the logic circuit described in Embodiment 1 or 2 will be described. Specifically, the driver circuit has the logic circuit shown in the first or second embodiment. The appearance and cross section of the liquid crystal display panel will be described with reference to FIG. 15. ) is a thin film transistor 4010, 4011, and a liquid crystal element 4013 on a first substrate 40 The plane of the panel is sealed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. FIG. 15(B) is a cross-sectional view taken along line MN in FIG. 15(A) or FIG. 15(C). Equivalent.

[0454] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealant 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the driving circuit 4004. The scanning line driver circuit 4004 is a circuit including a first substrate 4001, a sealant 4005, and a second substrate 4002. The liquid crystal layer 4008 is sealed by the insulating film 4006 on the first substrate 4001. In an area different from the area surrounded by the insulating material 4005, a single A signal line driver circuit 4003 formed of a crystalline semiconductor film or a polycrystalline semiconductor film is mounted. .

[0455] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, The wire bonding method, the TAB method, or the like can be used. This is an example of mounting a signal line driver circuit 4003 by the OG method, and FIG. 15(C) is an example of mounting a signal line driver circuit 4003 by the TAB method. This is an example in which a twisted signal line driver circuit 4003 is implemented.

[0456] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 15B, the pixel portion 4002 includes a thin film transistor. A thin film transistor 4010 and a thin film transistor 40 included in the scanning line driving circuit 4004 The thin film transistors 4010 and 4011 are provided with insulating layers 4041 and 4042 on the thin film transistors 4010 and 4011. No. 042 and 4021 are provided.

[0457] The thin film transistors 4010 and 4011 are the thin film transistors shown in the embodiments 3 to 10. Any one of the above may be used as appropriate and may be formed using similar processes and materials. Hydrogen and water are reduced in the oxide semiconductor layers of the thin film transistors 4010 and 4011. Therefore, the thin film transistors 4010 and 4011 are highly reliable thin film transistors. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. It's Jista.

[0458] A channel shape of the oxide semiconductor layer of the thin film transistor 4011 is formed on the insulating layer 4021. The conductive layer 4040 is provided in a position overlapping with the oxide semiconductor layer. By placing the layer at a position overlapping the channel formation region, the thin film transistor The amount of change in the threshold voltage of the transistor 4011 can be reduced. The potential of the gate electrode layer of the thin film transistor 4011 may be the same as or different from that of the gate electrode layer of the thin film transistor 4011. The conductive layer 4040 may function as a second gate electrode layer. The potential may be GND, 0 V, or may be in a floating state. 40 is not necessary.

[0459] In addition, the pixel electrode layer 4030 of the liquid crystal element 4013 is The liquid crystal element 4013 is electrically connected to the source electrode layer or the drain electrode layer. The counter electrode layer 4031 is formed on the second substrate 4006. The portion where the counter electrode layer 4031 and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 each have an insulating layer that functions as an alignment film. Edge layers 4032 and 4033 are provided, and the liquid crystal layer 4008 is disposed via the insulating layers 4032 and 4033. is held in place.

[0460] It is to be noted that the first substrate 4001 and the second substrate 4006 may each be a light-transmitting substrate. Glass, ceramics, and plastics can be used. is a FRP (Fiberglass-Reinforced Plastics) plate, P VF (polyvinyl fluoride) film, polyester film, or acrylic resin A film may be used.

[0461] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. This allows the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 to be controlled. A spherical spacer may be used. 31 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layers via conductive particles disposed between the pair of substrates. The conductive particles can be used as a sealing material. Included in 4005.

[0462] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the liquid crystal transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing 5% by weight or more of chiral agent is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. c or less, it is optically isotropic so no alignment treatment is required, and it has low viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This can prevent electrostatic damage caused by electrostatic discharge, and can prevent defects and damage to liquid crystal display devices during the manufacturing process. This reduces the loss, thereby improving the productivity of the liquid crystal display device. In particular, thin film transistors using oxide semiconductor layers are susceptible to static electricity. The electrical characteristics of the oxide semiconductor may vary significantly and deviate from the design range. US201002326333A1 - Use of blue phase liquid crystal material in liquid crystal display device having thin film transistors using a dielectric layer - Google Patents is more effective.

[0463] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0464] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer and a display layer are provided on the inner side. Although an example in which the polarizing plate is provided in the order of the electrode layers used in the element is shown, the polarizing plate may be provided on the inner side of the substrate. The laminated structure of the polarizing plate and the coloring layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the coloring layer may be changed. The conditions may be appropriately set according to the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0465] An insulating layer 4041 is provided on the thin film transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 is formed using a material similar to that of the oxide insulating layer described in the above embodiment. Here, the insulating layer 4041 is formed by a sputtering method. A silicon oxide layer is formed. In addition, an insulating layer 4042 is formed on and in contact with the insulating layer 4041. The insulating layer 4042 may be, for example, a silicon nitride layer. On the insulating layer 4042, a planarizing insulating layer is formed to reduce surface irregularities caused by the thin film transistor. An insulating layer 4021 that functions as a barrier is provided.

[0466] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant polymers such as imide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. ), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by laminating multiple insulating layers made of these materials, the insulating A layer 4021 may be formed.

[0467] The method for forming the insulating layer 4021 is not particularly limited. Depending on the material, the insulating layer 4021 may be formed by a sputtering method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, spin Clean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or a knife coater can be used. By using the same material as the annealing agent, a semiconductor device can be manufactured efficiently.

[0468] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium tin oxide (ITO) and indium oxide. IZO (indium zinc oxide) is a mixture of indium and zinc oxide (ZnO). ), a conductive material made by mixing indium oxide with silicon oxide (SiO2), organic indium, organic Tin, indium oxide with tungsten oxide, indium zinc oxide with tungsten oxide Lead oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, A light-transmitting conductive material such as In the case where it is not necessary to have translucency or where it is necessary to have reflectivity, tungsten is used. W, Molybdenum, Zirconium, Hafnium, Vanadium V, Nb, Ta, Cr, Co, Nickel (Ni), Titanium (Ti), Platinum (Pt), Aluminum (Al), Copper (Cu) One or more of the following metals are used: silver (Ag), their alloys, or their metal nitrides. It can be formed using.

[0469] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The formed pixel electrode has a sheet resistance of 10,000 Ω / □ or less and is transparent at a wavelength of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0470] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or a derivative thereof, or a copolymer of two or more of these.

[0471] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel driver circuit 4006 are separately formed. Various signals and potentials are provided to the portion 4002 through an FPC 4018 .

[0472] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed of the source electrodes of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0473] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0474] In FIG. 15, a signal line driver circuit 4003 is formed separately, and the first substrate 4001 In the example shown, the scanning line driver circuit is formed separately. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately. It may be implemented as follows.

[0475] In addition, light such as black matrix (light-shielding layer), polarizing member, phase difference member, and anti-reflection member For example, a circularly polarized light is generated by a polarizing substrate and a retardation substrate. Also, a backlight, a sidelight, or the like may be used as the light source.

[0476] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the polarity, a display pattern is formed on the screen. A voltage is applied between the pixel electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. The observer perceives it as a

[0477] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of liquid crystal display devices, There is a driving technique called black insertion, which displays black every other frame.

[0478] In addition, the response speed is improved by increasing the normal vertical sync frequency by 1.5 or 2 times. There is also a driving technology called double speed driving, which achieves this.

[0479] In addition, in order to improve the moving image characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a light source such as a photodiode (photodiode) light source or multiple EL light sources. There is also a driving technology that drives each light source independently within one frame period. In addition, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled by the same control, the L The timing of the ED light emission can also be synchronized. This driving technology allows the LEDs to be partially turned off. This is particularly useful for video displays with a large proportion of black areas occupying the entire screen. This has the effect of reducing power consumption.

[0480] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. The performance can be improved more than ever before.

[0481] In addition, thin film transistors are easily damaged by static electricity, so the pixel area or It is preferable that a protection circuit be provided over the same substrate as the driver circuit. For example, the protection circuit is configured by using a nonlinear element that uses a pixel section and a driving In this embodiment, a plurality of protection circuits are provided between the scan line input terminal and the signal line input terminal. A circuit is provided to prevent a surge voltage caused by static electricity or the like from being applied to the scanning lines, signal lines, and capacitance bus lines. The protection circuit is designed to prevent damage to pixel transistors, etc. When a surge voltage is applied, the charge is released to the common wiring. The path is made up of nonlinear elements arranged in parallel with the scanning line. is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it is possible to form the thin film transistors in the pixel area in the same process. By connecting the inlet and drain terminals together, it can have the same characteristics as a diode. Cut.

[0482] The LCD module also includes TN (Twisted Nematic) mode, I PS (In-Plane-Switching) mode, FFS (Fringe Field ld Switching) mode, ASM(Axially Symmetric a ligned Micro-cell) mode, OCB (Optically Comp ensated birefringence mode, FLC (Ferroelect ric Liquid Crystal) mode, AFLC (AntiFerroele tric Liquid Crystal) can be used.

[0483] As described above, the semiconductor device disclosed in the present specification is not particularly limited, and may be, for example, a TN liquid crystal, OCB LCD, STN LCD, VA LCD, ECB LCD, GH LCD, polymer dispersed LCD, Among them, normally black type liquid crystal panels are used. It is preferable that the display device is a transmissive liquid crystal display device that employs a vertical alignment (VA) mode. There are several types of vertical alignment modes, such as MVA (Multi-D Main Vertical Alignment mode, PVA (Pattern Use the ED Vertical Alignment mode, ASV mode, etc. can be done.

[0484] The present invention can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented vertically to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is a technique that is devised to tilt the liquid crystal molecules in the opposite direction. The methods described above can be used.

[0485] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0486] (Embodiment 12) In this embodiment, an example of a semiconductor device including the logic circuit described in Embodiment 1 or 2 will be described. Specifically, the driver circuit has the logic circuit shown in the first or second embodiment. An example of manufacturing an active matrix light-emitting display device will be described. An example of a light-emitting display device having a light-emitting element that utilizes electroluminescence will now be described. Reveal.

[0487] Light-emitting elements that utilize electroluminescence are made of organic or inorganic light-emitting materials. Generally, the former is an organic EL element, and the latter is an inorganic EL element. It's called a child.

[0488] In an organic EL element, electrons and positive charges are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. Light is emitted by the recombination of carriers (electrons and holes). Such a light-emitting element is called a current-excited light-emitting element.

[0489] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized light emission that utilizes organic EL elements. do.

[0490] FIG. 16 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. FIG.

[0491] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. In this study, an n-channel transistor using an oxide semiconductor layer for the channel formation region was fabricated on one screen. Here is an example using two elements.

[0492] The pixel 6400 includes a switching transistor 6401 and a driving transistor 6402. The switching transistor 6 401 has a gate connected to a scanning line 6406, and a first electrode (a source electrode and a drain electrode The second electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405. ) is connected to the gate of the driving transistor 6402. The gate of the transistor 2 is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode of the transistor 2 is connected to a power supply line 6407 via a capacitor element 6403. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode. It is electrically connected to a common potential line 6408 formed on the plate.

[0493] It is to be noted that a low power supply potential is set to a second electrode (common electrode) of the light emitting element 6404 . The low power supply potential is a low power supply potential based on the high power supply potential set on the power supply line 6407. <A potential that satisfies the high power supply potential. For example, GND, 0V, etc. are set as the low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to pass a current through the light emitting element 6404 to make the light emitting element 6404 emit light, a high power supply potential and a low The potential difference between the power supply potential and each of the light emitting elements 6404 is set to be equal to or greater than the forward voltage drop of the light emitting element 6404. Set the position.

[0494] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to use a gate capacitance of the driving transistor 6402 according to the channel type. A capacitance may be formed between the composition region and the gate electrode.

[0495] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is In this case, the driving transistor 6402 is fully turned on or off. In other words, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 is A voltage as high as possible is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0496] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 16 can be used.

[0497] When analog gradation driving is performed, the gate of the driving transistor 6402 is connected to the light emitting element 640 A voltage equal to or higher than the forward voltage of the light-emitting element 6404 plus the Vth of the driving transistor 6402 is applied. The forward voltage of 404 indicates the voltage required to obtain the desired brightness. By inputting a video signal that causes the transistor 6402 to operate in the saturation region, the light emitting element 6 A current can be passed through the transistor 404. The driving transistor 6402 is operated in the saturation region. Therefore, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 6404. It is possible to perform analog gray scale driving.

[0498] Note that the pixel configuration shown in Fig. 16 is not limited to this. For example, In addition, switches, resistors, capacitors, transistors, logic circuits, and the like may be added.

[0499] Next, the configuration of the light-emitting element will be described with reference to FIG. 17. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the n-type as an example. The driving TFTs 7001, 7011, and 7021 used in the semiconductor device of C) are The thin film transistor can be manufactured in the same manner as the thin film transistor shown in FIG. Here is an example using the

[0500] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The structure is a top emission structure that emits light from the surface on the substrate side, a bottom emission structure that emits light from the surface on the substrate side, and a structure that emits light from both the substrate side and the substrate. There are light-emitting elements with a double-sided emission structure that emit light from the side opposite the substrate. The present invention can also be applied to a light emitting device having a light emitting structure.

[0501] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0502] The driving TFT 7011 is an n-type TFT, and the light emitted from the light emitting element 7012 is incident on the first electrode 70. FIG. 17A shows a cross-sectional view of a pixel when light is emitted to the driving TFT 701. A light-emitting element is formed on a light-transmitting conductive layer 7017 electrically connected to the drain electrode layer of A first electrode 7013 of the EL layer 7012 is formed on the first electrode 7013. 4, and a second electrode 7015 are laminated in this order.

[0503] The light-transmitting conductive layer 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide, indium tin oxide, indium zinc oxide, oxide containing titanium A light-transmitting conductive layer such as silicon-added indium tin oxide can be used. .

[0504] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 of FIG. 1 is used as a cathode, a material having a small work function, specifically, e.g. For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth metals such as Yb and Er. In FIG. 17A, the first electrode 7013 has a thickness that is thick enough to transmit light (preferably Preferably, the thickness is about 5 nm to 30 nm. For example, an aluminum film having a thickness of 20 nm is used. The layer is used as a first electrode 7013 .

[0505] After a light-transmitting conductive layer and an aluminum layer are stacked, the conductive layer and the aluminum layer are selectively etched. In this case, a light-transmitting conductive layer 7017 and a first electrode 7013 may be formed. This is preferable since etching can be performed using the same mask.

[0506] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. Organic resin films such as amide, acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes The partition wall 7019 is formed by using a photosensitive resin material. 013, an opening is formed on the surface, and the side wall of the opening is formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7019, In this case, the step of forming a resist mask can be omitted.

[0507] In addition, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least The light-emitting layer may be included, and may be composed of a single layer or a plurality of layers may be laminated. When the EL layer 7014 is composed of a plurality of layers, the cathode and the An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a The layers are laminated in this order: the hole injection layer, the light emitting layer, and the hole injection layer. do not have.

[0508] The stacking order is not limited to the above, and the first electrode 7013 may function as an anode. A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are stacked on the electrode 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole By stacking the layers in the order of the injection layers, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. This is preferable.

[0509] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, the work function is large. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material such as the above is preferable. In addition, a shielding film 7016, for example, a light shielding film, is provided on the second electrode 7015. A metal that blocks light, a metal that reflects light, or the like is used. In this embodiment, the second electrode 7015 An ITO film is used as the shielding film 7016, and a Ti layer is used as the shielding film 7017.

[0510] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. Light emitted from the element 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0511] In FIG. 17A, a light-transmitting conductive layer is used as a gate electrode layer, and a source An example in which a light-transmitting thin film is used for the electrode layer and the drain electrode layer is shown. The light emitted from the element 7012 passes through the color filter layer 7033 and the substrate. You can make them give it to you.

[0512] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using lithography technology.

[0513] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. It is covered with a border layer 7035. In FIG. 17(A), the overcoat layer 7034 is a thin film. Although the thickness is shown, the overcoat layer 7034 is formed by the recesses caused by the color filter layer 7033. It has the function of flattening convexities.

[0514] In addition, a planarization insulating layer 7036, an insulating layer 7032, and an insulating layer 7031 are formed, and A contact hole reaching the drain electrode layer is disposed at a position overlapping with a partition wall 7019 .

[0515] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0516] In FIG. 17B, a transparent TFT 7021 electrically connected to the drain electrode layer of the driving TFT 7021 is A first electrode 7023 of a light-emitting element 7022 is formed on a conductive layer 7027 having a light-emitting property. An EL layer 7024 and a second electrode 7025 are laminated in this order on a first electrode 7023. .

[0517] The light-transmitting conductive layer 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide, indium tin oxide, indium zinc oxide, oxide containing titanium A light-transmitting conductive layer such as silicon-added indium tin oxide can be used. .

[0518] In addition, various materials can be used for the first electrode 7023. For example, When using 023 as a cathode, a material with a small work function, specifically, for example, Li or C, is used. Alkaline metals such as s, and alkaline earth metals such as Mg, Ca, Sr, and In addition to alloys containing Mg (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are preferred. In this embodiment mode, the first electrode 7023 is used as a cathode, and its thickness is set to be thick enough to transmit light. For example, an aluminum film having a thickness of 20 nm is The aluminum layer is used as the cathode.

[0519] After a light-transmitting conductive layer and an aluminum layer are stacked, the conductive layer and the aluminum layer are selectively etched. In this case, a light-transmitting conductive layer 7027 and a first electrode 7023 may be formed. It is preferable that the same mask be used for etching.

[0520] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. Organic resin films such as amide, acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes The partition wall 7029 is formed by using a photosensitive resin material, and the first electrode 7 023, an opening is formed on the surface, and the side wall of the opening is formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7029, In this case, the step of forming a resist mask can be omitted.

[0521] In addition, the EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 is a light-emitting layer. It is sufficient to include the material, and it may be composed of a single layer or multiple layers may be laminated. When the EL layer 7024 is composed of multiple layers, the layer that functions as the cathode may be a An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a hole transport layer are formed on the first electrode 7023. It should be noted that it is not necessary to provide all of these layers except for the light-emitting layer.

[0522] The stacking order is not limited to the above. The first electrode 7023 may be used as an anode, and a hose may be formed on the anode. Alternatively, the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode and electrons are injected onto the cathode. The power consumption is reduced by stacking layers in the order of the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer. It is preferable because it is small.

[0523] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, the work function is large. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment, the second electrode 7025 is used as an anode, and an I A TO layer is formed.

[0524] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. The light emitted from the electrode 7022 is incident on the second electrode 7025 side and the first electrode 7026 side as shown by the arrow. Eject on both sides of 023.

[0525] In FIG. 17B, a light-transmitting conductive layer is used as a gate electrode layer, and a source An example in which a light-transmitting thin film is used for the electrode layer and the drain electrode layer is shown. The light emitted from the electrode 7022 to the first electrode 7023 side passes through the color filter layer 7043. The light can be passed through the substrate and emitted through the substrate.

[0526] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using lithography technology.

[0527] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by edge layer 7045 .

[0528] In addition, a planarization insulating layer 7046, an insulating layer 7042, and an insulating layer 7041 are formed, and A contact hole reaching the drain electrode layer is disposed at a position overlapping with a partition wall 7029 .

[0529] However, when using light-emitting elements with a dual-side emission structure and both display surfaces are full color displays, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable that a sealing substrate having a color filter layer is provided above the second electrode 7025.

[0530] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0531] In FIG. 17C, a driving TFT 7001 is an n-type TFT, and light emitted from a light emitting element 7002 is FIG. 17C shows a cross-sectional view of a pixel in the case where the driving The drain electrode layer of the driving TFT 7001 is in contact with the first electrode 7003. 001 and a first electrode 7003 of a light-emitting element 7002 are electrically connected. An EL layer 7004 and a second electrode 7005 are laminated in this order on the layer 7003 .

[0532] In addition, various materials can be used for the first electrode 7003. For example, When using 003 as a cathode, a material with a small work function, specifically, for example, Li or C Alkaline metals such as s, and alkaline earth metals such as Mg, Ca, Sr, and In addition to alloys containing Mg (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are preferred.

[0533] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. Organic resin films such as amide, acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes The partition wall 7009 is formed by using a photosensitive resin material. An opening is formed on the surface of the substrate 003, and the side wall of the opening is formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7009, In this case, the step of forming a resist mask can be omitted.

[0534] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least The light-emitting layer may be included, and may be composed of a single layer or a plurality of layers may be laminated. When the EL layer 7004 is composed of a plurality of layers, the cathode and the An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole transport layer, and a hole transport layer are formed on a first electrode 7003 used as a light emitting layer. It is not necessary to provide all of these layers except for the light-emitting layer. stomach.

[0535] The stacking order is not limited to the above, and the hole injection onto the first electrode 7003 used as the anode may be selected. Alternatively, the layer may be laminated in the order of a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.

[0536] In FIG. 17(C), a hole is formed on a laminated film having a Ti layer, an aluminum layer, and a Ti layer laminated in that order. The injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are laminated in that order, and Mg: A laminate of Ag alloy thin film and ITO is formed.

[0537] However, when the driving TFT 7001 is an n-type, an electron injection layer and an electron The order of lamination of the electron transport layer, light emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the efficiency of the driving circuit. This is preferable because it can suppress the voltage rise caused by the voltage rise and reduce power consumption.

[0538] The second electrode 7005 is formed using a light-transmitting conductive material, for example. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide with silicon oxide added, etc. A light-transmitting conductive layer may be used.

[0539] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 17C, the light emitting element 70 Light emitted from 02 is emitted to the second electrode 7005 side as shown by the arrow.

[0540] In FIG. 17C, the drain electrode layer of the driving TFT 7001 is made of silicon oxide. A protective insulating layer 7051, a protective insulating layer 7052, a planarizing insulating layer 7056, a planarizing insulating layer 7053, and The insulating layer 7055 is electrically connected to the first electrode 7003 through a contact hole formed therein. The planarizing insulating layers 7036, 7046, 7053, and 7056 are made of polyimide, acrylic, Examples of the resin material that can be used include polystyrene, benzocyclobutene, polyamide, and epoxy. In addition to the above resin materials, low-dielectric constant materials (low-k materials), siloxane resins, and PSG are also available. (phosphorus glass), BPSG (boron phosphorus glass), etc. can be used. By stacking a plurality of insulating layers made of the above material, planarization insulating layers 7036, 7046, 7053, 7056 may be formed. The method for forming 056 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0541] In addition, a partition wall 70 is provided to insulate the first electrode 7003 from the first electrodes of adjacent pixels. The partition wall 7009 is made of an organic material such as polyimide, acrylic, polyamide, or epoxy. The partition wall 7009 is formed using a resin film, an inorganic insulating film, or an organic polysiloxane. An opening is formed on the first electrode 7003 using a photosensitive resin material, and the side wall of the opening is It is preferable to form the partition wall 70 so as to have an inclined surface having a continuous curvature. When a photosensitive resin material is used as the insulating layer 09, the step of forming a resist mask can be omitted. This can be done.

[0542] In the structure of FIG. 17C, when a full-color display is performed, for example, the light-emitting element 7 002 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also added. A light-emitting display device capable of full-color display using four types of light-emitting elements may be manufactured.

[0543] In the structure of FIG. 17(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By forming a material and combining it with color filters and color conversion layers, full color display is achieved. It is possible to do so.

[0544] The driving TFTs 7001, 7011, and 7021 used in the semiconductor device are Any one of the thin film transistors shown in the embodiments can be used as appropriate, and similar processes and The oxide semiconductor of the driving TFTs 7001, 7011, and 7021 can be formed of the same material. The conductor layer has reduced hydrogen and water. 1 is a highly reliable thin film transistor.

[0545] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic emission may be used to form an area color type light emitting device.

[0546] If necessary, an optical film such as a polarizing film, such as a circular polarizing plate, may be provided. .

[0547] Although the organic EL element has been described as the light-emitting element here, inorganic light-emitting elements may also be used. An EL element may also be provided.

[0548] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically In the example shown here, the current control TFT is connected directly between the driving TFT and the light emitting element. The configuration may be such that the two are connected to each other.

[0549] Next, the appearance and cross section of the light-emitting display panel (also called the light-emitting panel) will be described with reference to FIG. FIG. 18 shows a thin film transistor and a light emitting element formed on a first substrate. FIG. 18(B) is a plan view of a panel sealed between the two substrates by a sealant. This corresponds to a cross-sectional view taken along line HI in FIG.

[0550] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 450 is provided to surround the gate driver circuits 4503a and 4504b, and the scanning line driver circuits 4504a and 4504b. 5. Also, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided over the scanning line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 4 504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed together with the filling material 4507. Highly airtight and low outgassing protective film (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a plastic bag (such as a film) or a cover material.

[0551] In addition, a pixel portion 4502 and a signal line driver circuit 4503a are provided over a first substrate 4501. , 4503b, and the scanning line driver circuits 4504a, 4504b are each formed of a plurality of thin film transistors. In FIG. 18B, a thin film transistor 4510 included in a pixel portion 4502 , and a thin film transistor 4509 included in a signal line driver circuit 4503a.

[0552] The thin film transistors 4509 and 4510 are the same as those described in the above embodiment modes. Any one of them can be used as appropriate, and the thin film can be formed using similar steps and materials. Hydrogen and water are reduced in the oxide semiconductor layers of the transistors 4509 and 4510. The thin film transistors 4509 and 4510 are highly reliable thin film transistors.

[0553] Note that the thin film transistor 4509 is a thin film transistor having an oxide semiconductor layer In this embodiment, a conductive layer is provided in a position overlapping with a panel forming region. The transistors 4509 and 4510 are n-channel thin film transistors.

[0554] The channel of the oxide semiconductor layer of the thin film transistor 4509 is formed on the silicon oxide layer 4542. A conductive layer 4540 is provided in a position overlapping the panel formation region. By providing the semiconductor layer at a position overlapping the channel formation region, The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509 or may have a different potential. The conductive layer 45 may be formed of a conductive material and may function as a second gate electrode layer. The potential of 40 may be GND, 0V, or may be in a floating state.

[0555] In addition, a silicon oxide layer 4542 covering the oxide semiconductor layer of the thin film transistor 4510 is formed. The source electrode layer or the drain electrode layer of the thin film transistor 4510 is formed of a thin film transistor. In an opening formed in the silicon oxide layer 4542 and the insulating layer 4551 provided on the transistor, The wiring layer 4550 is electrically connected to the first electrode 4517. The thin film transistor 4510 and the first electrode 4517 are formed in contact with each other through the wiring layer 4 550.

[0556] A color filter layer 4545 is disposed on the insulating layer 45 so as to overlap the light emitting region of the light emitting element 4511. Formed on 51.

[0557] In addition, the color filter layer 4545 functions as a planarizing insulating film to reduce surface irregularities. The insulating layer 4542 is covered with an overcoat layer 4543.

[0558] In addition, an insulating layer 4544 is formed on the overcoat layer 4543. As the layer 4, for example, a silicon nitride layer may be formed by sputtering.

[0559] In addition, 4511 corresponds to a light-emitting element, and a first pixel electrode which is included in the light-emitting element 4511 is a pixel electrode. The electrode 4517 is a wiring connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is electrically connected to the first electrode 4550. The structure shown is a laminated structure of a first electrode 4517, an electroluminescent layer 4512, and a second electrode 4513. The light emitting element 4511 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4511. The configuration of 11 can be changed as appropriate.

[0560] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode 4517, and the sidewall of the opening is It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0561] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is completed or not.

[0562] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode A protective layer may be formed on the partition wall 4513 and the partition wall 4520. The protective layer may be formed of silicon nitride. A layer, a silicon oxynitride layer, a DLC layer, etc. can be formed.

[0563] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504 b, or various signals and potentials applied to the pixel portion 4502 are Powered by 8b.

[0564] The connection terminal electrode 4515 is formed of the same conductive layer as the first electrode 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the source electrode layer and the drain electrode layer of the thin film transistor 4509. The inner electrode layer is formed from the same conductive layer.

[0565] The connection terminal electrode 4515 is a terminal of the FPC 4518a and an anisotropic conductive layer 4519. The two are electrically connected via a

[0566] The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film or an acrylic plate. A light-transmitting material such as a glass film is used.

[0567] In addition, filler 4507 can be used with inert gases such as nitrogen and argon, as well as ultraviolet-curing gases. Resin or thermosetting resin can be used, PVC (polyvinyl chloride), acrylic , polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or E VA (ethylene vinyl acetate) can be used. For example, nitrogen is used as a filler. That's good.

[0568] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. In addition, optical films such as retardation plates (λ / 4 plates, λ / 2 plates) may be provided as appropriate. For example, the plate or the circular polarizer may be provided with an anti-reflection film by diffusing reflected light using surface irregularities. It is possible to apply an anti-glare coating to reduce glare.

[0569] The sealant is applied by screen printing, inkjet or dispenser. The sealing material is typically a visible light curing material, an ultraviolet light curing material, or a heat curing material. A material containing a chemically resistant resin can be used. A filler may also be included.

[0570] Signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b The driving element is formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be implemented. The circuit alone or a part of the circuit may be separately formed and mounted, and is not limited to the configuration of FIG. .

[0571] Through the above steps, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0572] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0573] (Embodiment 13) In this embodiment, an example of a semiconductor device including the logic circuit described in Embodiment 1 or 2 will be described. Specifically, the driver circuit has the logic circuit shown in the first or second embodiment. 1 shows an example of electronic paper.

[0574] FIG. 19 is a diagram showing an active matrix type electronic paper. The thin film transistor 581 that can be used is the thin film transistor shown in the above embodiment. Any one of them can be used as appropriate, and the same process and materials can be used to form the same embodiment. In this embodiment, the thin film transistor shown in the sixth embodiment is used as the thin film transistor 581. An example of application of the thin film transistor 581 is shown. Hydrogen and water are reduced in the oxide semiconductor layer of the thin film transistor 581. Therefore, the thin film transistor 581 is a highly reliable thin film transistor.

[0575] The electronic paper in FIG. 19 is an example of a display device that uses the twisting ball display method. The strikeball display method uses black and white spherical particles as display elements, and the electrode layer A first electrode layer and a second electrode layer are disposed between the first electrode layer and the second electrode layer, and a potential is applied to the first electrode layer and the second electrode layer. This method displays images by controlling the orientation of spherical particles by creating a difference.

[0576] A thin film transistor 581 provided on a substrate 580 is a thin film transistor of a bottom gate structure. The source electrode layer or the drain electrode layer is a silicon oxide layer 583, a protective insulating layer 5 84, contacting and electrically connecting with the first electrode layer 587 in an opening formed in the insulating layer 585 It has been done.

[0577] Between the first electrode layer 587 and the second electrode layer 588, there are a black area 590a and a white area 590b. 90b, and a spherical particle having a cavity 594 therearound that is filled with liquid. The spherical particles are filled with a filler 595 such as resin (see FIG. 19). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode and is provided on the opposing substrate 596. The second electrode layer 588 corresponds to a common electrode.

[0578] Also, instead of the twist ball, an electrophoretic element can be used. The body, positively or negatively charged white particles, and black particles that are charged with the opposite polarity to the white particles. The first electrode layer is a microcapsule having a diameter of about 10 μm to 200 μm. The microcapsules provided between the first electrode layer and the second electrode layer are Therefore, when an electric field is applied, the white particles and the black particles move in opposite directions, A display element that uses this principle is called an electrophoretic display element. This is generally called electronic paper. Electrophoretic display elements are more reflective than liquid crystal display elements. High reflectance means no auxiliary light is required, and the low power consumption means it can be displayed even in dimly lit areas. Even if the display unit is not powered, Since it is possible to hold the image displayed at any one time, it is possible to easily transmit the image from the source of the radio wave to a semiconductor device with a display function. (also simply referred to as a display device or a semiconductor device equipped with a display device) is moved away. It is also possible to store the displayed image.

[0579] In the electronic paper of the present embodiment, the voltage applied to the twist ball is controlled by a driving circuit. It is a reflective display device that displays images by controlling the pressure.

[0580] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0581] (Embodiment 14) In this embodiment, an example of a semiconductor device including the logic circuit described in Embodiment 1 or 2 will be described. Specifically, the driver circuit has the logic circuit shown in the first or second embodiment. An example of an electronic device (including a gaming machine) is shown. televisions, computer monitors, etc. Digital cameras, digital video cameras, digital photo frames, mobile phones (mobile phones (also called mobile phone devices), portable game machines, portable information terminals, audio playback devices, pachinko machines Examples of such machines include large game consoles.

[0582] FIG. 20A shows an example of a mobile phone. A mobile phone 1600 has a housing 160 In addition to the display unit 1602 incorporated in the device 1, operation buttons 1603a and 1603b, an external connection port, The device is equipped with a monitor 1604, a speaker 1605, a microphone 1606, etc.

[0583] In the mobile phone 1600 shown in FIG. 20A, when the display portion 1602 is touched with a finger or the like, You can input information. You can also make calls or send e-mails. This can be done by touching the display portion 1602 with a finger or the like.

[0584] The screen of the display unit 1602 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0585] For example, when making a call or composing an e-mail, the display unit 1602 is used for inputting characters. The main input mode is the character input mode, and the input operation of the characters displayed on the screen can be performed. In this case, it is possible to display a keyboard or number buttons on most of the screen of the display unit 1602. preferable.

[0586] In addition, the mobile phone 1600 includes a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above, the orientation of the mobile phone 1600 (portrait or landscape) can be determined, The screen display on the display unit 1602 can be automatically switched.

[0587] The screen mode can be changed by touching the display unit 1602 or by operating the housing 1601. This is done by operating the operation buttons 1603a and 1603b. For example, the display may be switched depending on the type of image to be displayed. If the image signal is video data, it switches to display mode, if it is text data, it switches to input mode. Replace.

[0588] In the input mode, the optical sensor of the display unit 1602 detects a signal and displays the If there is no input by touch operation on the display unit 1602 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the display mode to the display mode.

[0589] The display unit 1602 can also function as an image sensor. By touching the palm or fingers to the sensor 602, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may include a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0590] The semiconductor device described in the above embodiment can be applied to the display portion 1602. For example, A plurality of thin film transistors shown in the above other embodiments are arranged as pixel switching elements. It is possible.

[0591] FIG. 20(B) is also an example of a mobile phone. The portable information terminal shown in FIG. 20(B) is , can have multiple functions. For example, in addition to the telephone function, it can also have a built-in computer. It can also be equipped with various data processing functions.

[0592] The portable information terminal shown in FIG. 20B has two housings, a housing 1800 and a housing 1801. The housing 1801 includes a display panel 1802, a speaker 1803, a microphone, and a Phone 1804, pointing device 1806, camera lens 1807, external connection The housing 1800 includes a keyboard 1810 and an external memory slot. The housing 1801 includes a built-in antenna.

[0593] The display panel 1802 is equipped with a touch panel, and in FIG. A plurality of operation keys 1805 are indicated by dotted lines.

[0594] In addition to the above configuration, a non-contact IC chip, a small recording device, etc. may be built in. .

[0595] The display direction of the display panel 1802 changes appropriately depending on the usage mode. The camera lens 1807 is located on the same surface as the lens 1802, so video calls are possible. The speaker 1803 and microphone 1804 are not limited to voice calls, but can also be used for video calls, Recording and playback are possible. Furthermore, the housing 1800 and the housing 1801 can be slid apart. As shown in Figure 20(B), the bags can be folded from the unfolded state to the overlapped state, making them suitable for carrying. This makes it possible to miniaturize the device.

[0596] The external connection terminal 1808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the external memory slot 1811, it is possible to store and transfer a larger amount of data. Cut.

[0597] In addition to the above functions, it also has infrared communication function, TV reception function, etc. Good too.

[0598] FIG. 21A shows an example of a television device. The television device 9600 is A display portion 9603 is incorporated in the housing 9601. In addition, in this example, the housing 9601 is supported by a stand 9605. This shows the configuration.

[0599] The television device 9600 can be operated using an operation switch provided on the housing 9601 or a separate remote control. This can be done by using a remote control operation device 9610. The channel and volume can be controlled by the touch panel 9609, and the display 9603 shows The remote control unit 9610 can control the video. A display unit 9607 for displaying information output from the device 9610 may be provided.

[0600] The television device 9600 includes a receiver, a modem, and the like. This allows reception of general television broadcasts, and can also be used for wired or wireless reception via a modem. By connecting to a network, communication can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between sender and receiver, or between receivers). .

[0601] In the display portion 9603, the thin film transistor shown in the above embodiment is used as a switching element of a pixel. A plurality of transistors can be arranged.

[0602] FIG. 21B shows an example of a digital photo frame. The display frame 9700 includes a display unit 9703 built into a housing 9701. 03 is capable of displaying various images, such as images taken with a digital camera. By displaying image data, it can function like a normal photo frame.

[0603] In the display portion 9703, the thin film transistor shown in the above embodiment is used as a switching element of a pixel. A plurality of transistors can be arranged.

[0604] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, Equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back of the display unit. It is preferable to have a digital photo frame with a built-in camera because it improves the design. Insert a memory that stores image data taken with a digital camera into the media insertion section to create an image data. The captured image data can be displayed on the display portion 9703 .

[0605] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to configure the device so that desired image data is wirelessly acquired and displayed.

[0606] FIG. 22 shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 includes a display unit 9893 and is connected to the housing 9881 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891 .

[0607] In the display portion 9883, the thin film transistor shown in the above embodiment is used as a switching element of a pixel. A plurality of transistors can be arranged.

[0608] In addition, the portable gaming machine shown in FIG. 22 also includes a speaker unit 9884, a recording medium insertion unit 9 886, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor Sa9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature degree, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient 9889) microphones, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient that the device is equipped with the thin film transistor disclosed in the specification, and other auxiliary equipment is provided as appropriate. The portable game machine shown in FIG. The function of reading out the program or data stored in the device and displaying it on the display unit, as well as wireless communication with other portable gaming machines, The portable game machine shown in FIG. 22 has a function for communicating with the player and sharing information. The functions are not limited to these, and may have a variety of functions.

[0609] As described above, the driving circuit shown in the first or second embodiment can be used in various electronic devices as described above. The present invention can be applied to a display panel of any one of the above-mentioned types, thereby providing highly reliable electronic equipment.

[0610] (Embodiment 15) In this embodiment, an example of a semiconductor device including the logic circuit described in Embodiment 1 or 2 will be described. Specifically, the driver circuit has the logic circuit shown in the first or second embodiment. Electronic paper can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train displays, etc. This applies to in-vehicle advertising, credit card and other card displays, etc. An example of an electronic device is shown in Figure 23.

[0611] FIG. 23 shows an example of an electronic book. For example, an electronic book 2700 has a housing 2701. The housing 2701 and the housing 2703 are The opening and closing operations are performed by using the shaft portion 2711 as an axis. With this configuration, it becomes possible to operate like a paper book.

[0612] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 23) and An image can be displayed on a display unit (display unit 2707 in FIG. 23).

[0613] FIG. 23 shows an example in which an operation unit is provided on the housing 2701. 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a keyboard, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0614] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0615] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0616] (Embodiment 16) One embodiment of the present invention is a method for manufacturing a semiconductor device that functions as a carrier donor (or acceptor) in an oxide semiconductor. By removing possible impurities to extremely low levels, intrinsic or substantially intrinsic oxide is obtained. The present invention relates to a method for producing an oxide semiconductor, and applying the oxide semiconductor to a thin film transistor.

[0617] FIG. 24 shows the band structure between the source and drain of such a transistor. In an ideal state, the Fermi level of a highly purified oxide semiconductor is in the center of the forbidden band. Located.

[0618] In this case, the work function is φ m , the electron affinity of the oxide semiconductor is χ, then φ m =χ For example, the Fermi level of the electrode metal and the conduction band level of the oxide semiconductor at the junction surface are the same. If the right side of this equation is large, the contact is ohmic. 3.15 eV, electron affinity 4.3 eV, intrinsic (carrier density approx. 1×10 -7 / cm 3), and titanium ( When Ti) is used, no Schottky barrier is formed against electrons, as shown in Figure 24. do not have.

[0619] FIG. 25 shows the state of a transistor using an oxide semiconductor when a positive voltage is applied to the drain side. Since an oxide semiconductor has a wide band gap, it is highly purified and has an intrinsic Alternatively, the intrinsic carrier density of a substantially intrinsic oxide semiconductor is zero or very close to zero. When a voltage is applied between the source and drain, carriers (electrons) flow from the source side. ) is injected and can flow to the drain side.

[0620] FIG. 26(A) is an energy band diagram of a MOS structure when the gate voltage is positive. The figure shows a transistor using an oxide semiconductor. Since there are almost no thermally excited carriers in the oxide semiconductor, However, as shown in Figure 25, the carriers injected from the source side Rear (electrons) can propagate.

[0621] FIG. 26(B) is an energy band diagram of the MOS structure when the gate voltage is made negative. The oxide semiconductor has a small number of Since there are almost no carriers (positive holes), carriers are not accumulated near the gate insulating film. This means that the off-state current is small.

[0622] FIG. 27 shows a band diagram of a transistor using silicon semiconductor. The band gap of silicon semiconductor is 1.12 eV and the intrinsic carrier density is 1.45 × 10 1 0 / cm 3 (300K). Thermally excited carriers cannot be ignored even at room temperature, and the This results in a large variation in the off-current.

[0623] In this way, simply applying a wide band gap oxide semiconductor to a transistor Instead, impurities such as hydrogen that form donors are reduced as much as possible, and the carrier density is reduced to 1×10 14 / cm 3 Less than or equal to 1×10 12 / cm 3 By making it so that The carriers that are thermally excited at the operating temperature are eliminated, and only the carriers injected from the source side are included. This allows the transistor to operate. As a result, the off-state current can be reduced to 1×10 -13 [A] or less, and the off-current hardly changes with temperature change. A transistor that operates stably can be obtained.

[0624] (Embodiment 17) In this embodiment, the measured value of the off-state current in the evaluation element (also called TEG) is as follows. will be explained.

[0625] In Fig. 28, 200 thin-film transistors with L / W = 3 μm / 50 μm are connected in parallel. Specifically, the initial characteristics of a thin-film transistor with L / W=3μm / 10000μm are shown. FIG. 29(A) shows a plan view thereof, and FIG. 29(B) shows an enlarged top view thereof. The area enclosed by the dotted line in B) is the thin film for one step with L / W=3μm / 50μm and Lov=1.5μm. In order to measure the initial characteristics of the thin-film transistor, the substrate temperature was set to room temperature. The source-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10 V. The gate-to-source voltage (hereafter referred to as gate voltage or Vg) can be varied from -20V to +20V. The change in the source-drain current (hereinafter referred to as drain current or Id) when the In FIG. 28, Vg was varied from -20V to +5V. The range is shown in .

[0626] As shown in FIG. 28, a thin-film transistor with a channel width W of 10,000 μm has a Vd of 1 V And at 10V, the off-current is 1×10 -13 [A] or less, and measuring instruments (semiconductor Resolution of the parameter analyzer, Agilent 4156C (Agilent) (100fA) or less.

[0627] A method for manufacturing the thin film transistors that were measured will be described.

[0628] First, a silicon nitride layer is formed as a base layer on a glass substrate by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer as a gate electrode layer by a sputtering method. A tungsten layer was then formed. The tungsten layer was then selectively etched to form the gate. An electrode layer was formed.

[0629] Next, a 100 nm thick oxide / nitride layer was formed on the gate electrode layer by CVD as a gate insulating layer. A silicon layer was formed.

[0630] Next, an In-Ga-Zn-O metal oxide target was deposited on the gate insulating layer by sputtering. The thickness of the film was 50 mm. Here, the oxide semiconductor layer was selectively etched to form an island. A shaped oxide semiconductor layer was formed.

[0631] Next, the oxide semiconductor layer was subjected to a first heating process in a clean oven under a nitrogen atmosphere at 450° C. for 1 hour. The heat treatment was carried out.

[0632] Next, a titanium layer (thickness 15 mm) was formed on the oxide semiconductor layer as a source electrode layer and a drain electrode layer. The source electrode layer and the drain electrode layer were then formed by sputtering. The channel length L of one thin film transistor is 3 μm and the channel width W is 5 0μm, and by connecting 200 pieces in parallel, the effective L / W is 3μm / 10000μm. I made it happen.

[0633] Next, a protective insulating layer was formed by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. The silicon oxide layer, which is a protective layer, was selectively etched. The gate electrode layer, the source electrode layer, and the drain electrode layer were then etched to form openings. Thereafter, a second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0634] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0635] Through the above steps, a bottom gate type thin film transistor was fabricated.

[0636] As shown in Figure 28, a thin-film transistor is -13 [A] is the level This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced in the manufacturing process. The hydrogen concentration in the semiconductor layer is 5×10 19(atoms / cm 3 ) or less, preferably 5 ×10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 17 (atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectrometry) cormorant.

[0637] Although an example using an In-Ga-Zn-O-based oxide semiconductor has been shown, the present invention is not particularly limited thereto. Other oxide semiconductor materials, such as In-Sn-Zn-O, Sn-Ga-Zn-O, l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, In-Sn-O series , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, AlOx is mixed at 2.5 to 10 wt% as an oxide semiconductor material. In-Al-Zn-O system and In-Zn-O system with 2.5 to 10 wt% SiOx mixed A system can also be used.

[0638] In addition, the carrier density of the oxide semiconductor layer measured by a carrier measurement device is Carrier density 1.45×10 10 / cm 3 It is preferable that it is equal to or less than Specifically, 5×10 14 / cm 3 Less than or equal to 5×10 12 / cm 3 Below That is, the carrier density of the oxide semiconductor layer can be made as close to zero as possible.

[0639] In addition, the channel length L of the thin film transistor can be set to 10 nm or more and 1000 nm or less. This allows the circuit to operate at higher speeds, and the extremely small off-state current allows for even lower power consumption. It is also possible to reduce power consumption.

[0640] In addition, when the thin film transistor is in an off state, the oxide semiconductor layer is regarded as an insulator and is not connected to the circuit. Design can be done.

[0641] Next, the temperature characteristics of the off-current of the thin film transistor manufactured in this embodiment are evaluated. The temperature characteristics are important for the environmental resistance of the final product in which the thin-film transistor is used, as well as for maintaining the performance. It is important to consider the following points. Naturally, the smaller the change, the better, and the more freedom there is in product design. The degree increases.

[0642] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 12 The substrate on which the thin film transistor was formed was kept at a constant temperature of 0°C, and the drain voltage The Vg-Id characteristics were obtained by varying the gate voltage from -20V to +20V and the input voltage from 6V.

[0643] Figure 30(A) shows the Vg-Id characteristics measured at each of the above temperatures, which are overlaid. The area of ​​the off-current surrounded by the dotted line is shown in enlargement in FIG. The rightmost curve indicated by the arrow is taken at -30℃, and the leftmost curve is taken at 120℃. The obtained curve is somewhere between these two. The on-current has almost no temperature dependence. As is clear from the enlarged view of Figure 30(B), the off-state current is At all temperatures, except for the vicinity, the resolution of the measuring instrument is close to 1×10 -12 [A] or less In other words, even at a high temperature of 120°C, the off-state current is 1× 10 -12 [A] or less, and the effective channel width W is 10,000 μm. Considering these factors, it can be seen that the off-state current is very small.

[0644] Thin-film transistors using highly purified oxide semiconductors (purified OS) are The temperature dependence of the off-current is almost nonexistent. This is due to the energy gap of the oxide semiconductor. This is because the gate capacitance is 3 eV or more and the intrinsic carriers are very few. The drain region is in a degenerate state, which is also the reason why no temperature dependence appears. The operation of a thin-film transistor is based on the capacitance of the oxide semiconductor injected from the degenerated source region. The carrier density is not temperature dependent, so the above characteristics ( This can explain the lack of temperature dependence of the off-state current.

[0645] By using thin film transistors with extremely low off-state current, ) is fabricated, the off-current is small and there is almost no leakage, so the stored data can be retained. You can extend the time it lasts. [Explanation of symbols]

[0646] 11 Thin-film transistor 12 Thin-film transistor 13 Thin-film transistor 14 Thin-film transistor 15 Capacitive element 21 Thin-film transistor 22 Thin-film transistor 23 Thin-film transistor 24 Thin-film transistor 25 Capacitive element 31 Thin-film transistor 41 Thin-film transistor 101 Thin-film transistor 102 Thin-film transistor 103 Thin-film transistor 104 Thin-film transistor 105 Capacitive element 110 Pulse output circuit 111 Thin-film transistor 112 Thin-film transistor 113 Thin-film transistor 114 Thin-film transistor 115 Capacitive element 120 Pulse output circuit 121 Thin-film transistor 122 Thin-film transistor 123 Thin-film transistor 124 Thin-film transistor 125 Capacitive element 130 Pulse output circuit 201 Thin-film transistor 202 Thin-film transistor 203 Thin-film transistor 204 Thin-film transistor 205 Capacitive element 210 Pulse output circuit 211 Thin-film transistor 212 Thin-film transistor 213 Thin-film transistor 214 Thin-film transistor 215 Capacitive element 220 Pulse output circuit 221 Thin-film transistor 222 Thin-film transistor 223 Thin-film transistor 224 Thin-film transistor 225 Capacitive element 230 Pulse output circuit 300 Substrates 302 Gate insulating layer 303 Protective insulation layer 310 Thin-film transistor 311 Gate electrode layer 313 Channel formation region 314a High resistance source region 314b High-resistance drain region 315a Source electrode layer 315b Drain electrode layer 316 Oxide insulating layer 320 Substrate 322 Gate Insulation Layer 323 Protective Insulation Layer 330 Oxide semiconductor layer 331 Oxide semiconductor layer 332 Oxide semiconductor layer 340 Substrate 342 Gate Insulation Layer 343 Protective Insulation Layer 345 Oxide Semiconductor Layer 346 Oxide Semiconductor Layer 350 Thin Film Transistor 351 Gate electrode layer 352 Oxide semiconductor layer 355a Source electrode layer 355b Drain electrode layer 356 Oxide insulating layer 360 Thin Film Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel Formation Region 364a High resistance source region 364b High-resistance drain region 365a Source electrode layer 365b Drain electrode layer 366 Oxide Insulating Layer 370 Substrate 372a first gate insulating layer 372b second gate insulating layer 373 Protective Insulation Layer 380 Thin Film Transistor 381 Gate electrode layer 382 Oxide semiconductor layer 385a Source electrode layer 385b Drain electrode layer 386 Oxide Insulating Layer 390 Thin-film transistor 391 Gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Layer 394 Substrate 395a Source electrode layer 395b Drain electrode layer 396 Oxide Insulating Layer 397 Gate Insulation Layer 398 Protective Insulation Layer 399 Oxide Semiconductor Layer 400 Substrates 402 Gate insulating layer 407 Insulating Layer 410 Thin Film Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Source electrode layer or drain electrode layer 415b Source electrode layer or drain electrode layer 420 Silicon substrate 421a aperture 421b Aperture 422 Insulating layer 423 Aperture 424 Conductive layer 425 Thin Film Transistor 426 Thin Film Transistor 427 Conductive Layer 450 Substrate 452 Gate insulation layer 457 Insulating Layer 460 Thin Film Transistor 461 Gate electrode layer 461a Gate electrode layer 461b Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Source electrode layer or drain electrode layer 465a1 Source electrode layer or drain electrode layer 465a2 Source electrode layer or drain electrode layer 465b Source electrode layer or drain electrode layer 468 Wiring layer 580 Substrate 581 Thin Film Transistor 583 Silicon oxide layer 584 Protective Insulation Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 590a black area 590b White area 594 Cavity 595 Filling material 596 Opposing Substrate 1600 Mobile Phones 1601 Case 1602 Display section 1603a Operation button 1603b Operation button 1604 External connection port 1605 Speaker 1606 Mike 1800 Case 1801 Case 1802 Display Panel 1803 Speaker 1804 Microphone 1805 Operation key 1806 Pointing Device 1807 Camera Lenses 1808 External connection terminal 1810 Keyboard 1811 External memory slot 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4040 Conductive layer 4041 Insulation layer 4042 Insulation layer 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4542 Silicon oxide layer 4543 Overcoat layer 4544 Insulation layer 4545 Color filter layer 4550 wiring layer 4551 Insulation layer 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common potential line 7001 Driving TFT 7002 Light emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7011 Driving TFT 7012 Light emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive layer 7019 Bulkhead 7021 Driving TFT 7022 Light emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7026 Electrode 7027 Conductive layer 7029 Bulkhead 7031 Insulation layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7036 Planarizing insulating layer 7041 Insulation layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7046 Planarizing insulating layer 7051 Silicon oxide layer 7052 Protective insulation layer 7053 Planarizing insulating layer 7055 Insulation layer 7056 Planarizing insulating layer 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section

Claims

[Claim 1] a thin film transistor that, when turned off, brings a potential of a node to which one of a first terminal and a second terminal is electrically connected into a floating state; The channel forming region of the thin film transistor has a hydrogen concentration of 5×10 １９ (atoms / cm ３ 2. A logic circuit comprising the following oxide semiconductor:

Images