Semiconductor device and semiconductor diagnosis device

Abstract

To provide a technology capable of speeding up a clock.SOLUTION: A semiconductor device includes: a counter circuit configured to generate a reading signal when a count frequency reaches a predetermined number of times; a buffer configured to store test data and sequentially output the test data in storing order of the test data when the reading signal indicates an effective value; and a first scan test circuit that sequentially captures the test data output from the buffer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and is applicable to, for example, a semiconductor device including a scan chain. [Background technology]

[0002] In the field of scan testing, lock-up latches are used. Lock-up latches are a technology for fixing clock skew between scan shift registers on different branches of a clock tree (JP Patent Publication No. 2009-508101). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2009-508101 Summary of the Invention [Problem to be solved by the invention]

[0004] When the clock is made faster, normal transfer may not be possible even if a lock-up latch is provided between the scan shift registers.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A brief overview of representative aspects of this disclosure is as follows. The semiconductor device includes a counter circuit configured to generate a read signal when a count reaches a predetermined number, a buffer configured to store test data and, when the read signal indicates a valid value, to sequentially output the test data in the order in which the test data was stored, and a first scan test circuit that sequentially takes in the test data output from the buffer. Effect of the Invention

[0007] According to the semiconductor device, it is possible to increase the clock speed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram for explaining a scan test of a semiconductor device. [Diagram 2] FIG. 2 is a diagram for explaining a scan test of the logic circuit shown in FIG. [Diagram 3] FIG. 3 is a block diagram showing a schematic configuration of two logic circuits and their ATPG models in the embodiment. [Figure 4] FIG. 4 is a timing chart when the front-stage scan chain and the rear-stage scan chain are directly connected. [Diagram 5] FIG. 5 is a timing chart for the case where a lock-up latch is provided between the front-stage scan chain and the rear-stage scan chain. [Figure 6] FIG. 6 is a timing chart showing a case where a hold violation occurs when a lock-up latch is provided between a front-stage scan chain and a rear-stage scan chain. [Figure 7] FIG. 7 is a timing chart showing a case where a setup violation occurs when a lock-up latch is provided between a front-stage scan chain and a rear-stage scan chain. [Figure 8] FIG. 8 is a block diagram showing the configuration of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of the counter circuit shown in FIG. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of the FIFO shown in FIG. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of the transmission circuit shown in FIG. [Figure 12] FIG. 12 is a block diagram showing an example of the configuration of the receiving circuit shown in FIG. [Figure 13] FIG. 13 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a block diagram showing a configuration of a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a block diagram showing the configuration of a semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a diagram for explaining a scan test of the semiconductor device shown in FIG. [Figure 19] FIG. 19 is a diagram for explaining a scan test of a semiconductor device in a comparative example. [Figure 20] FIG. 20 is a block diagram showing the configuration of a semiconductor diagnostic device in the fourth embodiment. [Figure 21] FIG. 21 is a block diagram showing the configuration of a semiconductor device according to the fifth embodiment. [Figure 22] FIG. 22 is a diagram showing circuit data of the semiconductor device shown in FIG. [Figure 23] FIG. 23 is a diagram showing test design data of the semiconductor device shown in FIG. [Figure 24] FIG. 24 is a diagram showing the ATPG model shown in FIG. [Diagram 25] FIG. 25 is a diagram showing a flow of manufacturing, test pattern generation and diagnosis of the semiconductor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. However, in order to clarify the description, the following description and drawings are omitted and simplified as appropriate. In addition, the same components are given the same reference numerals, and repeated description may be omitted.

[0010] <Overview of the embodiment> The scan test, which is the premise of this disclosure, will be described with reference to FIGS. 1 and 2. FIG.

[0011] 1, the semiconductor device 1 includes a semiconductor chip 10 and a package substrate 30. The semiconductor chip 10 includes a logic circuit (LC) 100. The logic circuit 100 includes a combinational circuit (CC) 110, a scan chain (SC) 120, and a multiplexer 130. The semiconductor chip 10 also includes terminals 141, 142, 143, and 144.

[0012] The package substrate 30 is provided with an external terminal 41, an external terminal 42, an external terminal 43, and an external terminal 44. A scan input signal (SCAN_IN) is input to the external terminal 41, and the external terminal 41 is connected to a terminal 141. A scan enable signal (SCAN_EN) is input to the external terminal 42, and the external terminal 42 is connected to a terminal 142. A clock signal (CLOCK) is input to the external terminal 43, and the external terminal 43 is connected to a terminal 143. A scan output signal (SCAN_OUT) is output to the external terminal 44, and the external terminal 44 is connected to a terminal 144.

[0013] 2, in the scan test, flip-flops (FFs) 121 in a logic circuit 100 are connected in a shift register fashion to construct a scan chain 120, and test data is input and output by a shift operation. The test data includes a test pattern and a test result.

[0014] As a specific operation, the test device (TSTR) 2 enables SCAN_EN input to the external terminal 41, and inputs SCAN_IN as a test pattern to the external terminal 41. SCAN_IN input to the external terminal 41 is input in sequence to each flip-flop 121 via the terminal 141 and the multiplexer (selector) 122, and the test pattern is supplied to the combinational circuit 110.

[0015] Thereafter, the test apparatus 2 disables SCAN_EN input to the external terminal 41. Then, the value of the combinational circuit 110 is stored in each flip-flop 121 via the multiplexer 122.

[0016] After that, the test device 2 enables SCAN_EN input to the external terminal 41. Then, the value stored in the flip-flop 121 is output in sequence from the external terminal 44 as SCAN_OUT as the test result via the multiplexer 130 and the terminal 144. The test device 2 compares the output SCAN_OUT with an expected value. Here, the flip-flop 121 is a flip-flop that captures a data signal in synchronization with the rising edge of the clock signal (CLOCK).

[0017] A manufacturing test (package test) using a scan test is performed in synchronization with the test equipment 2. Therefore, to operate the scan test correctly, all of the FFs 121 in the scan chain 120 must be synchronously transferred with the CLOCK supplied from the test equipment 2. Also, SCAN_EN, SCAN_IN, and SCAN_OUT must all be directly controlled by the test equipment 2. Note that the external terminals 41, 42, 43, and 44 are shared with input terminals and output terminals of functions (original functions) other than the scan test of the logic circuit 100, from the viewpoint of not increasing the number of external terminals provided on the package board 30. SCAN_EN, SCAN_IN, and SCAN_OUT are enabled for input or output only in the test mode.

[0018] A technique (embodiment) capable of increasing the speed of a clock signal for a scan test in a state where scan chains of a plurality of logic circuits are cascaded will be described with reference to FIG.

[0019] The logic circuit 100a as a first semiconductor circuit includes a scan chain 120a as a first scan test circuit, a FIFO (First In First Out) 150a as a buffer, and a counter circuit (CNTR) 160a. The counter circuit 160a controls a read signal (RD) of the FIFO 150a. The FIFO 150a is disposed between the scan chain 120a and a scan chain 120b as a second scan test circuit of the logic circuit 100b. The logic circuit 100a includes a combinational circuit similar to the combinational circuit 110 of the logic circuit 100 shown in FIG.

[0020] The scan chain 120a has the same configuration as the scan chain 120 shown in FIG. 2. However, in FIG. 3, the scan chain 120a is illustrated in a simplified manner. For example, SCAN_EN and the multiplexer 122 are omitted. Also, the flip-flop 121 is illustrated as only two stages of flip-flops (FFA, FF1). CLKA is input to FFA and FF1 as a first clock signal. CLKA is a clock signal obtained by delaying CLKR as a second clock signal. Read data (R_DATA) from the FIFO 150a is input to the scan chain 120a.

[0021] Logic circuit 100b as a second semiconductor circuit has the same configuration as logic circuit 100 shown in FIG. 2. Scan chain 120b has the same configuration as scan chain 120 shown in FIG. 2. However, scan chain 120b is illustrated in a simplified manner in FIG. 3. For example, SCAN_EN and multiplexer 122 are omitted. Also, flip-flop 121 is illustrated as only two stages of flip-flops (FF2, FFB). CLKB is input to FF2 and FFB as a third clock signal. CLKB is input to logic circuit 100a as CLKR. An output signal (S_OUT) is output from scan chain 120b.

[0022] The FIFO 150a can absorb the asynchronous relationship between the two scan chains 120a and 120b (skew between CLKB and CLKA). The counter circuit 160a can fix the number of clock cycles required for transfer between the two scan chains 120a and 120b. This allows the scan chains 120a and 120b to be synchronized even if the CLOCK frequency is increased (even if the CLOCK is made faster).

[0023] FFB, which is the flip-flop at the final stage of the scan chain 120b on the input side of FIFO 150a, continues to write test data sent from FF2, which is the flip-flop at the previous stage, to FIFO 150a every cycle. At this time, it is preferable to synchronize writing from FFB to FIFO 150a. For example, only writing to FFB and FIFO 150a may be synchronized, or a circuit that transfers data by handshake may be inserted between logic circuit 100a and logic circuit 100b. In this case, however, the throughput within one period of CLKA and CLKB is guaranteed.

[0024] The FFA, which is the first flip-flop of the scan chain 120a on the output side of the FIFO 150a, continues to capture the R_DATA read from the FIFO 150a. However, the FIFO 150a updates its top data (changes the pointer) only after the counter circuit 160a enables RD. Therefore, the R_DATA captured by the FFA when RD is disabled is invalid.

[0025] For example, the counter circuit 160a enables RD in the fourth cycle of CLKA. In this case, FF3 starts outputting valid test data from the fifth cycle. The test data at this time is the data written from FF2 to the FIFO 150a in the first cycle.

[0026] This structure has four stages of FF pipeline between FFB and FFA, and can be considered to be almost equivalent to the state (ATPG model) where FFB and FFA can be transferred synchronously. However, the initial value of the FF pipeline is not strictly different from that of FIFO 150a. A test pattern is created for this ATPG (Automatic Test Pattern Generation) model (ATPG_M). The created test pattern is then used in the actual circuit with FIFO 150a and counter circuit 160a. This allows the scan test to be performed at a high speed.

[0027] The effects of the embodiment will be described with reference to FIGS.

[0028] When a scan test is performed with transfer between semiconductor chips, a large clock skew occurs between the flip-flop (FFB) at the last stage of the scan chain 120b and the flip-flop (FFA) at the first stage of the scan chain 120a, as shown in Fig. 4. This can cause a hold violation, preventing normal transfer. Fig. 4 shows an example of a clock skew of about 1 / 4 clock cycle.

[0029] One possible solution is to insert a lock-up latch (LUL) between the FFB and FFA, as shown in Figure 5, and delay the data transferred from the FFB by half a clock cycle before transmitting it to the FFA. This allows for synchronous transfer between semiconductor chips, enabling normal transfer.

[0030] To reduce test costs, there is a demand for faster clock speeds in scan tests to shorten test times. However, even in configurations that use LUL for transfer between semiconductor chips, a hold violation may occur when the clock speed is increased, as shown in Figure 6. This occurs when the clock skew (the timing difference between CLKA and CLKB) is longer than the rising edge of the clock. Figure 6 shows an example of a clock skew of approximately 3 / 4 clock cycles. When a hold violation occurs, the data in LUL is latched into the FFA one clock cycle earlier than it would be normally (expected).

[0031] Furthermore, problems with transfers between semiconductor chips are not limited to hold violations. There may also be problems with setup violations, in other words, as shown in Figure 7, the clock (CLKA) of the input semiconductor chip that receives the scan data (output of LUL) from the output semiconductor chip may move before the arrival of the data, preventing normal transfer. Figure 7 shows an example of a clock skew of about 3 / 4 clock cycle. If there is a setup violation, the data from LUL will be transferred one clock cycle later than it is expected to be latched correctly in the FFA.

[0032] Aligning the clock latencies of different semiconductor chips to eliminate skew is practically difficult because of the enormous design costs involved, and it is also impossible if the semiconductor chips are developed at different locations and are black boxes to each other. Whether a hold violation or a setup violation occurs, the only solution is to slow down the clock. In other words, the clock cannot be made faster.

[0033] In this embodiment, as described above, the FIFO 150 absorbs the asynchronous relationship between the two scan chains 120a and 120b, and the counter circuit 160a can fix the number of clock cycles required for transfer between the two scan chains 120a and 120b. This makes it possible to synchronize the scan chains 120a and 120b even if the CLOCK frequency is increased (even if the CLOCK speed is increased).

[0034] Below, some more specific embodiments are exemplified. In the following description of the embodiments, the same reference numerals as those in the above-mentioned summary of the embodiments may be used for parts having the same configurations and functions as those described in the above-mentioned summary of the embodiments. The description of such parts may be appropriately cited within the scope of technical inconsistency. Furthermore, a part of the above-mentioned summary of the embodiments and all or a part of the multiple embodiments may be appropriately applied in a composite manner within the scope of technical inconsistency.

[0035] [First embodiment] The semiconductor device according to the first embodiment will be described with reference to FIG.

[0036] The semiconductor device 1 includes a semiconductor chip 10a as a first semiconductor circuit and a semiconductor chip 10b as a second semiconductor circuit. The semiconductor device 1 further includes an external terminal 41 to which SCAN_IN is input, an external terminal 43 to which CLOCK is input, an external terminal 44 to which SCAN_OUT is output, and an external terminal 45 to which a control signal (CS) is input. The semiconductor device 1 also includes an external terminal to which SCAN_EN is input, similar to the external terminal 42 of the semiconductor device shown in FIG. 1, but is not shown.

[0037] The semiconductor chip 10a includes a scan chain 120a, a FIFO 150a, a counter circuit 160a, a setting register (S_REG) 170a, and a receiving circuit (RX) 180a. The semiconductor chip 10a further includes a terminal 141a, a terminal 143a, a terminal 144a, and a terminal 145a as input terminals. The output signal (SO) from the semiconductor chip 10b is input to the terminal 141a as an input signal (SI). The CLOCK from the external terminal 43 is input to the terminal 143a as CLKA. The SCAN_OUT from the scan chain 120a is output to the terminal 144a. The CS from the external terminal 45 is input to the terminal 145a. The setting register 170a holds the CS input from the terminal 145a. The semiconductor chip 10a includes a terminal to which SCAN_EN is input, similar to the external terminal 142 of the semiconductor chip shown in FIG. 1, but is omitted from the illustration.

[0038] The semiconductor chip 10b includes a scan chain 120b and a transmission circuit (TX) 190b. The semiconductor chip 10b further includes a terminal 141b to which SCAN_IN is input from the external terminal 41, a terminal 143b to which CLOCK is input as CLKB from the external terminal 43, and a terminal 144b as an output terminal to which SO from the transmission circuit 190b is output. SO includes test data from the test device 2 and a scan test result from the scan chain 120b. The semiconductor chip 10b includes a terminal to which SCAN_EN is input, similar to the external terminal 142 of the semiconductor chip shown in FIG. 1, but is not shown.

[0039] An example of the configuration of the counter circuit 160a will be described with reference to FIG.

[0040] The counter circuit 160a includes an incrementer 161, a selector 162, a counter register (C_REG) 163, a comparator (CMP) 164, and AND circuits 165 and 166. The counter circuit 160a starts counting using SCAN_EN as a trigger (here, a change from 0 to 1). When the value of the counter register 163 matches the value of the setting register 170a, the counter circuit 160a is configured to stop counting. The counter circuit 160a is also configured to enable RD and start reading from the FIFO 150a.

[0041] When SCAN_EN is "0" indicating invalidity, the output signal of the AND circuit 165 becomes "0", and the selector 162 selects the output signal (O1) of the counter register 163. As a result, the input signal (IN) of the counter register 163 becomes O1, the value of the counter register 163 does not change, and the output signals (O1, O2) of the counter register 163 do not change either. As a result, the output signal (O3) of the comparator 164 does not change either, and for example, continues to output "0" indicating a mismatch. Also, when SCAN_EN is "0", the output signal RD of the AND circuit 166 becomes "0" indicating invalidity.

[0042] When SCAN_EN is "1" indicating validity, and the output signal of the comparator 164 is "0" indicating mismatch, the output signal of the AND circuit 165 becomes "1", and the selector 162 selects the output signal of the incrementer 161. As a result, the input signal (IN) of the counter register 163 becomes the value of O1 incremented by +1, and the value of the counter register 163 becomes the value incremented by +1. As a result, the values ​​of O1 and O2 also become the value incremented by +1. The counter register 163 is counted up until it matches the value of the setting register 170a. When the output signal of the comparator 164 becomes "1" indicating match, SCAN_EN is "1", so that RD, which is the output signal of the AND circuit 166, becomes "1" indicating validity. Also, when the output signal of the comparator 164 becomes "1" indicating match, the output signal of the AND circuit 165 becomes "0", and the selector 162 selects O1 of the counter register 163. As a result, the value of the counter register 163 does not change, as in the case where SCAN_EN is "0." At this time, the value of the counter register 163 is the set value of the setting register 170a+1.

[0043] The comparison target of the comparator 164 may be a fixed set value without using the setting register 170a. Although an example of an up-counter has been described as the counter circuit 160a, the counter method is not limited and may be a down-counter, for example, as long as it can count any cycle.

[0044] An example of the configuration of the FIFO 150a will be described with reference to FIG.

[0045] The FIFO 150a includes a write system circuit 151 that operates in synchronization with CLKR, and a read system circuit 152 that operates in synchronization with CLKA. The write system circuit 151 includes a demultiplexer (DEMUX) 1511, a gray code counter (G_CNTR) 1512, and a register group 1513. The register group 1513 includes REG_1 to REG_M. The read system circuit 152 includes a multiplexer (MUX) 1521, a gray code counter (G_CNTR) 1522, and a register (REG) 1523.

[0046] When the write signal (WR) is valid, the count value of the Gray code counter 1512 changes with each change in CLKR. The count value is expressed in binary, and changes so that there is only one bit change between adjacent values. The demultiplexer 1511 selects a register from the register group 1513 that corresponds to the count value of the Gray code counter 1512, and the write data (W_DATA) is written to the selected register. The registers from the register group 1513 are selected in the order of REG_1 to REG_M.

[0047] When RD is valid, the count value of the Gray code counter 1522 changes every time CLKA changes. The multiplexer 1521 selects a register corresponding to the count value of the Gray code counter 1522 from the register group 1513, and the value of the selected register is read to the register 1523. The registers of the register group 1513 are selected in the order of REG_1 to REG_M. The data stored in the register 1523 is output to the scan chain 120a as R_DATA.

[0048] The counter circuits used in the write system circuit 151 and the read system circuit 152 are not limited to Gray code counters, but may be binary code counters.

[0049] An example of the configuration of the transmission circuit 190a will be described with reference to FIG.

[0050] The transmission circuit 190a includes a shift register consisting of M FFs 191 to 19M, where M is an integer equal to or greater than 3. FFs 191 to 19M are flip-flops that capture data signals in synchronization with the rising edge of CLKT as a fourth clock signal. FFs 191 are set (set to "1") when SCAN_EN is enabled, and FFs 192 to 19M are reset (set to "0") when SCAN_EN is enabled. An output signal (S_OUT) of the scan chain 120b is input to FFs 191.

[0051] When SCAN_EN becomes valid, the transmission circuit 190a outputs (M-1) consecutive "0"s, and then outputs "1" for one cycle as the output signal (SO). This "1" for one cycle is a flag indicating that this is the beginning of the test data. After that, S_OUT is transmitted sequentially as SO.

[0052] The configuration of the receiving circuit 180a will be described with reference to Fig. 12. Fig. 12 is a block diagram showing an example of the configuration of the receiving circuit shown in Fig. 8.

[0053] The receiving circuit 180a includes a shift register consisting of FF181, FF182, and FF183, FF184, an AND circuit 185, and an OR circuit 186. FF181, FF182, FF183, and FF184 are flip-flops that capture data signals in synchronization with the rising edge of CLKR. FF181, FF182, and FF183 are set (set to "1") when SCAN_EN is enabled, and FF184 is reset (set to "0") when SCAN_EN is enabled. SO from the transmitting circuit 190a is input to FF181 as an input signal (SI).

[0054] The AND circuit 185 becomes "1" when successive "0"s followed by "1" are input as SI. The output of the AND circuit 185 is input to FF184 via the OR circuit 186, FF184 becomes "1", and WR becomes valid. After that, the output of the AND circuit 185 becomes "0", but since the output of FF184 is input to FF184 via the OR circuit 186, FF184 holds "1".

[0055] The receiving circuit 180a enables WR when it detects a "1" after successive "0s". It adjusts so that the data after the detected "1" after the successive "0s" is output as W_DATA in accordance with the cycle in which WR is enabled.

[0056] The operations of the transmission circuit 190a, the reception circuit 180a, the FIFO 150a, and the counter circuit 160a will be described with reference to FIG.

[0057] CLKT has approximately the same phase as CLKB, and CLKR has approximately the same phase as CLKA, so they are omitted. The rising timings of CLKB are t0, t2, t4, ..., t14. The rising timings of CLKA are t1, t3, t5, ..., t15. Figure 13 shows an example where the clock skew (t1-t0) between CLKB and CLKA is approximately 3 / 4 clock cycle.

[0058] The transmission circuit 190a outputs "0" at t0, "0" at t2, and "1" at t4, and then outputs "A", "B", "C", "D", and "E" as test data at t6, t8, t10, t12, and t14.

[0059] The receiving circuit 180a inputs and outputs "0" at t1, "0" at t3, and "1" at t5, and then inputs and outputs "A" at t7, "B" at t9, "C" at t11, "D" at t13, and "E" at t15. The receiving circuit 180a detects the "1" input at t5 and enables WR at t7.

[0060] The FIFO 150a writes "A" to REG_1 when WR goes active at t7. Thereafter, it writes "B" to REG_2 at t9, "C" to REG_3 at t11, and "D" to REG_4 at t13. The counter circuit 160a counts up every clock cycle after the counter register 163 becomes "1" at t1, and enables RD when the counter register 163 becomes "6" at t11.

[0061] The FIFO 150a reads "A" from REG_1 when RD is enabled at t11. Then, it reads "B" from REG_2 at t13 and "C" from REG_3 at t15. The scan chain 120a inputs "A" at t13 and "B" at t15.

[0062] In the first embodiment, a transmission circuit 190b is provided after the scan chain 120b, and a reception circuit 180a is provided before the FIFO 150a, so that writing from the scan chain 120b to the FIFO 150a can be performed normally.

[0063] [Second embodiment] The semiconductor device according to the second embodiment will be described with reference to FIG.

[0064] The semiconductor device in the second embodiment is an example in which test data is configured with a plurality of bits (N bits, N>2) and is transferred between semiconductor chips using a serializer and deserializer (SerDes).

[0065] The semiconductor device 1 includes a semiconductor chip 10a as a first semiconductor circuit and a semiconductor chip 10b as a second semiconductor circuit. The semiconductor device 1 further includes an external terminal 41 to which SCAN_IN is input, an external terminal 43 to which CLOCK is input, an external terminal 44 to which SCAN_OUT is output, and an external terminal 45 to which CS is input. SCAN_IN is data of N bits length, and there are N external terminals 41. There are N external terminals 43, and SCAN_OUT is data of N bits length. Here, N is an integer of 2 or more. The semiconductor device 1 includes an external terminal to which SCAN_EN is input, similar to the external terminal 42 of the semiconductor device shown in FIG. 1, but is omitted from the illustration.

[0066] The semiconductor chip 10a includes a scan chain 120a, a FIFO 150a, a counter circuit 160a, a setting register (S_REG) 170a as a register, and a deserializer (DES) 280a as a receiving circuit. The semiconductor chip 10a further includes a terminal 141a to which an output signal (SO) from the semiconductor chip 10b is input as an input signal (SI), a terminal 143a to which a CLOCK from the external terminal 43 is input as a CLKA, a terminal 144a to which a SCAN_OUT from the scan chain 120a is output, and a terminal 145a to which a CS from the external terminal 45 is input. There are N terminals 144a. The semiconductor chip 10a includes a terminal to which a SCAN_EN is input, similar to the external terminal 142 of the semiconductor chip shown in FIG. 1, but the illustration is omitted.

[0067] The semiconductor chip 10b includes a scan chain 120b, a serializer (SER) 290b as a transmission circuit, a terminal 141b, a terminal 143b, and a terminal 144b. SCAN_IN is input from the external terminal 41 to the terminal 141b. CLOCK is input from the external terminal 43 as CLKB to the terminal 143b. SO is output from the serializer 290b to the terminal 144b. The serializer 290b and the deserializer 280a are connected to each other via the terminal 141b and the terminal 141a by a high-speed serial interface (SIF) exceeding 1 gigabit per second (Gbps). The semiconductor chip 10b includes a terminal to which SCAN_EN is input, similar to the external terminal 142 of the semiconductor chip shown in FIG. 1, but is omitted from the illustration.

[0068] The scan chains 120a and 120b have the same configuration as the scan chains 120a and 120b shown in Fig. 8. However, N-bit data is input in parallel to the scan chains 120a and 120b in this embodiment, and is output in parallel.

[0069] FIFO 150a has the same configuration as FIFO 150a shown in Fig. 10. However, in this embodiment, N-bit data is input in parallel to FIFO 150a and output in parallel. Write system circuit 151 operates in synchronization with CLKD as a second clock signal. Read system circuit 152 operates in synchronization with CLKA.

[0070] The counter circuit 160a has the same configuration as the counter circuit 160a shown in Fig. 9. The setting register 170a has the same configuration as the setting register 170a shown in Fig. 8.

[0071] The serializer 290b converts N-bit test data (S_OUT) into a 1-bit continuous serial data signal (SO) in synchronization with CLKS as a fourth clock signal, and outputs the converted signal. CLKS is a clock signal obtained by multiplying CLKB. The deserializer 280a converts a 1-bit continuous input signal (SI) into N-bit test data (W_DATA) in synchronization with CLKD, and outputs the converted signal. CLKD is a clock signal obtained by multiplying CLKA.

[0072] The operations of the serializer 290b, the deserializer 280a, the FIFO 150a, and the counter circuit 160a will be described with reference to FIG.

[0073] The rising timings of CLKB are t0, t2, t4, ..., t22. The rising timings of CLKA are t1, t3, t5, ..., t23. An example is shown in which the clock skew (t1-t0) between CLKB and CLKA is approximately 1 / 4 clock cycle. In Figure 15, an example is shown in which CLKS is a clock signal with three times the frequency (1 / 3 the period) of CLKB. In Figure 15, an example is shown in which CLKD is a clock signal with three times the frequency (1 / 3 the period) of CLKA.

[0074] The scan chain 120b outputs “A”, “B”, “C”, …, “L” as test data at t0, t2, t4, …, t20. The serializer 290b serializes “A” for three clock cycles after one clock cycle of CLKS following the rising edge of t2. The serialized “A” is input to the deserializer 280a via the SIF.

[0075] The deserializer 280a inputs the first serialized bit of "A" at the rising edge of CLKD, and inputs the remaining two serialized bits of "A" during the next two clock cycles of CLKD to deserialize them. At a predetermined timing for deserialization, the WR is activated.

[0076] When WR goes active, the FIFO 150a writes "A" to REG1. The counter circuit 160a counts up every clock cycle when the counter register 163 goes to "1" at t1, and when the counter register 163 goes to "6" at t11, it enables RD.

[0077] The FIFO 150a reads "A" from REG_1 when RD is enabled at t11. Then, it reads "B" from REG_2 at t13 and "C" from REG_3 at t15. The scan chain 120a inputs "A" at t13 and "B" at t15.

[0078] [Third embodiment] The semiconductor device according to the third embodiment will be described with reference to FIG.

[0079] The semiconductor device in the third embodiment is an example in which test data is sent from the semiconductor chip 10b to the semiconductor chip 10a, and the test data sent to the semiconductor chip 10a is further returned to the semiconductor chip 10b.

[0080] The semiconductor chip 10a in the third embodiment further includes a serializer 290a as a transmitting device in comparison with the semiconductor chip 10a in the second embodiment. The serializer 290a is disposed between the scan chain 120a and the terminal 144a. The number of terminals 144a is one, unlike the third embodiment.

[0081] The semiconductor chip 10b in the third embodiment further includes a FIFO 150b as a buffer, a counter circuit 160b, a setting register 170b, and a deserializer (DES) 280b as a receiving circuit, in addition to the semiconductor chip 10b in the second embodiment. The semiconductor chip 10b further includes a terminal 141c to which an output signal (SO) from the semiconductor chip 10a is input as an input signal (SI), a terminal 144c to which a SCAN_OUT from the FIFO 150b is output, and a terminal 145b to which a CS from an external terminal 45 is input. The serializer 290a and the deserializer 280b are connected by a high-speed serial interface (SIF) via the terminal 144a and the terminal 141c.

[0082] The FIFO 150b has the same configuration as the FIFO 150a. The write system circuit 151 operates in synchronization with CLKS as a fourth clock signal. The read system circuit 152 operates in synchronization with CLKB.

[0083] The counter circuit 160b has a similar configuration to the counter circuit 160a. The setting register 170b has a similar configuration to the setting register 170a.

[0084] The serializer 290a converts N-bit test data (S_OUT) into a 1-bit continuous serial data signal (SO) in synchronization with CLKD as a second clock signal, and outputs the converted signal. CLKS is a clock signal obtained by multiplying CLKB. The deserializer 280b converts a 1-bit continuous input signal (SI) into N-bit test data (W_DATA) in synchronization with CLKS, and outputs the converted signal. CLKS is a clock signal obtained by multiplying CLKB.

[0085] Next, a scan test of the semiconductor device according to this embodiment will be described with reference to FIGS.

[0086] 17, the semiconductor device 1 in this embodiment includes semiconductor chips 10a and 10b, a silicon interposer 20, and a package substrate 30. The silicon interposer 20 has wiring that connects terminals of the semiconductor chip 10a and terminals of the semiconductor chip 10b, and wiring that connects terminals of the semiconductor chip 10b and the package substrate 30. On the upper surface of the package substrate 30, wiring is provided that is electrically connected to the terminals of the semiconductor chip 10b via the wiring of the silicon interposer 20. On the lower surface of the package substrate 30, a plurality of external terminals 40 that are electrically connected to the terminals of the semiconductor chip 10b are connected.

[0087] As shown in Fig. 18, the semiconductor chip 10a has a combinational circuit 110a and a scan chain 120a. The semiconductor chip 10b has a combinational circuit 110b, a scan chain 120b, and a multiplexer 130. The multiple external terminals 40 include external terminals 41, 42, 43, 44, and 45. Since other components shown in Fig. 16 are omitted in Fig. 18, the description will be given with reference to Fig. 16 as appropriate.

[0088] SCAN_IN from the test device 2 is input to N external terminals 41, and input to the scan chain 120b via N terminals 141b (see FIG. 16) of the semiconductor chip 10b. SCAN_EN from the test device 2 is input to the external terminal 42, and input to the scan chain 120b via a terminal 142b of the semiconductor chip 10b. CLOCK from the test device 2 is input to the external terminal 43, and input to the scan chain 120b via a terminal 143b (see FIG. 16) of the semiconductor chip 10b. CS from the test device 2 is input to the external terminal 45, and input to the setting register 170b via a terminal 145b (see FIG. 16) of the semiconductor chip 10b.

[0089] The output signal of the scan chain 120b is output from a terminal 144b (see FIG. 16) and input as an input signal to the scan chain 120a via a terminal 141a (see FIG. 16) of the semiconductor chip 10a. SCAN_EN input via a terminal 142b of the semiconductor chip 10b is input to the scan chain 120a via a terminal 142a of the semiconductor chip 10a. CLOCK input via a terminal 143b (see FIG. 16) of the semiconductor chip 10b is input to the scan chain 120a via a terminal 143a (see FIG. 16) of the semiconductor chip 10a.

[0090] An output signal of the scan chain 120a is output from a terminal 144a (see FIG. 16) and is output from N external terminals 44 via a terminal 141c of the semiconductor chip 10b, the deserializer 280b, the FIFO 150b, the multiplexer 130 and N terminals 144c.

[0091] The scan chain 120a of the semiconductor chip 10a is connected to the scan chain 120b of the semiconductor chip 10b, and a scan test is performed via the semiconductor chip 10b. Furthermore, the semiconductor chip 10a inputs and outputs test data via the semiconductor chip 10b, which is connected to the external terminals 40. This makes it possible to perform a scan test even when the semiconductor chip 10a does not require external terminals or when fewer terminals than the number of external terminals required for the scan test are connected to the external terminals.

[0092] Another effect of the semiconductor device 1 in the third embodiment will be described with reference to FIG.

[0093] It is also possible to perform a scan test on the semiconductor chip 10a by providing external terminals 41a, 42a, 43a, and 44a dedicated to the scan test on the semiconductor chip 10a. However, the number of external terminals 40 would increase by (2N+2) compared to this embodiment. In other words, according to this embodiment, the increase in the number of external terminals can be suppressed.

[0094] [Fourth embodiment] A semiconductor diagnostic device according to the fourth embodiment will be described with reference to FIG.

[0095] The semiconductor diagnostic device in the fourth embodiment is an example of a device for diagnosing the semiconductor device 1a configured with the semiconductor chip 10a in the third embodiment. The semiconductor diagnostic device includes a test device 2 and a second test device 3.

[0096] The second test device 3 is configured by removing the scan chain 120b and the combinational circuit 110b to be tested from the semiconductor chip 10b in the third embodiment. The second test device 3 includes external terminals 41b, 43b, 44b, 45b, 41c, and 44c corresponding to the terminals 141b, 143b, 144b, 145b, 141c, and 144c of the semiconductor chip 10b in the third embodiment. A test data output (T_D_OUT) is input from the test device 2 to the external terminal 41b, a test clock (T_CLK) is input to the external terminal 43b, and CS is input from the external terminal 45b. A test data input (T_D_IN) output from the external terminal 44c is input to the test device 2.

[0097] The semiconductor device 1a in this embodiment includes external terminals 41a, 43a, 44a, and 45a corresponding to the terminals 141a, 143a, 144a, and 145a of the semiconductor chip 10a in the third embodiment. The semiconductor device 1a is connected to the second test device 3 in the same manner as the semiconductor chips 10a and 10b in the third embodiment.

[0098] The test device 2 can test (diagnose) the semiconductor device 1a without going through the scan chain 120b of the semiconductor chip 10b in the third embodiment.

[0099] [Fifth embodiment] The semiconductor device according to the fifth embodiment will be described with reference to FIG.

[0100] The semiconductor device in the fifth embodiment is an example in which the scan chain 120a of the semiconductor chip 10a in the third embodiment is replaced with a debug interface (DBGI / F) 120d.

[0101] The semiconductor device 1 in this embodiment includes a semiconductor chip 10a as a first semiconductor circuit and a semiconductor chip 10b as a second semiconductor circuit. The semiconductor chip 10b in this embodiment has a configuration in which the scan chain 120b and the combinational circuit 110b to be tested are removed from the semiconductor chip 10b in the third embodiment.

[0102] A test data input (T_D_IN) is input from the debugger device 4 to an external terminal 41, a test clock (T_CLK) is input to an external terminal 43, and CS is input from an external terminal 45. A test data output (T_D_OUT) is output from an external terminal 44 and input to the debugger device 4.

[0103] The debugger device 4 can debug the semiconductor chip 10a without using the scan chain 120b of the semiconductor chip 10b and the scan chain 120a of the semiconductor chip 10a in the third embodiment.

[0104] Test pattern generation and diagnosis of the semiconductor device in the first embodiment will be described with reference to FIGS.

[0105] 22, the circuit data of the semiconductor device 1 includes first circuit data (1CD) 1010a and second circuit data (2CD) 1010b. The first circuit data 1010a is circuit data of the semiconductor chip 10a. The second circuit data 1010b is circuit data of the semiconductor chip 10b.

[0106] The first circuit data (1CD) 1010a includes circuit data 1120a of the scan chain 120a, circuit data 1150a of the FIFO 150a, circuit data 1160a of the counter circuit 160a, circuit data 1170a of the setting register 170a, and circuit data 1180a of the receiving circuit 180a. The circuit data 1150a and the circuit data 1180a are a module (ATPG_M) 1200a to be replaced with an ATPG model.

[0107] The second circuit data (2CD) 1010b includes circuit data 1120b of the scan chain 120b and circuit data 1190b of the transmission circuit 190b. The circuit data 1190b is a module (ATPG_M) 1200b to be replaced with an ATPG model.

[0108] 23, the test design data of the semiconductor device 1 includes first test design data (1TD) 2010a, second test design data (2TD) 2010b, and third test design data (3TD) 2010c. The first test design data (1TD) 2010a is design data for generating test patterns for the semiconductor chip 10a. The second test design data (2TD) 2010b is design data for generating test patterns for the semiconductor chip 10b. The third test design data (3TD) 2010c is design data for generating test patterns for the semiconductor device 1.

[0109] The first test design data (1TD) 2010a includes test design data 2120a for the scan chain 120a, test design data 2160a for the counter circuit 160a, test design data 2170a for the setting register 170a, and test design data 2200a for the ATPG_M 2000a.

[0110] The second test design data (2TD) 2010b includes test design data 2120b of the scan chain 120b and test design data 2200b of the ATPG_M 2000b.

[0111] As shown in FIG. 24, the ATPG_Ms 2000a and 2000b configure an N-stage shift register using N FFs (FF_1, FF_2, FF_3, . . . , FF_N).

[0112] 25, a semiconductor chip (1CHIP) 10a is manufactured based on the first circuit data 1010a (step S11a). A semiconductor chip (1CHIP) 10b is manufactured based on the second circuit data 1010b (step S11b). The semiconductor chip 10a and the semiconductor chip 10b are packaged to manufacture a semiconductor device (SD) (step S12).

[0113] The ATPG_M2000a and ATPG_M2000b of the first circuit data 1010a and the second circuit data 1010b are replaced with ATPG to generate the count number (CN) first test design data 2010a, the second test design data 2010b, and the third test design data 2010c (step S21). A test pattern (TP) is generated by a test pattern generation tool based on the first test design data 2010a, the second test design data 2010b, and the third test design data 2010c (step S22).

[0114] The semiconductor device (SD) is diagnosed by the test pattern (TP) (step S13).

[0115] The disclosure made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above-described embodiments and can be modified in various ways. [Explanation of symbols]

[0116] 100a Logic circuit (first semiconductor circuit) 120a Scan chain (first scan test circuit) 150a···FIFO (buffer) 160a···Counter circuit

Claims

1. a counter circuit configured to count in synchronization with a first clock signal and generate a read signal when the count reaches a predetermined number; a buffer configured to store test data and, when the read signal indicates a valid value, to sequentially output the test data in the order in which the test data was stored in synchronization with the first clock signal; a first scan test circuit that sequentially captures the test data output from the buffer in synchronization with the first clock signal; Semiconductor device.

2. 2. The semiconductor device according to claim 1, The counter circuit includes: a counter register that counts up, counts down, or changes regularly in a manner similar thereto in synchronization with the first clock signal; a comparator for determining whether the value of the counter register matches or does not match the predetermined number of times; having performing a counting operation when scan enable is enabled and the comparator indicates a mismatch; configured to enable the read signal when a scan enable is enabled and the comparator indicates a match; Semiconductor device.

3. 2. The semiconductor device according to claim 1, Further, the predetermined number of times has a setting register that can be set to any value from outside the semiconductor device. Semiconductor device.

4. 3. The semiconductor device according to claim 2, The buffer comprises: a plurality of registers for storing the test data; reading the test data from a register in which valid data is stored earliest among the plurality of registers in synchronization with the first clock signal when the read signal is valid; configured to write the test data to an empty register of the plurality of registers in synchronization with a second clock signal when a write signal is valid; Semiconductor device.

5. 2. The semiconductor device according to claim 1, Further, a second semiconductor circuit is provided, The first semiconductor circuit further comprises: An input terminal; a receiving circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with a second clock signal; having The second semiconductor circuit is a second scan test circuit that captures test data input from an external source in synchronization with a third clock signal; An output terminal; a transmission circuit that outputs the test data output by the second scan test circuit to the output terminal in synchronization with a fourth clock signal; having The input terminal is connected to the output terminal. Semiconductor device.

6. 6. The semiconductor device according to claim 5, the transmission circuit is configured to output a flag indicating that the next data is the beginning of the test data to the output terminal, and then sequentially output the test data output by the second scan test circuit to the output terminal; the receiving circuit is configured to detect the flag input from the input terminal, and then enable a write signal to sequentially output the test data input from the input terminal to the buffer. Semiconductor device.

7. 6. The semiconductor device according to claim 5, the first scan test circuit has an input / output of N bits (N is an integer of 2 or more); the buffer has an N-bit input / output for storing test data of the first scan test circuit; the receiving circuit is a deserializer that converts a continuous 1-bit input signal into N-bit test data and outputs the N-bit test data; the second scan test circuit has an input / output of N bits; the transmission circuit is a serializer that converts N-bit test data into continuous serial data of 1 bit and outputs the serial data, and is configured to transfer the serial data to the reception circuit via a high-speed serial I / F; Semiconductor device.

8. 6. The semiconductor device according to claim 5, The first semiconductor circuit further comprises: An output terminal; a transmission circuit that outputs the test data output by the first scan test circuit to the output terminal in synchronization with a second clock signal; The second semiconductor circuit further comprises: a counter circuit configured to count in synchronization with a third clock signal and generate a read signal when the count reaches a predetermined number; a buffer configured to store test data and sequentially output the test data in synchronization with the third clock signal when the read signal indicates a valid value; An input terminal; a receiving circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with a fourth clock signal. Semiconductor device.

9. 9. The semiconductor device according to claim 8, the first scan test circuit has an input / output of N bits (N is an integer of 2 or more); the buffer has an N-bit input / output for storing test data of the first scan test circuit; the receiving circuit is a deserializer that converts a continuous 1-bit input signal into N-bit test data and outputs the N-bit test data; the second scan test circuit has an input / output of N bits; the transmission circuit is a serializer that converts N-bit test data into a continuous signal of 1 bit and outputs the signal; The serializer is configured to transfer the 1-bit continuous signal to the deserializer via a high-speed serial I / F. Semiconductor device.

10. a counter circuit configured to count in synchronization with a first clock signal and generate a read signal when the count reaches a predetermined number; a buffer configured to store test data and, when the read signal indicates a valid value, to sequentially output the test data in the order in which it was stored in synchronization with the first clock signal; a first scan test circuit configured to sequentially take in the test data output from the buffer in synchronization with the first clock signal; an input terminal; a receiving circuit configured to sequentially write the test data input to the input terminal into the buffer in synchronization with a second clock signal; an output terminal; and a transmitting circuit configured to output the test data output by the first scan test circuit to the output terminal in synchronization with the second clock signal, A first test device; a second test device having an output terminal connected to the input terminal of the first semiconductor circuit, a transmission circuit that outputs test data input from the first test device in synchronization with a third clock signal to the output terminal in synchronization with a fourth clock signal, a counter circuit configured to count in synchronization with the third clock signal and generate a read signal when the count reaches a predetermined number, a buffer that stores test data and is configured to sequentially output the test data in synchronization with the third clock signal when the read signal indicates a valid value, an input terminal connected to the output terminal of the first semiconductor circuit, a reception circuit that sequentially writes the test data input to the input terminal to the buffer in synchronization with a fourth clock signal, and an output terminal to which the test data from the buffer is output; Equipped with Semiconductor diagnostic equipment.

11. 11. The semiconductor diagnostic device of claim 10, the first test device has an N-bit test data output, a test clock output, and an N-bit test data input; the transmission circuit is a serializer that converts N-bit test data into a continuous signal of 1 bit; the receiving circuit is a deserializer that converts a continuous 1-bit signal into N-bit test data; the buffer has an input and output of N-bit test data; the transmission circuit of the second test device is configured to transmit to the reception circuit of the first semiconductor circuit via a high-speed serial I / F; The transmission circuit of the first semiconductor circuit is configured to transmit to the reception circuit of the second test device via a high-speed serial I / F. Semiconductor diagnostic equipment.

12. a first semiconductor circuit having: a counter circuit configured to count in synchronization with a first clock signal and generate a read signal when the count reaches a predetermined number; a buffer configured to store test data and, when the read signal indicates a valid value, to sequentially output the test data in the order in which it was stored in synchronization with the first clock signal; a debug interface that sequentially takes in the test data output from the buffer in synchronization with the first clock signal; an input terminal; a receiving circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with a second clock signal; an output terminal; and a transmitting circuit that outputs the test data output by the debug interface to the output terminal in synchronization with the second clock signal; a second semiconductor circuit having an output terminal connected to the input terminal of the first semiconductor circuit, a transmitting circuit that outputs test data input from a debugging device in synchronization with a third clock signal to the output terminal in synchronization with a fourth clock signal, a counter circuit configured to count in synchronization with the third clock signal and generate a read signal when the count reaches a predetermined number, a buffer that stores test data and is configured to sequentially output the test data in synchronization with the third clock signal when the read signal indicates a valid value, an input terminal connected to the output terminal of the first semiconductor circuit, a receiving circuit that sequentially writes the test data input to the input terminal to the buffer in synchronization with a fourth clock signal, and an output terminal to which the test data from the buffer is output; A semiconductor device comprising:

13. 13. The semiconductor device of claim 12, the transmission circuit is a serializer that converts N-bit test data into a continuous signal of 1 bit; the receiving circuit is a deserializer that converts a continuous 1-bit signal into N-bit test data; the buffer has an input and output of N-bit test data; the transmitting circuit of the second semiconductor circuit is configured to transmit to the receiving circuit of the first semiconductor circuit via a high-speed serial I / F; The transmission circuit of the first semiconductor circuit is configured to transmit to the reception circuit of the second semiconductor circuit via a high-speed serial I / F. Semiconductor device.

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