Over-current protection circuit, semiconductor device, electronic apparatus, and vehicle

Abstract

To provide an over-current protection circuit capable of fast responce.SOLUTION: An over-current protection circuit (OCP1) comprises: first and second transistors (M1 and M2) that form an amplifier input stage that receives input of a detection signal corresponding to a monitoring target current; a third transistor (M3) that forms an amplifier output stage that generates a current output signal dependent on a difference between the detection signal and a reference signal and causes negative feed-back input of the current output signal to the amplifier input stage; and a current mirror circuit that generates a current limiting signal by copying a signal based on the current output signal. A gate of a source follower circuit (M21) is connected to an input end of the current mirror circuit, and the source of the source follower circuit is connected to the gates of fourth and fifth transistors (M6 and M7). First current sources (M22, M23, and CS1) generate discharge currents for discharging the gates of the fourth and fifth transistors and control the values of the discharge currents.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to an overcurrent protection circuit, a semiconductor device, an electronic device, and a vehicle. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices such as vehicle-mounted IPDs (intelligent power devices) (see, for example, Patent Document 1).

[0003] Moreover, as a related technique for an overcurrent protection circuit incorporated in a semiconductor device, for example, Patent Document 2 can be mentioned. The overcurrent protection circuit proposed in Patent Document 2 can detect an overcurrent with high accuracy. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2017 / 187785 [Patent Document 2] JP 2023-50714 A

[0005] [overview] However, the overcurrent protection circuit proposed in Patent Document 2 has room for improvement in response speed.

[0006] The overcurrent protection circuit disclosed in this specification is an overcurrent protection circuit configured to limit a monitored current based on a current limit signal, and includes a first transistor and a second transistor configured to form an amplifier input stage that receives an input of a detection signal corresponding to the monitored current, a third transistor configured to form an amplifier output stage that generates a current output signal corresponding to a difference between the detection signal and a reference signal and negatively feeds the current output signal back to the amplifier input stage, and a current mirror circuit configured to generate the current limit signal by replicating a signal based on the current output signal. The current mirror circuit includes a fourth transistor, a fifth transistor, a source follower circuit, and a first current source. The gate of the source follower circuit is connected to an input terminal of the current mirror circuit, and the source of the source follower circuit is connected to the gate of the fourth transistor and the gate of the fifth transistor. The first current source is configured to control a value of a discharge current that discharges the gate of the fourth transistor and the gate of the fifth transistor.

[0007] The semiconductor device disclosed in this specification includes an output transistor, and the overcurrent protection circuit having the above-described configuration, configured so that an output current flowing through the output transistor is the current to be monitored.

[0008] The electronic device disclosed in this specification includes the semiconductor device having the above-described configuration.

[0009] The vehicle disclosed in this specification is equipped with an electronic device having the above-described configuration. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of an electronic device according to the first embodiment. [Diagram 2] FIG. 2 is a waveform diagram for explaining the operation of the second current mirror circuit. [Diagram 3] FIG. 3 is a waveform diagram of an output current of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a waveform diagram of the output current of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing a configuration of an electronic device according to the second embodiment. [Figure 6] FIG. 6 is a state transition diagram of the semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a waveform diagram of an output current of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a diagram illustrating a first configuration example of the control circuit. [Figure 9] FIG. 9 is a diagram for explaining the operation of the control circuit shown in FIG. [Figure 10] FIG. 10 is a diagram showing a second configuration example of the control circuit. [Figure 11] FIG. 11 is a diagram for explaining the operation of the control circuit shown in FIG. [Figure 12] FIG. 12 is an external view of the vehicle.

[0011] [Detailed Description] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon having a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0012] First Embodiment Fig. 1 is a diagram showing the configuration of an electronic device according to embodiment 1. An electronic device 10A shown in Fig. 1 includes a semiconductor device 1A, a load LD1, and DC power supplies VS1 and VS2.

[0013] The semiconductor device 1A is a low-side switch IC (a type of IPD) that establishes / cuts conduction between a load LD1 and a ground potential.

[0014] The semiconductor device 1A includes terminals T1 to T5 as means for establishing electrical connection with the outside of the device.

[0015] The terminal T1 is connected to a first end of a load LD1. The second end of the load LD1 is connected to a positive terminal of a DC power supply VS1. The terminal T2 is connected to a ground potential. The terminal T3 receives an input signal IN.

[0016] The terminal T4 receives an enable signal EN. When the enable signal EN is at a high level, a control circuit 2 (described later) is turned on (operating). When the enable signal EN is at a low level, the control circuit 2 (described later) is turned off (not operating). When the enable signal EN switches from a low level to a high level, the control circuit 2 (described later) is reset to its initial state and starts operating.

[0017] The terminal T5 is connected to the positive electrode of the DC power supply VS2. The negative electrodes of the DC power supplies VS1 and VS2 are connected to the ground potential. The DC power supply VS1 outputs a voltage VCC. The DC power supply VS2 outputs a voltage VDD. The voltages VCC and VDD may be the same voltage or different voltages.

[0018] The semiconductor device 1A includes an overcurrent protection circuit OCP1, a control circuit 2, and a MOS field effect transistor M15 which is an output transistor.

[0019] The control circuit 2 is connected to the terminals T3 and T4. The control circuit 2 turns the MOS field effect transistor M15 off when the input signal IN is at a LOW level, and turns the MOS field effect transistor M15 on when the input signal IN is at a HIGH level.

[0020] The control circuit 2 has an overheat protection function, and when the temperature in the vicinity of the MOS field effect transistor M15 exceeds a predetermined value, it turns off the MOS field effect transistor M15 regardless of the level of the input signal IN.

[0021] The MOS field effect transistor M15 is an N-channel MOS field effect transistor. The drain of the MOS field effect transistor M15 is connected to the terminal T1. The source and back gate of the MOS field effect transistor M15 are connected to the terminal T2. The MOS field effect transistor M15 is connected in series to the load LD1 via the terminal T1.

[0022] The overcurrent protection circuit OCP1 monitors the output current Ip (the source current of the MOS field effect transistor M15) and protects the MOS field effect transistor M15.

[0023] The overcurrent protection circuit OCP1 includes MOS field effect transistors M1 to M7, M11 to M15, and M21 to M23, and resistors R1 and R2.

[0024] The MOS field effect transistors M11 and M12 are P-channel MOS field effect transistors. The sources and back gates of the MOS field effect transistors M11 and M12 are connected to the terminal T5.

[0025] The control circuit 2 supplies a bias voltage Bias1 to each gate of the MOS field effect transistors M11 and M12. When the input signal IN is at a high level and overheat protection is not performed, the control circuit 2 sets the bias voltage Bias1 to a low level. At this time, the MOS field effect transistors M11 and M12 each operate as a current source that outputs a reference current.

[0026] On the other hand, when at least one of the first condition that the input signal IN is at a low level and the second condition that overheat protection is being performed is satisfied, the control circuit 2 sets the bias voltage Bias1 to a high level. At this time, the drain currents of the MOS field effect transistors M11 and M12 become zero.

[0027] The MOS field effect transistors M1 to M3 are N-channel MOS field effect transistors.

[0028] The drain of the MOS field effect transistor M11 is connected to the drain and gate of the MOS field effect transistor M2 and to the gate of the MOS field effect transistor M1.

[0029] The drain of the MOS field effect transistor M12 is connected to the drain of the MOS field effect transistor M1 and to the gate of the MOS field effect transistor M3.

[0030] The source and back gate of the MOS field effect transistor M1 are connected to a first terminal of the resistor R1 and to a source and back gate of the MOS field effect transistor M14, which is an N-channel MOS field effect transistor. The second terminal of the resistor R1 is connected to the ground potential via the terminal T2.

[0031] The source and back gate of the MOS field effect transistor M2 are connected to a first end of the resistor R2 and to the source and back gate of the MOS field effect transistor M3. The second end of the resistor R2 is connected to the ground potential via the terminal T2.

[0032] The drain current of the MOS field effect transistor M3 is duplicated by a first current mirror circuit composed of P-channel MOS field effect transistors M4 and M5, and a second current mirror circuit composed of N-channel MOS field effect transistors M6, M7, M21 to M23, and a current source CS1. Therefore, the drain current of the MOS field effect transistor M13, which is a P-channel MOS field effect transistor, is a current obtained by duplicating the drain current of the MOS field effect transistor M3. The drain current of the MOS field effect transistor M13 becomes a current limiting signal for limiting the output current Ip.

[0033] The sources and back gates of the MOS field effect transistors M4, M5, M13, and M21 are connected to the terminal T5. The drain and gate of the MOS field effect transistor M4 and the gate of the MOS field effect transistor M5 are connected to the drain of the MOS field effect transistor M3.

[0034] The drain of the MOS field effect transistor M5 is connected to the gate of the MOS field effect transistor M21 and the drain of the MOS field effect transistor M6. The source and back gate of the MOS field effect transistor M21 are connected to the gates of the MOS field effect transistors M6 and M7 and the drain of the MOS field effect transistor M22. A voltage VDD is applied to a first terminal of the current source CS1. The second terminal of the current source CS1 is connected to the gate of the MOS field effect transistor M22 and the gate and drain of the MOS field effect transistor M23. The sources and back gates of the MOS field effect transistors M6, M7, M22, and M23 are connected to the ground potential via the terminal T2.

[0035] The drain of the MOS field effect transistor M7 is connected to the drain of the MOS field effect transistor M13 and to a first end of the resistor R3.

[0036] The control circuit 2 supplies a bias voltage Bias2 to the gate of the MOS field effect transistor M13. When the input signal IN is at a high level and overheat protection is not performed, the control circuit 2 sets the bias voltage Bias2 to a low level. At this time, the MOS field effect transistor M13 operates as a current source.

[0037] On the other hand, when at least one of the first condition that the input signal IN is at a low level and the second condition that overheat protection is being performed is satisfied, the control circuit 2 sets the bias voltage Bias2 to a high level. At this time, the drain current of the MOS field effect transistor M13 becomes zero.

[0038] The second end of the resistor R3 is connected to the gates of MOS field effect transistors M14 and M15.

[0039] The MOS field effect transistor M14 outputs a sense current Is corresponding to the output current Ip. The resistor R1 converts the sense current Is into a detection signal (detection voltage) S1 corresponding to the output current Ip.

[0040] The MOS field effect transistors M1 and M2 form an amplifier input stage that receives an input of a detection signal (detection voltage) S1 corresponding to the output current Ip. The MOS field effect transistor M1 receives an input of a detection signal (detection voltage) S1 corresponding to the output current Ip. The MOS field effect transistor M2 receives an input of a reference signal (reference voltage) S2.

[0041] The MOS field effect transistor M3 forms an amplifier output stage that generates a current output signal (the source current and the drain current of the MOS field effect transistor M3) S3 according to the difference between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2, and inputs the current output signal (the source current of the MOS field effect transistor M3) S3 as a negative feedback to the above-mentioned amplifier input stage. This makes it possible to apply a highly accurate output current limit.

[0042] <Details of the second current mirror circuit> To achieve a high-speed response of the overcurrent protection circuit, it is necessary to shorten the startup time of the high-current gain current mirror circuit provided in the overcurrent protection circuit. Note that when the gain of the current mirror circuit is reduced, the reference current needs to be increased, which increases the current consumption of the overcurrent protection circuit and narrows the operating range of the amplifier provided in the front stage of the current mirror circuit.

[0043] Therefore, the overcurrent protection circuit OCP1 realizes a high-speed response by setting the total gain of the first current mirror circuit and the second current mirror circuit to a high current gain, setting the first current mirror circuit to a lower gain than the second current mirror circuit (for example, a current amplification factor of 1, i.e. a mirror ratio of 1:1), and configuring the second current mirror circuit to be capable of high-speed response.

[0044] The second current mirror circuit can supply a charging current to the gates of the MOS field effect transistors M6 and M7 by the MOS field effect transistor M21, which is a source follower circuit, and therefore can reduce the start-up time.

[0045] In the second current mirror circuit, the value of the discharge current that discharges each gate of the MOS field effect transistors M6 and M7 is controlled by a current source constituted by the current source CS1 and the MOS field effect transistors M22 and M23, so that the behavior (waveform) of the output current Ip when the output current Ip is limited can be controlled to a desired behavior (waveform).

[0046] Fig. 2 is a waveform diagram for explaining the operation of the second current mirror circuit. In Fig. 2, from the top, a waveform diagram of the gate voltage V1 of the MOS field effect transistor M21, a waveform diagram of the drain current Ids_M21 of the MOS field effect transistor M21, a waveform diagram of the gate voltage V2 of the MOS field effect transistors M6 and M7, a waveform diagram of the drain current Ids_M22 of the MOS field effect transistor M22, and a waveform diagram of the drain current Ids_M6 of the MOS field effect transistor M6 are depicted.

[0047] When the reference current (the drain current of the MOS field effect transistor M5) Iref increases due to the activation of the overcurrent protection circuit OCP1, the gate voltage V1 of the MOS field effect transistor M21 also increases.

[0048] Following the rise in the gate voltage V1 of the MOS field effect transistor M21, the drain current Ids_M21 of the MOS field effect transistor M21 starts to flow, which causes the MOS field effect transistor M21 to start charging the gates of the MOS field effect transistors M6 and M7, causing the gate voltage V2 of the MOS field effect transistors M6 and M7 to rise.

[0049] When the gate voltage V2 of the MOS field effect transistors M6 and M7 rises and the gate-source voltage of the MOS field effect transistor M6 exceeds the threshold voltage, the drain current Ids_M6 of the MOS field effect transistor M6 starts to flow.

[0050] Thereafter, when the gate voltage V2 of the MOS field effect transistors M6 and M7 further increases and exceeds the operating point, the MOS field effect transistor M6 lowers the gate voltage V1 of the MOS field effect transistor M21 in order to keep the drain current Ids_M6 of the MOS field effect transistor M6 at the steady value of the reference current Iref.

[0051] When the gate voltage V1 of the MOS field effect transistor M21 decreases, the charging current through the MOS field effect transistor M21 decreases, and the current Ibias (the drain current Ids_M22 of the MOS field effect transistor M22) corresponding to the discharging current becomes dominant over the charging current, so that the gate voltage V2 of the MOS field effect transistors M6 and M7 also decreases.

[0052] Thereafter, when the gate voltage V2 of the MOS field effect transistors M6 and M7 further drops below the operating point, the MOS field effect transistor M6 increases the gate voltage V1 of the MOS field effect transistor M21 in order to keep the drain current Ids_M6 of the MOS field effect transistor M6 at the steady value of the reference current Iref.

[0053] When the gate voltage V1 of the MOS field effect transistor M21 increases, the charging current through the MOS field effect transistor M21 increases and becomes dominant over the current Ibias (the drain current Ids_M22 of the MOS field effect transistor M22) corresponding to the discharging current, so that the gate voltage V2 of the MOS field effect transistors M6 and M7 also increases.

[0054] Thereafter, the gate voltage V1 of the MOS field effect transistor M21 and the gate voltage V2 of the MOS field effect transistors M6 and M7 repeatedly rise and fall, and converge to an operating point.

[0055] The rate at which the gate voltage V2 of the MOS field effect transistors M6 and M7 drops depends on the control value of the drain current Ids_M22 of the MOS field effect transistor M22, which is determined by the setting value of the output current of the current source CS1.

[0056] When the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is large, the time it takes for the gate voltage V2 to transition from rising to falling becomes shorter and the rate of change of the gate voltage V2 when it falls becomes larger, resulting in a smaller overshoot of the gate voltage V2 of the MOS field effect transistors M6 and M7. On the other hand, when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is small, the time it takes for the gate voltage V2 to transition from rising to falling becomes longer and the rate of change of the gate voltage V2 when it falls becomes smaller, resulting in a larger overshoot of the gate voltage V2 of the MOS field effect transistors M6 and M7.

[0057] After the output current Ip reaches a start value, the overcurrent protection circuit OCP1 limits the output current Ip so that it converges to a limit value smaller than the start value.

[0058] Therefore, for example, when the difference between the start value and the limit value is large as shown in Fig. 3, it is desirable to set the control value of the drain current Ids_M22 of the MOS field effect transistor M22 small so as to prioritize reducing the output current Ip to the limit value as soon as possible in order to suppress heat generation in the MOS field effect transistor M15, which is the output transistor. With such a setting, the discharge current that discharges the gate of the MOS field effect transistor M15 becomes large, so that the ringing of the output current Ip becomes large, but the time required to reduce the output current Ip from the start value to the limit value can be shortened. On the other hand, when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is set large, the ringing of the output current Ip becomes small, but the time required to reduce the output current Ip from the start value to the limit value becomes long.

[0059] In Fig. 3, the waveform of the output current Ip when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is set small is depicted by a thick solid line, and in Fig. 3, the waveform of the output current Ip when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is set large is depicted by a thin solid line.

[0060] For example, as shown in Fig. 4, when the difference between the start value and the limit value is small, it is desirable to set the control value of the drain current Ids_M22 of the MOS field effect transistor M22 large so as to prioritize the convergence of the output current Ip to the limit value quickly. With such a setting, the discharge current that discharges the gate of the MOS field effect transistor M15 becomes small, so that the time required to reduce the output current Ip from the start value to the limit value becomes long, but the ringing of the output current Ip becomes small. On the other hand, when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is set small, the time required to reduce the output current Ip from the start value to the limit value can be shortened, but the ringing of the output current Ip becomes large.

[0061] In Fig. 4, the waveform of the output current Ip when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is set small is depicted by a thick solid line, as in Fig. 3. Also, in Fig. 4, the waveform of the output current Ip when the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is set large is depicted by a thin solid line, as in Fig. 3.

[0062] <Second embodiment> Fig. 5 is a diagram showing the configuration of an electronic device according to a second embodiment. An electronic device 10B shown in Fig. 5 includes a semiconductor device 1B, a load LD1, and DC power supplies VS1 and VS2. In this embodiment, the load LD1 is a capacitive load such as a bulb lamp.

[0063] The semiconductor device 1B has a configuration in which the overcurrent protection circuit OCP1 in the semiconductor device 1A is replaced with an overcurrent protection circuit OCP2.

[0064] The overcurrent protection circuit OCP2 has a configuration in which MOS field effect transistors M31 to M34, a resistor R4, an inverter 3, and a latch circuit 4 are added to the overcurrent protection circuit OCP1.

[0065] The MOS field effect transistors M31 to M33 are N-channel MOS field effect transistors. The MOS field effect transistor M34 is a P-channel MOS field effect transistor.

[0066] When the enable signal EN is at a high level, the latch circuit 4 is in an on state (operating state). When the enable signal EN is at a low level, the latch circuit 4 is in an off state (non-operating state). When the enable signal EN switches from a low level to a high level, the latch circuit 4 is in an initial state and starts operating.

[0067] The source and back gate of the MOS field effect transistor M34 are connected to the terminal T5. The control circuit 2 supplies a bias voltage Bias1 to the gate of the MOS field effect transistor M34.

[0068] The drain of the MOS field effect transistor M34 is connected to the drain of the MOS field effect transistor M31 and the input terminal of the inverter 3. The gate of the MOS field effect transistor M31 is connected to the drain of the MOS field effect transistor M12, the drain of the MOS field effect transistor M1, and the gate of the MOS field effect transistor M3. The output signal of the inverter 3 is supplied to the latch circuit 4.

[0069] The second end of the resistor R2 is connected to the ground potential via the resistor R4 and the terminal T2. The second end of the resistor R2 and the first end of the resistor R4 are connected to the drain of the MOS field effect transistor M33. The second end of the resistor R4 is connected to the source and back gate of the MOS field effect transistor M33. The output of the latch circuit 4 is supplied to the gate of the MOS field effect transistor M33. The circuit formed by the resistors R2 and R4 and the MOS field effect transistor M33 is a variable resistor whose resistance value changes depending on whether the MOS field effect transistor M33 is on or off.

[0070] The source and back gate of the MOS field effect transistor M31 are connected to the ground potential via the terminal T2.

[0071] A MOS field effect transistor M32 is connected in parallel to the MOS field effect transistor M6. The output of the latch circuit 4 is supplied to the gate of the MOS field effect transistor M32.

[0072] The MOS field effect transistor M31 outputs a comparison result S4 between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2.

[0073] In the detection mode, the overcurrent protection circuit OCP2 determines whether the output current Ip, which is a current to be monitored, exceeds a first start value, and in the limit mode, determines whether the output current Ip exceeds a second start value that is smaller than the first start value. In the detection mode, the overcurrent protection circuit OCP2 does not limit the output current Ip. In the limit mode, the overcurrent protection circuit OCP2 limits the output current Ip to a limit value when the output current Ip exceeds the second start value. The overcurrent protection circuit OCP2 is in the detection mode in the initial state (when the semiconductor device 1B is started up or reset). Therefore, the state of the semiconductor device 1B transitions as shown in FIG. 6.

[0074] The overcurrent protection circuit OCP2 switches the start value in two stages.

[0075] Here, the operation of the overcurrent protection circuit OCP2 when switching from the detection mode to the limit mode will be described.

[0076] In the detection mode, if the sense current Is increases, the detection signal (detection voltage) S1 also increases. If the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2 approximately match, the comparison result S4 switches from HIGH level to LOW level, the MOS field effect transistor M33 turns on, and the reference signal (reference voltage) S2 tends to decrease. However, since the current output signal S3 is negatively fed back to the amplifier input stage, the reference signal (reference voltage) S2 tends to increase when the MOS field effect transistor M3 is on. Due to the balance between the two, the reference signal (reference voltage) S2 decreases while maintaining an approximately match state between the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2.

[0077] At this time, since the MOS field effect transistor M7 is half-on, the gate potentials of the MOS field effect transistors M14 and M15 decrease, and the sense current IS and the detection signal (detection voltage) S1 also decrease. Since the detection signal (detection voltage) S1 is negatively fed back to the amplifier input stage, the gate potentials of the MOS field effect transistors M14 and M15 are controlled so that the detection signal (detection voltage) S1 and the reference signal (reference voltage) S2 are approximately equal to each other.

[0078] The overcurrent protection circuit OCP2 tolerates rush current in detection mode, but after the rush current exceeds the tolerance range due to a load short circuit or the like, it can limit the current to a low current lower than the rush current in limit mode, while also preventing an increase in circuit size.

[0079] As shown in FIG. 7, since the difference between the first start value and the limit value is large, it is desirable to set the control value of the drain current Ids_M22 of the MOS field effect transistor M22 small immediately after switching from the detection mode to the limit mode.

[0080] On the other hand, since the difference between the second start value and the limit value is small as shown in FIG. 7, once the output current Ip converges to the limit value in the limit mode, it is desirable to set the control value of the drain current Ids_M22 of the MOS field effect transistor M22 to a large value.

[0081] Therefore, in this embodiment, the current source constituted by the current source CS1 and the MOS field effect transistors M22 and M23 is configured to vary the control value of the drain current Ids_M22 of the MOS field effect transistor M22. Specifically, the output current value of the current source CS1 is configured to be variable.

[0082] <First control example> In a first control example of a current source configured by a current source CS1 and MOS field effect transistors M22 and M23, a control value of the drain current Ids_M22 of the MOS field effect transistor M22 is varied based on a comparison result S4. Specifically, an output current value of the current source CS1 is varied based on the comparison result S4.

[0083] In a first control example of a current source constituted by the current source CS1 and the MOS field effect transistors M22 and M23, the overcurrent protection circuit OCP2 includes a control circuit shown in FIG. 8, for example.

[0084] The control circuit shown in Fig. 8 includes MOS field effect transistors M41 to M46 and a capacitor C1. The control circuit shown in Fig. 8 charges the capacitor C1 using the output of the latch circuit 4, which is a signal based on the comparison result S4, generates a signal DLY according to the charge amount of the capacitor C1, generates a control signal CNT using the signal DLY, and supplies the control signal CNT to a current source CS1. The control signal CNT is a delayed signal of the signal based on the comparison result S4.

[0085] The waveforms of the output of the latch circuit 4, the signal DLY, and the control signal CNT are as shown in FIG. 9, for example.

[0086] <Second control example> In a second control example of a current source constituted by the current source CS1 and the MOS field effect transistors M22 and M23, the control value of the drain current Ids_M22 of the MOS field effect transistor M22 is varied based on a signal (thermal protection detection signal) indicating that the monitored temperature (for example, the ambient temperature of the output transistor M15) has exceeded a predetermined value. Specifically, the output current value of the current source CS1 is varied based on the thermal protection detection signal.

[0087] In a second control example of a current source constituted by the current source CS1 and the MOS field effect transistors M22 and M23, the overcurrent protection circuit OCP2 includes a control circuit shown in FIG. 10, for example.

[0088] The control circuit shown in Fig. 10 includes a latch circuit 5. The control circuit shown in Fig. 10 latches the thermal protection detection signal to generate a control signal CNT, and supplies the control signal CNT to the current source CS1.

[0089] The waveforms of the thermal protection detection signal and the control signal CNT are as shown in FIG. 11, for example.

[0090] <Application to vehicles> 12 is an external view showing one configuration example of a vehicle. The vehicle X of this configuration example is equipped with various load driving devices that operate by receiving power supply from a battery.

[0091] The vehicle X includes not only engine vehicles but also electric vehicles (xEVs such as BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0092] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0093] The electronic device X11 is an electronic control unit that performs engine-related control (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related control (such as torque control and power regeneration control).

[0094] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamps) and DRL (daytime running lamps).

[0095] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0096] The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0097] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0098] The electronic device X16 is an electronic device that is installed in the vehicle X at the factory as a standard equipment or a manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0099] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0100] The electronic device X18 is an electronic device equipped with a high-voltage resistant motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0101] The electronic device 10A described above can be understood as any of the electronic devices X11 to X18. That is, the semiconductor device 1A described above can be incorporated into any of the electronic devices X11 to X18. The electronic device 10B described above can be understood as any of the electronic devices X11 to X18 that has a capacitive load. That is, the semiconductor device 1B described above can be incorporated into any of the electronic devices X11 to X18 that has a capacitive load.

[0102] <Other> The embodiments of the present disclosure may be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The various embodiments described above may be combined as appropriate within a range that does not cause inconsistency. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments.

[0103] For example, in the above embodiment, an example of application to a low-side switch IC has been given, but the same circuit configuration as in the above embodiment can also be applied to a high-side switch IC.

[0104] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0105] The overcurrent protection circuits (OCP1, OCP2) disclosed herein are overcurrent protection circuits configured to limit a monitored current based on a current limit signal, and include a first transistor (M1) and a second transistor (M2) configured to form an amplifier input stage that receives an input of a detection signal corresponding to the monitored current, a third transistor (M3) configured to form an amplifier output stage that generates a current output signal corresponding to a difference between the detection signal and a reference signal and negatively feeds back the current output signal to the amplifier input stage, and a third transistor (M4) configured to generate the current limit signal by duplicating a signal based on the current output signal. and a current mirror circuit configured to control a value of a discharge current that discharges the gate of the fourth transistor and the gate of the fifth transistor, the current mirror circuit including a fourth transistor (M6), a fifth transistor (M7), a source follower circuit (M21), and a current source (M22, M23, CS1), the gate of the source follower circuit being connected to an input terminal of the current mirror circuit, the source of the source follower circuit being connected to the gate of the fourth transistor and the gate of the fifth transistor, and the current source being configured to control a value of a discharge current that discharges the gate of the fourth transistor and the gate of the fifth transistor (first configuration).

[0106] According to the overcurrent protection circuit of the first configuration described above, a charging current can be supplied to the gate of the fourth transistor and the gate of the fifth transistor by the source follower circuit, so that the start-up time of the current mirror circuit can be shortened, thereby enabling a high-speed response.

[0107] Furthermore, according to the overcurrent protection circuit of the first configuration described above, the value of the discharge current that discharges the gate of the fourth transistor and the gate of the fifth transistor is controlled by the current source, so that the behavior (waveform) of the monitored current when the monitored current is limited can be controlled to a desired behavior (waveform).

[0108] In the overcurrent protection circuit of the first configuration described above, the current to be monitored may be limited so as to converge to a limit value smaller than the start value after the current to be monitored reaches a start value (second configuration).

[0109] In the overcurrent protection circuit of the second configuration, the start value may be switched (third configuration).

[0110] The overcurrent protection circuit of the third configuration may further include a sixth transistor (M31) configured to output a comparison result between the detection signal and the reference signal, and the value of the reference signal may be switched based on the comparison result (fourth configuration).

[0111] In the overcurrent protection circuit of the fourth configuration, the first current source may be configured to vary the discharge current based on a result of the comparison (fifth configuration).

[0112] In the overcurrent protection circuit of the fifth configuration, the first current source may be configured to vary the discharge current based on a delayed signal of a signal based on the comparison result (sixth configuration).

[0113] In the overcurrent protection circuit of the fifth configuration described above, the first current source may be configured to vary the discharge current based on a signal indicating that the monitored temperature has exceeded a predetermined value (seventh configuration).

[0114] In the overcurrent protection circuit of any of the above fourth to seventh configurations, a first main electrode of the first transistor is connected to a control electrode of each of the third transistor and the sixth transistor, a first main electrode of the second transistor is connected to a control electrode of each of the first transistor and the second transistor, a first main electrode of the third transistor is connected to an output node of the current output signal, a second main electrode of the first transistor is connected to an application terminal of the detection signal, a second main electrode of the second transistor is connected to a second main electrode of the third transistor, and a first main electrode of the sixth transistor is connected to a first potential node (eighth configuration).

[0115] In the overcurrent protection circuit of the above-mentioned eighth configuration, a configuration (ninth configuration) may be provided further including a second current source (M12) connected between a second potential node and the first main electrode of the first transistor and configured to generate a reference current, and a third current source (M11) connected between the second potential node and the first main electrode of the second transistor and configured to generate the reference current.

[0116] The overcurrent protection circuit of the above-mentioned eighth configuration may further include a fixed resistor (R1) configured to be connected between the second main electrode of the first transistor and the first potential node, and a variable resistor (R2, R2, M33) configured to be connected between the second main electrode of the second transistor and the first potential node (tenth configuration).

[0117] The overcurrent protection circuit of the above-mentioned 10th configuration may further include a latch circuit (4) configured to latch the comparison result, and the resistance value of the variable resistor may be configured to be variable based on the output of the latch circuit (11th configuration).

[0118] The semiconductor device (1A, 1B) of the present disclosure has a configuration (12th configuration) including an output transistor (M15) and an overcurrent protection circuit of any of the first to eleventh configurations, configured so that the output current flowing through the output transistor is the current to be monitored.

[0119] In the semiconductor device of the twelfth configuration above, the overcurrent protection circuit may be configured to limit the output current by controlling a drive signal of the output transistor based on the current output signal (thirteenth configuration).

[0120] The electronic device (10A, 10B) of the present disclosure has a configuration (14th configuration) including the semiconductor device of the twelfth or thirteenth configuration.

[0121] A vehicle (X) of the present disclosure has a configuration (15th configuration) including the electronic device of the above 14th configuration. [Explanation of symbols]

[0122] 1A, 1B Semiconductor device 2. Control circuit 3 Inverter 4, 5 Latch circuit 10A, 10B electronic equipment C1 Capacitor LD1 load M1~M7, M11~M15, M21~23, M31~M34, M41~46 MOS field effect transistors OCP1, OCP2 Overcurrent protection circuit R1~R4 resistance T1~T5 terminals VS1, VS2 DC power supply X Vehicle X11~X18 Electronic equipment

Claims

1. 1. An overcurrent protection circuit configured to limit a monitored current based on a current limit signal, comprising: a first transistor and a second transistor configured to form an amplifier input stage that receives an input of a detection signal corresponding to the monitored current; a third transistor configured to form an amplifier output stage that generates a current output signal corresponding to a difference between the detection signal and a reference signal and negatively feeds the current output signal back to the amplifier input stage; a current mirror circuit configured to generate the current limit signal by replicating a signal based on the current output signal; Equipped with the current mirror circuit includes a fourth transistor, a fifth transistor, a source follower circuit, and a first current source; a gate of the source follower circuit is connected to an input terminal of the current mirror circuit, and a source of the source follower circuit is connected to a gate of the fourth transistor and a gate of the fifth transistor; The first current source is configured to control a value of a discharge current that discharges a gate of the fourth transistor and a gate of the fifth transistor.

2. 2. The overcurrent protection circuit of claim 1, wherein after the monitored current reaches a start value, the monitored current is limited to converge to a limit value that is less than the start value.

3. The overcurrent protection circuit of claim 2 , wherein the starting value toggles.

4. a sixth transistor configured to output a comparison result between the detection signal and the reference signal; The overcurrent protection circuit of claim 3 , wherein the value of the reference signal is configured to switch based on the comparison result.

5. 5. The overcurrent protection circuit according to claim 4, wherein the first current source is configured to vary the discharge current based on a result of the comparison.

6. 6. The overcurrent protection circuit according to claim 5, wherein the first current source is configured to vary the discharge current based on a delayed signal of a signal based on the comparison result.

7. 6. The overcurrent protection circuit according to claim 5, wherein the first current source is configured to vary the discharge current based on a signal indicating that the monitored temperature has exceeded a predetermined value.

8. a first main electrode of the first transistor is connected to a control electrode of each of the third transistor and the sixth transistor; a first main electrode of the second transistor is connected to a control electrode of each of the first transistor and the second transistor; a first main electrode of the third transistor is connected to an output node of the current output signal; a second main electrode of the first transistor is connected to an application terminal of the detection signal; a second main electrode of the second transistor is connected to a second main electrode of the third transistor; 5. The overcurrent protection circuit according to claim 4, wherein a first main electrode of the sixth transistor is connected to a first potential node.

9. a second current source connected between a second potential node and the first main electrode of the first transistor and configured to generate a reference current; a third current source connected between the second potential node and the first main electrode of the second transistor and configured to generate the reference current; 9. The overcurrent protection circuit of claim 8, further comprising:

10. a fixed resistor configured to be connected between the second main electrode of the first transistor and the first potential node; a variable resistor configured to be connected between the second main electrode of the second transistor and the first potential node; 9. The overcurrent protection circuit of claim 8, further comprising:

11. a latch circuit configured to latch the comparison result; 11. The overcurrent protection circuit according to claim 10, wherein the resistance value of the variable resistor is variable based on an output of the latch circuit.

12. An output transistor; The overcurrent protection circuit according to any one of claims 1 to 11, configured to set an output current flowing through the output transistor as the current to be monitored; A semiconductor device comprising:

13. 13. The semiconductor device according to claim 12, wherein the overcurrent protection circuit is configured to limit the output current by controlling a drive signal of the output transistor based on the current output signal.

14. An electronic device comprising the semiconductor device according to claim 12.

15. A vehicle comprising the electronic device according to claim 14.

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