Semiconductor chip and semiconductor package

Abstract

To provide a semiconductor chip capable of ensuring connection strength with a die pad.SOLUTION: A semiconductor chip (100) includes a first surface (100a) and a second surface (100b). The second surface is the surface opposite to the first surface in the thickness direction of the semiconductor chip. A hole is formed in the second surface, extending toward the first surface along the thickness direction.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to semiconductor chips and semiconductor packages. [Background technology]

[0002] For example, JP 2021-141258 A (Patent Document 1) describes a semiconductor light-emitting element. The semiconductor light-emitting element described in Patent Document 1 has a first surface and a second surface. The first surface and the second surface are both end surfaces in the thickness direction of the semiconductor light-emitting element described in Patent Document 1. The semiconductor light-emitting element described in Patent Document 1 has a substrate, a semiconductor laminated structure, a first electrode, and a second electrode. The substrate forms the second surface. The semiconductor laminated structure is disposed on the substrate. The first electrode and the second electrode are disposed on the first surface and the second surface, respectively. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141258 A [Summary] The semiconductor light-emitting element described in Patent Document 1 is connected to a die pad using an adhesive so that the second electrode faces the die pad. However, the connection strength between the semiconductor light-emitting element described in Patent Document 1 and the die pad may be insufficient.

[0004] The semiconductor chip according to the present disclosure has a first surface and a second surface. The second surface is the surface opposite to the first surface in the thickness direction of the semiconductor chip. A hole is formed in the second surface, extending toward the first surface along the thickness direction. [Brief description of the drawings]

[0005] [Figure 1] FIG. 2 is a plan view of the semiconductor chip 100. [Diagram 2] 2 is a bottom view of the semiconductor chip 100. FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 11 is a bottom view of the semiconductor chip 100 according to the first modified example. [Diagram 5] FIG. 11 is a bottom view of the semiconductor chip 100 according to the second modification. [Figure 6] 11 is a cross-sectional view of a semiconductor chip 100 according to a third modified example. FIG. [Figure 7] 11 is a cross-sectional view of a semiconductor chip 100 according to a fourth modified example. FIG. [Figure 8] FIG. 2 is a plan view of a semiconductor package 200. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 8. [Figure 10] FIG. 2 is a cross-sectional view of a semiconductor chip 100A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Detailed Description] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are given the same reference symbols, and duplicated descriptions will not be repeated. The semiconductor chip according to the embodiment is a semiconductor chip 100, and the semiconductor package according to the embodiment is a semiconductor package 200.

[0007] (Configuration of semiconductor chip 100) The configuration of the semiconductor chip 100 will be described below.

[0008] FIG. 1 is a plan view of the semiconductor chip 100. FIG. 2 is a bottom view of the semiconductor chip 100. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. As shown in FIGS. 1, 2, and 3, the semiconductor chip 100 is, for example, an LED (Light Emitting Diode). However, the semiconductor chip 100 is not limited to this. The semiconductor chip 100 may be, for example, a phototransistor or a diode.

[0009] The semiconductor chip 100 has a first surface 100a and a second surface 100b. The first surface 100a and the second surface 100b are both end surfaces in the thickness direction of the semiconductor chip 100. The second surface 100b is the surface opposite the first surface 100a in the thickness direction of the semiconductor chip 100. The semiconductor chip 100 further has a side surface 100c. The side surface 100c is continuous with the first surface 100a and the second surface 100b.

[0010] The semiconductor chip 100 includes a substrate 10 , an epitaxial layer 20 , an electrode 30 and an electrode 31 .

[0011] The substrate 10 has a first surface 10a and a second surface 10b. The first surface 10a and the second surface 10b are both end surfaces of the substrate 10 in the thickness direction. The second surface 10b is the surface opposite to the first surface 10a in the thickness direction of the substrate 10. The second surface 100b is formed of the substrate 10. More specifically, the second surface 100b is formed of the second surface 10b. The substrate 10 is formed of a single crystal semiconductor material. The conductivity type of the substrate 10 is, for example, n-type.

[0012] The epitaxial layer 20 is disposed on the substrate 10. More specifically, the epitaxial layer 20 is disposed on the first surface 10a. The epitaxial layer 20 is formed by epitaxially growing n-type or p-type semiconductor layers in sequence on the substrate 10. The epitaxial layer 20 has a light emitting layer.

[0013] A hole 100d is formed in the second surface 100b. The hole 100d extends toward the first surface 100a along the thickness direction of the semiconductor chip 100. In a plan view (when viewed from the second surface 100b side along the normal direction of the second surface 100b), the hole 100d is, for example, circular.

[0014] The depth of the hole 100d is defined as depth D. The depth D is the distance between the second surface 100b and the bottom of the hole 100d in the thickness direction of the semiconductor chip 100. The thickness of the semiconductor chip 100 is defined as thickness T. The thickness T is the distance between the first surface 100a and the second surface 100b in the thickness direction of the semiconductor chip 100. The depth D is preferably 0.5 times or less than the thickness T. The bottom of the hole 100d is in the substrate 10. From another perspective, the hole 100d does not penetrate the substrate 10. The opening width of the hole 100d is constant, for example, regardless of the position in the thickness direction of the semiconductor chip 100. From another perspective, the hole 100d is cylindrical.

[0015] The electrode 30 is disposed on the first surface 100a. The electrode 31 is disposed on the second surface 100b (second surface 10b). The electrodes 30 and 31 are made of a conductive material such as a metal material. The electrodes 30 and 31 are electrically connected to the epitaxial layer 20 and the substrate 10, respectively.

[0016] <Variation 1> Fig. 4 is a bottom view of the semiconductor chip 100 according to Modification 1. As shown in Fig. 4, the hole 100d may be, for example, rectangular in plan view. That is, in the semiconductor chip 100, the planar shape of the hole 100d is not particularly limited.

[0017] <Variation 2> Fig. 5 is a bottom view of the semiconductor chip 100 according to the second modification. As shown in Fig. 5, the number of holes 100d may be more than one. The multiple holes 100d are arranged, for example, in a lattice pattern in a plan view. However, the arrangement of the holes 100d is not limited to this. Thus, in the semiconductor chip 100, the number and arrangement of the holes 100d are not particularly limited.

[0018] <Modification 3 and Modification 4> Fig. 6 is a cross-sectional view of the semiconductor chip 100 according to Modification 3. Fig. 7 is a cross-sectional view of the semiconductor chip 100 according to Modification 4. Figs. 6 and 7 show cross sections at positions corresponding to Fig. 3. As shown in Figs. 6 and 7, the opening width of the hole 100d may vary depending on the position in the thickness direction of the semiconductor chip 100. The opening width of the hole 100d may increase with increasing distance from the second surface 100b in the thickness direction of the semiconductor chip 100 (see Fig. 6), or may decrease with increasing distance from the second surface 100b in the thickness direction of the semiconductor chip 100 (see Fig. 7).

[0019] (Configuration of semiconductor package 200) The configuration of the semiconductor package 200 will be described below.

[0020] Fig. 8 is a plan view of the semiconductor package 200. Note that the reflector 70 and the sealing resin 80 are omitted in Fig. 8. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 8. As shown in Figs. 8 and 9, the semiconductor package 200 has a semiconductor chip 100, a substrate 40, an adhesive 50, bonding wires 60, a reflector 70, and a sealing resin 80.

[0021] The substrate 40 has a base material 41, a conductor pattern 42, a conductor pattern 43, a conductor pattern 44, a conductor pattern 45, a conductor layer 46, and a conductor layer 47. The base material 41 has a first surface 41a and a second surface 41b. The first surface 41a and the second surface 41b are both end surfaces in the thickness direction of the base material 41. The material constituting the base material 41 is an insulating material. The base material 41 is composed of, for example, reinforcing fibers and a resin material impregnated into the reinforcing fibers. The resin material is, for example, BT (bismaleimide triazine) resin.

[0022] Through holes 41c and 41d are formed in the base material 41. The through holes 41c and 41d penetrate the base material 41 in the thickness direction. The through holes 41c and 41d are disposed at both ends in the longitudinal direction of the base material 41 when viewed from the first surface 41a side along the normal direction of the first surface 41a.

[0023] The conductor pattern 42 and the conductor pattern 43 are disposed on the first surface 41a. The conductor pattern 42 has a die pad 42a. The conductor pattern 42 extends along the longitudinal direction of the substrate 41 from the die pad 42a to reach the through hole 41c. The conductor pattern 43 is spaced apart from the conductor pattern 42 (die pad 42a) in the longitudinal direction of the substrate 41. The conductor pattern 43 extends along the longitudinal direction of the substrate 41 to reach the through hole 41d.

[0024] The conductor patterns 44 and 45 are disposed on the second surface 41b. The conductor patterns 44 and 45 are spaced apart in the longitudinal direction of the base material 41. The conductor layers 46 and 47 are disposed on the inner wall surfaces of the through holes 41c and 41d, respectively. The conductor patterns 44 are connected to the conductor patterns 42 by the conductor layer 46. The conductor patterns 45 are connected to the conductor patterns 43 by the conductor layer 47. The constituent materials of the conductor patterns 42, 43, 44, 45, conductor layers 46 and 47 are, for example, copper or a copper alloy.

[0025] The semiconductor chip 100 is disposed on the die pad 42a so that the electrode 31 faces the die pad 42a. The adhesive 50 is interposed between the electrode 31 and the die pad 42a. The adhesive 50 is, for example, a conductive adhesive. Therefore, the electrode 31 and the die pad 42a are electrically connected by the adhesive 50. The adhesive 50 also penetrates into the hole 100d. More specifically, the adhesive 50 is also adhered to the inner wall surface of the hole 100d. The adhesive 50 is also adhered to the side surface 100c. However, the adhesive 50 is located below the epitaxial layer 20 (at a position close to the second surface 100b). From another perspective, the die pad 42a is not electrically connected to the epitaxial layer 20 by the adhesive 50, and the adhesive 50 does not cover the light emitting layer exposed from the side surface 100c.

[0026] The bonding wire 60 is connected at one end to the electrode 30 and at the other end to the conductor pattern 43. Thus, the semiconductor chip 100 is electrically connected to the conductor pattern 43. The bonding wire 60 is made of, for example, gold. The reflector 70 is disposed on the first surface 41a. When viewed from the first surface 41a side along the normal direction of the first surface 41a, the reflector 70 is disposed along the outer periphery of the first surface 41a. The reflector 70 is formed of a material that reflects light generated in the semiconductor chip 100.

[0027] The sealing resin 80 is filled in a space defined by the base material 41 and the reflector 70. The sealing resin 80 seals the conductor patterns 42 and 43, the semiconductor chip 100, the adhesive 50, and the bonding wires 60. The sealing resin 80 is made of a transparent resin that transmits light generated in the semiconductor chip 100. The semiconductor package 200 does not need to have the reflector 70. In that case, the sealing resin 80 is disposed on the first surface 41a so as to seal the conductor patterns 42 and 43, the semiconductor chip 100, the adhesive 50, and the bonding wires 60.

[0028] (Effects of semiconductor chip 100) The effects of the semiconductor chip 100 will be described below in comparison with a semiconductor chip according to a comparative example, which is referred to as a semiconductor chip 100A.

[0029] Fig. 10 is a cross-sectional view of the semiconductor chip 100A. As shown in Fig. 10, the semiconductor chip 100A has no hole 100d formed in the second surface 100b. Except for this, the configuration of the semiconductor chip 100A is the same as the configuration of the semiconductor chip 100.

[0030] In the semiconductor chip 100A, since the hole 100d is not formed, the connection between the semiconductor chip 100A and the die pad 42a using the adhesive 50 is a surface-to-surface connection. Therefore, in the semiconductor chip 100A, the connection area is insufficient, and the connection strength between the semiconductor chip 100A and the die pad 42a may be insufficient.

[0031] In order to compensate for such a lack of connection strength, the amount of adhesive 50 supplied is increased. However, if the amount of adhesive 50 supplied is increased, the adhesive 50 may reach the epitaxial layer 20 along the side surface 100c, and may electrically connect the epitaxial layer 20 and the die pad 42a (a short circuit may occur). Furthermore, if the amount of adhesive 50 supplied is increased, the adhesive 50 may cover the light emitting layer exposed from the side surface 100c, and may attenuate the light output from the semiconductor chip 100A.

[0032] Since the hole 100d is formed in the semiconductor chip 100, when the semiconductor chip 100 and the die pad 42a are connected using the adhesive 50, the adhesive 50 is not only interposed between the electrode 31 and the die pad 42a, but also enters the hole 100d. Therefore, the connection area of ​​the semiconductor chip 100 is increased, and the connection strength between the semiconductor chip 100A and the die pad 42a is improved.

[0033] In the semiconductor chip 100, the connection strength can be improved without increasing the amount of adhesive 50 supplied, so that it is possible to avoid supplying an excessive amount of adhesive 50. As a result, the adhesive 50 is positioned below the epitaxial layer 20, making it possible to prevent the epitaxial layer 20 and the die pad 42a from being electrically connected to each other and to prevent attenuation of the optical output.

[0034] (Additional Note) The above embodiment includes the following configurations.

[0035] <Appendix 1> A semiconductor chip comprising: The first page and a second surface; the second surface is an opposite surface to the first surface in a thickness direction of the semiconductor chip, A semiconductor chip, the second surface having a hole formed therein, the hole extending toward the first surface along the thickness direction.

[0036] <Appendix 2> 2. The semiconductor chip of claim 1, wherein the hole is circular or rectangular in a plan view.

[0037] <Appendix 3> 3. The semiconductor chip according to claim 1, wherein the number of the holes is more than one.

[0038] <Appendix 4> 4. The semiconductor chip according to claim 1, wherein the depth of the hole is 0.5 times or less than the thickness of the semiconductor chip.

[0039] <Appendix 5> the semiconductor chip has a substrate forming the second surface, and an epitaxial layer disposed on the substrate and including a light emitting layer; 5. The semiconductor chip of claim 1, wherein the bottom of the hole is in the substrate.

[0040] <Appendix 6> A die pad; The semiconductor chip according to claim 5; and an adhesive; the semiconductor chip is disposed such that the second surface faces the die pad, the semiconductor chip is connected to the die pad by the adhesive; The adhesive is below the epitaxial layer.

[0041] Although the embodiment of the present disclosure has been described above, the above-mentioned embodiment can be modified in various ways. The scope of the present invention is not limited to the above-mentioned embodiment. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0042] 10 substrate, 10a first surface, 10b second surface, 20 epitaxial layer, 30, 31 electrode, 40 substrate, 41 base material, 41a first surface, 41b second surface, 41c through hole, 41d through hole, 42 conductive pattern, 42a die pad, 43, 44, 45 conductive pattern, 46, 47 conductive layer, 50 adhesive, 60 bonding wire, 70 reflector, 80 sealing resin, 100 semiconductor chip, 100A semiconductor chip, 100a first surface, 100b second surface, 100c side, 100d hole, 200 semiconductor package, D depth, T thickness.

Claims

1. A semiconductor chip comprising: The first page and a second surface; the second surface is an opposite surface to the first surface in a thickness direction of the semiconductor chip, A hole is formed in the second surface, the hole extending toward the first surface along the thickness direction.

2. The semiconductor chip according to claim 1 , wherein the hole is circular or rectangular in plan view.

3. The semiconductor chip according to claim 1 , wherein the number of the holes is more than one.

4. The semiconductor chip according to claim 1 , wherein the depth of the hole is equal to or less than 0.5 times the thickness of the semiconductor chip.

5. the semiconductor chip has a substrate forming the second surface, and an epitaxial layer disposed on the substrate and including a light emitting layer; The semiconductor chip according to claim 1 , wherein a bottom of the hole is in the substrate.

6. A die pad; The semiconductor chip according to claim 5 ; and an adhesive; the semiconductor chip is disposed such that the second surface faces the die pad, the semiconductor chip is connected to the die pad by the adhesive; The adhesive is below the epitaxial layer.

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