Manufacturing method of semiconductor device

Abstract

To appropriately form a barrier metal in a range over a surface of an interlayer insulation layer and a surface of a semiconductor substrate.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming a silicon-containing layer in contact with a semiconductor substrate and an interlayer insulation layer in a range over a coated part and an opening part; forming a metal layer in the range over the coated part and the opening part; forming a silicide layer by reacting the metal layer and the silicon-containing layer through heat treatment; and forming a barrier metal layer in contact with a surface of the silicide layer in the range over the coated part and the opening part.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a technique for forming a barrier metal on the surface of a wafer. The wafer has a semiconductor substrate and an interlayer insulating layer provided on the surface of the semiconductor substrate. A contact hole is provided in the interlayer insulating layer, and the semiconductor substrate is exposed in the contact hole. The barrier metal is formed in an area spanning the inside and outside of the contact hole. That is, the barrier metal is formed so as to cover the surface of the semiconductor substrate and the surface of the interlayer insulating layer in the contact hole. The technique of Patent Document 1 prevents undercuts from occurring at the boundary between the side surface of the interlayer insulating layer and the surface of the semiconductor substrate, thereby preventing poor formation of the barrier metal at the boundary. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-297828 Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, the technology of Patent Document 1 prevents the formation of a barrier metal that is defective due to undercut (i.e., the shape of the semiconductor substrate). On the other hand, when the barrier metal is formed across the surface of the interlayer insulating layer and the surface of the semiconductor substrate, the formation of the barrier metal that is defective due to the difference in the base material may occur at the boundary between the interlayer insulating layer and the semiconductor substrate. That is, when the barrier metal is grown, the crystallinity and the surface direction of the barrier metal change depending on the base material. Therefore, a difference occurs in the crystallinity and the surface direction between the barrier metal grown on the surface of the interlayer insulating layer and the barrier metal grown on the surface of the semiconductor substrate, and the barrier metal is likely to be formed defective at the boundary between them. This specification proposes a technology for forming a barrier metal in an appropriate range across the surface of the interlayer insulating layer and the surface of the semiconductor substrate. [Means for solving the problem]

[0005] The method for manufacturing a semiconductor device disclosed in the present specification includes a wafer preparation step, a silicon-containing layer formation step, a metal layer formation step, a silicide layer formation step, a barrier metal formation step, and an electrode layer formation step. In the wafer preparation step, a wafer is prepared that has a semiconductor substrate made of a silicon-containing semiconductor and an interlayer insulating layer covering the surface of the semiconductor substrate, and the wafer is provided with a covering portion where the interlayer insulating layer is exposed and an opening where the surface of the semiconductor substrate is exposed. In the silicon-containing layer formation step, a silicon-containing layer is formed in a range that spans the covering portion and the opening, the silicon-containing layer being in contact with the semiconductor substrate and the interlayer insulating layer. In the metal layer formation step, a metal layer is formed in a range that spans the covering portion and the opening, the metal layer being in contact with the silicon-containing layer. In the silicide layer formation step, the metal layer and the silicon-containing layer are reacted with each other by heat treatment to form a silicide layer that is distributed in a range that spans the covering portion and the opening and is in contact with the semiconductor substrate in the opening. In the barrier metal forming step, a barrier metal layer is formed in contact with the silicide layer in an area spanning the covering portion and the opening, and in the electrode layer forming step, an electrode layer is formed in contact with the barrier metal layer in an area spanning the covering portion and the opening.

[0006] The "semiconductor containing silicon" is a semiconductor containing silicon as an element. For example, the "semiconductor containing silicon" may be a simple substance of silicon, or may be a semiconductor composed of a silicon compound.

[0007] The term "silicon-containing layer" refers to a layer made of a material containing silicon as an element. For example, the "silicon-containing layer" may be single crystal silicon, polysilicon, amorphous silicon, or a silicon compound.

[0008] In this manufacturing method, before forming the barrier metal, a silicon-containing layer in contact with the semiconductor substrate and the interlayer insulating layer is formed. Next, a metal layer is formed on the surface of the silicon-containing layer. Next, the silicon-containing layer and the metal layer are reacted by heat treatment to form a silicide layer in the range spanning the covering portion and the opening. Next, a barrier metal layer is formed on the surface of the silicide layer. Since the base material is the silicide layer in both the covering portion and the opening, the barrier metal layer can be suitably formed in the range spanning the covering portion and the opening. Therefore, poor formation of the barrier metal at the boundary between the covering portion and the opening (i.e., the portion covering the boundary between the semiconductor substrate and the interlayer insulating layer) is prevented. Therefore, after forming an electrode layer on the surface of the barrier metal, interdiffusion of materials between the electrode layer and the semiconductor substrate and between the electrode layer and the interlayer insulating layer is suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. [Diagram 2] 4A to 4C are explanatory views of a manufacturing method according to an embodiment. [Diagram 3] 4A to 4C are explanatory diagrams of a manufacturing method according to an embodiment. [Figure 4] 4A to 4C are explanatory views of a manufacturing method according to an embodiment. [Diagram 5] 4A to 4C are explanatory views of a manufacturing method according to an embodiment. [Figure 6] FIG. 13 is a cross-sectional view showing a case where the silicon-containing layer remains. [Figure 7]4A to 4C are explanatory views of a manufacturing method according to an embodiment. [Figure 8] 4A to 4C are explanatory views of a manufacturing method according to an embodiment. [Figure 9] FIG. [Figure 10] 4A to 4C are explanatory views of a manufacturing method according to an embodiment. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. 13 is an explanatory diagram of a third modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the example manufacturing method disclosed in the present specification, in the step of forming the silicide layer, the metal layer may remain unreacted on a surface of the silicide layer, and the manufacturing method may further include a step of removing the unreacted metal layer before the step of forming the barrier metal layer.

[0011] In the example manufacturing method disclosed herein, the semiconductor substrate of the wafer prepared in the step of preparing the wafer may have a high-concentration layer exposed in the opening and having an impurity concentration capable of making ohmic contact with the silicide layer, and in the step of forming the silicon-containing layer, a thickness of the silicon-containing layer formed on the surface of the semiconductor substrate may be thinner than a thickness of the high-concentration layer.

[0012] According to this configuration, the high concentration layer can be prevented from being eroded throughout its thickness by the silicidation reaction.

[0013] In one example manufacturing method disclosed in the present specification, in the step of forming the metal layer, a thickness of the metal layer formed in the opening may be equal to or greater than a thickness of the silicon-containing layer in the opening.

[0014] According to this configuration, the silicon-containing layer in the opening can be silicided throughout its entire thickness, and the silicide layer can be reliably brought into contact with the semiconductor substrate.

[0015] In one example of the manufacturing method disclosed in this specification, the wafer prepared in the step of preparing the wafer may have a step at a boundary between the opening and the covering portion.

[0016] When such a step exists, the barrier metal layer is likely to be poorly formed, and therefore the technique disclosed in this specification is particularly useful.

[0017] In the manufacturing method disclosed herein, the interlayer insulating layer may protrude from the surface of the semiconductor substrate, and in the step of forming the silicon-containing layer, a thickness of the silicon-containing layer formed on a side surface of the interlayer insulating layer may be thinner than a thickness of the silicon-containing layer formed on the surface of the semiconductor substrate.

[0018] According to this configuration, the occurrence of voids in the opening can be suppressed.

[0019] The semiconductor device 10 shown in FIG. 1 is a MOSFET (metal oxide semiconductor field effect transistor). The semiconductor device 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductor materials containing silicon (for example, silicon single crystal, etc.). A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12. A trench 14 is provided on the upper surface 12a of the semiconductor substrate 12. A gate insulating film 16 and a gate electrode 18 are provided in each trench 14. The upper surface of each gate electrode 18 is covered with an interlayer insulating layer 20. The interlayer insulating layer 20 is made of silicon oxide or the like. The interlayer insulating layer 20 is disposed on the upper surface 12a of the semiconductor substrate 12 with a gap therebetween. A source electrode 22 is disposed on the upper part of the semiconductor substrate 12. The source electrode 22 covers the surface of the interlayer insulating layer 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 in an area not covered by the interlayer insulating layer 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating layer 20.

[0020] The source electrode 22 has a silicide layer 22a, a barrier metal layer 22b, and an electrode layer 22c. The silicide layer 22a is in contact with the upper surface 12a of the semiconductor substrate 12 in an area where the interlayer insulating layer 20 is not provided. The silicide layer 22a also covers the upper surface and side surfaces of the interlayer insulating layer 20. The barrier metal layer 22b covers the surface of the silicide layer 22a. The electrode layer 22c covers the surface of the barrier metal layer 22b. The barrier metal layer 22b prevents interdiffusion of materials between the electrode layer 22c and the semiconductor substrate 12 and between the electrode layer 22c and the interlayer insulating layer 20.

[0021] The semiconductor substrate 12 has an n-type source layer 40, a p-type contact layer 42, a p-type body layer 44, an n-type drift layer 46, and an n-type drain layer 48. The source layer 40 and the contact layer 42 are arranged in a range including the upper surface 12a of the semiconductor substrate 12. The source layer 40 has a high n-type impurity concentration, and is in ohmic contact with the source electrode 22 (more specifically, the silicide layer 22a). The contact layer 42 has a high p-type impurity concentration, and is in ohmic contact with the source electrode 22 (more specifically, the silicide layer 22a). The body layer 44 has a lower p-type impurity concentration than the contact layer 42. The body layer 44 is arranged below the source layer 40 and the contact layer 42. The drift layer 46 is arranged below the body layer 44. The drain layer 48 has a higher n-type impurity concentration than the drift layer 46. The drain layer 48 is arranged below the drift layer 46. The drain layer 48 is in ohmic contact with the drain electrode 24 on the lower surface 12b.

[0022] Next, a method for manufacturing the semiconductor device 10 in the embodiment will be described. Note that the manufacturing method in the embodiment is characterized by the method for forming the source electrode 22, and therefore, the method for forming the source electrode 22 will be described below.

[0023] (Wafer preparation process) First, a wafer 11 shown in FIG. 2 is prepared. The wafer 11 has a semiconductor substrate 12, a gate electrode 18, and an interlayer insulating layer 20. The gate electrode 18 is disposed in a trench 14. The interlayer insulating layer 20 covers the upper surface of the gate electrode 18 and the upper surface 12a around it. The interlayer insulating layer 20 is disposed at intervals on the upper surface 12a. In the range where the interlayer insulating layer 20 is not provided, the upper surface 12a is exposed. In the following, in the state of FIG. 2 (i.e., the state before the source electrode 22 is formed), the region where the interlayer insulating layer 20 is exposed is referred to as a covering portion 80, and the region where the upper surface 12a is exposed is referred to as an opening 82. In the semiconductor substrate 12, a source layer 40, a contact layer 42, a body layer 44, and a drift layer 46 are provided. The source layer 40 and the contact layer 42 are exposed to the upper surface 12a in the opening 82. The source layer 40 and the contact layer 42 have impurity concentrations high enough to make ohmic contact with the silicide layer 22a formed in a later process. The interlayer insulating layer 20 is provided so as to protrude upward from the upper surface 12a of the semiconductor substrate 12. Therefore, the upper surface of the interlayer insulating layer 20 is disposed above the upper surface 12a of the semiconductor substrate 12. Therefore, a step is provided between the upper surface in the opening 82, 12a, and the upper surface of the interlayer insulating layer 20. That is, a step is provided at the boundary between the opening 82 and the covering portion 80.

[0024] (Silicon-containing layer forming process) Next, as shown in FIG. 3, a silicon-containing layer 84 is formed by CVD (chemical vapor deposition) in a range spanning the covering portion 80 and the opening 82. In this embodiment, the silicon-containing layer 84 is made of polysilicon. However, the silicon-containing layer 84 may be made of any material as long as it is a material that is silicided in a silicide layer forming process described later. For example, the silicon-containing layer 84 may be made of single crystal silicon, amorphous silicon, SiC, or the like. The silicon-containing layer 84 is formed so as to contact the upper surface 12a (i.e., the source layer 40 and the contact layer 42) in the opening 82. The silicon-containing layer 84 is also formed so as to cover the upper surface and side surfaces of the interlayer insulating layer 20. Since the silicon-containing layer 84 can be formed with a relatively high coverage, the silicon-containing layer 84 is also appropriately formed in the boundary portion between the semiconductor substrate 12 and the interlayer insulating layer 20. The silicon-containing layer 84 is formed such that a thickness T2 of a portion covering the side surface of the interlayer insulating layer 20 is thinner than a thickness T1 of a portion covering the upper surface 12a within the opening 82. Moreover, the silicon-containing layer 84 is formed such that a thickness T2 of a portion covering the side surface of the interlayer insulating layer 20 is thinner than a thickness T3 of a portion covering the upper surface of the interlayer insulating layer 20. Moreover, the silicon-containing layer 84 is formed such that a thickness T1 is thinner than a thickness T4 of the source layer 40 and the contact layer 42.

[0025] (Metal layer formation process) Next, as shown in FIG. 4, a metal layer 86 is formed in a range spanning the covering portion 80 and the opening 82. In this embodiment, the metal layer 86 is made of nickel. However, the metal layer 86 may be made of any metal as long as it is a metal that can be silicided. For example, the metal layer 86 may be made of titanium, chromium, cobalt, molybdenum, palladium, tungsten, platinum, or the like. The metal layer 86 is formed so as to be in contact with the entire surface of the silicon-containing layer 84 in a range spanning the covering portion 80 and the opening 82. The metal layer 86 is formed so that a thickness T5 of the metal layer 86 formed in the opening 82 is equal to or greater than a thickness T1 of the silicon-containing layer 84 in the opening 82.

[0026] (Silicide layer formation process) Next, the wafer 11 is heat-treated to react the metal layer 86 with the silicon-containing layer 84. As a result, as shown in FIG. 5, a silicide layer 22a is formed in a range spanning the covering portion 80 and the opening 82. Before the heat treatment (i.e., in the state shown in FIG. 4), the thickness T5 of the metal layer 86 is equal to or greater than the thickness T1 of the silicon-containing layer 84 in the opening 82, so that the silicon-containing layer 84 is silicided in its entire thickness direction by the heat treatment. In the opening 82, the silicide reaction progresses through the silicon-containing layer 84 to the inside of the semiconductor substrate 12. Therefore, as shown in FIG. 5, the position of the upper surface 12a of the semiconductor substrate 12 moves downward in the opening 82. However, before the heat treatment (i.e., in the state shown in FIG. 4), the thickness T1 of the silicon-containing layer 84 is thinner than the thickness T4 of the source layer 40 and the contact layer 42, so that the source layer 40 and the contact layer 42 remain below the silicide layer 22a as shown in FIG. 5. In the opening 82, the silicide layer 22a is in ohmic contact with the source layer 40 and the contact layer 42. The silicide layer 22a is also formed on the surface of the interlayer insulating layer 20. Before the heat treatment (i.e., the state of FIG. 4), the thickness T2 of the silicon-containing layer 84 is thin on the side surface of the interlayer insulating layer 20, so that the thickness T11 of the silicide layer 22a formed on the side surface of the interlayer insulating layer 20 is thinner than the thickness T12 of the silicide layer 22a formed on the upper surface of the interlayer insulating layer 20 and the thickness T13 of the silicide layer 22a formed on the upper surface 12a, as shown in FIG. 5. In addition, an unreacted metal layer 86 (i.e., a metal layer 86 that has not been silicided) remains on the surface of the silicide layer 22a.

[0027] In other embodiments, the unreacted metal layer 86 may not remain on the surface of the silicide layer 22a. In other embodiments, the unreacted silicon-containing layer 84 may remain between the interlayer insulating layer 20 and the silicide layer 22a, as shown in FIG.

[0028] (Metal layer removal process) 7, the unreacted metal layer 86 is removed by etching. This exposes the entire surface of the silicide layer 22a. If no unreacted metal layer 86 remains in the silicide layer formation step, the metal layer removal step can be omitted.

[0029] (Barrier metal layer formation process) 8, a barrier metal layer 22b is formed in a range spanning the covering portion 80 and the opening 82. For example, the barrier metal layer 22b may be made of titanium nitride, molybdenum, or the like. The barrier metal layer 22b is formed in a range spanning the covering portion 80 and the opening 82 so as to be in contact with the entire surface of the silicide layer 22a.

[0030] 9 shows a barrier metal layer forming process of a comparative example. In FIG. 9, a silicide layer 22a is formed on the upper surface 12a of the semiconductor substrate 12, while the silicide layer 22a is not formed on the surface of the interlayer insulating layer 20. Therefore, in the case of FIG. 9, the barrier metal layer 22b grows in the opening 82 with the silicide layer 22a as the base, and the barrier metal layer 22b grows in the covering portion 80 with the interlayer insulating layer 20 as the base. There is a difference in crystallinity and surface direction between the barrier metal layer 22b grown with the silicide layer 22a as the base and the barrier metal layer 22b grown with the interlayer insulating layer 20 as the base. Therefore, the barrier metal layer 22b is poorly formed at the boundary between the silicide layer 22a and the interlayer insulating layer 20, and a discontinuity 28 of the barrier metal layer 22b is formed at the boundary. In particular, in FIG. 9, a step is provided at the boundary between the silicide layer 22a and the interlayer insulating layer 20, so that the barrier metal layer 22b is likely to be poorly formed at the boundary.

[0031] In contrast, in the manufacturing method of the embodiment, the silicide layer 22a is exposed over the entire range spanning the opening 82 and the covering portion 80, so that the barrier metal layer 22b can be suitably formed over the entire range spanning the opening 82 and the covering portion 80 as shown in Fig. 8. In other words, poor formation of the barrier metal layer 22b at the boundary between the opening 82 and the covering portion 80 can be prevented.

[0032] (Electrode layer formation process) Next, as shown in FIG. 10, an electrode layer 22c is formed in a range spanning the covering portion 80 and the opening 82. The electrode layer 22c is made of a metal. For example, the electrode layer 22c may be made of aluminum, copper, or the like. The electrode layer 22c is formed so as to contact the entire surface of the barrier metal layer 22b in a range spanning the covering portion 80 and the opening 82. Since the barrier metal layer 22b does not have a broken portion, the barrier metal layer 22b can appropriately prevent interdiffusion of materials, and the reliability of the semiconductor device 10 can be prevented from decreasing. In addition, since the thickness T11 (see FIG. 5) of the silicide layer 22a is thin on the side surface of the interlayer insulating layer 20, the space in the opening 82 is wide, and the electrode layer 22c can be appropriately grown in the opening 82. Therefore, the generation of voids in the opening 82 can be suppressed.

[0033] In the above-described embodiment, the interlayer insulating layer 20 protrudes upward from the upper surface 12a. However, as shown in Fig. 11, the upper surface of the interlayer insulating layer 20 may be located at the same height as the upper surface 12a of the semiconductor substrate 12. Also, as shown in Fig. 12, the upper surface of the interlayer insulating layer 20 may be located below the upper surface 12a of the semiconductor substrate 12 (i.e., inside the trench 14). Even when the wafer of Figs. 11 and 12 is used, the manufacturing method disclosed in this specification can prevent poor formation of the barrier metal on the boundary between the covering portion 80 and the opening 82.

[0034] In the above-described embodiment, the source electrode 22 is formed on the upper part of the trench gate electrode. However, the manufacturing method disclosed in this specification may be used when the source electrode 22 is formed on the upper part of a planar gate electrode as shown in FIG.

[0035] In the above-mentioned embodiment, the manufacturing process of the MOSFET is described, but the manufacturing method disclosed in this specification may be used in the manufacturing process of an IGBT (insulated gate bipolar transistor). In the above-mentioned embodiment, the interlayer insulating layer 20 is an interlayer insulating layer that insulates between the source electrode 22 and the gate electrode 18, but the interlayer insulating layer may be any interlayer insulating layer provided on the surface of a semiconductor substrate. Therefore, the manufacturing method disclosed in this specification may be used not only for the manufacturing of switching elements, but also for the manufacturing of other semiconductor devices such as diodes.

[0036] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A method for manufacturing a semiconductor device, comprising: A step of preparing a wafer having a semiconductor substrate made of a silicon-containing semiconductor and an interlayer insulating layer covering a surface of the semiconductor substrate, the wafer being provided with a covering portion where the interlayer insulating layer is exposed and an opening portion where the surface of the semiconductor substrate is exposed; forming a silicon-containing layer in contact with the semiconductor substrate and the interlayer insulating layer in an area spanning the covering portion and the opening; forming a metal layer in contact with the silicon-containing layer in an area spanning the covering portion and the opening; a step of reacting the metal layer with the silicon-containing layer by heat treatment to form a silicide layer that is distributed across the covering portion and the opening and that is in contact with the semiconductor substrate within the opening; forming a barrier metal layer in contact with the silicide layer in an area spanning the covering portion and the opening; forming an electrode layer in contact with the barrier metal layer in an area spanning the covering portion and the opening; The manufacturing method comprising the steps of: (Configuration 2) In the step of forming the silicide layer, the metal layer remains unreacted on a surface of the silicide layer, 2. The manufacturing method according to configuration 1, further comprising the step of removing unreacted part of the metal layer before the step of forming the barrier metal layer. (Configuration 3) the semiconductor substrate of the wafer prepared in the step of preparing the wafer has a high-concentration layer that is exposed in the opening and has an impurity concentration capable of making ohmic contact with the silicide layer, In the step of forming the silicon-containing layer, a thickness of the silicon-containing layer formed on the surface of the semiconductor substrate is thinner than a thickness of the high concentration layer. The method for producing the present invention according to claim 1 or 2. (Configuration 4) 4. The method according to any one of claims 1 to 3, wherein in the step of forming the metal layer, a thickness of the metal layer formed in the opening is equal to or greater than a thickness of the silicon-containing layer in the opening. (Configuration 5) 5. The manufacturing method according to any one of configurations 1 to 4, wherein the wafer prepared in the step of preparing the wafer has a step at a boundary between the opening and the covering portion. (Configuration 6) the interlayer insulating layer protrudes from the surface of the semiconductor substrate; In the step of forming the silicon-containing layer, a thickness of the silicon-containing layer formed on the side surface of the interlayer insulating layer is thinner than a thickness of the silicon-containing layer formed on the surface of the semiconductor substrate. The manufacturing method according to configuration 5.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0038] 12: semiconductor substrate, 20: interlayer insulating layer, 22: source electrode, 22a: silicide layer, 22b: barrier metal layer, 22c: electrode layer, 40: source layer, 42: contact layer, 80: covering portion, 82: opening, 84: silicon-containing layer, 86: metal layer

Claims

1. A method for manufacturing a semiconductor device, comprising: A step of preparing a wafer having a semiconductor substrate made of a silicon-containing semiconductor and an interlayer insulating layer covering a surface of the semiconductor substrate, the wafer being provided with a covering portion where the interlayer insulating layer is exposed and an opening portion where the surface of the semiconductor substrate is exposed; forming a silicon-containing layer in contact with the semiconductor substrate and the interlayer insulating layer in an area spanning the covering portion and the opening; forming a metal layer in contact with the silicon-containing layer in an area spanning the covering portion and the opening; a step of reacting the metal layer with the silicon-containing layer by heat treatment to form a silicide layer that is distributed across the covering portion and the opening and that is in contact with the semiconductor substrate within the opening; forming a barrier metal layer in contact with the silicide layer in an area spanning the covering portion and the opening; forming an electrode layer in contact with the barrier metal layer in an area spanning the covering portion and the opening; The manufacturing method comprising the steps of:

2. In the step of forming the silicide layer, the metal layer remains unreacted on a surface of the silicide layer, 2. The method according to claim 1, further comprising the step of removing unreacted portions of the metal layer before the step of forming the barrier metal layer.

3. the semiconductor substrate of the wafer prepared in the step of preparing the wafer has a high-concentration layer that is exposed in the opening and has an impurity concentration capable of making ohmic contact with the silicide layer, In the step of forming the silicon-containing layer, a thickness of the silicon-containing layer formed on the surface of the semiconductor substrate is thinner than a thickness of the high concentration layer. The method according to claim 1 or 2.

4. The method according to claim 1 , wherein in the step of forming the metal layer, a thickness of the metal layer formed in the opening is equal to or greater than a thickness of the silicon-containing layer in the opening.

5. The manufacturing method according to claim 1 , wherein the wafer prepared in the step of preparing the wafer has a step at a boundary between the opening and the covering portion.

6. the interlayer insulating layer protrudes from the surface of the semiconductor substrate; In the step of forming the silicon-containing layer, a thickness of the silicon-containing layer formed on the side surface of the interlayer insulating layer is thinner than a thickness of the silicon-containing layer formed on the surface of the semiconductor substrate. The method according to claim 5 .

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