Integrated circuit

Abstract

To realize a logic circuit with a complex configuration that includes series and parallel transistors and branches that combine both, which was not possible with conventional horizontal gate-around transistor (GAA) or vertical GAA configurations, thereby achieving high-speed, low-cost characteristics for the entire logic LSI.SOLUTION: In a plurality of lateral FETs having the same conductivity type of the channel portion vertically stacked at the same position on the same plane, the gate electrodes 204 of the plurality of lateral FETs are vertically stacked via insulating films 207, and the connection of the vertical source and drain electrodes 206 of the plurality of lateral FETs is realized by a logic LSI composed of a logic circuit realized by a stacked structure realized by vertical FETs arranged at the source and drain electrode portions of adjacent upper and lower lateral FETs.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] This relates to integrated circuits using gate-all-around lateral and vertical transistors. [Background technology]

[0002] In the past, LSIs have progressed in accordance with Moore's Law as planar transistors have become increasingly miniaturized, and there has been steady progress in increasing capacity, reducing costs, increasing speed, and reducing power consumption.

[0003] As a result, MPUs, which are representative of logic LSIs, have achieved GHz operation using more than one billion planar transistors, and NAND flash memory, which uses planar transistors and is the memory LSI with the highest capacity, has been increased to 64 Gbit (Reference 1).

[0004] However, miniaturization of this planar transistor is approaching its limit in recent years due to short channel effects and the like.

[0005] In order to solve the problem of the difficulty in miniaturizing planar transistors in the past, transistors that can use all four sides as channels have been proposed. Among the transistors that can use all four sides as channels, horizontal transistors are called gate-around transistors (hereafter abbreviated as lateral GAA), and vertical transistors are called GAA or surrounding gate transistors (hereafter abbreviated as vertical GAA or SGT).

[0006] In the lateral GAA, the source and drain electrodes are arranged on the same plane. Therefore, the source electrodes of multiple lateral GAAs stacked vertically can be shared vertically (and the drain electrodes can also be shared), making it easy to connect stacked lateral GAAs in parallel. In contrast, in the vertical GAA, the source and drain electrodes are connected vertically, not on the same plane, so connecting vertical GAAs vertically makes it easy to connect them in series.

[0007] On the other hand, stacking horizontal GAAs does not allow for series connections. Also, stacking horizontal GAAs does not allow for parallel connections. In fact, in large-scale logic LSIs, circuits are made up of complex combinations of transistors with series and parallel connections and branches that combine both, so there was a problem that large-scale logic LSIs could not be constructed using only stacked horizontal GAAs or only stacked vertical GAAs.

[0008] To realize a low-cost logic LSI with a small pattern area without sacrificing high-speed characteristics, stacked horizontal GAA and stacked vertical GAA are promising candidates, but there is a problem that a logic LSI composed of logic circuits with complex connection characteristics such as series and parallel transistors and branches that combine both cannot be realized with either of them alone. References 1M. Sako et al., “A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology”, ISSCC Dig.Tech.Papers, 2015. Summary of the Invention Problem that the invention is trying to solve

[0009] To realize an inexpensive logic LSI with a small pattern area without sacrificing high-speed characteristics, stacked horizontal GAA and stacked vertical GAA are promising candidates, but there is a problem that using only one of them is not possible to realize a logic LSI composed of logic circuits with complex connection characteristics in which transistors are connected in series and parallel, or where branches that combine both are present. In other words, at present, no logic LSI using stacked GAA with a small pattern area without sacrificing high-speed characteristics has been proposed. Means to solve the problem

[0010] In a plurality of lateral FETs having the same conductivity type of the channel portion stacked vertically at the same position on the same plane, the gate signal electrodes of the plurality of lateral FETs are stacked vertically via an insulating film, and the connection of the source and drain electrodes of the plurality of lateral FETs in the vertical direction is realized by a logic LSI composed of a logic circuit realized by a stacked structure realized by vertical FETs arranged at the source and drain electrode portions of the adjacent upper and lower lateral FETs.

[0011] The present invention has the effect of making it possible for the first time to realize a logic circuit, which is a component of a logic LSI having a complex configuration with series and parallel transistors and branches that combine both, in a small planar pattern area without sacrificing high-speed characteristics. As a result, it is possible to realize logic circuits with complex configurations that include series and parallel transistors and branches that combine both, which was not possible with conventional horizontal GAA or vertical GAA configurations, and it is possible to achieve high-speed, low-cost characteristics for the entire logic LSI using this invention. BEST MODE FOR CARRYING OUT THEINVENTION

[0012] A first embodiment of an integrated circuit according to the present invention will now be described with reference to the drawings. [First embodiment] (Configuration of the first embodiment)

[0013] A first embodiment of the present invention will now be described. A cross-sectional circuit diagram of the first embodiment is shown in Fig. 1. The diagram on the left shows the basic elements that make up the first embodiment. The drain electrodes of vertical GAA 11 and 12 are connected to the source electrode 16 and drain electrode 17 of horizontal GAA 10 to which gate signal 13 is input. The gate electrodes of the vertical GAA are 14 and 15, and the source electrodes are 18 and 19, respectively.

[0014] This basic element allows signals to be freely connected in both the vertical and horizontal directions by controlling the gate input. Moreover, since the vertical GAA 11 and 12 are formed directly under the source and drain electrodes of the horizontal GAA 10, the planar pattern area can be realized in the same minute area as the size of the horizontal GAA 10.

[0015] The right side of Fig. 1 shows a first embodiment of the present invention in which the basic elements are stacked vertically (two are stacked in Fig. 1 as an example). Two basic elements are stacked vertically, and the source of the vertical GAA21 of the basic element stacked on top is connected to the source of the horizontal GAA30 of the basic element stacked below and the drain electrode of the vertical GAA31. Similarly, the drain of the vertical GAA12 of the basic element stacked on top is connected to the drain of the horizontal GAA30 of the basic element stacked below and the drain electrode of the vertical GAA32.

[0016] In this first embodiment, by controlling the gate input, signals can be freely connected vertically and horizontally, and as a result, it is possible to arbitrarily set the wiring that connects in series, parallel, and in series and parallel at a certain node, so-called branching wiring. For example, when horizontal GAA 20 and 30 are connected in parallel, the power supply voltage is applied to the gate voltage of vertical GAA 21, 22, 31, and 32 to make them conductive. On the other hand, when horizontal GAA 20 and 30 are connected in series, the power supply voltage is applied to the gate voltage of vertical GAA 22 and 31 to make them conductive, and the ground voltage is applied to the gate voltage of vertical GAA 211 and 32 to make them non-conductive.

[0017] There are various other ways to realize series connections, such as making vertical GAA 21 and 31 conductive, making vertical GAA 22 and 32 conductive, or making the vertical GAA and three horizontal GAA conductive. Furthermore, by making horizontal GAA 20 and vertical GAA 22 non-conductive and the rest conductive, a signal that branches at node 28 can be created. Using series and parallel connections, CMOS NAND logic and NOR logic can be realized. Using a branching structure, composite gate logic that is more complex than CMOS NAND logic and NOR logic can be realized. Furthermore, by inputting a signal from the source or drain, a pass gate logic circuit can also be realized. In other words, all basic logic circuits used in logic LSIs can be realized.

[0018] In the first embodiment, the basic elements are stacked vertically. Therefore, in the first embodiment, like the basic elements, the planar pattern area can be realized in a minute area equal to the size of the horizontal GAA 10. As will be described later, by devising the manufacturing process, the manufacturing cost can be reduced regardless of the number of layers, which leads to a reduction in the cost per layer.

[0019] 2 shows a top view of the first embodiment of FIG. 1. The vertical GAA 21 is embedded in the source region of the horizontal GAA 20, and the vertical GAA 22 is embedded in the drain region. Therefore, if the length of the gate portion of each GAA is the design rule F, and the distance between adjacent horizontal GAA is F, the long side length of the first embodiment can be realized in 4F. If the vertical direction is 2F, the first embodiment is 4F*2F=8F regardless of the number of basic elements to be stacked. 2 The gates 23 and 33 of the horizontal GAA and the gates 24, 34, 25 and 35 of the vertical GAA are taken out from the lateral direction as shown in the figure.

[0020] FIG. 3 shows an example of two first embodiments connected horizontally. When connected horizontally, the vertical GAA of the drain part of the first embodiment on the left is shared with the vertical GAA of the source part of the first embodiment on the right. The horizontal connection is not limited to two, and any number of first embodiments can be connected. This makes it possible to realize logic circuits (such as lookup tables, small-scale memories, selectors, multiplexers, demultiplexers, encoders, match / no-match circuits, majority logic, full adders, multipliers, FPGA wiring switches (SW) and gate switches (CB), and AI product-sum calculation circuits) that are more complex than NAND logic and NOR logic that could not be realized in the first embodiment.

[0021] The first embodiment, which is connected horizontally in Fig. 3, can be connected in the same way to the front and rear to realize a three-dimensional array according to the first embodiment. This allows for a variety of applications, such as large-scale memory arrays featuring common gates, AI product-sum calculation circuits, or switches connecting GAAs of different heights (used when connecting different calculation units at high speed).

[0022] Although the threshold voltages of the GAAs are the same in the examples shown in FIG. 1 to FIG. 3, the threshold voltage can be increased by programming any GAA. FIG. 4 shows the case where the vertical GAA 121 is programmed. When programming the vertical GAA 121, the gate voltage of the vertical GAA 31 connected in series in the vertical direction is set to the pass voltage (an intermediate voltage that is not programmed), the gate voltage of the vertical GAA 121 is set to the program voltage (a voltage several times the pass voltage), and the drain voltage of the vertical GAA 121 and the source voltage of the vertical GAA 31 are set to the ground voltage. The gate voltages 23, 33, 25, and 35 are set to the ground voltage so that the other GAAs are not programmed, and the vertical GAA to be programmed and the vertical GAA connected thereto are separated. By programming the GAAs that are not used, unnecessary power consumption can be reduced by not charging and discharging the gate of the programmed GAA during evaluation (reading). When erasing the programmed vertical GAA for a new use after programming, a negative program voltage is applied to the gate of the vertical GAA 31 to lower the threshold voltage.

[0023] 5 shows the case where the horizontal GAA 130 is programmed. When programming the vertical GAA 130, the gate voltage 24 of the vertical GAA 21 and the gate voltage 35 of the vertical GAA 29 connected vertically are set to a passing voltage, the gate voltage of the vertical GAA 130 is set to a program voltage, and the drain voltage of the vertical GAA 21 and the source voltage of the vertical GAA 29 are set to a ground voltage. To prevent programming of other GAAs, the gate voltages 23, 34, and 25 are set to a ground voltage and are isolated from the vertical GAA to be programmed and the vertical GAAs connected to it. If you want to program a vertical GAA and a horizontal GAA at the same time, you can use the horizontal connection method shown in Figure 3 and isolate the GAAs you want to program by setting the gate voltage of the GAA between them to ground voltage.

[0024] FIG. 6 shows a cross-sectional view (cross-sectional view of AA' in FIG. 2) in the direction of drain current flow of the first embodiment. 201 is a substrate of a horizontal type GAA, 202 is a substrate of a vertical type GAA, 203 is a gate insulating film of the vertical and horizontal GAA, 204 is a gate electrode of the horizontal type GAA, 205 is a gate electrode of the vertical type GAA, 206 is a source drain wiring, and 207 is a thick insulating film. The stacked horizontal GAAs are separated by a thick insulating film 207, which separates the gate electrodes 204 and 205 of the stacked horizontal GAA. At the height of the thick insulating film, a vertical GAA is formed at the source and drain electrode part of the horizontal GAA. The source and drain electrodes of the horizontal GAA are connected vertically by low-resistance source and drain wiring 206. The substrate 202 of the vertical GAA is connected to the lower part of the low-resistance source and drain wiring. The vertical GAA is formed at a position offset in height from the horizontal GAA (the height of the thick insulating film, the GAA have complementary heights).

[0025] The gate electrodes of the horizontal and vertical GAA are taken out in the horizontal direction of the AA' cross section in Figure 2. Figure 7 shows how the gate electrode of the horizontal GAA is taken out (BB' cross section in Figure 2). Figure 8 shows how the gate electrode of the vertical GAA is taken out (CC' cross section in Figure 2). In either case, the length of the gate electrode of the lower GAA taken out in the horizontal direction is longer so that it can be connected vertically to the wiring (not shown) that runs on the top of the chip. Also, as mentioned above, the gate electrode of the vertical GAA is formed at a different height from the gate electrode of the horizontal GAA (complementary heights to each other, height of the thick insulating film).

[0026] An example of a manufacturing process for realizing the first embodiment is shown in Figures 9-14. A cross-sectional view of AA' in Figure 2 is shown. Figure 9 shows the lamination process steps required for preparation to form the vertical GAA and horizontal GAA. First, a thick insulating film is formed to the height at which the lower vertical GAA is to be formed. Next, in order to form the lower horizontal GAA, SiGe that will later be replaced with the gate electrode for the horizontal GAA, silicon that will become the substrate for the horizontal GAA, and SiGe that will later be replaced with the gate electrode for the GAA are formed. Next, the layers required to form the upper vertical GAA and horizontal GAA are formed in the same way as for the lower stage.

[0027] Figure 10 shows the process up to the formation of the gate insulating film for the lateral GAA. First, the SiGe is removed to be replaced with the gate electrode for the lateral GAA later. Next, a gate insulating film is formed on the silicon substrate for the lateral GAA.

[0028] Figure 11 shows the formation of the gate electrode of the lateral GAA and the formation of an insulating film on the source and drain parts. The gate electrode is formed by pouring it in from the side into the part where the SiGe has been removed. If necessary to separate the gate electrodes stacked in the vertical direction, an additional process is performed to add it. After that, an insulating film is formed on the source and drain parts. In a later process, part of this insulating film is used to separate the gate electrode and source and drain parts of the lateral GAA.

[0029] Figure 12 shows the formation of the gate electrode of the vertical GAA. The insulating film of the gate electrode formation part of the vertical GAA is removed, and the gate electrode is poured in from the side to form the gate electrode. If necessary, an extra process is added to separate the gate electrodes stacked vertically.

[0030] Figure 13 shows the process of forming a trench in the source / drain area of ​​the horizontal GAA and forming a gate insulating film for the vertical GAA. Next, a trench is formed in the source / drain area of ​​the horizontal GAA, and a gate insulating film for the vertical GAA is formed on the gate electrode of the vertical GAA.

[0031] Figure 14 shows the process of embedding the vertical GAA substrate and horizontal GAA wiring in the trench. Next, the silicon substrate is embedded in the substrate portion of the vertical GAA, and wiring is embedded in the source / drain portion of the horizontal GAA. In order to reduce the number of processes, a method is adopted in which these are formed at once, regardless of the number of layers.

[0032] 9-14, the number of steps does not depend on the number of layers in the manufacturing process for realizing the first embodiment. Therefore, the manufacturing cost per basic element can be reduced as the number of layers increases (as the number of layers of the basic elements to be laminated increases).

[0033] In the present invention, a stacked structure is used in which a plurality of lateral FETs having the same conductivity type of their channel portions are stacked vertically at the same position on the same plane, the gate signal electrodes of the plurality of lateral FETs are stacked vertically via insulating films, and the vertical source and drain electrodes of the plurality of lateral FETs are connected by vertical FETs arranged at the source and drain electrode portions of the adjacent upper and lower horizontal FETs.

[0034] As a result, it is now possible for the first time to realize logic circuits, which are components of logic LSIs with complex configurations that include series and parallel transistors and branches that combine both, in a small planar pattern area without sacrificing high-speed characteristics. Furthermore, it is possible to realize a logic circuit with a complex configuration in which transistors are connected in series and parallel, or in a combination of both, which could not be realized with the conventional horizontal GAA or vertical GAA configuration, and it is possible to realize high-speed, low-cost characteristics of the entire logic LSI using the present invention.

[0035] The present invention is not limited to this embodiment. If the horizontal and vertical GAA are all formed with programmable FeFETs (ferroelectric transistors), high-speed reconfigurable logic and AI multiplication and accumulation operations can be realized. As a result, it can be applied to all currently commercialized integrated circuits such as system LSIs, logic LSIs, and FPGAs. In addition, by using this invention, it is possible to realize vertical or horizontal wiring in an integrated circuit by making vertical or horizontal GAA conductive or non-conductive. In addition, if the vertical and horizontal GAA are made into variable resistance types with threshold control, there is a possibility that they can be used as basic elements of a new type of artificial brain computer in the future. [Brief description of the drawings]

[0036] [Figure 1] 1 is a circuit diagram of a first embodiment of a stacked GAA of an integrated circuit according to the present invention, seen from a cross-sectional direction. [Diagram 2] 1 is a top view of a first embodiment of a stacked GAA of an integrated circuit according to the present invention; [Diagram 3] This is an example in which two stacked GAAs of the first embodiment of the integrated circuit according to the present invention are connected horizontally. [Figure 4] 1 is a circuit diagram showing a case where a vertical GAA 121 is programmed in a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Diagram 5] 1 is a circuit diagram showing a case where a horizontal GAA 130 is programmed in a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Figure 6] 2 is a cross-sectional view (cross-sectional view taken along line AA′ in FIG. 2) in the direction in which a drain current flows in a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Figure 7]1 is a cross-sectional view showing a method of extracting a gate electrode of a lateral GAA in a first embodiment of a stacked GAA of an integrated circuit according to the present invention; [Figure 8] 1 is a cross-sectional view showing a method of extracting a gate electrode of a vertical GAA in a first embodiment of a stacked GAA of an integrated circuit according to the present invention; [Figure 9] 1A to 1C are cross-sectional views showing process steps required for forming a vertical GAA and a horizontal GAA of a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Figure 10] 1A to 1C are cross-sectional views showing the process up to the formation of a gate insulating film for a lateral GAA of a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Figure 11] 1A to 1C are cross-sectional views showing the process of forming a gate electrode of a lateral GAA and forming an insulating film on a source / drain portion in a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Figure 12] 1A to 1C are cross-sectional views showing the process of forming a gate electrode of a vertical GAA in a stacked GAA of an integrated circuit according to a first embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views showing the process of forming trenches in the source / drain portions of the horizontal GAA and forming a gate insulating film of the vertical GAA in a first embodiment of the stacked GAA of an integrated circuit according to the present invention. [Figure 14] 1A to 1C are cross-sectional views showing a process of embedding a vertical GAA substrate and a horizontal GAA wiring in a trench in a first embodiment of a stacked GAA of an integrated circuit according to the present invention. [Explanation of symbols]

[0037] Reference numeral 10 denotes a lateral GAA of a basic element, and 16, 13, and 17 denote the source, gate, and drain electrodes of the lateral GAA 10, respectively. Reference numeral 11 denotes a vertical GAA formed on the source side of the basic element, and 14 and 18 denote its gate and source electrodes, respectively. Reference numeral 12 denotes a vertical GAA formed on the drain side of the basic element, and 15 and 19 denote its gate and source electrodes, respectively. Horizontal GAA 20 and vertical GAA 21, 22 constitute basic elements stacked on top. 23, 24, 25 indicate the gate signals of each GAA. Horizontal GAA 30 and vertical GAA 31, 32 constitute basic elements stacked on the bottom. 33, 34, 35 indicate the gate signals of each GAA. 43, 53 indicate the gate signals of the horizontal GAA of the basic elements arranged horizontally in the first embodiment, and 45, 55 indicate the gate signals of the vertical GAA. Vertical GAA 121 shows a programmed vertical GAA. Horizontal GAA 130 shows a programmed horizontal GAA. Reference numeral 201 denotes a horizontal GAA substrate, 202 denotes a vertical GAA substrate, 203 denotes a GAA gate insulating film, 204 denotes a horizontal GAA gate electrode, 205 denotes a vertical GAA gate electrode, 206 denotes a source / drain wiring, 207 denotes an insulating film, 208 denotes a SiGe film, and 209 denotes a trench hole formed in the source / drain portion of the horizontal GAA.

Claims

1. An integrated circuit comprising a plurality of lateral FETs having the same conductivity type of their channel portions stacked vertically at the same position on the same plane, the gate signal electrodes of the lateral FETs being stacked vertically via an insulating film, and a number of logic circuits being integrated, the stacked structure being realized by vertical FETs arranged at the source and drain electrode portions of the adjacent upper and lower lateral FETs for connection of the vertical source and drain electrodes of the lateral FETs.

2. 2. The integrated circuit according to claim 1, wherein the lateral FET and the vertical FET are of a gate-around type using four sides as a channel.

3. 3. The integrated circuit according to claim 1, wherein the lateral FET and the vertical FET are programmable elements, such as a threshold voltage.

4. In the integrated circuit of claims 1 to 3, the logic circuit realized by the stacked lateral and vertical FETs is further connected to adjacent stacked lateral and vertical FETs in the left / right and front / rear directions by a new lateral FET.

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