Semiconductor device

Abstract

To provide a semiconductor device which has an integration degree improved.SOLUTION: A semiconductor device comprises: a first active pattern F1 and a second active pattern on an inter-lower layer insulation film 100; gate electrodes G1 to G4 on the first and second active patterns; a first source region S1, a second source region S2 and a drain region D1 on the first active pattern; a third source region and a drain region on the second active pattern; a first contact CA1 coupled to each of the first and third source regions; a second contact CA2 coupled to the second source region; a third contact CA3 coupled to the drain region D1; and a penetration via that is arranged in an internal part of the inter-lower layer insulation film, is extended in a first horizontal direction between the first active pattern and the second active pattern, and couples a lower wiring layer of a first contact lower part and a first contact of the lower wiring layer. Each of a second contact and a third contact is electrically insulated from the lower wiring layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to an MBCFET TM This paper relates to a semiconductor device including a multi-bridge channel field effect transistor (Multi-Bridge Channel Field Effect Transistor). [Background technology]

[0002] As one of the scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Such multi-gate transistors are easy to scale because they use a three-dimensional channel. In addition, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE), which affects the potential of the channel region due to the drain voltage, can be effectively suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 1,121,7528 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide a semiconductor device in which the area in which a through via is formed is minimized to improve the integration degree. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present invention made to achieve the above object includes a lower interlayer insulating film, a first active pattern and a second active pattern each extending in a first horizontal direction on the lower interlayer insulating film and spaced apart in a second horizontal direction different from the first horizontal direction, a gate electrode extending in the second horizontal direction on the first active pattern and the second active pattern, a first source region disposed on a first side of the gate electrode on the first active pattern, a second source region disposed on a second side of the gate electrode facing the first side of the gate electrode in the first horizontal direction on the first active pattern, a third source region disposed on the first side of the gate electrode on the second active pattern, a drain region disposed on the second side of the gate electrode on the second active pattern, and a drain region extending in the second horizontal direction on the first side of the gate electrode and a first contact connected to each of the third source regions, a second contact extending in the second horizontal direction on a second side of the gate electrode and connected to the second source region, a third contact extending in the second horizontal direction on the second side of the gate electrode and spaced apart from the second contact in the second horizontal direction and connected to the drain region, a lower wiring layer disposed within the lower interlayer insulating film, extending in the first horizontal direction between the first active pattern and the second active pattern, at least a portion of which protrudes vertically from an upper surface of the lower interlayer insulating film below the first contact, and a through via disposed between the first source region and the third source region and connecting the lower wiring layer and the first contact, wherein each of the second contact and the third contact is electrically insulated from the lower wiring layer between the second source region and the drain region.

[0007] A semiconductor device according to another aspect of the present invention made to achieve the above object includes a lower interlayer insulating film, a first active pattern and a second active pattern each extending in a first horizontal direction on the lower interlayer insulating film and spaced apart in a second horizontal direction different from the first horizontal direction, first to fourth gate electrodes each extending in the second horizontal direction on the first active pattern and the second active pattern and spaced apart sequentially in the first horizontal direction, a gate cut extending in the first horizontal direction between the first active pattern and the second active pattern to separate each of the first to fourth gate electrodes in the second horizontal direction, a first source region disposed on the first active pattern between the first gate electrode and the second gate electrode, a second source region disposed on the first active pattern between the second gate electrode and the third gate electrode, a first drain region disposed on the first active pattern between the third gate electrode and the fourth gate electrode, a third source region disposed on the second active pattern between the first gate electrode and the second gate electrode, and a gate cut between the second gate electrode and the third gate electrode. a second drain region disposed on the second active pattern between the gate electrode and the second gate electrode; a fourth source region disposed on the second active pattern between the third gate electrode and the fourth gate electrode; a first contact extending in the second horizontal direction between the first gate electrode and the second gate electrode and connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction between the second gate electrode and the third gate electrode and connected to the second source region; a third contact extending in the second horizontal direction between the third gate electrode and the fourth gate electrode and connected to the first drain region; a fourth contact extending in the second horizontal direction between the second gate electrode and the third gate electrode and spaced apart from the second contact in the second horizontal direction and connected to the second drain region; a fifth contact extending in the second horizontal direction between the third gate electrode and the fourth gate electrode and spaced apart from the third contact in the second horizontal direction and connected to the fourth source region;and a through via intersecting the gate cut and connecting between the lower wiring layer and the first contact, wherein between the second gate electrode and the third gate electrode, each of the second contact and the fourth contact is electrically insulated from the lower wiring layer, and between the third gate electrode and the fourth gate electrode, each of the third contact and the fifth contact is electrically insulated from the lower wiring layer.

[0008] A semiconductor device according to one embodiment includes a lower interlayer insulating film, a first active pattern and a second active pattern each extending in a first horizontal direction on the lower interlayer insulating film and spaced apart in a second horizontal direction different from the first horizontal direction, a first plurality of nanosheets stacked vertically on the first active pattern at a distance from each other, a second plurality of nanosheets stacked vertically on the second active pattern at a distance from each other, a gate electrode extending in the second horizontal direction on the first active pattern and the second active pattern and surrounding the first plurality of nanosheets and the second plurality of nanosheets, a gate cut extending in the first horizontal direction between the first active pattern and the second active pattern and separating the gate electrode in the second horizontal direction, a first source region disposed on a first side of the gate electrode on the first active pattern, a second source region disposed on a second side of the gate electrode facing the first side of the gate electrode in the first horizontal direction on the first active pattern, and a second source region disposed on the first side of the gate electrode on the second active pattern. a third source region, a drain region disposed on a second side of the gate electrode on the second active pattern, a first contact extending in the second horizontal direction at a first side of the gate electrode and connected to each of the first source region and the third source region, a second contact extending in the second horizontal direction at a second side of the gate electrode and connected to the second source region, a third contact extending in the second horizontal direction at the second side of the gate electrode and connected to the drain region, spaced apart from the second contact in the second horizontal direction, a lower wiring layer disposed within the lower interlayer insulating film, extending in the first horizontal direction between the first active pattern and the second active pattern, at least a portion of which protrudes vertically from an upper surface of the lower interlayer insulating film under the first contact to vertically overlap each of the first active pattern and the second active pattern, and a through via disposed between the first source region and the third source region, intersecting a gate cut to connect between the lower wiring layer and the first contact, and formed integrally with the first contact.a lower insulating film disposed between an upper surface of the lower interlayer insulating film and lower surfaces of the first active pattern and the second active pattern, and in contact with the lower wiring layer; and a field insulating film disposed on the upper surface of the lower interlayer insulating film and surrounding each of a sidewall of the lower insulating film, a sidewall of the first active pattern, and a sidewall of the second active pattern, wherein, between a second source region and a drain region, each of a second contact and a third contact is electrically insulated from the lower wiring layer, and between the first source region and the third source region, an upper surface of the lower insulating film is formed higher than an upper surface of the lower wiring layer. Effect of the Invention

[0009] According to the semiconductor device of the present invention, the area in which the through vias are formed can be minimized, thereby reducing the difficulty of the process and improving the integration degree. [Brief description of the drawings]

[0010] [Figure 1] 1 is a layout diagram for explaining a semiconductor device according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view taken along line BB' in FIG. 1. [Figure 4] 2 is a cross-sectional view taken along line CC' in FIG. 1. [Diagram 5] 2 is a cross-sectional view taken along line DD' in FIG. [Figure 6] 2 is a cross-sectional view taken along line EE' in FIG. [Figure 7] 2 is a cross-sectional view taken along line FF' in FIG. [Figure 8] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 9] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 10]1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 11] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 12] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 13] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 14] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 15] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 16] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 17] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 18] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 19] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 20] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 21] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 22] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 23] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 24] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 25]1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 26] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 27] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 28] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 29] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 30] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 31] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 32] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 33] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 34] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 35] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 36] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 37] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 38] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 39] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 40]1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 41] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 42] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 43] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 44] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 45] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 46] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 47] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 48] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 49] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 50] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 51] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 52] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 53] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 54] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 55]1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 56] 1A to 1C are views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 57] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention. [Figure 58] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention. [Figure 59] FIG. 11 is a cross-sectional view illustrating a first example of a semiconductor device according to still another embodiment of the present invention. [Figure 60] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a second example of still another embodiment of the present invention. [Figure 61] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a third example of still another embodiment of the present invention. [Figure 62] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fourth example of still another embodiment of the present invention. [Figure 63] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fifth example of still another embodiment of the present invention. [Figure 64] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fifth example of still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the drawings relating to the semiconductor device according to the following embodiments, the semiconductor device is exemplarily a nanosheet-containing transistor (MBCFET). TMIn the following description, the semiconductor device includes a multi-bridge channel field effect transistor (MFFET), but the technical idea of ​​the present invention is not limited thereto. In other embodiments, the semiconductor device includes a fin field effect transistor (FinFET) including a channel region in a fin pattern shape, a tunneling FET, or a three-dimensional (3D) transistor. Furthermore, the semiconductor device according to still other embodiments includes a bipolar junction transistor or a lateral double diffused transistor (LDMOS), etc.

[0012] A semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS.

[0013] FIG. 1 is a layout diagram for explaining a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 1. FIG. 4 is a cross-sectional view taken along line C-C' in FIG. 1. FIG. 5 is a cross-sectional view taken along line D-D' in FIG. 1. FIG. 6 is a cross-sectional view taken along line E-E' in FIG. 1. FIG. 7 is a cross-sectional view taken along line F-F' in FIG. 1.

[0014] 1 to 7, a semiconductor device according to an embodiment of the present invention includes a lower interlayer insulating film 100, first and second active patterns (F1, F2), a lower insulating film 101, a field insulating film 105, first to eighth nanosheets (NW1 to NW8), first to fourth gate electrodes (G1 to G4), first to fourth gate spacers (111 to 114), a gate insulating film 121, a capping pattern 122, first to fourth source regions (S1 to S4), first and The second drain region (D1, D2), a first etching stop film 130, a first upper interlayer insulating film 140, a gate cut GC, first to fifth contacts (CA1 to CA5), first and second contact isolation layers (CAS1, CAS2), a through via VPR, a lower wiring layer 150, a second etching stop film 160, a second upper interlayer insulating film 165, first to fourth vias (V1 to V4), a third upper interlayer insulating film 170, and first to third upper wiring layers (181, 182, 183).

[0015] The lower interlayer insulating film 100 includes, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Examples of low dielectric constant materials include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen Silses Quioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethylcycloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), and TriMethylSilyl. Polyimide nanofoams such as Borate (TMSB), DiAcetoxyDitertiaryButoxySiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polypropylene oxide, CDO (Carbon Doped silicon) Oxide), OSG (Organo Silicate Glass), SiLK, Amorphous Fluorinated Carbon, silica Examples of suitable materials include, but are not limited to, aerogels, silica xerogels, mesoporous silica, or combinations thereof.

[0016] Hereinafter, the first horizontal direction DR1 and the second horizontal direction DR2 are defined as directions parallel to the upper surface of the lower interlayer insulating film 100. The second horizontal direction DR2 is defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 is defined as a direction perpendicular to the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 is defined as a direction perpendicular to the upper surface of the lower interlayer insulating film 100.

[0017] Each of the first and second active patterns (F1, F2) extends in a first horizontal direction DR1 on the upper surface of the lower interlayer insulating film 100. The second active pattern F2 is spaced apart from the first active pattern F1 in a second horizontal direction DR2. For example, each of the first and second active patterns (F1, F2) includes silicon. However, the technical idea of ​​the present invention is not limited thereto. In other embodiments, each of the first and second active patterns (F1, F2) includes silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0018] The lower insulating film 101 is disposed on an upper surface of the lower interlayer insulating film 100. The lower insulating film 101 protrudes from the upper surface of the lower interlayer insulating film 100 in a vertical direction DR3. For example, the lower insulating film 101 is disposed between an upper surface of the lower interlayer insulating film 100 and a lower surface of the first active pattern F1. Also, the lower insulating film 101 is disposed between an upper surface of the lower interlayer insulating film 100 and a lower surface of the second active pattern F2. For example, a sidewall of the lower insulating film 101 is aligned with each of the sidewalls of the first active pattern F1 and the sidewalls of the second active pattern F2. The lower insulating film 101 includes an insulating material. The lower insulating film 101 includes a material different from the field insulating film 105. For example, the lower insulating film 101 includes a material having an etching selectivity with the field insulating film 105.

[0019] The field insulating film 105 is disposed on the upper surface of the lower interlayer insulating film 100. The field insulating film 105 surrounds the sidewalls of the lower insulating film 101, the sidewalls of the first active pattern F1, and the sidewalls of the second active pattern F2. For example, at least a portion of each of the first and second active patterns (F1, F2) protrudes in the vertical direction DR3 from the upper surface of the field insulating film 105, but the technical idea of ​​the present invention is not limited thereto. The field insulating film 105 includes, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0020] Each of the first to fourth plurality of nanosheets (NW1, NW2, NW3, NW4) is disposed on the first active pattern F1. The second plurality of nanosheets NW2 is spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. The third plurality of nanosheets NW3 is spaced apart from the second plurality of nanosheets NW2 in the first horizontal direction DR1. The fourth plurality of nanosheets NW4 is spaced apart from the third plurality of nanosheets NW3 in the first horizontal direction DR1.

[0021] Each of the fifth to eighth plurality of nanosheets (NW5, NW6, NW7, NW8) is disposed on the second active pattern F2. The sixth plurality of nanosheets NW6 is spaced apart from the fifth plurality of nanosheets NW5 in the first horizontal direction DR1. The seventh plurality of nanosheets NW7 is spaced apart from the sixth plurality of nanosheets NW6 in the first horizontal direction DR1. The eighth plurality of nanosheets NW8 is spaced apart from the seventh plurality of nanosheets NW7 in the first horizontal direction DR1. Each of the fifth to eighth plurality of nanosheets (NW5, NW6, NW7, NW8) is spaced apart from each of the first to fourth plurality of nanosheets (NW1, NW2, NW3, NW4) in the second horizontal direction DR2.

[0022] Each of the first to eighth plurality of nanosheets (NW1 to NW8) includes a plurality of nanosheets stacked at a distance from one another in the vertical direction DR3. Although Figs. 1 to 3 show a case in which each of the first to eighth plurality of nanosheets (NW1 to NW8) includes three nanosheets stacked at a distance from one another in the vertical direction DR3, this is for convenience of explanation, and the technical idea of ​​the present invention is not limited thereto. In other embodiments, each of the first to eighth plurality of nanosheets (NW1 to NW8) includes four or more nanosheets stacked at a distance from one another in the vertical direction DR3.

[0023] For example, each of the first to eighth plurality of nanosheets (NW1 to NW8) includes silicon (Si). However, the technical idea of ​​the present invention is not limited thereto. In another embodiment, each of the first to eighth plurality of nanosheets (NW1 to NW8) includes silicon germanium (SiGe).

[0024] The first to fourth gate electrodes (G1, G2, G3, G4) each extend in the second horizontal direction DR2 on the first active pattern F1, the second active pattern F2, and the field insulating film 105. The second gate electrode G2 is spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The third gate electrode G3 is spaced apart from the second gate electrode G2 in the first horizontal direction DR1. The fourth gate electrode G4 is spaced apart from the third gate electrode G3 in the first horizontal direction DR1.

[0025] The first gate electrode G1 surrounds each of the first plurality of nanosheets NW1 and the fifth plurality of nanosheets NW5. The second gate electrode G2 surrounds each of the second plurality of nanosheets NW2 and the sixth plurality of nanosheets NW6. The third gate electrode G3 surrounds each of the third plurality of nanosheets NW3 and the seventh plurality of nanosheets NW7. The fourth gate electrode G4 surrounds each of the fourth plurality of nanosheets NW4 and the eighth plurality of nanosheets NW8.

[0026] Each of the first to fourth gate electrodes (G1, G2, G3, G4) is made of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride, or tantalum carbonitride. The first to fourth gate electrodes (G1, G2, G3, G4) each include at least one of conductive metal oxide, conductive metal oxynitride, and the oxidized form of the above-mentioned materials.

[0027] The first gate spacer 111 extends in the second horizontal direction DR2 along both side walls of the first gate electrode G1 on the upper surface of the topmost nanosheet of the first plurality of nanosheets NW1, the upper surface of the topmost nanosheet of the fifth plurality of nanosheets NW5, and the field insulating film 105. The second gate spacer 112 extends in the second horizontal direction DR2 along both side walls of the second gate electrode G2 on the upper surface of the topmost nanosheet of the second plurality of nanosheets NW2, the upper surface of the topmost nanosheet of the sixth plurality of nanosheets NW6, and the field insulating film 105. The third gate spacer 113 extends in the second horizontal direction DR2 along the upper surface of the topmost nanosheet of the third plurality of nanosheets NW3, the upper surface of the topmost nanosheet of the seventh plurality of nanosheets NW7, and the field insulating film 105 along both side walls of the third gate electrode G3. The fourth gate spacer 114 extends in the second horizontal direction DR2 along both sidewalls of the fourth gate electrode G4 on the upper surface of the uppermost nanosheet of the fourth plurality of nanosheets NW4, on the upper surface of the uppermost nanosheet of the eighth plurality of nanosheets NW8, and on the field insulating film 105.

[0028] Each of the first to fourth gate spacers (111, 112, 113, 114) is made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and at least one of combinations thereof. However, the technical idea of ​​the present invention is not limited thereto.

[0029] The gate insulating film 121 is disposed between the first gate electrode G1 and the first gate spacer 111. The gate insulating film 121 is disposed between the second gate electrode G2 and the second gate spacer 112. The gate insulating film 121 is disposed between the third gate electrode G3 and the third gate spacer 113. The gate insulating film 121 is disposed between the fourth gate electrode G4 and the fourth gate spacer 114. The gate insulating film 121 is disposed on the sidewalls of each of the first to fourth gate electrodes (G1, G2, G3, G4) in the first horizontal direction DR1. The gate insulating film 121 is disposed between each of the first to fourth gate electrodes (G1, G2, G3, G4) and the first and second active patterns (F1, F2). The gate insulating film 121 is disposed between each of the first to fourth gate electrodes (G1, G2, G3, G4) and the field insulating film 105.

[0030] The gate insulating film 121 is disposed between the first gate electrode G1 and each of the first and fifth plurality of nanosheets (NW1, NW5). The gate insulating film 121 is disposed between the second gate electrode G2 and each of the second and sixth plurality of nanosheets (NW2, NW6). The gate insulating film 121 is disposed between the third gate electrode G3 and each of the third and seventh plurality of nanosheets (NW3, NW7). The gate insulating film 121 is disposed between the fourth gate electrode G4 and each of the fourth and eighth plurality of nanosheets (NW4, NW8).

[0031] The gate insulating film 121 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a dielectric constant larger than that of silicon oxide. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0032] The semiconductor device according to another embodiment includes a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film 121 includes a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0033] The ferroelectric material film has a negative capacitance, and the paraelectric material film has a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is smaller than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance has a positive value and is larger than the absolute value of each individual capacitance.

[0034] When a ferroelectric material layer having a negative capacitance and a paraelectric material layer having a positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series increases. With the increase in the total capacitance value, a transistor including the ferroelectric material layer has a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0035] The ferroelectric material film has ferroelectric properties. The ferroelectric material film includes at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide is a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide is a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0036] The ferroelectric material film further includes a dopant. For example, the dopant includes at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film varies depending on which ferroelectric material the ferroelectric material film includes.

[0037] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film includes, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0038] When the dopant is aluminum (Al), the ferroelectric material film contains 3 to 8 at% (atomic %) of aluminum, where the ratio of the dopant is the ratio of aluminum to the total of hafnium and aluminum.

[0039] When the dopant is silicon (Si), the ferroelectric material film contains 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film contains 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film contains 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film contains 50 to 80 at% zirconium.

[0040] The paraelectric material film has paraelectric properties. The paraelectric material film includes at least one of silicon oxide and metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film includes at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0041] The ferroelectric material film and the paraelectric material film contain the same material. The ferroelectric material film has ferroelectric properties, but the paraelectric material film does not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0042] The ferroelectric material film has a thickness that provides ferroelectric properties. The thickness of the ferroelectric material film is, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness that exhibits ferroelectric properties differs for each ferroelectric material, the thickness of the ferroelectric material film differs depending on the ferroelectric material.

[0043] As an example, the gate insulating film 121 includes one ferroelectric material layer. As another example, the gate insulating film 121 includes a plurality of ferroelectric material layers spaced apart from each other. The gate insulating film 121 has a stacked film structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0044] The capping pattern 122 extends in the second horizontal direction DR2 on each of the first to fourth gate electrodes (G1, G2, G3, G4), the gate insulating film 121, and the first to fourth gate spacers (111, 112, 113, 114). The capping pattern 122 is made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and at least one of combinations thereof, although the technical idea of ​​the present invention is not limited thereto.

[0045] The first source region S1 is disposed on the first active pattern F1 between the first gate electrode G1 and the second gate electrode G2. The second source region S2 is disposed on the first active pattern F1 between the second gate electrode G2 and the third gate electrode G3. The first drain region D1 is disposed on the first active pattern F1 between the third gate electrode G3 and the fourth gate electrode G4. The third source region S3 is disposed on the second active pattern F2 between the first gate electrode G1 and the second gate electrode G2. The second drain region D2 is disposed on the second active pattern F2 between the second gate electrode G2 and the third gate electrode G3. The fourth source region S4 is disposed on the second active pattern F2 between the third gate electrode G3 and the fourth gate electrode G4.

[0046] For example, each of the first to fourth source regions (S1, S2, S3, S4) and the first and second drain regions (D1, D2) contacts the gate insulating film 121. However, the technical idea of ​​the present invention is not limited thereto. In another embodiment, an inner spacer is disposed between each of the first to fourth source regions (S1, S2, S3, S4) and the first and second drain regions (D1, D2) and the gate insulating film 121. In this case, the inner spacer is made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0047] The first upper interlayer insulating film 140 covers the first to fourth source regions (S1, S2, S3, S4) and the first and second drain regions (D1, D2) on the field insulating film 105. The first upper interlayer insulating film 140 surrounds the sidewalls of the first to fourth gate spacers (111, 112, 113, 114) and the capping pattern 122. For example, the top surface of the first upper interlayer insulating film 140 is formed on the same plane as the top surface of the capping pattern 122, but the technical idea of ​​the present invention is not limited thereto. The first upper interlayer insulating film 140 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material, for example.

[0048] The first etch stop layer 130 is disposed between each of the first to fourth source regions (S1, S2, S3, S4), the first and second drain regions (D1, D2), and the first upper interlayer insulating film 140. The first etch stop layer 130 is disposed between each of the sidewalls of the first to fourth gate spacers (111, 112, 113, 114) and the capping pattern 122, and the first upper interlayer insulating film 140. The first etch stop layer 130 is disposed between the field insulating film 105 and the first upper interlayer insulating film 140. For example, the first etch stop layer 130 is formed conformally. The first etch stop layer 130 includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0049] The gate cut GC extends in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. For example, the gate cut GC separates each of the first to fourth gate electrodes (G1, G2, G3, G4) in the second horizontal direction DR2. For example, the gate cut GC extends from the upper surface of the capping pattern 122 to the inside of the field insulating film 105. Although not shown, the gate cut GC extends from the upper surface of the first upper interlayer insulating film 140 to the inside of the field insulating film 105.

[0050] For example, the gate cut GC is disposed between the first source region S1 and the third source region S3, between the second source region S2 and the second drain region D2, and between the first drain region D1 and the fourth source region S4. For example, the gate cut GC is spaced apart from each of the first to fourth source regions (S1, S2, S3, S4) and the first and second drain regions (D1, D2) in the second horizontal direction DR2. The gate cut GC is made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), or a combination thereof, but the technical idea of ​​the present invention is not limited thereto.

[0051] Each of the first to fifth contacts (CA1 to CA5) is disposed inside the first upper interlayer insulating film 140. The first contact CA1 extends in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The first contact CA1 crosses the gate cut GC. For example, the gate cut GC is not disposed in the portion where the first contact CA1 is disposed. That is, the first contact CA1 separates the gate cut GC in the first horizontal direction DR1. The first contact CA1 is connected to each of the first source region S1 and the third source region S3.

[0052] The second contact CA2 extends in the second horizontal direction DR2 between the second gate electrode G2 and the third gate electrode G3. For example, the gate cut GC is spaced apart from the second contact CA2 in the second horizontal direction DR2. The second contact CA2 is coupled to the second source region S2. The third contact CA3 extends in the second horizontal direction DR2 between the third gate electrode G3 and the fourth gate electrode G4. For example, the gate cut GC is spaced apart from the third contact CA3 in the second horizontal direction DR2. The third contact CA3 is coupled to the first drain region D1.

[0053] The fourth contact CA4 extends in the second horizontal direction DR2 between the second gate electrode G2 and the third gate electrode G3. The fourth contact CA4 is spaced apart from the second contact CA2 in the second horizontal direction DR2. For example, the fourth contact CA4 is spaced apart from the gate cut GC in the second horizontal direction DR2. The fourth contact CA4 is coupled to the second drain region D2. The fifth contact CA5 extends in the second horizontal direction DR2 between the third gate electrode G3 and the fourth gate electrode G4. The fifth contact CA5 is spaced apart from the third contact CA3 in the second horizontal direction DR2. For example, the fifth contact CA5 is spaced apart from the gate cut GC in the second horizontal direction DR2. The fifth contact CA5 is coupled to the fourth source region S4.

[0054] For example, each of the first to fifth contacts (CA1 to CA5) is formed of a single film. Each of the first to fifth contacts (CA1 to CA5) includes a conductive material. Each of the first to fifth contacts (CA1 to CA5) includes at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0055] The silicide layer SL is disposed between the first contact CA1 and each of the first source region S1 and the third source region S3. The silicide layer SL is disposed between the second contact CA2 and the second source region S2. The silicide layer SL is disposed between the third contact CA3 and the first drain region D1. The silicide layer SL is disposed between the fourth contact CA4 and the second drain region D2. The silicide layer SL is disposed between the fifth contact CA5 and the fourth source region S4. The silicide layer SL includes, for example, a metal silicide material.

[0056] Each of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 is disposed inside the first upper interlayer insulating film 140. For example, each of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 is disposed on the gate cut GC. For example, each of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 has an upper surface formed on the same plane as an upper surface of the first upper interlayer insulating film 140.

[0057] The first contact isolation layer CAS1 is disposed between the second contact CA2 and the fourth contact CA4. The first contact isolation layer CAS1 separates the second contact CA2 and the fourth contact CA4 in the second horizontal direction DR2. The second contact isolation layer CAS2 is disposed between the third contact CA3 and the fifth contact CA5. The second contact isolation layer CAS2 separates the third contact CA3 and the fifth contact CA5 in the second horizontal direction DR2. For example, the width of the first contact isolation layer CAS1 in the second horizontal direction DR2 is larger than the width of the second contact isolation layer CAS2 in the second horizontal direction DR2.

[0058] For example, the lower surface of each of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 is formed lower than the lower surfaces of each of the first to fifth contacts (CA1 to CA5). However, the technical idea of ​​the present invention is not limited thereto. Each of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 includes a material different from the first upper interlayer insulating film 140. For example, each of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 includes at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof.

[0059] The through via VPR is disposed inside the first upper interlayer insulating film 140. The through via VPR is disposed between the first gate electrode G1 and the second gate electrode G2. The through via VPR is disposed between the first source region S1 and the third source region S3. A sidewall of the through via VPR is spaced in the second horizontal direction DR2 from the first etch stop layer 130 disposed on the sidewalls in the second horizontal direction DR2 of each of the first source region S1 and the third source region S3. The through via VPR is disposed under the first contact CA1. The through via VPR is connected to the lower surface of the first contact CA1. That is, the upper surface of the through via VPR contacts the lower surface of the first contact CA1.

[0060] For example, the through via VPR intersects with the gate cut GC. The through via VPR is not disposed between the second source region S2 and the second drain region D2. Also, the through via VPR is not disposed between the first drain region D1 and the fourth source region S4. That is, the through via VPR is disposed only between the first source region S1 and the third source region S3.

[0061] For example, the through via VPR is integrally formed with the first contact CA1. For example, the through via VPR is formed of a single layer. For example, the through via VPR includes the same material as the first contact CA1. That is, the through via VPR includes at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo). For example, the width of the through via VPR in the second horizontal direction DR2 increases continuously as it approaches the bottom surface of the first contact CA1.

[0062] The lower wiring trench 150T is formed inside the lower interlayer insulating film 100. The lower wiring trench 150T extends in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. For example, at least a part of the lower wiring trench 150T is formed inside the field insulating film 105. For example, between the first source region S1 and the third source region S3, the lower wiring trench 150T is formed inside the lower interlayer insulating film 100 and the field insulating film 105. For example, between the first source region S1 and the third source region S3, both side walls of the lower wiring trench 150T in the second horizontal direction DR2 are defined by the lower interlayer insulating film 100 and the lower insulating film 101. For example, in the remaining region except between the first source region S1 and the third source region S3, the lower wiring trench 150T is not formed inside the field insulating film 105. However, the technical idea of ​​the present invention is not limited thereto.

[0063] The lower wiring layer 150 is disposed inside the lower wiring trench 150T. The lower wiring layer 150 extends in a first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. For example, the lower wiring layer 150 overlaps the gate cut GC in a vertical direction DR3. For example, the lower wiring layer 150 overlaps the lower insulating film 101 in the vertical direction DR3. For example, the lower wiring layer 150 overlaps each of the first active pattern F1 and the second active pattern F2 in the vertical direction DR3. For example, the lower wiring layer 150 is spaced apart from each of the first active pattern F1 and the second active pattern F2.

[0064] For example, between the first source region S1 and the third source region S3, at least a part of the lower wiring layer 150 protrudes in the vertical direction DR3 from the upper surface of the lower interlayer insulating film 100. For example, between the first source region S1 and the third source region S3, the upper surface of the lower insulating film 101 is formed higher than the upper surface of the lower wiring layer 150. For example, between the first source region S1 and the third source region S3, the sidewall of the lower wiring layer 150 contacts the sidewall of the lower insulating film 101. For example, between the first source region S1 and the third source region S3, the upper surface of the lower wiring layer 150 contacts the field insulating film 105, the first etch stop film 130, the first upper interlayer insulating film 140, and the through via VPR.

[0065] For example, below each of the first to fourth gate electrodes (G1, G2, G3, G4), the upper surface of the lower wiring layer 150 is formed on the same plane as the upper surface of the lower interlayer insulating film 100. Between the second source region S2 and the second drain region D2, the upper surface of the lower wiring layer 150 is formed on the same plane as the upper surface of the lower interlayer insulating film 100. Between the first drain region D1 and the fourth source region S4, the upper surface of the lower wiring layer 150 is formed on the same plane as the upper surface of the lower interlayer insulating film 100.

[0066] For example, below each of the first to fourth gate electrodes (G1, G2, G3, G4), the upper surface of the lower wiring layer 150 contacts the lower surface of the lower insulating film 101 and the lower surface of the field insulating film 105. Between the second source region S2 and the second drain region D2, the upper surface of the lower wiring layer 150 contacts the lower surface of the lower insulating film 101 and the lower surface of the field insulating film 105. Between the first drain region D1 and the fourth source region S4, the upper surface of the lower wiring layer 150 contacts the lower surface of the lower insulating film 101 and the lower surface of the field insulating film 105.

[0067] For example, below each of the first to fourth gate electrodes (G1, G2, G3, G4), the upper surface of the lower wiring layer 150 is spaced apart from the gate cut GC in the vertical direction DR3. Between the second source region S2 and the second drain region D2, the upper surface of the lower wiring layer 150 is spaced apart from the gate cut GC in the vertical direction DR3. Between the first drain region D1 and the fourth source region S4, the upper surface of the lower wiring layer 150 is spaced apart from the gate cut GC in the vertical direction DR3.

[0068] The lower wiring layer 150 includes a conductive material. For example, the lower wiring layer 150 is a power rail or a ground rail. Although FIGS. 4 to 7 show the case where the lower wiring layer 150 is formed of a single layer, the technical idea of ​​the present invention is not limited thereto. In another embodiment, the lower wiring layer 150 is formed of multiple layers. For example, the width of the lower wiring layer 150 in the second horizontal direction DR2 increases continuously as it approaches the lower surface of the lower interlayer insulating film 100.

[0069] For example, the lower wiring layer 150 is electrically connected to the first contact CA1 through the through via VPR. For example, between the second source region S2 and the second drain region D2, the lower wiring layer 150 is electrically insulated from each of the second contact CA2 and the fourth contact CA4. That is, between the second gate electrode G2 and the third gate electrode G3, the lower wiring layer 150 is electrically insulated from each of the second contact CA2 and the fourth contact CA4. Also, between the first drain region D1 and the fourth source region S4, the lower wiring layer 150 is electrically insulated from each of the third contact CA3 and the fifth contact CA5. That is, between the third gate electrode G3 and the fourth gate electrode G4, the lower wiring layer 150 is electrically insulated from each of the third contact CA3 and the fifth contact CA5.

[0070] The second etch stop layer 160 is disposed on the upper surfaces of the first upper interlayer insulating layer 140, the capping pattern 122, the gate cut GC, the first and second contact isolation layers (CAS1, CAS2), and the first to fifth contacts (CA1 to CA5). Although FIGS. 2 to 7 show the case where the second etch stop layer 160 is formed as a single layer, the technical idea of ​​the present invention is not limited thereto. In another embodiment, the second etch stop layer 160 is formed as a multi-layer. The second etch stop layer 160 includes at least one of, for example, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The second upper interlayer insulating layer 165 is disposed on the second etch stop layer 160. The second upper interlayer insulating layer 165 includes at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0071] The first via V1 penetrates the second upper interlayer insulating film 165 and the second etch stop film 160 in the vertical direction DR3 to be connected to the first contact CA1. The second via V2 penetrates the second upper interlayer insulating film 165 and the second etch stop film 160 in the vertical direction DR3 to be connected to the third contact CA3. The third via V3 penetrates the second upper interlayer insulating film 165 and the second etch stop film 160 in the vertical direction DR3 to be connected to the fourth contact CA4. The fourth via V4 penetrates the second upper interlayer insulating film 165 and the second etch stop film 160 in the vertical direction DR3 to be connected to the fifth contact CA5.

[0072] 2 to 7 show the first to fourth vias (V1, V2, V3, V4) each formed of a single layer, but this is for convenience of explanation and the technical idea of ​​the present invention is not limited thereto. In other embodiments, the first to fourth vias (V1, V2, V3, V4) each formed of multiple layers. Each of the first to fourth vias (V1, V2, V3, V4) includes a conductive material.

[0073] The third upper interlayer insulating film 170 is disposed on the second upper interlayer insulating film 165. The third upper interlayer insulating film 170 includes at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Each of the first to third upper wiring layers (181, 182, 183) is disposed inside the third upper interlayer insulating film 170. For example, each of the first to third upper wiring layers (181, 182, 183) extends in the first horizontal direction DR1.

[0074] For example, the second upper wiring layer 182 is spaced apart from the first upper wiring layer 181 in the second horizontal direction DR2. The third upper wiring layer 183 is spaced apart from the second upper wiring layer 182 in the second horizontal direction DR2. For example, the first upper wiring layer 181 is electrically connected to the third contact CA3 through the second via V2. The second upper wiring layer 182 is electrically connected to the first contact CA1 through the first via V1. In addition, the second upper wiring layer 182 is electrically connected to the fifth contact CA5 through the fourth via V4. The third upper wiring layer 183 is electrically connected to the fourth contact CA4 through the third via V3.

[0075] Each of the first to third upper wiring layers (181, 182, 183) includes a conductive material. Although FIGS. 2 to 7 show the first to third upper wiring layers (181, 182, 183) formed of a single film, the technical idea of ​​the present invention is not limited thereto. In another embodiment, each of the first to third upper wiring layers (181, 182, 183) is formed of multiple films. For example, the widths of the first to third upper wiring layers (181, 182, 183) in the second horizontal direction DR2 are successively decreased toward the top surface of the second upper interlayer insulating film 165.

[0076] In the semiconductor device according to an embodiment of the present invention, the through via VPR is formed only under the contact CA1 connected to the two source regions (S1, S3), and the through via VPR is not formed under the remaining contacts (CA2, CA3, CA4, CA5). As a result, the semiconductor device according to an embodiment of the present invention can minimize the area where the through via VPR is formed, thereby reducing process difficulty and improving the integration degree of the semiconductor device.

[0077] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS.

[0078] 8 to 56 are views of intermediate stages illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0079] 8 and 9, a stacked structure 20 is formed on a substrate 10. The substrate 10 is a silicon substrate or SOI (silicon-on-insulator). Alternatively, the substrate 10 may include silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the technical idea of ​​the present invention is not limited thereto.

[0080] The laminated structure 20 includes a first semiconductor layer 21 and a second semiconductor layer 22 alternately laminated on the substrate 10. For example, the first semiconductor layer 21 is formed at the bottom of the laminated structure 20, and the second semiconductor layer 22 is formed at the top of the laminated structure 20. However, the technical idea of ​​the present invention is not limited thereto. In another embodiment, the first semiconductor layer 21 is also formed at the top of the laminated structure 20. The first semiconductor layer 21 includes, for example, silicon germanium (SiGe). The second semiconductor layer 22 includes, for example, silicon (Si).

[0081] Next, a portion of the laminated structure 20 is etched. While the laminated structure 20 is being etched, a portion of the substrate 10 is also etched. This etching process defines a first active pattern F1 and a second active pattern F2 on the upper surface of the substrate 10 and below the laminated structure 20. The first active pattern F1 and the second active pattern F2 each extend in a first horizontal direction DR1. The second active pattern F2 is spaced apart from the first active pattern F1 in a second horizontal direction DR2.

[0082] Next, a field insulating film 105 is formed on the upper surface of the substrate 10. The field insulating film 105 surrounds the sidewalls of the first active pattern F1 and the second active pattern F2. Next, a pad oxide film 30 is formed so as to cover the upper surface of the field insulating film 105, the exposed sidewalls of the first active pattern F1, the sidewalls of the second active pattern F2, and the sidewalls and upper surface of the stacked structure 20. For example, the pad oxide film 30 is formed conformally. The pad oxide film 30 is formed of, for example, silicon oxide (SiO 2 ).

[0083] 10 and 11, first to fourth dummy gates (DG1, DG2, DG3, DG4) and first to fourth dummy capping patterns (DC1, DC2, DC3, DC4) extending in the second horizontal direction DR2 are formed on the pad oxide film 30 on the stacked structure 20 and the field insulating film 105. The first dummy capping pattern DC1 is formed on the first dummy gate DG1, the second dummy capping pattern DC2 is formed on the second dummy gate DG2, the third dummy capping pattern DC3 is formed on the third dummy gate DG3, and the fourth dummy capping pattern DC4 is formed on the fourth dummy gate DG4.

[0084] The second dummy gate DG2 and the second dummy capping pattern DC2 are spaced apart in the first horizontal direction DR1 from the first dummy gate DG1 and the first dummy capping pattern DC1. The third dummy gate DG3 and the third dummy capping pattern DC3 are spaced apart in the first horizontal direction DR1 from the second dummy gate DG2 and the second dummy capping pattern DC2. The fourth dummy gate DG4 and the fourth dummy capping pattern DC4 are spaced apart in the first horizontal direction DR1 from the third dummy gate DG3 and the third dummy capping pattern DC3.

[0085] While the first to fourth dummy gates (DG1, DG2, DG3, DG4) and the first to fourth dummy capping patterns (DC1, DC2, DC3, DC4) are formed, the remaining pad oxide film 30 is removed on the substrate 10 except for the portions overlapping the first to fourth dummy gates (DG1, DG2, DG3, DG4) in the vertical direction DR3.

[0086] Next, a spacer material layer SM is formed so as to cover the sidewalls of the first to fourth dummy gates (DG1, DG2, DG3, DG4), the sidewalls and upper surface of the first to fourth dummy capping patterns (DC1, DC2, DC3, DC4), the sidewalls and upper surface of the exposed stacked structure 20, and the upper surface of the field insulating film 105. For example, the spacer material layer SM is formed conformally. The spacer material layer SM includes at least one of, for example, silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof.

[0087] 12 to 14, the stacked structure (20 in FIG. 10) is etched using the first to fourth dummy gates (DG1, DG2, DG3, DG4) and the first to fourth dummy capping patterns (DC1, DC2, DC3, DC4) as a mask to form the first to third source / drain trenches (ST1, ST2, ST3). For example, the first source / drain trench ST1 is formed on the first active pattern F1 between the first dummy gate DG1 and the second dummy gate DG2. The second source / drain trench ST2 is formed on the first active pattern F1 between the second dummy gate DG2 and the third dummy gate DG3. The third source / drain trench ST3 is formed on the first active pattern F1 between the third dummy gate DG3 and the fourth dummy gate DG4. For example, each of the first to third source / drain trenches (ST1, ST2, ST3) extends into the first active pattern F1. Although not shown, source / drain trenches having shapes similar to those of the first to third source / drain trenches (ST1, ST2, ST3) are formed on the second active pattern F2.

[0088] During the formation of the first to third source / drain trenches (ST1, ST2, ST3), the spacer material layer (SM in FIG. 10) formed on the upper surfaces of the first to fourth dummy capping patterns (DC1, DC2, DC3, DC4) and a portion of each of the first to fourth dummy capping patterns (DC1, DC2, DC3, DC4) are etched. The spacer material layer (SM in FIG. 10) remaining on the sidewalls of each of the first to fourth dummy gates (DG1, DG2, DG3, DG4) are defined as first to fourth gate spacers (111, 112, 113, 114).

[0089] After the first to third source / drain trenches (ST1, ST2, ST3) are formed, the second semiconductor layer (22 in Figure 10) remaining under each of the first to fourth dummy gates (DG1, DG2, DG3, DG4) is defined as the first to eighth nanosheets (NW1 to NW8 in Figures 2 and 3).

[0090] 15 to 17, a first source region S1 is formed inside the first source / drain trench (ST1 in FIG. 12), a second source region S2 is formed inside the second source / drain trench (ST2 in FIG. 12), and a first drain region D1 is formed inside the third source / drain trench (ST3 in FIG. 12). Although not shown, a third source region (S3 in FIG. 3) is formed between the fifth plurality of nanosheets (NW5 in FIG. 3) and the sixth plurality of nanosheets (NW6 in FIG. 3), a second drain region (D2 in FIG. 3) is formed between the sixth plurality of nanosheets (NW6 in FIG. 3) and the seventh plurality of nanosheets (NW7 in FIG. 3), and a fourth source region (S4 in FIG. 3) is formed between the seventh plurality of nanosheets (NW7 in FIG. 3) and the eighth plurality of nanosheets (NW8 in FIG. 3).

[0091] Next, a first etch stop film 130 is formed on the exposed surface of the field insulating film 105, the exposed surfaces of the first to fourth source regions (S1 to S4), the exposed surfaces of the first and second drain regions (D1, D2), and the exposed sidewalls of the first to fourth gate spacers (111, 112, 113, 114). Next, a first upper interlayer insulating film 140 is formed on the first etch stop film 130. Next, a planarization process is performed to expose the upper surfaces of the first to fourth dummy gates (DG1, DG2, DG3, DG4).

[0092] 18 and 19, the first to fourth dummy gates (DG1, DG2, DG3, DG4), the first semiconductor layer 21, and the pad oxide film 30 are etched.

[0093] 20 and 21, a gate insulating film 121, first to fourth gate electrodes (G1, G2, G3, G4) and a capping pattern 122 are sequentially formed in the portions where the first to fourth dummy gates (DG1, DG2, DG3, DG4), the first semiconductor layer 21, and the pad oxide film 30 are etched.

[0094] 22 to 25, a gate cut GC is formed between a first active pattern F1 and a second active pattern F2. The gate cut GC extends in a first horizontal direction DR1. For example, the gate cut GC separates the second gate electrode G2 in a second horizontal direction DR2. The gate cut GC extends from each of an upper surface of the capping pattern 122 and an upper surface of the first upper interlayer insulating film 140 to the inside of the field insulating film 105.

[0095] Next, a first contact isolation layer CAS1 and a second contact isolation layer CAS2 are formed inside the first upper interlayer insulating film 140. For example, the upper surfaces of the first contact isolation layer CAS1 and the second contact isolation layer CAS2 are formed on the same plane as the upper surface of the first upper interlayer insulating film 140. For example, the first contact isolation layer CAS1 is formed between the second source region S2 and the second drain region D2. The second contact isolation layer CAS2 is formed between the first drain region D1 and the fourth source region S4.

[0096] 26 to 30, first to fifth contact trenches (CT1 to CT5) are formed inside the first upper interlayer insulating film 140. For example, the first contact trench CT1 is formed on each of the first source region S1 and the third source region S3. The second contact trench CT2 is formed on the second source region S2. The third contact trench CT3 is formed on the first drain region D1. The fourth contact trench CT4 is formed on the second drain region D2. The fifth contact trench CT5 is formed on the fourth source region S4.

[0097] 31 to 33, a protective layer 40 is formed on each of the first upper interlayer insulating film 140, the first contact isolation layer CAS1, the second contact isolation layer CAS2, the first to fourth source regions (S1 to S4), and the first and second drain regions (D1, D2). The protective layer 40 includes, for example, SOH (Spin On Hardmask). Next, a mask pattern M is formed on the protective layer 40. The mask pattern M exposes a portion of the protective layer 40 formed between the first source region S1 and the third source region S3.

[0098] Next, the protective layer 40, the first upper interlayer insulating film 140, and the gate cut GC are etched using the mask pattern M as a mask to form a through-via trench VPRT. For example, the bottom surface of the through-via trench VPRT is defined by the first etch stop film 130 formed on the top surface of the field insulating film 105 and a part of the gate cut GC.

[0099] 34 to 36, the mask pattern M and the protective layer 40 are removed. As a result, a first contact trench CT1 is formed on the through-via trench VPRT. Also, second to fifth contact trenches (CT2, CT3, CT4, CT5) are formed inside the first upper interlayer insulating film 140, respectively.

[0100] 37 to 41, a through via VPR is formed inside a through via trench (VPRT in FIG. 34), and a first contact CA1 is formed inside a first contact trench (CT1 in FIG. 34). The through via VPR and the first contact CA1 are formed by the same manufacturing process. The through via VPR and the first contact CA1 are integrally formed. In addition, the through via VPR and the first contact CA1 include the same material.

[0101] In addition, a second contact CA2 is formed inside the second contact trench (CT2 in Figure 35), a third contact CA3 is formed inside the third contact trench (CT3 in Figure 36), a fourth contact CA4 is formed inside the fourth contact trench (CT4 in Figure 35), and a fifth contact CA5 is formed inside the fifth contact trench (CT5 in Figure 36).

[0102] 42 to 47, a second etch stop layer 160 and a second upper interlayer insulating film 165 are sequentially formed on the upper surfaces of the first upper interlayer insulating film 140, the capping pattern 122, the gate cut GC, the first and second contact isolation layers (CAS1, CAS2), and the first to fifth contacts (CA1 to CA5). Next, first to fourth vias (V1, V2, V3, V4) are formed through the second upper interlayer insulating film 165 and the second etch stop layer 160 in the vertical direction DR3 and are individually connected to the first contact CA1, the third contact CA3, the fourth contact CA4, and the fifth contact CA5, respectively. Next, a third upper interlayer insulating film 170 and first to third upper wiring layers (181, 182, 183) are formed on the second upper interlayer insulating film 165.

[0103] 48 to 50, the substrate (10 in FIGS. 42 to 47) is etched to expose the lower surface of the field insulating film 105. Also, a part of the first active pattern F1 and a part of the second active pattern F2 are etched. For example, the lower surfaces of the remaining first active pattern F1 and second active pattern F2 are formed higher than the upper surface of the field insulating film 105 adjacent to the gate cut GC.

[0104] 51 to 53, a lower insulating film 101 is formed in a portion where a part of the first active pattern F1 and a part of the second active pattern F2 are etched. Next, a planarization process is performed so that the lower surface of the lower insulating film 101 and the lower surface of the field insulating film 105 are flush with each other.

[0105] 54 to 56, a lower interlayer insulating film 100 is formed on the lower surfaces of the lower insulating film 101 and the field insulating film 105. Next, a lower wiring trench 150T is formed inside the lower interlayer insulating film 100. The lower wiring trench 150T extends in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2.

[0106] For example, between the first source region S1 and the third source region S3, the upper surface of the lower wiring trench 150T exposes the lower surface of the through via VPR. For example, between the first source region S1 and the third source region S3, both side walls of the lower wiring trench 150T in the second horizontal direction DR2 are defined by the lower interlayer insulating film 100 and the lower insulating film 101. For example, in the remaining region except between the first source region S1 and the third source region S3, the upper surface of the lower wiring trench 150T is defined by the lower surface of the field insulating film 105.

[0107] 2 to 7, a lower wiring layer 150 is formed inside the lower wiring trench 150T. The lower wiring layer 150 extends in a first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. Between the first source region S1 and the third source region S3, the lower wiring layer 150 is connected to the through via VPR. Through these manufacturing processes, the semiconductor device shown in FIGS. 2 to 7 is manufactured.

[0108] A semiconductor device according to another embodiment of the present invention will be described below with reference to Figures 57 and 58. The differences from the semiconductor device shown in Figures 1 to 7 will be mainly described.

[0109] 57 and 58 are cross-sectional views illustrating a semiconductor device according to another embodiment of the present invention.

[0110] 57 and 58, in a semiconductor device according to another embodiment of the present invention, the through via VPR2 and the first to third contacts (CA21, CA22, CA23) are each formed of a double film. Although not shown, the fourth and fifth contacts are also formed of a double film.

[0111] For example, the through via VPR2 and each of the first to third contacts (CA21, CA22, CA23) include a contact barrier layer 291 and a contact filling layer 292. The contact barrier layer 291 forms the sidewalls and bottom surfaces of the through via VPR2 and each of the first to third contacts (CA21, CA22, CA23). However, the contact barrier layer 291 is not disposed between the through via VPR2 and the first contact CA21. The contact filling layer 292 is disposed on the contact barrier layer 291 of each of the through via VPR2 and the first to third contacts (CA21, CA22, CA23). For example, the upper surface of the contact filling layer 292 of the through via VPR2 contacts the lower surface of the contact filling layer 292 of the first contact CA21.

[0112] Each of the contact barrier layer 291 and the contact fill layer 292 includes a conductive material. The contact barrier layer 291 includes at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The contact fill layer 292 includes at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0113] A first example of a semiconductor device according to still another embodiment of the present invention will be described below with reference to Fig. 59. The following will focus on the differences from the semiconductor device shown in Figs.

[0114] FIG. 59 is a cross-sectional view illustrating a first example of a semiconductor device according to still another embodiment of the present invention.

[0115] 59, in a semiconductor device according to a first example of still another embodiment of the present invention, a lower wiring layer 350 is spaced apart from a lower insulating film 301 in a second horizontal direction DR2.

[0116] For example, the lower wiring trench 350T is formed between the lower insulating film 301 disposed under the first active pattern F1 and the lower insulating film 301 disposed under the second active pattern F2. The lower wiring layer 350 is disposed inside the lower wiring trench 350T. The lower wiring layer 350 is spaced apart in the second horizontal direction DR2 from the lower insulating film 301 disposed under the first active pattern F1 and the lower insulating film 301 disposed under the second active pattern F2.

[0117] For example, the lower wiring layer 350 does not overlap the first active pattern F1 and the second active pattern F2 in the vertical direction DR3. In addition, the lower wiring layer 350 does not overlap the lower insulating film 301 disposed below the first active pattern F1 and the lower insulating film 301 disposed below the second active pattern F2 in the vertical direction DR3.

[0118] A semiconductor device according to a second example of yet another embodiment of the present invention will be described below with reference to Fig. 60. The following will focus on the differences from the semiconductor device shown in Figs.

[0119] FIG. 60 is a cross-sectional view illustrating a second example of a semiconductor device according to still another embodiment of the present invention.

[0120] 60, in a second example semiconductor device according to yet another embodiment of the present invention, a lower wiring layer 450 is spaced apart from each of a first active pattern F41 and a second active pattern F42 in a second horizontal direction DR2, and a lower insulating film (101 in FIGS. 2 to 7) is not disposed.

[0121] For example, the lower surfaces of the first and second active patterns F41 and F42 contact the upper surface of the lower interlayer insulating film 100. A lower wiring trench 450T is formed between the first and second active patterns F41 and F42. The lower wiring layer 450 is disposed inside the lower wiring trench 450T. The lower wiring layer 450 is spaced apart from the first and second active patterns F41 and F42 in the second horizontal direction DR2. For example, the lower wiring layer 450 does not overlap the first and second active patterns F41 and F42 in the vertical direction DR3.

[0122] A semiconductor device according to a third example of still another embodiment of the present invention will be described below with reference to Fig. 61. The following description will focus on the differences from the semiconductor device shown in Figs.

[0123] FIG. 61 is a cross-sectional view illustrating a third example of a semiconductor device according to still another embodiment of the present invention.

[0124] 61, in a semiconductor device according to a third example of the present invention, a portion of a sidewall of the through via VPR5 in the second horizontal direction DR2 contacts the first etch stop layer 130. In the semiconductor device according to the third example of the present invention, as shown in FIG.

[0125] For example, the through via VPR5 includes a first portion VPR5_1 in contact with the lower wiring layer 150 and a second portion VPR5_2 in contact with the first contact CA1. For example, a sidewall in the second horizontal direction DR2 of the first portion VPR5_1 of the through via VPR5 is spaced in the second horizontal direction DR2 from a first etch stop film 130 disposed on each sidewall in the second horizontal direction DR2 of the first source region S1 and the third source region S3. A first upper interlayer insulating film 140 is disposed between a sidewall in the second horizontal direction DR2 of the first portion VPR5_1 of the through via VPR5 and the first etch stop film 130. For example, a sidewall in the second horizontal direction DR2 of the second portion VPR5_2 of the through via VPR5 is in contact with the first etch stop film 130 disposed on each sidewall in the second horizontal direction DR2 of the first source region S1 and the third source region S3.

[0126] A fourth example of a semiconductor device according to still another embodiment of the present invention will be described below with reference to Fig. 62. The following description will focus on the differences from the semiconductor device shown in Figs.

[0127] FIG. 62 is a cross-sectional view illustrating a fourth example of a semiconductor device according to still another embodiment of the present invention.

[0128] 62, in a semiconductor device according to a fourth embodiment of the present invention, the sidewall of the through via VPR6 in the second horizontal direction DR2 is in contact with the first etch stop layer 130 entirely.

[0129] For example, the sidewall of the through via VPR6 in the second horizontal direction DR2 is entirely in contact with the first etch stop layer 130 between the first source region S1 and the third source region S3. That is, the first upper interlayer insulating film 140 is not disposed between the sidewall of the through via VPR6 in the second horizontal direction DR2 and the first etch stop layer 130.

[0130] A semiconductor device according to a fifth example of still another embodiment of the present invention will be described below with reference to Figures 63 and 64. The following description will focus on the differences from the semiconductor device shown in Figures 1 to 7.

[0131] 63 and 64 are cross-sectional views illustrating a semiconductor device of a fifth example according to still another embodiment of the present invention.

[0132] 63 and 64, in a fifth example of a semiconductor device according to still another embodiment of the present invention, a lower wiring layer 750 extends in a second horizontal direction DR2.

[0133] For example, the bottom wiring trench 750T is formed inside the lower interlayer insulating film 100. The bottom wiring trench 750T extends in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The bottom wiring trench 750T extends in the vertical direction DR3 below each of the first source region S1 and the third source region S3. For example, the top surface of the bottom wiring trench 750T below each of the first source region S1 and the third source region S3 is defined as the bottom surface of each of the first source region S1 and the third source region S3.

[0134] For example, the lower wiring layer 750 is disposed inside the lower wiring trench 750T. The lower wiring layer 750 extends in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The lower wiring layer 750 protrudes in the vertical direction DR3 from the upper surface of the lower interlayer insulating film 100 below each of the first source region S1 and the third source region S3. The sidewall of the lower wiring layer 750 protruding in the vertical direction DR3 from the upper surface of the lower interlayer insulating film 100 is surrounded by the first active pattern F61 and the field insulating film 105. For example, the lower wiring layer 750 contacts the lower surfaces of each of the first source region S1 and the third source region S3.

[0135] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0136] 10 Substrate 20 Laminated structure 21, 22 First and second semiconductor layers 30 Pad oxide film 100 Lower interlayer insulating film 101, 301 Lower insulating film 105 Field Insulation Film 111~114 1st~4th gate spacers 121 Gate insulating film 122 Capping Pattern 130, 160 First and second etching stop films 140, 165, 170 First to third upper interlayer insulating films 150, 350, 450, 750 Bottom wiring layer 150T, 350T, 450T, 750T Bottom Wiring Trench 181, 182, 183 1st to 3rd upper wiring layer 291 Contact Barrier Layer 292 Contact filling layer CA1, CA21 1st Contact CA2, CA22 2nd Contact CA3, CA23 3rd Contact CA4, CA5 4th and 5th contacts CAS1, CAS2 First and second contact isolation layers CT1~CT5 1st~5th contact trenches D1, D2 First and second drain regions DC1~DC4 1st~4th dummy capping patterns DG1~DG4 1st~4th dummy gates F1, F41, F61 First active pattern F2, F42 Second active pattern G1 to G4 First to fourth gate electrodes GC Gate Cut M Mask Pattern NW1 to NW8: 1st to 8th nanosheets S1~S4 1st to 4th source regions SL Silicide layer SM Spacer material layer V1~V4 1st~4th vias VPR, VPR2, VPR5, VPR6 Through Vias VPR5_1, VPR5_2 1st and 2nd parts VPRT Through Via Trench

Claims

1. A lower interlayer insulating film; a first active pattern and a second active pattern each extending in a first horizontal direction on the lower interlayer insulating film and spaced apart from each other in a second horizontal direction different from the first horizontal direction; a gate electrode extending in the second horizontal direction on the first active pattern and the second active pattern; a first source region disposed on the first active pattern at a first side of the gate electrode; a second source region disposed on a second side of the gate electrode on the first active pattern and facing the first side of the gate electrode in the first horizontal direction; a third source region disposed on the second active pattern and on a first side of the gate electrode; a drain region disposed on the second active pattern on a second side of the gate electrode; a first contact extending in the second horizontal direction from a first side of the gate electrode and connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction from a second side of the gate electrode and connected to the second source region; a third contact extending in the second horizontal direction from a second side of the gate electrode and spaced apart from the second contact in the second horizontal direction and connected to the drain region; a lower wiring layer disposed within the lower interlayer insulating film, extending in the first horizontal direction between the first active pattern and the second active pattern, and at least a portion of the lower wiring layer protruding vertically from an upper surface of the lower interlayer insulating film below the first contact; a through via disposed between the first source region and the third source region and connecting the lower wiring layer and the first contact; a second contact formed on said first wiring layer and a third contact formed on said second source region and a third contact formed on said second drain region, said second contact being electrically insulated from said lower wiring layer between said second source region and said drain region;

2. The semiconductor device according to claim 1 , wherein the first contact and the through via are integrally formed.

3. The semiconductor device according to claim 2 , wherein each of the first contact and the through via is formed of a single film.

4. 2. The semiconductor device according to claim 1, wherein an upper surface of the lower wiring layer is formed on the same plane as an upper surface of the lower interlayer insulating film between the second source region and the drain region.

5. a lower insulating film disposed between an upper surface of the lower interlayer insulating film and lower surfaces of the first active pattern and the second active pattern and in contact with the lower wiring layer; 2. The semiconductor device of claim 1, further comprising: a field insulating film disposed on an upper surface of the lower interlayer insulating film and surrounding a sidewall of the lower insulating film, a sidewall of the first active pattern, and a sidewall of the second active pattern.

6. 6. The semiconductor device according to claim 5, wherein an upper surface of the lower insulating film is formed higher than an upper surface of the lower wiring layer between the first source region and the third source region.

7. an etch stop layer disposed along the second horizontal sidewall of the first source region; an upper interlayer insulating film covering the etch stop film; The semiconductor device of claim 1 , wherein the through via is spaced apart from the etch stop layer in the second horizontal direction.

8. A lower interlayer insulating film; a first active pattern and a second active pattern each extending in a first horizontal direction on the lower interlayer insulating film and spaced apart from each other in a second horizontal direction different from the first horizontal direction; first to fourth gate electrodes each extending in the second horizontal direction on the first active pattern and the second active pattern and spaced apart from each other in the first horizontal direction; a gate cut extending in the first horizontal direction between the first active pattern and the second active pattern and isolating each of the first to fourth gate electrodes in the second horizontal direction; a first source region disposed on the first active pattern between the first gate electrode and the second gate electrode; a second source region disposed on the first active pattern between the second gate electrode and the third gate electrode; a first drain region disposed on the first active pattern between the third gate electrode and the fourth gate electrode; a third source region disposed on the second active pattern between the first gate electrode and the second gate electrode; a second drain region disposed on the second active pattern between the second gate electrode and the third gate electrode; a fourth source region disposed on the second active pattern between the third gate electrode and the fourth gate electrode; a first contact extending in the second horizontal direction between the first gate electrode and the second gate electrode and connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction between the second gate electrode and the third gate electrode and connected to the second source region; a third contact extending in the second horizontal direction between the third gate electrode and the fourth gate electrode and connected to the first drain region; a fourth contact extending in the second horizontal direction between the second gate electrode and the third gate electrode, spaced apart from the second contact in the second horizontal direction and connected to the second drain region; a fifth contact extending in the second horizontal direction between the third gate electrode and the fourth gate electrode, spaced apart from the third contact in the second horizontal direction and connected to the fourth source region; a lower wiring layer disposed within the lower interlayer insulating film and extending in the first horizontal direction under the gate cut; a through via intersecting the gate cut and connecting between the lower wiring layer and the first contact, Between the second gate electrode and the third gate electrode, each of the second contact and the fourth contact is electrically insulated from the lower wiring layer; a third contact and a fifth contact between the third gate electrode and the fourth gate electrode, the third contact and the fifth contact being electrically insulated from the lower wiring layer, the fifth contact being electrically insulated from the lower wiring layer.

9. 9. The semiconductor device of claim 8, wherein the gate cut is vertically spaced apart from the lower wiring layer between the second source region and the second drain region and between the first drain region and the fourth source region.

10. an etch stop layer disposed along the second horizontal sidewall of the first source region; an upper interlayer insulating film covering the etch stop film; The semiconductor device according to claim 8 , wherein at least a portion of the through via is in contact with the etching stop film.

Images