Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device which can increase the degree of integration and a data storage system including the semiconductor device.SOLUTION: The semiconductor device includes: a peripheral circuit structure; a laminate structure vertically overlapped with the peripheral circuit structure; and a separation structure penetrating the laminate structure. The laminate structure includes a plurality of blocks separated from one another by a first part of the separation structure. Each of the blocks includes an insulation layer and a conductive layer alternately laminated in a vertical direction. The blocks include a plurality of first blocks and a plurality of capacitor blocks arranged between ones adjacent to each other of the first blocks.SELECTED DRAWING: Figure 6b

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same, and more particularly, to a semiconductor device capable of increasing integration density and a data storage system including the same. [Background technology]

[0002] 2. Description of the Related Art In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing large amounts of data. Accordingly, research is being conducted into methods for increasing the data storage capacity of semiconductor devices.

[0003] For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above problems in the conventional semiconductor device, and an object of the present invention is to provide a semiconductor device that allows an increase in the degree of integration. Another object of the present invention is to provide a data storage system including the semiconductor device. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor device according to the present invention includes a peripheral circuit structure, a stacked structure vertically overlapping the peripheral circuit structure, and an isolation structure penetrating the stacked structure, the stacked structure including a plurality of blocks separated from each other by a first portion of the isolation structure, each of the plurality of blocks including an insulating layer and a conductive layer stacked alternately in a vertical direction, and the plurality of blocks including a plurality of first blocks and a plurality of capacitor blocks disposed between adjacent first blocks among the plurality of first blocks.

[0006] In order to achieve the above object, a semiconductor device according to the present invention includes a first chip structure and a second chip structure vertically overlapping the first chip structure, the first chip structure includes a peripheral circuit, the second chip structure includes a stacked structure, an isolation structure penetrating the stacked structure, a plurality of contact plugs, and an input / output pad, the stacked structure includes a plurality of blocks spaced apart from each other, each of the plurality of blocks includes an insulating layer and a conductive layer that are stacked alternately in a vertical direction, the plurality of blocks include a plurality of memory blocks and a capacitor block, and the first and second chip structures are formed by interposing a peripheral circuit and a stacked structure. the first I / O contact plug is electrically connected to a first one of the I / O pads; the capacitor block includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being formed of a first plurality of conductive layers among the conductive layers, the second capacitor electrode being formed of a second plurality of conductive layers among the conductive layers, and the first capacitor electrode being electrically connected to the first I / O pad via the first I / O contact plug and the routing wiring structure.

[0007] In order to achieve the above object, the data storage system according to the present invention comprises a semiconductor device including an input / output pad, and a controller electrically connected to the semiconductor device via the input / output pad and controlling the semiconductor device, wherein the semiconductor device further comprises a peripheral circuit structure, a stacked structure vertically overlapping the peripheral circuit structure, and an isolation structure penetrating the stacked structure, wherein the stacked structure comprises a plurality of blocks separated from each other by the isolation structure, each of the plurality of blocks comprising an insulating layer and a conductive layer alternately stacked in the vertical direction, and the plurality of blocks comprises a plurality of first blocks and a plurality of capacitor blocks disposed between adjacent first blocks among the plurality of first blocks, and the plurality of capacitor blocks are separated from each other by the isolation structure. Effect of the Invention

[0008] According to the semiconductor device and data storage system of the present invention, it is possible to provide a semiconductor device including a capacitor block located at the same level as a memory block, and a data storage system including the same. The capacitor block can provide a high-capacitance capacitor because a capacitor electrode can be formed using a conductive layer located at the same level as the conductive layer in the memory block. Therefore, the plane area occupied by the high-capacity capacitor can be minimized, and the integration degree of the semiconductor device can be improved.

[0009] In addition, since the capacitors in the capacitor block and the peripheral circuits can be arranged to overlap each other vertically, a signal path electrically connecting the capacitors and the peripheral circuits can be minimized. Therefore, the RC delay can be minimized, improving the performance of the semiconductor device. Also, a first capacitor of a first capacitor block of the plurality of capacitor blocks is provided to be electrically connected to the first I / O pad. The first capacitor of the first capacitor block electrically connected to the first I / O pad can act as a damper when the I / O speed increases. Additionally, the blocks including the capacitor blocks, the dummy blocks, and the memory blocks may be isolated from each other by isolation structures. Therefore, the distance between the blocks can be minimized, and the integration density of the semiconductor device can be improved. [Brief description of the drawings]

[0010] [Figure 1a] 1 is a perspective view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 1b] 1 is a perspective view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 1c] 1 is a block diagram showing a schematic configuration of a data storage system including a semiconductor device according to an embodiment of the present invention; [Figure 1d] 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a top view showing a portion of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a perspective view showing a portion of a semiconductor device according to an embodiment of the present invention; [Figure 4a] FIG. 3 is a partial enlarged view showing the area marked "A" in FIG. 2. [Figure 4b] FIG. 4b is a partially enlarged view showing the area marked "C" in FIG. 4a. [Diagram 5] FIG. 3 is a top view showing the area marked "B" in FIG. 2. [Figure 6a] FIG. 4b is a cross-sectional view showing a schematic view of a region cut along line II' in FIG. 4a. [Figure 6b] 4b is a cross-sectional view showing a schematic view of a region cut along line II-II' in FIG. 4a; [Figure 6c] 6 is a cross-sectional view showing a schematic view of a region cut along line III-III' in FIG. 5. [Figure 7a] 4b is a cross-sectional view showing a schematic view of a region cut along line IV-IV' in FIG. 4a; [Figure 7b] 4b is a cross-sectional view showing a schematic view of a region cut along line VV' in FIG. 4a; [Figure 7c] 6 is a cross-sectional view showing a schematic view of a region cut along line IV-IV' in FIG. 5. [Figure 8a] This is a conceptual cross-sectional view for explaining the electrical connection relationship of conductive layers within a memory block among the components of the semiconductor device CH described in Figures 1a to 7c, the electrical connection relationship of a vertical memory structure, and the electrical connection relationship of an upper plate pattern including a common source. [Figure 8b] FIG. 8B is a partial enlarged view of the area marked "D" in FIG. 8a. [Figure 8c] FIG. 7C is a conceptual cross-sectional view for explaining the electrical connection relationship of conductive layers in a capacitor block among the components of the semiconductor device described in FIGS. 1a to 7c. [Figure 8d] FIG. 8B is a partial enlarged view of the area marked "E" in FIG. 8C. [Figure 9] FIG. 4c is a top view for explaining an example in which the arrangement of the components in FIG. 4b is modified. [Figure 10a] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 10b] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 10c] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 10d] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 10e] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 10f] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 10g] FIG. 8B is a partially enlarged cross-sectional view showing a modification of the partially enlarged cross-sectional view of FIG. 8D. [Figure 11] FIG. 8c is a partially enlarged cross-sectional view showing a modification of the partially enlarged view of FIG. 8b. [Figure 12a] 11 is a partially enlarged cross-sectional view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 12b] 11 is a partially enlarged cross-sectional view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 12c] 11 is a partially enlarged cross-sectional view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 12d] 11 is a partially enlarged cross-sectional view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 13] FIG. 11 is a top view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 14a] 14 is a cross-sectional view showing a region cut along line Ia-Ia' in FIG. 13. [Figure 14b] 14 is a cross-sectional view showing a region cut along line IIa-IIa' in FIG. 13. [Figure 15] FIG. 11 is a top view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 16a] 16 is a cross-sectional view showing a region cut along line IVa-IVa' in FIG. 15. [Figure 16b] 16 is a cross-sectional view showing a region cut along line Vb-Vb' in FIG. 15. FIG. [Figure 17] 16 is a cross-sectional view showing a modified example of a capacitor block in the semiconductor device according to the embodiment of the present invention, taken along line Vb-Vb' in FIG. 15. [Figure 18] 3 is a top view showing a modified example of the capacitor block shown in the top view of FIG. 2. FIG. [Figure 19] 3 is a top view showing a modified example of the capacitor block shown in the top view of FIG. 2. FIG. [Figure 20] FIG. 11 is a perspective view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 21a] FIG. 11 is a top view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 21b]FIG. 11 is a perspective view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 22a] FIG. 11 is a top view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 22b] FIG. 11 is a perspective view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Diagram 23] FIG. 22b is a cross-sectional view showing a region cut along line XX'. [Figure 24] FIG. 11 is a top view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Diagram 25] FIG. 11 is a perspective view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 26a] FIG. 25 is a partial enlarged view showing the area indicated by "Aa" in FIG. 24. [Figure 26b] FIG. 25 is a partial enlarged view showing the area indicated by "Ba" in FIG. 24. [Figure 26c] FIG. 26b is a partially enlarged view showing the area marked "Baa" in FIG. 26b. [Figure 27a] FIG. 26b is a cross-sectional view showing a region cut along line VI-VI' in FIG. 26a. [Figure 27b] 26b is a cross-sectional view showing a region cut along line VII-VII' in FIG. 26b. [Figure 28] 1 is a flowchart for explaining an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] 1 is a block diagram showing a schematic configuration of a data storage system including a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out the semiconductor device and data storage system according to the present invention will be described with reference to the drawings.

[0012] Hereinafter, terms such as "upper," "middle," and "lower" may be used in place of other terms, such as "first," "second," and "third," to describe elements of the specification. Terms such as "first," "second," and "third" may be used to describe various components, but the components are not limited by these terms, and a "first component" may be termed a "second component."

[0013] A schematic configuration of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 1a to 7c. 1a to 7c, FIG. 1a is a perspective view showing a data storage system including a semiconductor device according to an embodiment of the present invention, FIG. 1b is a perspective view showing a semiconductor device according to an embodiment of the present invention, FIG. 1c is a block diagram showing a data storage system including a semiconductor device according to an embodiment of the present invention, FIG. 1d is a block diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a top view showing a portion of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a perspective view showing a portion of a semiconductor device according to an embodiment of the present invention, FIG. 4a is a partially enlarged view showing an area marked "A" in FIG. 2, and FIG. 4b is a partially enlarged view showing an area marked "A" in FIG. 2. FIG. 5 is a partial enlarged view showing the area marked "B" in FIG. 2. FIG. 6a is a cross-sectional view showing the area marked "C" in FIG. 4a. FIG. 6b is a cross-sectional view showing the area marked "B" in FIG. 4a. FIG. 6c is a cross-sectional view showing the area marked "B" in FIG. 5. FIG. 7a is a cross-sectional view showing the area marked "C" in FIG. 4a. FIG. 7b is a cross-sectional view showing the area marked "B" in FIG. 4a. FIG. 7c is a cross-sectional view showing the area marked "B" in FIG. 5.

[0014] First, referring to Figures 1a, 1b, and 1c, a data storage system 11 according to one embodiment of the present invention includes a main board 5, a controller 10 mounted on the main board 5, one or more semiconductor packages 15, and a DRAM 20. The semiconductor package 15 and the DRAM 20 are connected to the controller 10 by a wiring pattern 25 formed on the main substrate 5 .

[0015] The main board 5 includes a connector 30 including a plurality of pins to be coupled with an external host (HOST in FIG. 1c). In the connector 30, the number and arrangement of the pins can be changed depending on the communication interface between the data storage system 1 and the external host HOST. In an exemplary embodiment, the data storage system 1 can communicate with an external host via any of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc.

[0016] In the exemplary embodiment, the data storage system 1 operates with power supplied from an external host (HOST in FIG. 1c) via a connector 30. The data storage system 1 further includes a PMIC (Power Management Integrated Circuit) that distributes power supplied from an external host HOST to the controller 10 and the semiconductor package 15. The controller 10 writes data to or reads data from the semiconductor package 15 to improve the operating speed of the data storage system 1 .

[0017] The DRAM 20 is a buffer memory for reducing the speed difference between the semiconductor package 15, which is a data storage space, and the external host. The DRAM 20 included in the data storage system 1 can also function as a kind of cache memory, and can provide space for temporarily storing data during control operations for the semiconductor package 15. When the data storage system 1 includes a DRAM 20 , the controller 10 further includes a DRAM controller for controlling the DRAM 20 in addition to the NAND controller for controlling the semiconductor package 15 .

[0018] The semiconductor package 15 includes first and second semiconductor packages (15a, 15b) spaced apart from each other. The first and second semiconductor packages (15a, 15b) are each a semiconductor package including a plurality of semiconductor devices CH. The semiconductor device CH is called a semiconductor chip. Each of the first and second semiconductor packages (15a, 15b) includes a package substrate 50, a semiconductor device CH on the package substrate 50, an adhesive layer 60 disposed on the lower surface of each of the semiconductor devices CH, a connection structure 70 that electrically connects the semiconductor device CH and the package substrate 50, and a molding layer 80 that covers the semiconductor device CH and the connection structure 70 on the package substrate 50. Package substrate 50 is a printed circuit board that includes package top pads 55 . Each of the semiconductor devices CH includes an input / output pad IOP.

[0019] In the exemplary embodiment, the connection structure 70 is a bond wire that electrically connects the input / output pad IOP and the package top pad 55 . Therefore, in each of the first and second semiconductor packages (15a, 15b), the semiconductor devices CH are electrically connected to each other by the bonding wire method, and are electrically connected to the package upper pads 55 of the package substrate 50. According to an embodiment, in each of the first and second semiconductor packages (15a, 15b), the semiconductor devices CH are electrically connected to each other by a connection structure including a through electrode (Through Silicon Via: TSV) instead of a bonding wire type connection structure 70.

[0020] In an exemplary embodiment, the controller 10 and the semiconductor device CH are included in one package. For example, the controller 10 and the semiconductor device CH are mounted on the main substrate 5 and another separate interposer substrate, and the controller 10 and the semiconductor device CH are connected to each other by wiring formed on the interposer substrate. Each of the semiconductor devices CH includes a first chip structure (CH_L) and a second chip structure (CH_U) on the first chip structure (CH_L). In each of the semiconductor devices CH, the second chip structure (CH_U) includes a plurality of memory mats MAT spaced apart from each other. In each of the semiconductor devices CH, the second chip structure (CH_U) includes an input / output pad IOP.

[0021] Each of the semiconductor devices CH includes a memory cell array MCA and a peripheral circuit PC. In each semiconductor device CH, each of the multiple memory mats MAT of the second chip structure (CH_U) includes a memory cell array MCA, and a part of the second chip structure (CH_U) and the first chip structure (CH_L) include a peripheral circuit PC.

[0022] In the following, one of the semiconductor devices CH will be mainly described. Moreover, the following description will focus on one of the memory mats MAT of one semiconductor device CH.

[0023] The controller 10 writes data DATA to the semiconductor device CH or reads data DATA stored in the semiconductor device CH. The controller 10 transmits a command CMD, an address ADDR, a control signal CTRL, and data DATA to the semiconductor device CH in order to write data DATA to the semiconductor device CH. The controller 10 transmits a command CMD, an address ADDR, and a control signal CTRL to the semiconductor device CH in order to read out data DATA stored in the semiconductor device CH.

[0024] The semiconductor device CH includes a non-volatile memory device such as a NAND flash memory, a phase change memory PRAM, a resistive memory ReRAM or a magnetoresistive memory MRAM. The semiconductor device CH responds to signals received from the controller 10 to perform operations such as writing, reading, and erasing data DATA. In the second chip structure (CH_U), the memory cell array MCA includes memory cells that are arranged three-dimensionally and can store data.

[0025] Next, referring to FIG. 1d in conjunction with FIGS. 1a, 1b, and 1c, in the semiconductor device CH, a second chip structure (CH_U) includes a plurality of memory blocks mBLK and a plurality of capacitor blocks cBLK. A plurality of memory blocks mBLK constitute a memory cell array MCA. A plurality of capacitor blocks cBLK constitute a capacitor array CPA. Each of the multiple capacitor blocks cBLK includes at least one capacitor CAP.

[0026] The semiconductor device CH includes an address decoder 93 , a control logic 94 , a page buffer 95 , an input / output circuit 96 , and a voltage generating circuit 97 . The peripheral circuits (PC in FIG. 1c) include an address decoder 93, a control logic 94, a page buffer 95, an input / output circuit 96, and a voltage generation circuit 97.

[0027] At least one of the address decoder 93, the control logic 94, the page buffer 95, the input / output circuit 96, and the voltage generating circuit 97 in the first chip structure (CH_L) forms a circuit together with the capacitor CAP in the second chip structure (CH_U). For example, the voltage generating circuit 97 configures a circuit including a capacitor CAP of at least one of the capacitor blocks cBLK. For example, the voltage generating circuit 97 converts an externally input voltage to a level most suitable for the operation of the semiconductor device CH, and supplies power for driving each circuit. Thus, the peripheral circuit (PC in FIG. 1c) includes an address decoder 93, control logic 94, a page buffer 95, an input / output circuit 96, and a voltage generation circuit 97, along with a capacitor CAP. The address decoder 93, control logic 94, page buffer 95, input / output circuit 96, and voltage generation circuit 97 located in the first chip structure (CH_L) are electrically connected to a plurality of capacitor blocks cBLK located in the second chip structure (CH_U) via capacitor routing wiring CAR.

[0028] The second chip structure (CH_U) further includes word lines WL, string select lines SSL, ground select lines GSL, bit lines BL, erase control lines ECL, and a common source CSL. The memory cell array MCA is connected to word lines WL, string selection lines SSL, ground selection lines GSL, bit lines BL, erase control lines ECL, and a common source CSL. The memory cell array MCA is connected to an address decoder 93 via word lines WL, string selection lines SSL, ground selection lines GSL, and a common source CSL, and is connected to a page buffer 95 via bit lines BL.

[0029] The address decoder 93 selects one of the memory blocks mBLK in the memory cell array MCA. The address decoder 93 selects one of the word lines WL of the selected memory block. The address decoder 93 transmits a voltage provided by a voltage generating circuit 97 to the word lines WL and selection lines (SSL, GSL) of a selected memory block. The address decoder 93 transmits a positive (+) high program voltage to a selected word line during a program operation, and transmits a positive (+) high erase voltage to the bulk of a selected memory block during an erase operation.

[0030] The control logic 94 receives commands CMD and control signals CTRL from the controller 10, and controls the address decoder 93, the page buffer 95, and the input / output circuit 96 in response to the received signals. The control logic 94 controls a voltage generating circuit 97 that generates various voltages required for the operation of the semiconductor device CH. For example, the control logic 94 adjusts the voltage levels provided to the word lines WL and bit lines BL when performing a memory operation, such as a program operation or an erase operation.

[0031] A voltage generating circuit 97, which constitutes a circuit including the capacitors of at least one of the multiple capacitor blocks cBLK, generates various levels of voltages, such as multiple selected read voltages, multiple unselected read voltages, multiple program pulses, multiple pass voltages, and multiple erase pulses, under the control of the control logic 94, and provides them to the address decoder 93 and the memory cell array MCA. For example, the voltage generating circuit 97 generates a positive (+) high voltage corresponding to multiple program pulses or multiple erase pulses.

[0032] The voltage generating circuit 97 includes a charge pump including at least one pumping capacitor to generate the various levels of voltage as described above. The pumping capacitor of the voltage generating circuit 97 is a capacitor of at least one of the capacitor blocks (cBLK1, cBLK2, . . . cBLKm) in the second chip structure (CH_U).

[0033] The page buffer 95 acts as either a write driver or a sense amplifier depending on the mode of operation. During a read operation, the page buffer 95 senses the bit line BL of the memory cell selected under the control of the control logic 94 . The sensed data is stored in a latch provided inside the page buffer 95 . The page buffer 95 dumps the data stored in the latches to the input / output circuit 96 under the control of the control logic 94 .

[0034] The input / output circuit 96 temporarily stores a command CMD, an address ADDR, a control signal CTRL, and data DATA provided from the outside of the semiconductor device CH via an input / output pad IOP. The input / output circuit 96 temporarily stores read data from the semiconductor device CH, and outputs it to the outside via the input / output pad IOP at a specified time.

[0035] The I / O pad IOP includes a first I / O pad IOP1 connected to a first capacitor of a first capacitor block of the plurality of capacitor blocks cBLK, and a second I / O pad IOP2 not connected to any capacitor of the plurality of capacitor blocks cBLK. The first capacitor of the first capacitor block cBLK is connected to the first I / O pad IOP1 to reduce noise in a signal transmitted through the first I / O pad IOP1. The first capacitor of the first capacitor block cBLK is connected to the first I / O pad IOP, so that the first capacitor acts as a damper when the I / O speed increases.

[0036] Next, some components of the semiconductor device CH will be described with reference to FIGS. Figure 2 is a partial top view of a second chip structure (CH_U) showing the input / output pad IOP of one of the multiple memory mats MAT in Figure 1b, together with the memory cell array MCA of one adjacent memory mat, with the input / output pad IOP at the center, and Figure 3 is an oblique view conceptually showing some components of the semiconductor device CH.

[0037] 2 and 3 in addition to FIGS. 1a to 1d, a second chip structure (CH_U in FIG. 1b) of the semiconductor device CH includes a stack structure ST including a conductor stack region STc and an insulator stack region STi. The second chip structure (CH_U in FIG. 1b) of the semiconductor device CH further comprises an isolation structure SP penetrating the stack structure ST in the vertical direction Z.

[0038] The separation structure SP includes a first horizontal portion (SP_H) extending in a first direction X, and second and third horizontal portions (SP_Va, SP_Vb) extending in a second direction Y perpendicular to the first direction X. The conductor stack region STc includes a plurality of blocks (mBLK, dBLK, cBLK, STe) that are separated from one another by isolation structures SP.

[0039] The multiple blocks (mBLK, dBLK, cBLK, STe) include multiple memory blocks mBLK and multiple capacitor blocks cBLK described in FIG. 1d. The multiple blocks (mBLK, dBLK, cBLK, STe) further include at least one dummy block dBLK and an edge block STe.

[0040] The edge block STe may be in the shape of a square ring surrounding the outside of the isolation structure SP and is in contact with the insulator stack region STi. The edge block STe surrounds a plurality of memory blocks mBLK, a plurality of capacitor blocks cBLK, and at least one dummy block dBLK. The multiple blocks (mBLK, dBLK, cBLK, STe) include a first block (mBLK, dBLK). The capacitor blocks cBLK are arranged between adjacent first blocks (mBLK, dBLK) among the first blocks.

[0041] The at least one dummy block dBLK includes a first dummy block (dBLK_1) and a second dummy block (dBLK_2). Each of the multiple memory blocks mBLK, the first dummy block (dBLK_1), and the second dummy block (dBLK_2) is in a line shape extending in the first direction X. Each of the capacitor blocks cBLK has a line shape or a bar shape extending in the first direction X. In the first direction X, the length of each of the plurality of memory blocks mBLK is greater than the length of each of the plurality of capacitor blocks cBLK.

[0042] The plurality of memory blocks mBLK and the plurality of capacitor blocks cBLK are disposed between the first dummy block dBLK1 and the second dummy block dBLK2. Each of the multiple memory blocks mBLK includes a memory area MA and at least one connection area CA. For example, at least one connection area CA includes a first connection area CA1 and a second connection area CA2 arranged on both sides of the memory area MA.

[0043] The capacitor blocks cBLK are arranged in a first direction X and spaced apart from each other. The plurality of capacitor blocks cBLK include a first capacitor block cBLK1, a second capacitor block cBLK2, a third capacitor block cBLK3, and a fourth capacitor block cBLK4. The capacitor blocks cBLK are separated from one another by vertical portions (SP_V) of the isolation structures SP. A side surface of at least one of the plurality of capacitor blocks cBLK is surrounded by an isolation structure SP. For example, the entire side surface of each of the multiple capacitor blocks cBLK is surrounded by an isolation structure SP.

[0044] Of the first and second dummy blocks (dBLK1, dBLK2), the first dummy block dBLK is adjacent to a plurality of capacitor blocks cBLK in the second direction Y. A first memory block mBLKa of the plurality of memory blocks mBLK is adjacent to the plurality of capacitor blocks cBLK in the second direction Y. The capacitor blocks cBLK are arranged in the second direction Y between the first memory block mBLKa and the first dummy block dBLK1.

[0045] The first chip structure (CH_L) includes a plurality of lower circuits (PC_1, PC_2, PC_3, CAP_C). The plurality of lower circuits (PC_1, PC_2, PC_3, CAP_C) include a first lower circuit (PC_1), a second lower circuit (PC_2), a third lower circuit (PC_3), and a fourth circuit (CAP_C). The plurality of lower circuits (PC_1, PC_2, PC_3, CAP_C) constitute a peripheral circuit structure, and the plurality of lower circuits (PC_1, PC_2, PC_3, CAP_C) are peripheral circuits.

[0046] A plurality of lower circuits (PC_1, PC_2, PC_3, CAP_C) overlap with a plurality of blocks (mBLK, cBLK, dBLK) in the vertical direction Z. Each of the multiple capacitor blocks cBLK includes the capacitor described above (CAP in FIG. 1d). The first and second lower circuits (PC_1, PC_2) constitute the page buffer (95 in FIG. 1d) and the address decoder (93 in FIG. 1d) described above. For example, the first lower circuit (PC_1) constitutes an address decoder (93 in FIG. 1d), and the second lower circuit (PC_2) constitutes a page buffer (95 in FIG. 1d).

[0047] Together with the capacitors of the multiple capacitor blocks (cBLK in FIG. 3), at least one of the third and fourth lower circuits (PC_3, CAP_C in FIG. 3) constitutes at least one of a control logic (94 in FIG. 1d), an input / output circuit (96 in FIG. 1d), and a voltage generation circuit (97 in FIG. 1d) that constitute a circuit including the capacitors (CAP in FIG. 1d) of the multiple capacitor blocks (cBLK in FIG. 1d) described above. For example, the third lower circuit (PC_3) constitutes an input / output circuit (96 in FIG. 1d), and the fourth lower circuit (CAP_C) constitutes a control logic (94 in FIG. 1d) and / or a voltage generation circuit (97 in FIG. 1d).

[0048] The fourth circuit (CAP_C) configured to be electrically connected to the capacitors (CAP in FIG. 1d) of the multiple capacitor blocks cBLK includes a first capacitor connection circuit (CAP_C1) configured to be electrically connected to the first capacitor of the first capacitor block cBLK1, a second capacitor connection circuit (CAP_C2) configured to be electrically connected to the second capacitor of the second capacitor block cBLK2, a third capacitor connection circuit (CAP_C3) configured to be electrically connected to the third capacitor of the third capacitor block cBLK3, and a fourth capacitor connection circuit (CAP_C4) configured to be electrically connected to the fourth capacitor of the fourth capacitor block cBLK4. Among the peripheral circuits, the first capacitor connection circuit (CAP_C1) is the first peripheral circuit, the second capacitor connection circuit (CAP_C2) is the second peripheral circuit, the third capacitor connection circuit (CAP_C3) is the third peripheral circuit, and the fourth capacitor connection circuit (CAP_C4) is the fourth peripheral circuit.

[0049] In the first chip structure (CH_L), at least a portion of at least one of the fourth circuits (CAP_C) configured to be electrically connected to the capacitors CAP of the plurality of capacitor blocks cBLK vertically overlaps at least a portion of at least one of the plurality of capacitor blocks cBLK. For example, the first capacitor connection circuit (CAP_C1) in the fourth circuit (CAP_C), which is a peripheral circuit, is electrically connected to the first capacitor of the first capacitor block cBLK1 to form a circuit, and the first capacitor connection circuit (CAP_C1) vertically overlaps at least a portion of the first capacitor of the first capacitor block cBLK1.

[0050] Next, illustrative examples of semiconductor device CH will be described with reference to FIGS. 4a, 4b, 5, 6a, 6b, 6c, 7a, 7b and 7c in addition to FIGS. 1a to 3. Referring to Figures 4a, 4b, 5, 6a to 6c, and 7a to 7c together with Figures 1a to 3, the first chip structure (CH_L) includes a substrate SUB, a peripheral active region 203a on the substrate SUB, and a peripheral element isolation region 203s on the substrate SUB that defines the peripheral active region 203a. The substrate SUB is a semiconductor substrate.

[0051] The first chip structure (CH_L) further includes a peripheral transistor PTR on a substrate SUB, a lower wiring structure 208, a lower insulating structure 220, and a lower bonding pad 214. Each of the peripheral transistors PTR includes peripheral source / drain regions pSD spaced apart from each other in the peripheral active region 203a, a peripheral channel region pCH disposed between the peripheral source / drain regions pSD in the peripheral active region 203a, and a peripheral gate pG on the peripheral channel region pCH.

[0052] The lower wiring structure 208 is electrically connected to the peripheral transistor PTR. The electrical connection relationship of the peripheral transistors PTR will be described later with reference to FIGS. 9a to 9d. The lower wiring structure 208 includes a number of lower horizontal portions 210 located at different levels, and a number of lower vertical portions 212 located at different levels. Each of the multiple lower horizontal portions 210 is a lower interconnection line or a lower pad. For example, the lower horizontal portions 210 may be referred to as lower traces or lower pads. The plurality of lower vertical portions 212 are referred to as lower vias or lower contact plugs.

[0053] The plurality of lower horizontal portions 210 include a first lower horizontal portion 210a, a second lower horizontal portion 210b on the first lower horizontal portion 210a, and a third lower horizontal portion 210c on the second lower horizontal portion 210b. The multiple lower vertical portions 212 include a first lower vertical portion 212a below the first lower horizontal portion 210a, a second lower vertical portion 212b between the first lower horizontal portion 210a and the second lower horizontal portion 210b, a third lower vertical portion 212c between the second lower horizontal portion 210b and the third lower horizontal portion 210c, and a fourth lower vertical portion 212d on the third lower horizontal portion 210c.

[0054] The lower bonding pad 214 is on the lower wiring structure 208 and is electrically connected to the lower wiring structure 208 . The lower insulating structure 220 covers the peripheral transistor PTR and the lower wiring structure 208 on the peripheral active region 203 a and the peripheral element isolation region 203 s, and covers the side surfaces of the lower bonding pad 214 . The upper surface of the lower insulating structure 220 is coplanar with the upper surface of the lower bond pad 214 .

[0055] The second chip structure (CH_U) includes a stack structure ST and an isolation structure SP as described in FIG. As described in FIG. 2, the stacked structure ST includes a conductive stacked region STc and an insulator stacked region STi, and the conductive stacked region STc includes a plurality of blocks (mBLK, dBLK, cBLK, STe) separated from each other by an isolation structure SP.

[0056] The stacked structure ST vertically overlaps the peripheral circuit structure, ie, a plurality of lower circuits (PC_1, PC_2, PC_3, CAP_C). The conductor stacked region STc includes insulating layers 124 and conductive layers 126 that are stacked alternately and repeatedly in the vertical direction Z. The insulating layer 124 includes silicon oxide. Of the insulating layers 124 and conductive layers 126, the bottom layer is the bottom insulating layer and the top layer is the top insulating layer. In the conductor stack region STc, the conductive layer 126 located in the memory block mBLK is a gate electrode, and the conductive layer 126 located in the capacitor block cBLK is a capacitor electrode.

[0057] The insulator stacked region STi includes first insulating layers 120 and second insulating layers 122 that are alternately and repeatedly stacked in the vertical direction Z. The first insulating layer 120 is disposed at the same level as the insulating layer 124 and comprises the same material as the insulating layer 124 . The second insulating layer 122 is disposed at the same level as the conductive layer 126 and comprises a different material than the first insulating layer 124 . For example, the first insulating layer 120 includes silicon oxide and the second insulating layer 122 includes silicon nitride.

[0058] An isolation structure SP as described in FIG. 2 penetrates the conductor stack region STc in the vertical direction Z. The multiple blocks (mBLK, dBLK, cBLK, STe) are separated from one another by isolation structures SP. Therefore, the isolation structure SP isolates a plurality of blocks (mBLK, dBLK, cBLK, STe).

[0059] At least one of the multiple blocks (mBLK, dBLK, cBLK, STe) has a side surface surrounded by an isolation structure SP. For example, each of the multiple blocks (mBLK, dBLK, cBLK, STe) has a side surface surrounded by an isolation structure SP. Thus, a number of blocks (mBLK, dBLK, cBLK, STe) are defined by the separation structures SP.

[0060] The second chip structure (CH_U) further includes a plurality of vertical structures (VSm, VSmd1, VSmd2, VScd, VSdd, VSde, VDdi) penetrating the stack structure ST. The multiple vertical structures VS include a vertical memory structure VSm penetrating the memory region MA of the memory block mBLK, a vertical support structure VSmd2 penetrating the memory region MA of the memory block mBLK and arranged between the vertical memory structures VSm, a vertical support structure VSmd1 penetrating the connection region CA of the memory block mBLK, a vertical support structure VSdd penetrating at least one dummy block dBLK, a vertical support structure VScd penetrating multiple capacitor blocks cBLK, a vertical support structure VSde penetrating the edge block STe, and a vertical support structure VSdi penetrating the insulator stack region STi.

[0061] In a top view, each of the vertical memory structures VSm includes a ring-shaped channel layer 108 , an information storage structure 106 surrounding the outer surface of the channel layer 108 , and a pad layer 112 in contact with the channel layer 108 . The channel layer 108 comprises a semiconductor material, such as silicon. The pad layer 112 includes at least one of doped polysilicon, a metal nitride (eg, TiN), a metal (eg, W), and a metal-semiconductor compound (eg, TiSi). The information storage structure 106 includes a first dielectric layer 106c, a second dielectric layer 106a, and an information storage layer 106b between the first dielectric layer 106c and the second dielectric layer 106a. The first dielectric layer 106c includes silicon oxide or silicon oxide doped with impurities. The second dielectric layer 106a includes at least one of silicon oxide and a high-k dielectric. The information storage layer 106b includes a material capable of trapping charges and storing information, such as silicon nitride. The information storage layer 106b includes areas in which information can be stored in a semiconductor device such as a flash memory device.

[0062] In an embodiment, information storage structure 106 includes an information storage layer 106b capable of trapping charge to store information, although the invention is not limited in this respect. For example, information storage structure 106 may be a structure used in a ferroelectric memory that can store information using remnant polarization of dipoles.

[0063] The second chip structure (CH_U) further includes an isolation pattern 103 penetrating one or more lower conductive layers of the conductive layers 126 in the plurality of memory blocks mBLK. In a top view such as Figure 4b, one separation pattern 103 is arranged between the horizontal portions (SP_H) of a pair of separation structures SP adjacent to each other in the second direction Y, a vertical memory structure VSm is arranged between the horizontal portions (SP_H) and the separation pattern 103, and a vertical support structure VSmd2 is arranged in the intermediate region between the horizontal portions (SP_H). The separation pattern 103 vertically overlaps the vertical support structure VSmd2. Each of the vertical memory structures VSm vertically overlaps two of the bit lines BL and is electrically connected to one of the two bit lines BL that overlap vertically.

[0064] The second chip structure (CH_U) further includes an upper wiring structure 140 disposed below the stacked structure ST, an upper bonding pad 148 below the upper wiring structure 140, and an upper insulating structure 150 below the stacked structure ST, covering the upper wiring structure 140 and covering the sides of the upper bonding pad 148. The upper wiring structure 140 includes a plurality of upper horizontal portions 142 disposed at different levels, and a plurality of upper vertical portions 144 disposed at different levels.

[0065] Each of the multiple upper horizontal portions 142 is an upper interconnection line or an upper pad. For example, the upper horizontal portions 142 may be referred to as upper wirings or upper pads. The plurality of upper vertical portions 144 are referred to as upper vias or upper contact plugs. The plurality of upper horizontal portions 142 include a first upper horizontal portion 142a, a second upper horizontal portion 142b below the first upper horizontal portion 142a, and a third upper horizontal portion 142c below the second upper horizontal portion 142b.

[0066] The multiple upper vertical portions 144 include a first upper vertical portion 144a on the first upper horizontal portion 142a, a second upper vertical portion 144b between the first upper horizontal portion 142a and the second upper horizontal portion 142b, a third upper vertical portion 144c between the second upper horizontal portion 142b and the third upper horizontal portion 142c, and a fourth upper vertical portion 144d below the third upper horizontal portion 142c.

[0067] The upper bond pad 148 is below the upper interconnect structure 140 and is electrically connected to the upper interconnect structure 140 . The upper insulating structure 150 covers the upper wiring structure 140 under the stacked structure ST and covers the sides of the upper bonding pads 148 . The lower surface of the upper insulating structure 150 is coplanar with the lower surface of the upper bond pad 148 . The lower surface of the upper insulating structure 150 is bonded to and in contact with the upper surface of the lower insulating structure 220 . The lower surface of upper bond pad 148 contacts and is bonded to the upper surface of lower bond pad 214 . Upper bond-pad 148 comprises the same metal material as lower bond-pad 214 . For example, upper bond-pad 148 and lower bond-pad 214 comprise copper.

[0068] The second chip structure (CH_U) further includes an upper plate pattern 160c and a pad pattern 160p on the stack structure ST, an insulating layer 170 on the side surfaces of the upper plate pattern 160c and the pad pattern 160p, and a capping insulating layer 174 on the plate pattern 160c, the pad pattern 160p and the insulating layer 174. The upper plate pattern 160c includes a portion disposed on the conductive layer region STc and a portion disposed on the insulating layer region STi. The upper plate pattern 160c is connected to the vertical memory structures VSm of the plurality of memory blocks mBLK.

[0069] Each of the top plate pattern 160c and the pad pattern 160p includes a first layer 162 and a second layer 164 on the first layer 162. The first layer 162 is a polysilicon layer having an N-type conductivity, and the second layer 164 is a conductive layer including at least one of a metal-semiconductor compound, a metal nitride, and a metal. In the upper plate pattern 160c, a portion connected to the vertical memory structure VSm, for example, the first layer 162, is a common source or a common source region. The insulating layer 170 includes an insulating material such as silicon oxide, a low-k dielectric, or silicon nitride.

[0070] The second chip structure (CH_U) further includes the input / output pad IOP described in FIGS. 1a, 1b, 1d, and 2. The input / output pad IOP passes through at least a portion of the capping insulating layer 174 . The input / output pad IOP is connected to the pad pattern 160p. The second chip structure (CH_U) further includes contact plugs (CPc1, CPc2, CPio) and insulating spacers 132 surrounding the sides of the contact plugs (CPc1, CPc2, CPio). The contact plugs (CPg, CPc1, CPc2, CPio) include a gate contact plug CPg, a capacitor contact plug (CPc1, CPc2), and an input / output contact plug CPio.

[0071] The gate contact plug CPg is electrically connected to the conductive layer 126 located in the connection area CA in the memory block mBLK, that is, the gate electrode. The gate contact plugs CPg are extended to different lengths in order to contact the conductive layers 126 disposed at different levels in a direction from below the conductive stack structure STc toward the conductive stack structure STc. For example, based on the cross-sectional structure of FIG. 7a, the gate contact plugs CPg have lower surfaces disposed at the same level under the memory blocks mBLK, and extend from their lower surfaces to different lengths to contact conductive layers 126 disposed at different levels, and the upper surfaces of the gate contact plugs CPg that contact the conductive layers 126 disposed at different levels are disposed at different levels.

[0072] The capacitor contact plugs (CPc1, CPc2) are electrically connected to the conductive layer 126 located in the capacitor block cBLK, ie, the capacitor electrodes. The capacitor contact plugs CPc1 and CPc2 are extended to different lengths to contact the conductive layers 126 disposed at different levels in a direction from below the conductive stack structure STc toward the conductive stack structure STc. For example, when viewed based on the cross-sectional structures of Figures 7b and 7c, the capacitor contact plugs (CPc1, CPc2) have lower surfaces disposed at the same level under the capacitor block cBLK, extend from their lower surfaces to different lengths to contact conductive layers 126 disposed at different levels, and the upper surfaces of the capacitor contact plugs (CPc1, CPc2) that contact the conductive layers 126 disposed at different levels are disposed at different levels. The capacitor contact plugs (CPc1, CPc2) include a capacitor contact plug CPc1 electrically connected to a first capacitor electrode of the capacitor block cBLK and a capacitor contact plug CPc2 electrically connected to a first capacitor electrode of the capacitor block cBLK.

[0073] In the following, for easier understanding, the first capacitor block cBLK1 and the second capacitor block cBLK2 of the capacitor block cBLK will be mainly described. The capacitor contact plugs (CPc1, CPc2) include a first capacitor contact plug CPc1a connected to a conductive layer constituting a first capacitor electrode in the conductive layer 126 of the first capacitor block cBLK1, a second capacitor contact plug CPc2a connected to a conductive layer constituting a second capacitor electrode in the conductive layer 126 of the first capacitor block cBLK1, a third capacitor contact plug CPc1b connected to a conductive layer constituting the first capacitor electrode in the conductive layer 126 of the second capacitor block cBLK2, and a fourth capacitor contact plug CPc2b connected to a conductive layer constituting the second capacitor electrode in the conductive layer 126 of the second capacitor block cBLK2.

[0074] Among each conductive layer 126 of the capacitor block cBLK, when an odd-numbered conductive layer constitutes a first capacitor electrode, the first capacitor contact plug CPc1 is connected to the odd-numbered conductive layer, and when an even-numbered conductive layer constitutes a second capacitor electrode, the second capacitor contact plug CPc2 is connected to the odd-numbered conductive layer. In the embodiment, odd-numbered and even-numbered are defined based on the lowest conductive layer among the conductive layers 126 stacked in the vertical direction Z.

[0075] In the embodiment, a case is described in which, among each conductive layer 126 of the capacitor block cBLK, the odd-numbered conductive layers form first capacitor electrodes and the even-numbered conductive layers form second capacitor electrodes, but the embodiment is not limited to this. In one example, among each conductive layer 126 of the capacitor block cBLK, in a pair of conductive layers adjacent to each other in the vertical direction Z, a pair of conductive layers positioned in odd positions may form a first capacitor electrode, and a pair of conductive layers positioned in even positions may form a second capacitor electrode.

[0076] In an embodiment, each of the capacitors in the capacitor block cBLK includes a capacitor electrode and a dielectric between the capacitor electrodes, and a capacitor (CAP in FIG. 8d) including capacitor electrodes (CAP_E1, CAP_E2 in FIG. 8d) and a capacitor dielectric (124c in FIG. 8d) can be understood from FIG. 8d described below. Illustrative examples of capacitors including such capacitor electrodes and capacitor dielectrics are described below with reference to Figures 8a-8d.

[0077] The input / output contact plugs CPio pass through the insulator stack regions STi. The upper wiring structure 140, the lower wiring structure 208, the lower bond pads 214, and the upper bond pads 148 form a routing wiring structure RWS. The input / output contact plugs CPio include a first input / output contact plug CPio1 electrically connected to the first input / output pad IOP1. The first capacitor electrode of the first capacitor in the first capacitor block cBLK1 is electrically connected to the first I / O pad IOP1 via the first I / O contact plug CPio1 and the routing wiring structure RWS, and the second capacitor electrode is grounded to the ground region GND of the first chip structure (CH_L) via the routing wiring structure RWS. The first capacitor in the first capacitor block cBLK1 acts as a damper when the I / O speed via the first I / O pad IOP1 increases.

[0078] The second chip structure (CH_U) includes a bit line BL formed of a part of the horizontal portion (142a, 142b, 142c) of the upper wiring structure 140, for example, the first horizontal portion 142a, and a bit line contact plug BCP formed of the first vertical portion 144a of the vertical portions (144a, 144b, 144c, 144d) of the upper wiring structure 140. Each of the bit lines BL extends in a second direction Y, and the bit lines BL are spaced apart from each other in a first direction X. The bit line BL is electrically connected to the vertical memory structure VSm. The bit line contact plug BCP is disposed between the bit line BL and the vertical memory structure VSm, and electrically connects the bit line BL and the vertical memory structure VSm.

[0079] The second chip structure (CH_U) includes a first capacitor electrode wiring CW1a, a second capacitor electrode wiring CW2a, a third capacitor electrode wiring CW1b, and a fourth capacitor electrode wiring CW2b, which are configured at least in part of the routing wiring structure RWS. For example, the first to fourth capacitor electrode wirings (CW1a, CW2a, CW1b, CW2b) are formed from a part of the horizontal portion (142a, 142b, 142c) of the upper wiring structure 140, for example, the first horizontal portion 142a.

[0080] The first capacitor electrode wiring CW1a is electrically connected to the first capacitor contact plug CPc1a, and the second capacitor electrode wiring CW2a is electrically connected to the second capacitor contact plug CPc2a. The third capacitor electrode wiring CW1b is electrically connected to the third capacitor contact plug CPc1b, and the fourth capacitor electrode wiring CW2b is electrically connected to the fourth capacitor contact plug CPc2b.

[0081] The I / O contact plug CPio is electrically connected through a routing wiring structure RWS to a transistor PTRio, which is electrically connected to an I / O pad IOP among the peripheral transistors PTR. The I / O contact plugs CPio include a first I / O contact plug CPio1 electrically connected to the first I / O pad IOP1 and a second I / O contact plug CPio2 electrically connected to the second I / O pad IOP2. The first I / O pad IOP1 is electrically connected to the first peripheral transistor PTRio1 via a first I / O contact plug CPio1 and a routing wire structure RWS. The second I / O pad IOP2 is electrically connected to the second peripheral transistor PTRio2 via a second I / O contact plug CPio2 and a routing wire structure RWS.

[0082] Next, with reference to FIGS. 8a, 8b, 8c and 8d, the electrical connection relationships of the components of the semiconductor device CH described with reference to FIGS. 1a to 7c will be described. FIG. 8a is a conceptual cross-sectional view for explaining the electrical connection relationship of the conductive layer 126 in the memory block mBLK among the components of the semiconductor device CH described in FIGS. 1a to 7c, the electrical connection relationship of the vertical memory structure VSm, and the electrical connection relationship of the upper plate pattern 160c including a common source. FIG. 8b is a partially enlarged view of the area indicated by "D" in FIG. 8a. FIG. 8c is a conceptual cross-sectional view for explaining the electrical connection relationship of the conductive layer 126 in the capacitor block cBLK among the components of the semiconductor device CH described in FIGS. 1a to 7c. FIG. 8d is a partially enlarged view of the area indicated by "E" in FIG. 8c.

[0083] 8a-8d in conjunction with FIGS. 1a-7c, the routing wiring structure RWS includes an upper wiring structure 140, a lower wiring structure 208, a lower bond pad 214, and an upper bond pad 148, as described above. The vertical memory structure VSm is electrically connected to a first peripheral transistor PTRb of the peripheral transistors PTR through a routing wire structure RWS. The bit line BL described above is electrically connected to the vertical memory structure VSm and is comprised of a portion of the routing wire structure RWS, for example the first upper horizontal portion 142a. The first peripheral transistor PTRb is a transistor that constitutes the page buffer (95 in FIG. 1d) in the peripheral circuit (PC in FIG. 1c) described above.

[0084] Within memory block mBLK, conductive layers 126 include lower conductive layers (126L1, 126L2), upper conductive layers (126U1, 126U2), and an intermediate conductive layer 126M between the lower conductive layers (126L1, 126L2) and the upper conductive layers (126U1, 126U2). The lower conductive layers (126L1, 126L2) include a first lower conductive layer 126L1 and a second lower conductive layer 126L2 on the first lower conductive layer 126L1. The upper conductive layers (126U1, 126U2) include a first upper conductive layer 126U1 and a second upper conductive layer 126U2 on the first upper conductive layer 126U1.

[0085] The first bottom conductive layer 126L1 and the second top conductive layer 126U2 are the erase control lines (ECL in FIG. 1d) described in FIG. 1d. The second lower conductive layer 126L2 is the string select line SSL described in FIG. The middle conductive layer 126M is the word line (WL in FIG. 1d) described in FIG. The first upper conductive layer 126U1 is the ground selection line GSL described in FIG.

[0086] A gate contact plug CPg electrically connected to the conductive layer 126 in the memory block mBLK is electrically connected to a second transistor PTRg of the peripheral transistors PTR via a routing wire structure RWS. Therefore, the conductive layer 126 constituting the erase control line (ECL in FIG. 1d), the string select line SSL, the word line (WL in FIG. 1d), and the ground select line GSL described in FIG. 1d are electrically connected to the second transistor PTRg via the gate contact plug CPg and the routing wiring structure RWS.

[0087] The upper plate pattern 160c is electrically connected to a third transistor PTRs among the peripheral transistors PTR via a source contact plug CPs and a routing wire structure RWS penetrating the insulator stack region STi. The first layer 162 of the top plate pattern 160c is the common source (CSL in FIG. 1d) described in FIG. Therefore, the first layer 162 of the upper plate pattern 160c is electrically connected to the third transistor PTRs through the source contact plug CPs and the routing wire structure RWS.

[0088] The upper second transistor PTRg and the third transistor PTRs are transistors that configure the address decoder 93. Each capacitor block cBLK includes a capacitor CAP as described in FIG. 1d. Here, since FIG. 8c is a cross-sectional view mainly showing one capacitor cBLK among the capacitor blocks cBLK, the following description will focus on one capacitor cBLK.

[0089] Within the capacitor block cBLK, the conductive layer 126 includes a first lower conductive layer (126_1), a second lower conductive layer (126_2), a third lower conductive layer (126_3), a fourth lower conductive layer (126_4), a fifth lower conductive layer (126_5), a sixth lower conductive layer (126_6), a seventh lower conductive layer (126_7), an eighth lower conductive layer (126_8), and a ninth lower conductive layer (126_9) stacked in sequence. In the drawings, the conductive layers 126 are illustrated with nine layers as an illustrative example, although in embodiments, the conductive layers 126 may be more than nine layers.

[0090] The capacitor CAP in the capacitor block cBLK includes a first capacitor electrode (CAP_E1), a second capacitor electrode (CAP_E2), and a capacitor dielectric layer 124c. Within the capacitor block cBLK, the first capacitor electrode (CAP_E1) includes odd-numbered conductive layers (126_1, 126_3, 126_5, 126_7, 126_9) among the conductive layers 126, and the second capacitor electrode (CAP_E2) includes even-numbered conductive layers (126_2, 126_4, 126_6, 126_8) among the conductive layers 126. In this case, the capacitor dielectric layer 124c is an insulating layer disposed in the insulating layer 124 between the odd-numbered conductive layers (126_1, 126_3, 126_5, 126_7, 126_9) and the even-numbered conductive layers (126_2, 126_4, 126_6, 126_8).

[0091] In the embodiment, odd-numbered and even-numbered are defined based on the lowest conductive layer among the conductive layers 126 stacked in the vertical direction Z. In the embodiment, a case is described in which, among each conductive layer 126 of the capacitor block cBLK, the odd-numbered conductive layers (126_1, 126_3, 126_5, 126_7, 126_9) constitute a first capacitor electrode (CAP_E1), and the even-numbered conductive layers (126_2, 126_4, 126_6, 126_8) constitute a second capacitor electrode (CAP_E2), but the embodiment is not limited to this.

[0092] For example, in each conductive layer 126 of the capacitor block cBLK, a plurality of conductive layers adjacent to each other in the vertical direction constituting a first capacitor electrode (CAP_E1) and another pair of conductive layers adjacent to each other in the vertical direction constituting a second capacitor electrode (CAP_E2) may be arranged alternately and repeatedly in the vertical direction. For example, the first and second conductive layers (126_1, 126_2) adjacent to each other and the fifth and sixth conductive layers (126_5, 126_6) adjacent to each other constitute the first capacitor electrode (CAP_E1), and the third and fourth conductive layers (126_3, 126_4) adjacent to each other and the seventh and eighth conductive layers (126_7, 126_8) adjacent to each other constitute the second capacitor electrode (CAP_E2). Here, the ninth conductive layer (126_9) is an electrically isolated dummy.

[0093] In the following, in order to make the embodiment easier to understand, an example will be mainly described in which, among the respective conductive layers 126 of the capacitor block cBLK, the odd-numbered conductive layers (126_1, 126_3, 126_5, 126_7, 126_9) form the first capacitor electrode (CAP_E1), and the even-numbered conductive layers (126_2, 126_4, 126_6, 126_8) form the second capacitor electrode (CAP_E2).

[0094] Each conductive layer 126 of the capacitor block cBLK is electrically connected to a capacitor contact plug CPc. The capacitor contact plugs CPc include a first capacitor contact plug CPc1 connected to the odd-numbered conductive layers (126_1, 126_3, 126_5, 126_7, 126_9) constituting the first capacitor electrode (CAP_E1), and a second capacitor contact plug CPc2 connected to the even-numbered conductive layers (126_2, 126_4, 126_6, 126_8) constituting the second capacitor electrode (CAP_E2).

[0095] The first capacitor contact plugs CPc1 are electrically connected by a first capacitor electrode wiring CW1, and the second capacitor contact plugs CPc2 are electrically connected by a second capacitor electrode wiring CW2. A conductive via CCP formed by the first upper vertical portion 144a of the upper vertical portion of the upper wiring structure 140 of the routing wiring structure RWS is arranged between the first and second capacitor contact plugs (CPc1, CPc2) and the first and second capacitor electrode wirings (CW1, CW2). Here, the conductive via CCP is referred to as a contact plug or a conductive stud.

[0096] The insulating spacer 132 covering the side surface of the capacitor contact plug CPc is disposed at a lower level than the conductive layer in contact with the capacitor contact plug CPc. For example, the capacitor contact plug CPc shown in FIG. 8d is electrically connected to the fifth conductive layer (126_5), and the insulating spacer 132 is arranged at a level lower than the fifth conductive layer (126_5) and separates the capacitor contact plug CPc from the first to fourth conductive layers (126_1, 126_2, 126_3, 126_4), which are arranged at a level lower than the fifth conductive layer (126_5). Thus, the insulating spacer 132 electrically connects the capacitor contact plug CPc to the conductive layer at the desired location.

[0097] The first and second capacitor electrode wirings (CW1, CW2) are formed as part of the routing wiring structure RWS. For example, the first and second capacitor electrode wirings (CW1, CW2) are formed of a portion of the horizontal portions (142a, 142b, 142c) of the upper wiring structure 140 of the routing wiring structure RWS, for example, the first horizontal portion 142a. At least one of the first and second capacitor electrode wirings (CW1, CW2) is electrically connected to one of the circuits PTRc via a routing wiring structure RWS.

[0098] Any one of the circuits PTRc configured to be electrically connected to the capacitor CAP via the first and second capacitor electrode wirings (CW1, CW2) and the routing wiring structure RWS includes a transistor or a PN diode. For example, in FIG. 8c, the portion of the circuit PTRc electrically connected to the first capacitor electrode (CAP_E1) of the capacitor CAP is illustrated as a transistor, but in some embodiments, the portion of the circuit PTRc electrically connected to the first capacitor electrode (CAP_E1) may also be a PN diode.

[0099] The conductor stack region STc further includes a dielectric layer 127 covering the upper and lower surfaces of each of the conductive layers 126 and covering at least a portion of each of the side surfaces of the conductive layers 126 . For example, the dielectric layer 127 covers the upper and lower surfaces of the conductive layer 126, extends between the sides of the conductive layer 126 and the sides of the vertical structures (VSm, VSmd1, VSmd2, VScd, VSd, VSde) that penetrate the conductor stack region STc, and extends between the sides of the insulating spacer 132 and the conductive layer 126 that is horizontally adjacent to the insulating spacer 132. The contact plugs CPg and CPc penetrate the dielectric layer 127 covering the bottom surface of the conductive layer 126 to contact the conductive layer 126 .

[0100] Various modifications of the components of the above-described embodiments will now be described. Various modifications of the components of the above-described embodiments will be described below with a focus on modified or substituted components. Here, the components described above may be directly cited without additional detailed description, or the description may be omitted. In addition, the modified or alternative components described below will be described with reference to the following drawings, and the modified or alternative components may be combined with each other or with the components described above to form a semiconductor device according to an embodiment of the present invention.

[0101] Next, with reference to FIG. 9, an example in which the arrangement shape of the components in the top view of FIG. 4b is modified will be described. FIG. 9 is a top view for explaining an example in which the arrangement shape of the components in the top view of FIG. 4b is modified.

[0102] 9, a plurality of isolation patterns 103 are disposed between horizontal portions (SP_H) of a pair of isolation structures SP adjacent to each other in the second direction Y. As shown in FIG. The vertical memory structures VSm are arranged in a zigzag manner in a first direction X and spaced apart from each other in a second direction Y. The center-to-center distance of the bit lines BL is substantially the same as the center-to-center distance of the vertical memory structures VSm arranged in a zigzag manner in the first direction X. Therefore, each of the vertical memory structures VSm arranged in a zigzag pattern in the first direction X is vertically overlapped and electrically connected to one of the bit lines BL.

[0103] Next, various modifications of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. 10a, 10b, 10c, 10d, 10e, 10f, and 10g, respectively. 10a, 10b, 10c, 10d, 10e, 10f, and 10g are partially enlarged sectional views showing modifications of the partially enlarged sectional view of FIG. 8d. In the following, one of the capacitor contact plugs CPc will be mainly described. In the following, the contact plug described is one of the capacitor contact plugs CPc, but may also be one of the gate contact plugs CPg depending on the embodiment.

[0104] In a variant, referring to FIG. 10a, the insulating spacer described above (132 in FIG. 8d) includes a vertical portion 132V covering the side of the contact plug CPc and a protruding portion 132P extending from the vertical portion 132V between the adjacent insulating layer 124.

[0105] In a modified example, referring to FIG. 10b, the above-described vertical support structure VScd includes a first vertical support structure VScda that penetrates the conductive layer 126 and the insulating layer 124 located at a higher level than the contact plug CPc while contacting the upper region of the contact plug CPc. The first vertical support structure VScda contacts the contact plug CPc through the conductive layer 126_5 that contacts the contact plug CPc. In FIG. 10b, an insulating spacer 132a as in FIG. 10a is shown, but such an insulating spacer 132a may be replaced by an insulating spacer 132 as in FIG. 8d. In the drawings of the following embodiments, when components that can be modified or substituted as described above are shown, the components that can be modified or substituted can be understood from the modified embodiments described above without separate description.

[0106] In a modified embodiment, referring to FIG. 10c, although FIG. 10b illustrates one contact plug CPc contacting one first vertical support structure VScda, the embodiment is not limited thereto. For example, one contact plug CPc may be transformed into a contact plug (CPc_1) that contacts a plurality of first vertical support structures VScdb. Each of the plurality of first vertical support platform structures VScdb is substantially identical to the first vertical support platform structure VScda described in FIG. 10b.

[0107] In a modified example, referring to FIG. 10d, the first vertical support structure described above (VScdb in FIG. 10c) may be modified to a first vertical support structure VScdc extending downward from the upper region of the contact plug (CPc_1) to a level lower than the first conductive layer (126_1).

[0108] In a modified example, referring to FIG. 10e, the contact plug (CPc_1 in FIG. 10c) described above may be replaced with a contact plug (CPc_2) that covers the side and top surfaces of the insulating pillar 181. The contact plug CPc_2 is shaped to cover the lower surface of the first vertical support structure VScdb.

[0109] In a variant, referring to FIG. 10f, the contact plug (CPc_2) described above contacts the conductive pad 183 covering the lower surface of the insulating pillar 181 described above. The conductive pad 183 is disposed at a lower level than the first conductive layer (126_1) and is electrically connected to the conductive via CCP described above.

[0110] In a modified example, referring to FIG. 10g, the contact plug described above (CPc in FIG. 10b) is replaced with an insulating pillar 181, a first contact plug (CPc_3b) covering the side and top surfaces of the insulating pillar 181 and contacting the desired conductive layer (126_6), an insulating spacer 131 covering the outer surface of the first contact plug (CPc_3b), and a second contact plug (CPc_3a) disposed on the outer surface of the insulating spacer 131 and contacting the conductive layer (126_5) located directly below the conductive layer (126_6) in contact with the first contact plug (CPc_3b). Thus, the vertically adjacent conductive layers 126_5, 126_6 are connected to a contact structure including the first and second contact plugs CPc_3b, CPc_3a. In FIG. 10g, the first and second contact plugs (CPc_3b, CPc_3a) are shown as being electrically connected to conductive vias CCP, but in some embodiments, the first and second contact plugs (CPc_3b, CPc_3a) are electrically connected by a single conductive via CCP.

[0111] Next, with reference to FIG. 11, a modification of the above-described vertical memory structure (VSm in FIG. 8b) and the first layer (162 in FIG. 8b) of the top plate pattern 160c will be described. FIG. 11 is a partially enlarged cross-sectional view showing a modification of the partially enlarged view of FIG. 8b. In a modified example, referring to FIG. 11, a first layer (162 in FIG. 8b) of an upper plate pattern 160c includes a first material layer 161a, a second material layer 161b on the first material layer 161a, and a third material layer 161c on the second material layer 161b.

[0112] In the vertical memory structure VSm, the information storage structure 106a covers the sides and top surface of the channel layer 108, the first material layer 161a covers the sides of the information storage structure 106a on the topmost insulating layer of the insulating layers 124, the second material layer 161b penetrates the information storage structure 106a and contacts the channel layer 108, and the third material layer 161c is separated from the channel layer 108 by the information storage structure 106a. At least one of the first to third material layers (161a, 161b, 161c) includes doped silicon.

[0113] Next, various examples of the routing structure RWS constituting the capacitor routing (CAR in FIG. 6b) described above will be described with reference to FIGS. 12a to 12d, respectively. 12a to 12d are cross-sectional views showing various variations in the cross-sectional structure of FIG. 6b, which explains that "the capacitor routing wiring (CAR in FIG. 6b) is composed of the first horizontal portion 142a of the horizontal portion (142a, 142b, 142c) of the upper wiring structure 140 within the routing wiring structure RWS."

[0114] In a variant, referring to FIG. 12a, the capacitor routing line (CAR in FIG. 6b) is formed in the second horizontal portion 142b of the horizontal portions (142a, 142b, 142c) of the upper wiring structure 140 within the routing wiring structure RWS. In a variant, referring to FIG. 12b, the capacitor routing line (CAR in FIG. 6b) is formed in the third horizontal portion 142c of the horizontal portions (142a, 142b, 142c) of the upper wiring structure 140 within the routing wiring structure RWS.

[0115] In a variant, referring to FIG. 12c, the capacitor routing line (CAR in FIG. 6b) is formed in the third horizontal portion 210c of the horizontal portions (210a, 210b, 210c) of the lower wiring structure 208 within the routing wiring structure RWS. In a variant, referring to FIG. 12d, the capacitor routing line (CAR in FIG. 6b) is formed in the second horizontal portion 210b of the horizontal portions (210a, 210b, 210c) of the lower wiring structure 208 within the routing wiring structure RWS.

[0116] Next, a modified example of the capacitor block cBLK in the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. 13, 14a, and 14b. FIG. 13 is a top view showing the deformed components in the top view corresponding to FIG. 4a, FIG. 14a is a cross-sectional view showing the area cut along line Ia-Ia' in FIG. 13 and showing the deformed components in a cross-sectional structure corresponding to FIG. 6a, and FIG. 14b is a cross-sectional view showing the area cut along line IIa-IIa' in FIG. 13 and showing the deformed components in a cross-sectional structure corresponding to FIG. 6b.

[0117] 13, 14a, and 14b, in the capacitor block cBLK, the capacitor contact plug CPc1' electrically connected to the conductive layer 126 is electrically connected by a first capacitor electrode wiring CW1'. Therefore, in the capacitor block cBLK, the conductive layer 126 is one first capacitor electrode. In the capacitor block cBLK, the support structure VScd penetrating the conductive stack region STc in the capacitor block cBLK may be replaced with an electrode plug CPc2' and a dielectric layer 133 covering the side and top surfaces of the electrode plug CPc2'. The electrode plug CPc2' is electrically connected by a second capacitor electrode wiring CW2'. Therefore, the electrode plug CPc2' is one second capacitor electrode.

[0118] Thus, the capacitor of capacitor block cBLK (CAP in FIG. 1d) includes a capacitor including a first capacitor electrode formed by conductive layer 126, a second capacitor electrode formed by electrode plug CPc2′, and a dielectric layer 133 between the first capacitor electrode and the second capacitor electrode. The above-described upper plate pattern 160c may cover the capacitor CAP of the capacitor block cBLK, but may be modified to an upper plate pattern 160c' that does not cover the capacitor CAP of the capacitor block cBLK, depending on the embodiment.

[0119] Next, with reference to FIGS. 15, 16a, and 16b, modifications of the memory block mBLK and the capacitor block cBLK in the semiconductor device according to the embodiment of the present invention will be described. FIG. 15 is a top view showing the deformed components in a top view corresponding to FIG. 4a, FIG. 16a shows an area cut along line IVa-IVa' in FIG. 15, and FIG. 16b shows an area cut along line Vb-Vb' in FIG. 15.

[0120] 15, 16a, and 16b, the conductor stack region STc in which the above-described gate contact plugs CPg and capacitor contact plugs CPc are arranged is transformed into a conductor stack region STc' including a conductive layer 126 arranged in a stepped manner and having pad regions (PADg, PADc) connected to the contact plugs (CPg, CPc). Therefore, the memory block mBLK described above is transformed into a memory block mBLK' including a conductive layer 126 including a gate pad area PADg arranged in a stepped manner, and the capacitor block cBLK described above is transformed into a capacitor block cBLK' including a conductive layer 126 including a capacitor pad area PADc arranged in a stepped manner. The capacitor pad region PADc is electrically connected to the capacitor contact plug CPc, and the gate pad region PADg is electrically connected to the gate contact plug CPg.

[0121] Next, with reference to FIG. 17, a modification of the capacitor block cBLK in the semiconductor device according to the embodiment of the present invention will be described. FIG. 17 shows a section taken along line Vb-Vb' in FIG. Referring to Figure 17, in the embodiment described above with reference to Figures 1a to 17, the capacitor (CAP in Figures 1 and 8d) is described as using all of the conductive layers 126 in the capacitor block cBLK as the capacitor electrodes described above ((CAP_E1, CAP_E2) in Figure 8d), but the embodiment is not limited to this.

[0122] For example, in order to adjust the capacitance of a capacitor (CAP in Figures 1 and 8d), the capacitor block cBLK described above can be transformed into a capacitor block cBLK' in which only a portion of the conductive layer 126 is used as a capacitor electrode (CAP_E1, CAP_E2 in Figure 8d). For example, the lower conductive layer located in the lower region of the conductive layer 126 in the capacitor block cBLK' is an electrode layer used for the capacitor electrodes (CAP_E1, CAP_E2 in FIG. 8d), and the upper conductive layer located in the upper region of the conductive layer 126 in the capacitor block cBLK' is a dummy conductive layer not used for the capacitor electrodes (CAP_E1, CAP_E2 in FIG. 8d).

[0123] Next, modified examples of the capacitor block cBLK will be described with reference to FIGS. 18 and 19 are top views showing modifications of the capacitor block cBLK in the top view of FIG.

[0124] In the modified example, referring to FIG. 18, in the first direction X, at least some of the first to fourth capacitor blocks (cBLK1, cBLK2, cBLK3, cBLK4) of the capacitor block cBLK have lengths different from each other. For example, in the first direction X, the second capacitor block cBLK2 has a first length L1, and the third capacitor block cBLK3 has a second length L2 that is smaller than the first length L1.

[0125] In the modified example, referring to FIG. 19, in the second direction Y, each of the memory blocks mBLK has a first width W1, and at least one of the first to fourth capacitor blocks (cBLK1, cBLK2, cBLK3, cBLK4) of the capacitor block cBLK has a second width W2 different from the first width W1. The second width W2 is greater than the first width W1, but the embodiment is not limited thereto. For example, the second width W2 may be smaller than the first width W1.

[0126] Next, a modification of the capacitor block cBLK will be described with reference to FIG. FIG. 20 is a perspective view for explaining a modified example of the region in which a fourth circuit (CAP_C) configured to be electrically connected to capacitors (CAP in FIG. 1d) of multiple capacitor blocks cBLK is arranged in the perspective view of FIG. 3.

[0127] In a modified example, referring to FIG. 20, the first capacitor connection circuit (CAP_C1') configured to be electrically connected to the capacitors of the first capacitor block cBLK1, the second capacitor connection circuit (CAP_C2') configured to be electrically connected to the capacitors of the second capacitor block cBLK2, the third capacitor connection circuit (CAP_C3') configured to be electrically connected to the capacitors of the third capacitor block cBLK3, and the fourth capacitor connection circuit (CAP_C4') configured to be electrically connected to the capacitors of the fourth capacitor block cBLK4, partially overlap with a portion of the capacitor block cBLK, and partially do not overlap with the capacitor block cBLK.

[0128] For example, the first capacitor connection circuit (CAP_C1') configured to be electrically connected to the capacitor of the first capacitor block cBLK1 (CAP in Figure 1d) vertically overlaps with the first capacitor block cBLK1, while the second to fourth capacitor connection circuits (CAP_C2', CAP_C3', CAP_C4') do not vertically overlap with the capacitor block cBLK.

[0129] At least one of the second and third capacitor-connecting circuits (CAP_C2', CAP_C3') is adjacent to or surrounded by the first lower circuit (PC_1). The fourth capacitor-connected circuit (CAP_4') is adjacent to or surrounded by the second lower circuit (PC_2).

[0130] The embodiment of the present invention described with reference to Figures 2 to 20 focuses on one memory mat MAT among the multiple memory mats (MAT in Figure 1b) of the semiconductor device CH described in Figure 1b, but the embodiment is not limited to this. In the following, a first mat and a second mat adjacent to each other in the first direction X among the multiple memory mats (MATs in FIG. 1b) of the semiconductor device CH described in FIG. 1b will be mainly described.

[0131] First, referring to Figures 21a and 21b, an illustrative example of a semiconductor device CH including a first mat MAT1 and a second mat MAT2 adjacent to each other in a first direction X among the multiple memory mats (MATs in Figure 1b) described in Figure 1b will be described. 21a and 21b, FIG. 21a is a top view showing an illustrative example of a semiconductor device CH according to one embodiment of the present invention, and FIG. 21b is a perspective view showing an illustrative example of a semiconductor device CH according to one embodiment of the present invention.

[0132] 21a and 21b, the semiconductor device CH includes a first mat MAT1 and a second mat MAT2 adjacent to each other in a first direction X. As shown in FIG. Each of the first and second mats (MAT1, MAT2) may include the first chip structure (CH_L) and the second chip structure (CH_U) described with reference to FIGS.

[0133] As described in FIGS. 2 to 20, the second chip structure (CH_U) includes a plurality of blocks (cBLK, mBLK, dBLK) described in FIGS. The second chip structure (CH_U) further includes an intermediate block iBLK disposed between the first and second MATs (MAT1, MAT2).

[0134] The separation structure SP described in Figures 2 to 20 is transformed into a separation structure SPi that defines a plurality of blocks (cBLK, mBLK, dBLK) in the first and second mats (MAT1, MAT2) and extends between the first and second mats (MAT1, MAT2) to define an intermediate block iBLK. The conductor stacking region STc described in Figures 2 to 20 is transformed into a conductor stacking region STca including multiple blocks (cBLK, mBLK, dBLK) in the first and second mats (MAT1, MAT2), an intermediate block iBLK, and a rectangular ring-shaped edge block SPe surrounding the outer surface of the isolation structure SPi. Each of the multiple blocks (cBLK, mBLK, dBLK), the intermediate block iBLK, and the edge block SPe includes the insulating layer 124 and the conductive layer 126 described with reference to FIGS. The insulator laminated region STi described above has a shape surrounding the outside of the conductor laminated region STca. Therefore, the semiconductor device CH includes a stack structure ST' including a conductor stack region STca and an insulator stack region STi.

[0135] The above-described multiple lower circuits (PC_1, PC_2, PC_3, CAP_C) are disposed below the respective first and second MATs (MAT1, MAT2). In the embodiment, the intermediate block iBLK is a dummy block, but the embodiment is not limited to this. At least a portion of the intermediate block iBLK is a capacitor block cBLK. Therefore, when at least a portion of the intermediate block iBLK is a capacitor block, the capacitor block (cBLK in FIG. 1d) includes a capacitor block cBLK contained within the first and second MATs (MAT1, MAT2) and a capacitor block iBLK arranged between the first and second MATs (MAT1, MAT2).

[0136] Next, an illustrative example in which the intermediate block (iBLK in Figs. 21a and 21b) is replaced by a capacitor block cBLK including a capacitor (CAP in Fig. 1d) will be described with reference to Figs. 22a, 22b and 23. FIG. 22a is a top view showing an illustrative example of a semiconductor device CH according to one embodiment of the present invention, FIG. 22b is an oblique view showing an illustrative example of a semiconductor device CH according to one embodiment of the present invention, and FIG. 23 is a cross-sectional view showing an area cut along line X-X' in FIG. 22b.

[0137] 22a, 22b, and 23, at least one of the intermediate blocks (iBLK in FIGS. 21a and 21b) described in FIGS. 21a and 21b may be replaced with a capacitor block cBLK. In Figures 22a, 22b, and 23, the first and second MATs (MAT1, MAT2) are shown as not including a capacitor block cBLK, however, as described in the immediately preceding embodiment, in some embodiments, the first and second MATs (MAT1, MAT2) may also include a capacitor block cBLK.

[0138] The capacitor block cBLK is disposed between the blocks (mBLK, dBLK) of the first MAT1 and the blocks (mBLK, dBLK) of the second MAT2. Each of the capacitor blocks cBLK has a bar shape extending in the first direction X. The capacitor blocks cBLK are spaced apart from each other in the second direction Y by isolation structures SPi. Each of the capacitor blocks cBLK disposed between the first and second mats (MAT1, MAT2) includes an insulating layer 124 and a conductive layer 126 as described with reference to FIGS.

[0139] In such a capacitor block cBLK, the conductive layer 126 constituting the capacitor electrode is electrically connected to the capacitor contact plug CPc as described above. The capacitor contact plugs CPc are electrically connected by capacitor electrode wirings CW. Each of the first and second mats (MAT1, MAT2) includes the top plate pattern 160c described above. The upper plate pattern 160c of the first mat MAT1 and the plate pattern 160c of the second mat MAT2 are spaced apart from each other in the first direction X.

[0140] As described above, the first chip structure (CH_L) includes a fourth circuit (CAP_C) configured to be electrically connected to the capacitors (CAP in FIG. 1d) of the multiple capacitor blocks cBLK. At least a portion of the fourth circuit (CAP_C) vertically overlaps at least a portion of the plurality of capacitor blocks cBLK.

[0141] Next, a modified example of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. 24, 25, 26a, 26b, 26c, 27a and 27b. 24 to 27b, FIG. 24 is a top view showing a modified example of a semiconductor device CH according to one embodiment of the present invention, FIG. 25 is an oblique view showing a modified example of a semiconductor device CH according to one embodiment of the present invention, FIG. 26a is a partially enlarged view showing the area indicated by "Aa" in FIG. 24, FIG. 26b is a partially enlarged view showing the area indicated by "Ba" in FIG. 24, FIG. 26c is a partially enlarged view showing the area indicated by "Baa" in FIG. 26b, FIG. 27a is a cross-sectional view showing the area cut along line VI-VI' in FIG. 26a, and FIG. 27b is a cross-sectional view showing the area cut along line VII-VII' in FIG. 26b.

[0142] Referring to Figures 24 to 27b, the capacitor block cBLK described in Figures 2 to 20 is arranged between the adjacent dummy block dBLK and first memory block mBLKa in the second direction U, but the embodiment is not limited to this. For example, as shown in FIGS. 24 to 27b, a capacitor block (cBLK in FIG. 1d) is disposed between a plurality of memory blocks mBLK among the memory blocks mBLK that are parallel to each other and spaced apart from each other in the second direction Y.

[0143] As described above, the first chip structure (CH_L) has at least a portion of the fourth circuit (CAP_C) configured to be electrically connected to the capacitors (CAP in FIG. 1d) of the multiple capacitor blocks cBLK, vertically overlapping at least a portion of the multiple capacitor blocks cBLK and disposed between the first and second lower circuits (PC_1, PC_2). The upper plate pattern 160c described above covers the upper part of the stack region STc in the memory block mBLK and also covers the upper part of the stack region STc in the capacitor block cBLK. The bit lines BL described above cross a plurality of memory blocks mBLK in the second direction Y. Therefore, the bit lines BL cross the capacitor blocks cBLK disposed between the memory blocks mBLK.

[0144] Each of the capacitor blocks cBLK may include the insulating layer 124 and the conductive layer 126 as described in Figures 2 to 20. The conductive layer 126, which may constitute a capacitor electrode in the capacitor block cBLK, may be electrically connected to the capacitor contact plug CPc as described above. The capacitor contact plug CPc may be electrically connected by capacitor electrode wirings CW1 and CW2.

[0145] The upper wiring structure 140 further includes an upper horizontal portion 142c disposed at a higher level than the first horizontal portion 142a, which may constitute a bit line BL. The upper horizontal portion 142c constitutes the capacitor electrode wirings (CW1, CW2). The vertical portion 144 of the upper wiring structure 140 further includes a first upper vertical portion constituting a first contact plug CP between the capacitor electrode wirings (CW1, CW2) and the capacitor contact plug CPc, which electrically connects the capacitor electrode wirings (CW1, CW2) and the capacitor contact plug CPc, and a second upper vertical portion constituting a second contact plug cPL below the capacitor electrode wirings (CW1, CW2), passing between the bit lines BL, and electrically connected to the wiring formed by the second horizontal portion 142b.

[0146] The bit lines BL are parallel to each other at regular intervals in the memory block mBLK, and in the region where the second contact plugs cPL are arranged, the interval between the bit lines BL increases so that the second contact plugs cPL can pass between the bit lines BL. Therefore, the bit line BL adjacent to the second contact plug cPL among the bit lines BL has a line shape extending in the second direction Y on the memory block mBLK, and has a curved shape on the capacitor block cBLK.

[0147] Next, an illustrative example of a method for forming the above-mentioned semiconductor device CH will be described with reference to FIG. Referring to FIG. 28 in conjunction with FIGS. 1 to 27b, a first semiconductor chip is formed (S10). The first semiconductor chip is the first chip structure (CH_L) of the embodiment described with reference to FIGS. 1 to 27b.

[0148] A second semiconductor chip is formed (S20). The second semiconductor chip includes a part of the second chip structure (CH_U) of the embodiment described with reference to FIGS. 1 to 27b. For example, the second semiconductor chip includes a stack structure ST including an insulator stack region STi and a conductor stack region STc constituting a plurality of blocks (mBLK, dBLK, cBLK) in the second chip structure (CH_U) of the embodiment described with reference to Figures 1 to 27b, a vertical structure VS, an upper bonding pad 148, and an upper wiring structure 140.

[0149] The first semiconductor chip and the second semiconductor chip are bonded together (S30). Bonding the first semiconductor chip and the second semiconductor chip includes bonding the lower bonding pads (214 in FIG. 6a) of the first semiconductor chip and the upper bonding pads (214 in FIG. 6a) of the second semiconductor chip using a metal-to-metal bonding process. A superstructure including an input / output pad IOP is formed (S40). The upper structure further includes a top plate pattern 160c.

[0150] Next, with reference to FIG. 29, a data storage system including a semiconductor device according to an embodiment of the present invention will be described. FIG. 29 is a block diagram showing a schematic configuration of an electronic system (data storage system) including a semiconductor device according to an embodiment of the present invention. Referring to FIG. 29, an electronic system 1000 according to an embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 .

[0151] The electronic system 1000 may be a storage device that includes one or more semiconductor devices 1100 or an electronic device that includes a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communications device that includes one or more semiconductor devices 1100 .

[0152] The semiconductor device 1100 may be a non-volatile memory device, for example, a semiconductor device according to any one of the embodiments described with reference to FIGS. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F is a first chip structure (CH_L) of any one of the embodiments described above, and the second structure 1100S is a second chip structure (CH_U) of any one of the embodiments described above.

[0153] The first chip structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. In an exemplary embodiment, the peripheral circuit 14 of the first chip structure 1100F of any one of the embodiments described above is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second chip structure 1100S is a memory vertical structure including bit lines BL, common source lines CSL, word lines WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings CSTR between the bit lines BL and the common source lines CSL. In the exemplary embodiment, at least a portion of the above-mentioned upper plate pattern 160c constitutes a common source line CSL.

[0154] In an exemplary embodiment, the first and second gate bottom lines (LL1, LL2), the word line WL, and the first and second gate top lines (UL1, UL2) are conductive layers 126 of the memory block mBLK of any one of the embodiments described above. Thus, the conductive layer 126 of the memory block mBLK includes first and second gate lower lines (LL1, LL2), a word line WL, and first and second gate upper lines (UL1, UL2). At least some of the first and second gate lower lines (LL1, LL2) and the first and second gate upper lines (UL1, UL2) are select gate electrodes.

[0155] In the second chip structure 1100S, each memory cell string CSTR includes a lower transistor (LT1, LT2) adjacent to a common source line CSL, an upper transistor (UT1, UT2) adjacent to a bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistor (LT1, LT2) and the upper transistor (UT1, UT2). The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment. The plurality of memory cell transistors MCT include an information storage region capable of storing information (data).

[0156] In an exemplary embodiment, the upper transistors (UT1, UT2) comprise string select transistors and the lower transistors (LT1, LT2) comprise ground select transistors. The gate lower lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0157] In an exemplary embodiment, the lower transistors (LT1, LT2) include a series-connected lower erase control transistor LT1 and a ground select transistor LT2. The upper transistors (UT1, UT2) include a series-connected string select transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 is used for an erase operation that erases data stored in the memory cell transistor MCT by utilizing a Gate Induce Drain Leakage (GIDL) phenomenon.

[0158] The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from within the first chip structure 1100F to the second chip structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from within the first structure 1100F to the second structure 1100S.

[0159] In the first chip structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform a control operation on at least one selected memory cell transistor among the multiple memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130 .

[0160] The semiconductor device 1000 communicates with the controller 1200 via an input / output pad 1101 that is electrically connected to the logic circuit 1130 . The input / output pads 1101 are electrically connected to the logic circuit 1130 via input / output connection wiring 1135 that extends from within the first chip structure 1100F to the second chip structure 1100S. The input / output pad 1101 is the input / output pad IOP described above.

[0161] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 includes multiple semiconductor devices 1100 , where the controller 1200 controls the multiple semiconductor devices 1100 .

[0162] The processor 1210 controls the overall operation of the electronic system 1000 , including the controller 1200 . The processor 1210 operates according to predetermined firmware, and controls the NAND controller 1220 to access the semiconductor device 1100 . The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100 . Control commands for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. are transmitted via the NAND interface 1221.

[0163] The host interface 1230 provides communication between the electronic system 1000 and an external host. When a control command is received from an external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0164] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0165] 1 Semiconductor device 5 Main Board 10 Controller 15 Semiconductor Package 15a, 15b (first and second) semiconductor packages 20 DRAM 25 Wiring Pattern 30 Connectors 40 Upper wiring structure 50 Package Substrate 55 Package Top Pad 60 Adhesive layer 70 Connecting Structures 80 Molding Layer 93 Address Decoder 94 Control Logic 95 page buffer 96 Input / Output Circuit 97 Voltage Generation Circuit 103 Separation Pattern 120 First insulating layer 122 Second insulating layer 124 Insulating layer 126 Conductive Layer 132 Insulating spacer 140 Upper wiring structure 142 Upper horizontal part 142a, 142b, 142c (1st to 3rd) Upper horizontal part 144 Upper vertical section 144a, 144b, 144c, 144d (1st to 4th) upper vertical part 148 Upper bonding pad 150 Upper insulation structure 160c top plate pattern 160p Pad Pattern 162 1st layer 164 2nd layer 170 Insulating Layer 174 Capping insulation layer 208 Lower wiring structure 210 Lower horizontal part 210a, 210b, 210c (1st to 3rd) lower horizontal part 212 Lower vertical part 212a, 212b, 212c, 212d (1st to 4th) lower vertical part 214 Lower Bonding Pad 220 Lower insulation structure CAP Capacitor cBLK Capacitor block IOP Input / Output Pad mBLK Memory Block RWS Routing Wiring Structure SP separation structure ST Laminated structure STc Conductive layered area STi insulator stack area

Claims

1. A peripheral circuit structure; a stacked structure vertically overlapping the peripheral circuit structure; a separation structure penetrating the laminated structure, the laminated structure includes a plurality of blocks separated from one another by first portions of the isolation structures; each of the plurality of blocks includes insulating and conductive layers stacked alternately in a vertical direction; a first capacitor block disposed between adjacent first blocks among the first blocks; and a second capacitor block disposed between adjacent first blocks among the first blocks.

2. the plurality of capacitor blocks are separated from one another by a second portion of the isolation structure; Each of the plurality of capacitor blocks includes a capacitor; 2. The semiconductor device according to claim 1, wherein the capacitor includes a capacitor electrode formed of the conductive layer, and a capacitor dielectric layer formed of the insulating layer.

3. the peripheral circuit structure includes a first peripheral circuit; the first peripheral circuit is electrically connected to a first capacitor of a first capacitor block among the plurality of capacitor blocks to form a circuit; 3. The semiconductor device according to claim 2, wherein the first peripheral circuit vertically overlaps at least a portion of the first capacitor.

4. 2. The semiconductor device according to claim 1, wherein a side surface of at least one of the plurality of capacitor blocks is surrounded by the isolation structure.

5. 2 . The semiconductor device according to claim 1 , wherein each of the plurality of blocks has a side surface surrounded by the isolation structure.

6. the first block includes a plurality of memory blocks and at least one dummy block; 2. The semiconductor device according to claim 1, wherein the conductive layer in the plurality of memory blocks includes a word line.

7. the plurality of memory blocks includes a first memory block adjacent to the plurality of capacitor blocks; 7. The semiconductor device according to claim 6, wherein the plurality of capacitor blocks are disposed between the first memory block and the at least one dummy block.

8. a vertical memory structure extending through the plurality of memory blocks; a first vertical support structure passing through the plurality of capacitor blocks; a bit line electrically connected to the vertical memory structure, 7. The semiconductor device according to claim 6, wherein at least a portion of the plurality of capacitor blocks does not vertically overlap the bit line.

9. the plurality of memory blocks includes a plurality of first memory blocks and a plurality of second memory blocks; 7. The semiconductor device according to claim 6, wherein the capacitor block is disposed between the plurality of first memory blocks and the plurality of second memory blocks.

10. a vertical memory structure extending through the memory block; a bit line electrically connected to the vertical memory structure, 10. The semiconductor device of claim 9, wherein at least one of the plurality of capacitor blocks vertically overlaps the bit line.

11. Each of the first blocks extends in a first direction; the plurality of capacitor blocks are disposed between adjacent first blocks in a second direction perpendicular to the first direction; The semiconductor device according to claim 1 , wherein the plurality of capacitor blocks are spaced apart from each other in the second direction.

12. 2. The semiconductor device according to claim 1, further comprising a signal path electrically connecting one of the plurality of capacitor blocks to the peripheral circuit structure.

13. a first chip structure; a second chip structure vertically overlapping the first chip structure, the first chip structure includes a peripheral circuit; The second chip structure includes: A laminated structure; a separation structure penetrating the laminated structure; A plurality of contact plugs; an input / output pad; The laminated structure includes a plurality of blocks spaced apart from one another, each of the plurality of blocks includes insulating and conductive layers stacked alternately in a vertical direction; the plurality of blocks include a plurality of memory blocks and a capacitor block; the first and second chip structures further include a routing structure between the peripheral circuit and the stack structure; the plurality of contact plugs includes a first input / output contact plug penetrating the stack structure; the first I / O contact plug is electrically connected to a first I / O pad among the I / O pads; the capacitor block includes a first capacitor electrode and a second capacitor electrode; the first capacitor electrode is formed from a plurality of first conductive layers among the conductive layers; the second capacitor electrode is formed from a second plurality of the conductive layers; the first capacitor electrode is electrically connected to the first I / O pad via the first I / O contact plug and the routing wiring structure.

14. 14. The semiconductor device of claim 13, wherein the second capacitor electrode is grounded to a ground region of the first chip structure via the routing wire structure.

15. The routing structure of the first chip structure is lower vertical portions arranged at different levels; a lower wiring structure including lower horizontal portions disposed at different levels; The routing structure of the second chip structure is upper vertical portions arranged at different levels; an upper wiring structure including upper horizontal portions disposed at different levels; 14. The semiconductor device of claim 13, wherein at least one of the lower and upper horizontal portions of the routing wiring structure constitutes a capacitor routing wiring that electrically connects the first capacitor electrode and the first input / output pad.

16. The plurality of contact plugs include a first capacitor contact plug connected to the first conductive layers constituting the first capacitor electrode; a second capacitor contact plug connected to the second conductive layers constituting the second capacitor electrode; The routing structure of the second chip structure is a first capacitor connection wiring that electrically connects the first capacitor contact plugs to each other; 16. The semiconductor device according to claim 15, further comprising: a second capacitor connection wiring that electrically connects the second capacitor contact plugs to each other.

17. The routing wiring structure of the first chip structure further includes a lower bonding pad on the lower wiring structure, the routing wiring structure of the second chip structure further includes an upper bond pad; The semiconductor device of claim 15 , wherein the upper bonding pad is disposed under the upper wiring structure and bonded to the lower bonding pad.

18. the isolation structure surrounds a side surface of the capacitor block; 16. The semiconductor device of claim 15, wherein a block adjacent to the capacitor block among the plurality of blocks is separated from the capacitor block by the isolation structure.

19. a semiconductor device including an input / output pad; a controller electrically connected to the semiconductor device via the input / output pad and controlling the semiconductor device; The semiconductor device includes: A peripheral circuit structure; a stacked structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating the laminate structure, the laminated structure includes a plurality of blocks separated from one another by the separation structures, each of the plurality of blocks includes insulating and conductive layers stacked alternately in a vertical direction; the plurality of blocks include a plurality of first blocks and a plurality of capacitor blocks disposed between adjacent first blocks among the plurality of first blocks; The plurality of capacitor blocks are separated from each other by the isolation structure.

20. Each of the plurality of capacitor blocks includes a capacitor; the capacitor includes a capacitor electrode formed of the conductive layer and a capacitor dielectric layer formed of the insulating layer; 20. The data storage system of claim 19, wherein a side surface of at least one of the plurality of capacitor blocks is surrounded by the isolation structure.

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