Dynamic control of output driver in switching amplifier

Abstract

To provide a switching amplifier that optimally controls the slew rate to control overshoot and undershoot and reduce EMI.SOLUTION: A switching driver circuit with a slew rate control 500 includes a slew control circuit 510 including a current source 511 coupled in series at a connection node 512-3 with a first switch transistor 512-1 and a second switch transistor 512-2 connected in parallel. The connection node is coupled to a control terminal 503 of an output transistor DN2. The first switch transistor includes a control terminal coupled to a switching input signal LG-N. The second switch transistor includes a control terminal coupled to either the switching input signal or a dynamically modulated switching input signal 519 depending on the current direction at the output node.SELECTED DRAWING: Figure 5

Description

[Background technology]

[0001]

[0001] The present invention relates to the field of electronic circuits in audio systems. More particularly, the present invention relates to dynamic control techniques for improving device performance. Embodiments of the present invention may also be applied to other circuits, such as efficient switched power conversion circuits.

[0002] Switching amplifiers, also known as switching amplifiers, are electronic amplifiers in which transistors operate as binary switches. They are either fully on or fully off. Switching amplifiers ideally employ rail-to-rail output switching, where their output transistors virtually always carry either zero current or zero voltage. Thus, their power losses are minimal, and they achieve high efficiency over a wide range of power levels. Their advantageous high efficiency has driven their use in a variety of audio applications, from mobile phones to flat screen televisions and home theater receivers. Switching audio power amplifiers are more efficient than class AB audio power amplifiers. Because of their higher efficiency, switching amplifiers require smaller power supplies and eliminate heat sinks, significantly reducing the overall system cost, size, and weight.

[0003]

[0003] A switching audio power amplifier converts an audio signal into high frequency pulses and switches the output according to an audio input signal. Some switching amplifiers use a pulse width modulator (PWM) to generate a series of regulated pulses whose width varies with the amplitude of the audio signal. The variable width pulses switch the power output transistors at a fixed frequency. Other switching amplifiers may rely on other types of pulse modulators. The following discussion primarily refers to pulse width modulators, but those skilled in the art will recognize that switching amplifiers can be configured with other types of modulators.

[0004]

[0004] Figure 1 is a simplified circuit diagram of a conventional switching amplifier. As shown in Figure 1, switching amplifier 100 is a differential amplifier. A differential input audio signal INP, INM is input to comparators 101, 102, which compare the input signals INP, INM with a triangular wave VREF generated from oscillator 103 to generate PWM signals 106, 107. The PWM signals 106 and 107 are coupled to the gates of transistors M1, M2, M3, and M4, respectively. The differential output signals of the switching amplifier are provided at terminals labeled OUTP and OUTN, respectively. As shown in Figure 1, the output terminals OUTP and OUTN are connected to a speaker load 110, represented by an inductor L1 and a resistor R1.

[0005]

[0005] Figure 2 is a waveform diagram showing the modulation of signals in the switching amplifier of Figure 1. As shown in Figure 2, a differential input signal, for example audio signals INM and INP, is compared to a triangular reference waveform by two comparators as described above in connection with Figure 1. The output signal of the comparator is a fixed frequency pulse signal whose pulse width is proportional to the input signal. Two PWM signals are shown in Figure 2 as OUTP and OUTN.

[0006]

[0006] Device breakdown and electromagnetic interference (EMI) are major issues in switching audio amplifiers and DC-DC switching regulators. Any system employing pulse width modulation to drive large power transistors with low voltage devices is susceptible to these problems.

[0007]

[0007] The cause of these problems was the inability to control all signal transition edges during turn-off, resulting in large overshoots and undershoots. Existing techniques often rely on increasing the dead time or applying a much slower slew rate to prevent EMI and device damage problems. However, such designs have the drawback of slowing down circuit speed and poor total harmonic distortion (THD) performance. There is a trade-off in controlling slew rate versus EMI and device breakdown as well as THD performance, and the two are inversely related, making the optimal design of slew control to meet both specification parameters a difficult task.

[0008]

[0008] Therefore, there is a need for improved solutions to the problems discussed above. definition

[0009]

[0009] Terms used in this disclosure generally have their ordinary meaning in the art within the context of the present invention. Certain terms are discussed below to provide additional guidance to the practitioner regarding the description of the present invention. It will be understood that the same thing may be said in more than one way. Therefore, alternative phrases and synonyms may be used.

[0010]

[0010] As used herein, a switching amplifier refers to an electronic amplifier in which the amplifying device (a transistor, typically a MOSFET) operates as an electronic switch, rather than as a linear gain device like other amplifiers. They operate by rapidly switching back and forth between supply rails and are fed by a modulator that uses pulse width, pulse density, or related techniques to encode the input into a pulse train. Common types of switching amplifiers include class D amplifiers and switched mode power controlled amplifiers.

[0011]

[0011] A Class D amplifier is a type of switching amplifier that is often used in audio amplifier applications.

[0012]

[0012] As used herein, a switching control signal or switching signal refers to a signal that switches back and forth between supply rails to control an amplifying device, such as is used in a switching amplifier.

[0013]

[0013] As used herein, a differential amplifier or single-ended amplifier refers to a differential amplifier that amplifies the difference between its two inputs, while a single-ended amplifier amplifies the difference between its single input and ground.

[0014] As used herein, slew rate refers to the change in voltage or current, or another electrical quantity, per unit time.

[0015] As used herein, total harmonic distortion (THD) refers to a measurement of how much of the distortion in a voltage or current is due to harmonics in the signal.

[0016] As used herein, an H-bridge circuit refers to an electronic circuit that switches the polarity of a voltage applied to a load. Its common circuit diagram includes four switching elements arranged as the branches of the letter "H" and the load connected as a crossbar.

[0017] As used herein, dead time refers to the time when both the high-side and low-side transistors in a half-bridge switching circuit are off.

[0018]

[0018] A power converter is an electrical or electromechanical device for transforming electrical energy, such as converting between AC and DC, or changing voltage, current, or frequency, or some combination of these transformations. Power converters often include voltage regulation.

[0019]

[0019] Switching regulators, or switched mode power supplies (SMPS), use active devices that switch on and off to maintain an average value of the output. In contrast, linear regulators are operated like variable resistors, continuously adjusting a voltage divider network to maintain a constant output voltage, dissipating power continuously.

[0020] A voltage reference is an electronic device that ideally produces a fixed (constant) voltage regardless of the load on the device, power supply fluctuations, temperature changes, and the passage of time.

[0021] A reference voltage is a voltage value that is the subject of a comparison operation.

[0022]

[0022] When the term "same" is used to describe two quantities, it means that the values ​​of the two quantities are determined to be the same within measurement or manufacturing limits. Summary of the Invention

[0023]

[0023] The inventors have observed that switching amplifiers are susceptible to device breakdown and EMI problems, and that conventional solutions often result in poor slew rate and poor THD performance. An embodiment of the present invention addresses these problems by dynamically adjusting the slew rate and maintaining THD performance. Critical signal transition edges are identified by input switching signals and output current detection. A slew control circuit is dynamically turned on only at critical signal transition edges to avoid overshoots and undershoots and improve breakdown and EMI problems. At non-critical output transition edges, slew rate control is not applied to allow high slew rate edges.

[0024]

[0024] In some embodiments, the slew rate information from the output is combined with the current direction so that the drive strength is dynamically adjusted, which results in maintaining good THD performance and optimally controls the slew rate to control overshoot and undershoot during all transitions (both during turn-off and turn-on) and reduce EMI.

[0025] According to some embodiments of the present invention, a switching amplifier circuit includes a first output stage including a first pull-up transistor and a first pull-down transistor connected in series at a first output node between a first and a second reference voltage. The first pull-up and pull-down transistors have control terminals for receiving a first differential switching control signal from the switched modulator. The first output node provides a first differential output signal to a first end of a load device. The switching amplifier circuit also includes a second output stage including a second pull-up transistor and a second pull-down transistor connected in series at a second output node between the first and the second reference voltage. The second pull-up and pull-down transistors have control terminals for receiving a second differential switching control signal from the switched modulator. The second output node provides a second differential output signal to a second end of the load device. The switching amplifier circuit also includes a current direction detection circuit coupled to the first output of the switched modulator and the second output of the switched modulator for determining a direction of the output current and providing a current direction signal indicative of whether the output current flows from the first output node to the second output node or the output current flows from the second output node to the first output node. The switching amplifier circuit also includes first, second, third, and fourth slew control circuits responsive to the current direction signal and coupled to the first pull-up transistor, the first pull-down transistor, the second pull-up transistor, and the second pull-down transistor, respectively. The first slew control circuit is activated only during a turn-off of the first pull-up transistor when the output current flows from the first output node to the second output node. The second slew control circuit is activated only during a turn-off of the first pull-down transistor when the output current flows from the second output node to the first output node. The third slew control circuit is activated only during a turn-off of the second pull-up transistor when the output current flows from the second output node to the first output node. The fourth slew control circuit is activated only during the turn-off of the second pull-down transistor when the output current flows from the first output node to the second output node.

[0026] In some embodiments of the above switching amplifier circuit, a given slew control circuit is coupled to a control terminal of the output transistor, the slew control circuit including a current source coupled in series with a first switch transistor and a second switch transistor connected in parallel, the first switch transistor having a control terminal coupled to a switching input signal, and the second switch transistor having a control terminal coupled to either the switching input signal or a dynamically modulated switching signal that reduces the slew rate depending on the current direction at the output node.

[0027] In some embodiments, the dynamically modulated switching input signal includes the switching input signal and a first pulse signal determined by a high pass filter coupled to the output node.

[0028] In some embodiments, the second switch transistor is characterized by an on-resistance that is 25% or less of the on-resistance of the first switch transistor.

[0029] In some embodiments, the second switch transistor is characterized by an on-resistance that is 50% or less than the on-resistance of the first switch transistor.

[0030] In some embodiments, a given slew control circuit is a PMOS slew control circuit, the first and second switch transistors are PMOS transistors, and the PMOS slew control circuit further includes an OR circuit having a first input node for receiving a switching input signal, a second input node for receiving a current sense signal, and an output node. The PMOS slew control circuit also includes a p-channel MOS transistor having a drain node coupled to the output node of the OR circuit via a resistor, and a high pass filter coupled between the output node of the output transistor and a gate node of the p-channel MOS transistor. The drain of the p-channel MOS transistor provides the dynamically modulated switching input signal. The PMOS slew control circuit also includes a multiplexer configured to select one of the input switching signal and the dynamically modulated switching input signal in response to a current direction signal.

[0031] In some embodiments, the first pull-up transistor is a PMOS transistor and the first slew control circuit is a PMOS slew control circuit.

[0032] In some embodiments, the second pull-up transistor is a PMOS transistor and the second slew control circuit is a PMOS slew control circuit.

[0033] In some embodiments, the given slew control circuit is an NMOS slew control circuit, the first and second switch transistors are NMOS transistors, and the NMOS slew control circuit further includes an AND circuit having a first input node for receiving a switching input signal, a second input node for receiving a current sense signal, and an output node. The NMOS slew control circuit further includes an n-channel MOS transistor having a drain node coupled to the output node of the AND circuit via a resistor, and a high pass filter coupled between the output node of the output transistor and a gate node of the n-channel MOS transistor. The drain of the n-channel MOS transistor provides the dynamically modulated switching input signal. The NMOS slew control circuit also includes a multiplexer configured to select one of the input switching signal and the dynamically modulated switching input signal in response to a current direction signal.

[0034] In some embodiments, the first pull-down transistor is an NMOS transistor and the third slew control circuit is an NMOS slew control circuit.

[0035] In some embodiments, the second pull-down transistor is an NMOS transistor and the fourth slew control circuit is an NMOS slew control circuit.

[0036] According to some embodiments of the present invention, an output driver with slew rate control includes an output transistor including a control terminal coupled to a switching input signal, a drain node coupled to an output node for coupling to a load device, and a source node coupled to a reference voltage. The output driver also has a slew control circuit including a current source coupled in series at a connection node with a first switch transistor and a second switch transistor connected in parallel. The connection node is coupled to the control terminal of the output transistor. The first switch transistor has a control terminal coupled to the switching input signal. The second switch transistor has a control terminal coupled to either the switching input signal or the dynamically modulated switching input signal depending on the current direction at the output node.

[0037] According to some embodiments of the present invention, a method for operating an output driver includes controlling an output transistor with a switching input signal at a control terminal of the output transistor and regulating a turn-off current of the output transistor using a slew control circuit. The slew control circuit includes a current source coupled in series at a connection node with a first switch transistor and a second switch transistor connected in parallel. The connection node is coupled to the control terminal of the output transistor. Regulating the turn-off current includes turning on the first switch transistor using the switching input signal and turning on the second switch transistor using either the switching input signal or a dynamically modulated switching input signal depending on a current direction at an output node of the output transistor.

[0038]

[0038] In some embodiments, the above method also includes forming a dynamically modulated switching input by modifying the switching input signal using a pulse signal determined by a high-pass filter coupled to the output node.

[0039] In some embodiments, the method also includes configuring the second switch transistor with an on-resistance that is 25% or less of the on-resistance of the first switch transistor.

[0040] In some embodiments, the method also includes generating a dynamically modulated switching input by using a delay cell to add a delay according to the sensed output signal. [Brief description of the drawings]

[0041] [Figure 1] FIG. 1 is a simplified circuit diagram illustrating a conventional switching amplifier. [Diagram 2] 2 is a waveform diagram showing modulation of a signal in the switching amplifier of FIG. 1. [Diagram 3] 2 is a simplified waveform diagram illustrating problems associated with conventional switching amplifiers in accordance with some embodiments of the present invention. [Figure 4] FIG. 2 is a simplified circuit diagram illustrating a switching driver circuit with dynamic slew rate control in accordance with some embodiments of the present invention. [Diagram 5] 1 is a simplified circuit diagram illustrating a switching amplifier circuit having a slew control circuit according to some embodiments of the present invention. [Figure 6] 1 is a simplified circuit diagram illustrating a switching amplifier circuit having a slew control circuit according to some embodiments of the present invention. [Figure 7] FIG. 2 is a simplified circuit diagram of a current direction detection circuit according to some embodiments of the present invention. [Figure 8] 4A-4C are waveform diagrams illustrating simulated waveforms of a switching amplifier circuit without dynamic slew rate control in accordance with some embodiments of the present invention. [Figure 9] 4A-4C are waveform diagrams illustrating simulated waveforms of a switching amplifier circuit with dynamic slew rate control in accordance with some embodiments of the present invention. [Figure 10]4 is a simplified flow chart illustrating a method for operating an output driver according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042]

[0051] FIG. 3 is a simplified waveform diagram illustrating some problems associated with conventional switching amplifiers, in accordance with some embodiments of the present invention. The transitions of the output signals at nodes OUTP and OUTN of the switching amplifier 100 of FIG. 1 are shown in FIG. 3 for both positive and negative conduction periods of an input signal, e.g., an audio signal. In the following description, reference is made to the circuit diagram of FIG. 1. The first half-bridge 111 has a high-side transistor M1 and a low-side transistor M2, and the second half-bridge 112 has a high-side transistor M3 and a low-side transistor M4. In the following description, the transistors M1 and M2 are also referred to as the high-side transistor and the low-side transistor, respectively, associated with the node OUTP. Similarly, the transistors M3 and M4 are also referred to as the high-side transistor and the low-side transistor, respectively, associated with the node OUTN.

[0043]

[0052] In this embodiment, when the input audio signal amplitude increases, the load current will flow from OUTP to OUTN for half a period, then reverse direction from OUTN to OUTP for the remaining half period. The PWM generation is done so that the current is flowing from OUTP to OUTN, and when OUTP goes from low to high (PMOS on), the slewing of OUTP is controlled. However, when OUTN goes from low to high (NMOS off), there is no control, thus resulting in overshoot as mentioned above in the figure. This leads to EMI deterioration and device breakdown problems.

[0044]

[0053] In Fig. 3, during the positive half-cycle of the sinusoidal input signal, the output current flows from the output node OUTP to the output node OUTN. Initially, the high-side PMOS transistor M1 of the first half-bridge is on and the low-side NMOS transistor M4 of the second half-bridge is on. The regions of interest are marked as A1, A2, ..., A11.

[0045]

[0054] In region A1, the high-side PMOS transistor is turned off and only the body diode of the low-side NMOS transistor M2 of the first half-bridge conducts current.

[0046]

[0055] In region A2, the low-side NMOS transistor of OUTPM2 is turned on, and the current direction is maintained.

[0047]

[0056] In region A3, the low-side NMOS transistor M2 of OUTP is turned off and the body diode of the high-side PMOS transistor M1 of OUTP conducts current, causing an overshoot. However, this part is controlled by the current source. In region A4, the high-side PMOS transistor M1 of OUTP is turned on.

[0048]

[0057] In region A5, the low-side NMOS transistor M4 of the second half-bridge is turned off and the body diode of the high-side PMOS M3 of the second half-bridge is conducting. This turn-off operation of the low-side NMOS M4 of the second half-bridge is not controlled and the magnitude of the overshoot peak can be as high as 3V above the supply voltage. This overshoot also causes ringing after the peak. The higher peak can cause worse EMI problems and the ringing causes worse THD.

[0049]

[0058] In region A6, after peaking and ringing, the high-side PMOS transistor of the second half-bridge is turned on and the voltage level settles down to the power supply voltage Vdd.

[0050]

[0059] In region A7, the high-side PMOS transistor of the second half-bridge is off, causing a small peak due to conduction through the body diode of the second half-bridge PMOS.

[0051]

[0060] In the region A8, the high-side PMOS transistor M1 on the OUTP side is on, and the low-side NMOS transistor M4 on the OUTN side is on.

[0052]

[0061] In region A9, the switching signal transitions negative. The high-side PMOS transistor M1 on the OUTP side is off and the body diode of the low-side NMOS transistor M2 on the OUTP side conducts to maintain the current direction. This region is not under control. The peak of the undershoot can be as high as 2V and also causes ringing. Similar to region A5, the high peak undershoot voltage causes EMI and the ringing worsens THD.

[0053]

[0062] In region A10, OUTP's low-side NMOS transistor M2 turns on and after a small negative peak, the signal settles to the same ground voltage as in region A2, and the process repeats from region A1 to A8 for all positive input swings.

[0054]

[0063] As mentioned above in regions A1-A8 above during the positive half-cycle of the input, region 5 causes overshoot at the output node OUTN when the low-side transistor M4 on the OUTN side is off, and the voltage at OUTN swings above VDD in an uncontrolled manner due to the inductor current. Similarly, during regions 1 and 9, when the high-side transistor M1 on the OUTP side is off, the voltage at the output node OUTP drops, causing an undershoot due to the inductor current to fall below GND in an uncontrolled manner. In regions A1 and A5, similar to A9, large voltage swings and ringing cause EMI and THD problems.

[0055]

[0064] Referring to the negative conduction period of Figure 3, the input signal goes negative and the current direction reverses from node OUTN to node OUTP. Eight regions B1-B8 are marked in Figure 3 and are described below.

[0056]

[0065] In region B1, the low-side NMOS transistor M2 of OUTP is on, and the low-side NMOS transistor M4 of OUTN is off.

[0057]

[0066] In region B2, the low-side NMOS transistor M2 of OUTP is on, and the high-side PMOS transistor M3 of OUNT is also on.

[0058]

[0067] In region B3, the low-side NMOS transistor M2 of OUTP is off and the body diode of the high-side PMOS transistor M1 of OUTN conducts current, causing a large upward swing and subsequent ringing, which is an uncontrolled signal edge that creates EMI and THD problems.

[0059]

[0068] In region B4, the high-side PMOS transistor M1 of OUTN is turned on and the voltage on node OUTN settles to VDD.

[0060]

[0069] In region B5, the high-side PMOS transistor M1 of OUTP is turned off.

[0061]

[0070] In region B6, the low-side NMOS transistor M2 of OUTP is turned on and the high-side PMOS transistor M3 of OUTN is also on. Current still flows from node OUTN to node OUTP.

[0062]

[0071] In region B7, OUTN's high-side PMOS transistor M3 is turned off and conducts through the body diode of OUTN's low-side NMOS transistor M4. This is an uncontrolled signal edge, creating EMI and THD problems.

[0063]

[0072] In region B8, the low-side NMOS transistor M4 of OUTN turns on and the voltage on node OUTN settles to ground.

[0064]

[0073] As described above, in region B3, large overshoot and ringing on the OUTP side cause EMI and THD problems, and in region B7, large undershoot and ringing on the OUTN side cause EMI and THD problems.

[0065]

[0074] As discussed above with reference to Figure 3, the inventors have identified certain signal transition edges that cause EMI and THD problems, while other signal transition edges do not cause these problems. Thus, in embodiments of the present invention, slew rate control to slow down circuit speed is not applied to all signal transition edges.

[0066]

[0075] In some embodiments, slew rate control is applied to node OUTN during turn-off when the current direction is from node OUTP to node OUTN. Under this condition, the low-side NMOS transistor pull-down transistor is turned off and current flows through the body diode of the NMOS transistor. Similarly, during the negative half-cycle of the input signal, the current direction is from node OUTN to node OUTP. When slew rate control is applied to node OUTP turn-off and the low-side NMOS transistor M2 of OUTP is turned off, current flows through the body diode of the high-side PMOS transistor M1 of OUTP. In other words, in the negative half-cycle, slew control is applied to node OUTP during turn-off when the current direction is from node OUTN to node OUTP.

[0067]

[0076] The above two scenarios refer to using slew rate control to improve overshoot and ringing problems, as shown in regions A5 and B3 of FIG. 3. Similarly, EMI and THD problems may also occur during undershoot and ringing of the signal. For example, in region A1, similar to A9 showing undershoot, slew rate control is applied to the high-side PMOS transistor M1 of OUTP with the current direction from node OUTP to node OUTN. In this region, the high-side PMOS transistor M1 of OUTP is turned off and the current flows out of the PMOS transistor. In region B7, the current direction is from node OUTN to node OUTP. Now, during the turn-off of the high-side PMOS transistor M3 of OUTN, slew rate control is applied to node OUTN and the current flows out of the PMOS transistor.

[0068]

[0077] As discussed above, the inventors have identified certain signal transition edges that may lead to excessive overshoot or undershoot and signal ringing that may damage devices or degrade device performance. However, certain other signal transition edges do not produce such excessive overshoot or undershoot. Thus, embodiments of the present invention teach selectively or dynamically applying slew rate control only at critical signal transition edges, rather than at all signal transition edges. In contrast, applying slew rate control at all transition edges, as described in some prior art examples, would unnecessarily slow down the circuit speed and degrade circuit performance.

[0069]

[0078] FIG. 4 is a simplified circuit diagram illustrating a switching amplifier circuit with dynamic slew rate control according to some embodiments of the present invention. As shown in FIG. 4, the switching amplifier circuit 400 includes a first push-pull output stage 411, also referred to as a first half-bridge, which includes a first pull-up transistor UP1 and a first pull-down transistor DN1 connected in series at a first output node OUTP between first and second reference voltages Vdd and Vss, which in some embodiments may be provided by power and ground terminals. The first pull-up and pull-down transistors have control terminals 411-1 and 411-2 that receive a first differential switching control signal 431 from a switched modulator 440, which includes two comparators 441 and 442 and an oscillator 443. The first output node OUTP provides a first differential output signal 410-1 to a first end 401-1 of a load device 401. In the example of FIG. 4, the load device 401 is an audio speaker represented by an inductor L1 and a resistor R1. In this example, switched modulator 440 is similar to the PWM signal generator described above in connection with FIGS.

[0070]

[0079] The switching amplifier circuit 400 also includes a second push-pull output stage 412, also referred to as a second half-bridge, comprising a second pull-up transistor UP2 and a second pull-down transistor DN2 having conductive paths connected in series between first and second reference voltages Vdd and Vss and defining a second output node OUTN at the junction between the conductive paths, each of the second pull-up and pull-down transistors having control terminals receiving a second differential switching control signal 432 from the switched modulator 440, and the second output node OUTN provides a second differential output signal 410-2 to a second end 401-2 of the load device 401.

[0071]

[0080] The switching amplifier circuit 400 also includes a current direction detection circuit 430 coupled to a PWM control 431 for OUTP and a PWM control 432 for OUTN to determine the direction of the output current IL and provide a current direction signal IL-Dir to indicate whether the output current flows from the first output node OUTP to the second output node OUTN or the output current flows from the second output node OUTN to the first output node OUTP. In some embodiments, the current direction signal IL-Dir is positive when the output current flows from the first output node OUTP to the second output node OUTN and the current direction signal IL-Dir is negative when the output current flows from the second output node OUTN to the first output node OUTP.

[0072]

[0081] The switching amplifier circuit 400 also includes first, second, third, and fourth slew control circuits 421, 422, 423, and 424 coupled to control terminals of the first pullup transistor UP1, the first pulldown transistor DN1, the second pullup transistor UP2, and the second pulldown transistor DN2, respectively, responsive to the current direction signal IL-Dir. The slew control circuits are configured to reduce the slew rate at the output nodes at critical conditions, which will be described below. The first slew control circuit 421 is activated only during the turn-off of the first pullup transistor UP1 when the output current flows from the first output node OUTP to the second output node OUTN. The second slew control circuit 422 is activated only during the turn-off of the first pulldown transistor DN1 when the output current flows from the second output node OUTN to the first output node OUTP. The third slew control circuit 423 is activated only during the turn-off of the second pull-up transistor UP2 when the output current flows from the second output node OUTN to the first output node OUTP. The fourth slew control circuit 424 is activated only during the turn-off of the second pull-down transistor DN2 when the output current flows from the first output node OUTP to the second output node OUTN.

[0073]

[0082] Examples of slew control circuits are described below in conjunction with Figures 5 and 6. Figure 5 illustrates an NMOS slew control circuit and Figure 6 illustrates a PMOS slew control circuit. In the switching amplifier circuit 400 of Figure 4, the first pullup transistor UP1 is a PMOS transistor and the first slew control circuit 421 is a PMOS slew control circuit. The second pullup transistor UP2 is a PMOS transistor and the third slew control circuit 423 is a PMOS slew control circuit. The first pulldown transistor DN1 is an NMOS transistor and the second slew control circuit 422 is an NMOS slew control circuit. The second pulldown transistor DN2 is an NMOS transistor and the fourth slew control circuit 424 is an NMOS slew control circuit.

[0074]

[0083] In summary, to dynamically control the turn-off of the output transistors, the high-pass filter converts the rate at which the output voltage rises into a transient spike, which is combined with the signal from the switched input signal, so that the turn-off of the output transistors is dynamically performed. As a result, the EMI and overshoot issues are greatly improved. In addition, in filterless switching PWM applications, this design also reduces the device's insulation breakdown. Furthermore, the pull-down or pull-up current is split into two parts, one weak and the other strong, and these two parts dynamically control the slew rate based on the current direction.

[0075]

[0084] FIG. 5 is a simplified circuit diagram illustrating a switching amplifier circuit having a slew control circuit, according to some embodiments of the present invention. FIG. 5 illustrates a portion of a switching amplifier circuit 500, which may be an example of switching amplifier circuit 400 of FIG. 4. As shown in FIG. 5, switching amplifier circuit 500 includes differential output nodes OUTP and OUTN on either side of a load device 501. Similar to switching amplifier circuit 400 of FIG. 4, switching amplifier circuit 500 has an H-bridge configuration with high-side pullup transistor UP1 and pulldown transistor DN1, and low-side pullup transistor UP2 and pulldown transistor DN2. As shown in FIG. 5, pulldown transistor DN2 is an NMOS output transistor.

[0076]

[0085] As shown in Figure 5, pull-down transistor DN2 is an output transistor that includes a control terminal 501 coupled to a switching input signal LG-N, which is a switched control signal that may be derived from a PWM modulator similar to switched control signal 432 of Figure 4. Transistor DN2 also has a drain node coupled to an output node OUTN for coupling to a load device, and a source node coupled to a reference voltage Vss, provided in this example by a ground node. Switching driver circuit 500 also includes a current direction detection circuit 530 similar to current direction detection circuit 430 of Figure 4. Current direction detection circuit 530 is coupled to an output node OUTP, which provides a current direction signal IL-Dir that indicates the direction of current in load device 501 between output nodes OUTP and OUTN.

[0077]

[0086] The switching driver circuit also includes a slew control circuit 510 including a current source 511 coupled in series at a connection node with a first switch transistor 512-1 and a second switch transistor 512-2 connected in parallel, the connection node 512-3 being coupled to a control terminal 503 of the transistor DN2. The first switch transistor 512-1 has a control terminal coupled to a switching input signal LG-N. The second switch transistor 512-2 has a control terminal coupled to either the switching input signal LG-N or a dynamically modulated switching input signal 519 depending on the current direction at the output node OUTN. As shown in FIG. 5, the current direction is provided by a current direction signal IL-Dir provided by a current direction detection circuit 530.

[0078]

[0087] In the example of FIG. 5, the output transistor DN2 is an NMOS transistor, and the slew control circuit 510 further includes an AND circuit 513 having a first input node 513-1 for receiving the switching input signal LG-N, a second input node 513-2 for receiving the current detection signal IL-Dir, and an output node 513-3. The slew control circuit 510 further includes an n-channel MOS transistor 514 having a drain node 514-1 coupled to the output node of the AND circuit 513 via a resistor 516, and a high-pass filter 517 coupled between the output node OUTN of the output transistor DN2 and a gate node 514-2 of the n-channel MOS transistor. The drain node 514-1 of the n-channel MOS transistor 514 provides a dynamically modulated switching signal 519. The multiplexer circuit 518 is configured to select one of the switching input signal LG-N and the dynamically modulated switching input signal 519 in response to the current direction signal IL-DIR. In this configuration, the second switch transistor 512-2 receives either the switching input signal LG-N or the dynamically modulated switching input signal 519, depending on the current direction at the output node OUTN.

[0079]

[0088] 5 also shows the associated waveforms. High-pass filter 517 is comprised of capacitor C and resistor R and generates pulse signal 514-P at node 514-2 of transistor 514. Switching input signal LG-N is shown as pulse signal 504-P. Dynamically modulated switching input signal 519 is shown by waveform 519-P. It can be seen that dynamically modulated switching input signal 519-P includes switching input signal 504-P and a negative pulse signal 514-P determined by a high-pass filter coupled to output node OUTN. Negative pulse signal 514-P is generated by high-pass filter 517 during the turn-off of transistor DN2. When the current direction signal IL-Dir indicates that the load current IL is flowing into the output node OUTN, the gate node of the second switch transistor 512-2 receives the dynamically modulated switching input signal 519-P, which slows down the turn-off of transistor DN2 and provides slew rate control to reduce electromagnetic interference (EMI) and total harmonic distortion (THD). During other times, both of the first switch transistors 512-1 and 512-2 receive the switching input signal LG-N at its full strength, allowing transistor DN2 to turn off efficiently without losing speed.

[0080]

[0089] In some embodiments, resistor 516 in slew control circuit 510 provides a high impedance, for example 20KΩ, so that the direct output 513-3 of AND gate 513 maintains the same voltage as the switched signal LG-N while allowing node 514-1 to be pulled down by high pass filter 17. In high pass filter 517, the RC time constant is set to about 5 nsec in some embodiments, similar to the slew time of the signal at node OUTN.

[0081]

[0090] In some embodiments, the second switch transistor 512-2 is configured to provide more current drive capability than the first switch transistor 512-1. For example, the second switch transistor 512-2 may have the same channel length as the first switch transistor 512-1 but twice its width, in which case the second switch transistor 512-2 is characterized by an on-resistance that is 50% or less than the on-resistance of the first switch transistor 512-1. In other embodiments, the second switch transistor 512-2 is characterized by an on-resistance that is 25% or less than the on-resistance of the first switch transistor 512-1. In yet other embodiments, the second switch transistor 512-2 is characterized by an on-resistance that is 25% or less than the on-resistance of the first switch transistor 512-1.

[0082]

[0091] FIG. 6 is a simplified circuit diagram illustrating a switching amplifier circuit having a slew control circuit according to some embodiments of the present invention. FIG. 6 illustrates a portion of a switching driver circuit 600 similar to the switching amplifier circuit 500 of FIG. 5 but with a slew control circuit for a PMOS output transistor. In contrast, the switching amplifier circuit 500 of FIG. 5 has a slew control circuit for an NMOS output transistor. As will be explained in more detail below, the slew control circuit 610 of FIG. 6 is similar to the slew control circuit 510 of FIG. 5, with the circuit details reflecting the differences between PMOS and NMOS. For example, the NMOS transistors in the slew control circuit 510 are replaced with PMOS transistors in the slew control circuit 610. Similarly, the AND gate circuits are replaced with OR gate circuits, the power terminals are replaced with ground terminals, etc. For completeness, a detailed description is presented below.

[0083]

[0092] As shown in Figure 6, switching driver circuit 600 has differential output nodes OUTP and OUTN on either side of a load device 601. Similar to switching amplifier circuit 400 of Figure 4, switching driver circuit 600 has an H-bridge configuration with high-side pullup transistor UP1 and pull-down transistor DN1, and low-side pullup transistor UP2 and pull-down transistor DN2. As shown in Figure 6, pullup transistor DP2 is a PMOS output transistor.

[0084]

[0093] As shown in Figure 6, pull-up transistor DP2 is an output transistor that includes a control terminal coupled to a switching input signal LG-N, which is a switched control signal that may be derived from a PWM modulator, similar to switched control signal 432 of Figure 4. Transistor DP2 also has a drain node coupled to an output node OUTN for coupling to a load device, and a source node coupled to a reference voltage Vss, provided in this example by a ground node. Switching driver circuit 600 also includes a current direction detection circuit 630, similar to current direction detection circuit 430 of Figure 4. Current direction detection circuit 630 is coupled to output node OUTP, which provides a current direction signal IL-Dir that indicates the direction of current in load device 601 between output nodes OUTP and OUTN.

[0085]

[0094] The switching driver circuit also includes a slew control circuit 610 including a current source 611 coupled in series at a connection node with a first switch transistor 612-1 and a second switch transistor 612-2 connected in parallel, the connection node 612-3 being coupled to a control terminal 603 of the transistor DP2. The first switch transistor 612-1 has a control terminal coupled to a switching input signal LG-N. The second switch transistor 612-2 has a control terminal coupled to either the switching input signal LG-N or a dynamically modulated switching input signal 619 depending on the current direction at the output node OUTN. As shown in FIG. 6, the current direction is provided by a current direction signal IL-Dir provided by a current direction detection circuit 630.

[0086]

[0095] In the example of Fig. 6, the output transistor DP2 is a PMOS transistor, and the slew control circuit 610 further comprises an OR circuit 613 having a first input node 613-1 for receiving the switching input signal LG-N, a second input node 613-2 for receiving the current detection signal IL-Dir, and an output node 613-3. The slew control circuit 610 further comprises a p-channel MOS transistor 614 having a drain node 614-1 connected to the output node of the AND circuit 613 via a resistor 616, and a high-pass filter 617 coupled between the output node OUTN of the output transistor DN2 and a gate node 614-2 of the n-channel MOS transistor. The drain node 614-1 of the p-channel MOS transistor 614 provides a dynamically modulated switching signal 619. The multiplexer circuit 618 is configured to select one of the switching input signal LG-N and the dynamically modulated switching input signal 619 in response to the current direction signal IL-DIR. In this configuration, the second switch transistor 612-2 receives either the switching input signal LG-N or the dynamically modulated switching input signal 619, depending on the current direction at the output node OUTN.

[0087]

[0096] 6 also shows the relevant waveforms. The high-pass filter 617 is composed of a capacitor C and a resistor R and generates a pulse signal 614-P at node 614-2 of the transistor 614. The switching input signal LG-N is shown as a pulse signal 604-P. The dynamically modulated switching input signal 619 is shown by waveform 619-P. It can be seen that the dynamically modulated switching input signal 619-P includes the switching input signal 604-P and a transient positive pulse superimposed on the switching input signal 604-P, caused by the generation of a negative pulse 614-P on the gate of the PMOS transistor 614, the width of which is determined by a high-pass filter coupled to the output node OUTN. The negative pulse signal 614-P is generated by the high-pass filter 617 during the turn-off of the transistor DP2. When the current direction signal IL-Dir indicates that the load current IL is flowing into the output node OUTN, the gate node of the second switch transistor 612-2 receives the dynamically modulated switching input signal 619-P, which slows down the turn-off of the transistor DP2 and provides slew rate control to reduce electromagnetic interference (EMI) and total harmonic distortion (THD). During other times, both the first switch transistor 612-1 and the second switch transistor 612-2 receive the switching input signal LG-N at its full strength, allowing the transistor DN2 to turn off efficiently without losing speed.

[0088]

[0097] In some embodiments, the second switch transistor 612-2 is configured to provide more current drive capability than the first switch transistor 612-1. For example, the second switch transistor 612-2 may have the same channel length as the first switch transistor 612-1 but twice its width, in which case the second switch transistor 612-2 is characterized by an on-resistance that is 50% or less than the on-resistance of the first switch transistor 612-1. In other embodiments, the second switch transistor 612-2 is characterized by an on-resistance that is 25% or less than the on-resistance of the first switch transistor 612-1. In yet other embodiments, the second switch transistor 612-2 is characterized by an on-resistance that is 25% or less than the on-resistance of the first switch transistor 612-1.

[0089]

[0098] As mentioned above, slew control circuit 510 of Figure 5 is an example of NMOS slew control circuit 424 in switching amplifier circuit 400 of Figure 4, and slew control circuit 610 of Figure 6 is an example of PMOS slew control circuit 423 in switching amplifier circuit 400 of Figure 4. Similarly, slew control circuit 510 of Figure 5 is an example of NMOS slew control circuit 422 in switching amplifier circuit 400 of Figure 4, and slew control circuit 610 of Figure 6 is an example of PMOS slew control circuit 421 in switching amplifier circuit 400 of Figure 4.

[0090]

[0099] FIG. 7 is a simplified circuit diagram of a current direction detection circuit according to some embodiments of the present invention. Current direction detection circuit 700 is an example of current direction detection circuit 430 in FIG. 4, current direction detection circuit 530 in FIG. 5, and current direction detection circuit 630 in FIG. 6. As shown in FIG. 7, current direction detection circuit 700 receives gate pre-drive signals PWMN and PWMP as inputs. Alternatively, in some embodiments, current direction detection circuit 700 receives signals at output nodes OUTN and OUTP to determine the current direction. Current direction detection circuit 700 includes inverters 711, 712, 715, and 716 coupled to NAND circuits 713 and 714 that generate intermediate signals 717 and 718. Intermediate signals 717 and 718 are coupled to D flip-flop 720, which is also coupled to VDD, providing outputs Q and Q-bar. Current direction detection circuit 700 inputs the OUTP and OUTN gate predrive signals, determines which is leading and which is lagging, and then generates a flip-flop output Q indicating the current direction based on which OUTP or OUTN signal comes first. As discussed above in connection with FIG. 3, during the positive half-cycle, the signal at node OUTP comes first and during the negative half-cycle, the signal at node OUTN comes first.

[0091]

[0100] 8 is a waveform diagram showing simulated waveforms of a switching amplifier circuit without dynamic slew rate control according to some embodiments of the present invention. The horizontal axis shows time and the vertical axis shows the waveform of the signal. In FIG. 8, curve 810 is the signal at node OUTP. Curves 821 and 822 are the gate voltages of the high-side PMOS and NMOS transistors, respectively, that drive node OUTP. Curves 831 and 832 are the gate voltages of the low-side PMOS and NMOS transistors, respectively, that drive node OUTP. Curve 840 shows the signal at node OUTN. On curve 810, region 811 shows the edges of the uncontrolled signal with a peak at about 6.5V and additional ringing that may cause device damage as well as EMI and THD.

[0092]

[0101] FIG. 9 is a waveform diagram showing simulated waveforms of a switching amplifier circuit with dynamic slew rate control according to some embodiments of the present invention. In FIG. 9, the horizontal axis shows time and the vertical axis shows the waveform of the signal. In FIG. 9, curve 910 is the signal at node OUTP. Curves 921 and 922 are the gate voltages of the high-side PMOS transistor and the low-side NMOS transistor, respectively, that drive node OUTP. Curve 931 is the pre-gate drive signal to the low-side NMOS transistor provided by the slew control circuit, as described above in connection with FIG. 4. Curve 932 is the gate voltage of the low-side NMOS transistor that drives node OUTP. Curves 941 and 942 show the drain current waveforms. It can be seen on curve 910 that region 911 shows the controlled edge of the signal. The overshoot is reduced to approximately a diode voltage above the supply, shown at the marker as 5.96V for a 5.5V supply. In this case, device damage as well as EMI and THD problems are avoided.

[0093]

[0102] 10 is a simplified flowchart illustrating a method for operating an output driver according to some embodiments of the present invention. The flowchart of FIG. 10 outlines a method 1000 for operating an output driver. An example of an output driver is described above with reference to FIGS. 1-9. For example, the switching driver circuit 400 is an example of a differential output driver with dynamic slew rate control. The above-described method can also be described using a single-ended example with reference to FIG. 10 as follows.

[0094]

[0103] At 1010, the method includes controlling an output transistor with a switching input signal at a control terminal of the output transistor. As an example, in Figure 4, the output transistor DN2 is controlled by a switching input signal 432 at a control terminal of the output transistor DN2. In Figure 4, the output transistor DN2 is controlled by a switching input signal LG-N.

[0095]

[0104] At 1020, the method includes adjusting the turn-off current of the output transistor using a slew control circuit including a current source coupled in series at a connection node of a first switch transistor 512-1 and a second switch transistor 512-2 connected in parallel, the connection node being coupled to a control terminal of the output transistor. An example is described above in connection with FIG. 5. The slew control circuit 510 includes a current source 511 coupled in series at a connection node 512-3 with a first switch transistor 512-1 and a second switch transistor 512-2 connected in parallel. The connection node 512-3 is coupled to a control terminal of the output transistor DN2.

[0096]

[0105] At 1030, the method includes turning on the first switch transistor 512-1 using the switching input signal LG-N.

[0097]

[0106] At 1040, the method includes turning on a second switch transistor 512-2 using either a switching input signal LG-N or a dynamically modulated switching input signal 519 depending on the current direction at an output node OUTN of the output transistor DN2.

[0098]

[0107] In some embodiments, the method also includes forming a dynamically modulated switching input by modifying the switching input signal using a negative pulse signal determined by a high pass filter coupled to the output node. One example of a dynamically modulated switching input is shown and described in connection with FIG. 5, where the dynamically modulated switching input 519 is formed by modifying the switching input signal LG_N using a negative pulse signal 514-2 determined by a high pass filter 517 coupled to the output node OUTN. The negative pulse signal is generated using a high pass filter coupled to the output node.

[0099]

[0108] In some embodiments, the method includes configuring the second switch transistor 512-2 with an on-resistance that is 25% or less than the on-resistance of the first switch transistor 512-1. In some embodiments, the method includes configuring the second switch transistor 512-2 with an on-resistance that is 50% or less than the on-resistance of the first switch transistor 512-1.

[0100]

[0109] Features of some embodiments are described above to highlight some aspects of the present disclosure. It is understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes in light thereof will be suggested to those skilled in the art and should be included within the spirit and scope of the present disclosure. [Explanation of symbols]

[0101] 100 Switching Amplifier 101 Comparator 102 Comparator 103 Oscillator 106 PWM signals 107 PWM signal 110 Speaker Load 111 First Half Bridge 112 Second Half Bridge 400 Switching amplifier circuits, switching driver circuits 401 Load Device 401-1 First end 401-2 Second end 410-1 First differential output signal 410-2 Second differential output signal 411 1st push-pull output stage 411-1 Control terminal 411-2 Control terminal 412 Second push-pull output stage 421 First through control circuit, PMOS through control circuit 422 Second through control circuit, NMOS through control circuit 423 Third through control circuit, PMOS through control circuit 424 Fourth through control circuit, NMOS through control circuit 430 Switched Modulator, Current Direction Detection Circuit 431 First differential switching control signal, PWMP control 432 Second differential switching control signal, PWM control 432 Switching Input Signal 440 Switched Modulator 441 Comparator 442 Comparator 443 Oscillator 500 Switching amplifier circuits, switching driver circuits 501 Load device, control terminal 503 Control terminal 504-P Pulse signal, switching input signal 510 Through control circuit 511 Current source 512-1 First switch transistor 512-2 Second switch transistor 512-3 Connection Node 513 AND gate, AND circuit 513-1 First input node 513-2 Second input node 513-3 Output Node 514 n-channel MOS transistor 514-1 Drain Node 514-2 Gate node, negative pulse signal 514-P Negative pulse signal 516 resistor 517 High Pass Filter 518 Multiplexer Circuit 519 Switching Input Signal 519-P Switching input signal, waveform 530 Current direction detection circuit 600 Switching driver circuit 601 Load Device 603 Control terminal 604-P Pulse signal, switching input signal 610 Through control circuit 611 Current source 612-1 First switch transistor 612-2 Second switch transistor 612-3 Connection Node 613 OR circuit, AND circuit 613-1 First input node 613-2 Second input node 613-3 Output node 614 p-channel MOS transistor 614-1 Drain node 614-2 Gate Node 614-P Negative pulse signal 616 resistor 617 High Pass Filter 618 Multiplexer Circuit 619 Switching Input Signal 619-P Switching input signal, waveform 630 Current Direction Detection Circuit 700 Current direction detection circuit 711 Inverter 712 Inverter 713 NAND Circuit 715 Inverter 716 Inverter 717 Intermediate Signal 718 Intermediate Signal 720 D Flip Flop 810 curve 811 area 821 Curve 822 curve 831 Curve 832 curve 840 curve 910 curve 911 area 921 curve 922 curve 931 curve 932 curve 941 Curve 942 curve A1 area A2 area A3 area A4 area A5 area A6 area A7 area A8 area A9 area A10 area B1 area B2 area B3 area B4 area B5 area B6 area B7 area B8 area C Capacitor DN1 First pull-down transistor DN2 Second pull-down transistor, output transistor IL Output current IL load current IL-DIR Current direction signal IL-Dir Current direction signal, current detection signal INM Differential input audio signal INP Differential input audio signal L1 Inductor LG-N Switching input signal M1 High-side PMOS transistor of the first half-bridge M2 Low-side NMOS transistor of the first half-bridge M3 High-side PMOS transistor of the second half-bridge M4 Low-side NMOS transistor of the second half-bridge OUTN Differential output node, second output node, output terminal OUTP Differential output node, first output node, output terminal Q Flip-Flop Output R resistor R1 resistor UP1 First pull-up transistor, high-side pull-up transistor UP2 Second pullup transistor, low-side pullup transistor VREF triangle wave Vdd First reference voltage, power supply voltage Vss Second reference voltage

Claims

1. a first output stage comprising a first pull-up transistor and a first pull-down transistor connected in series at a first output node between first and second reference voltages, the first pull-up and pull-down transistors each having a control terminal and receiving a first differential switching control signal from a switched modulator, the first output node providing a first differential output signal to a first end of a load device; a second output stage comprising a second pull-up transistor and a second pull-down transistor connected in series at a second output node between the first and second reference voltages, the second pull-up and pull-down transistors each having a control terminal receiving a second differential switching control signal from the switched modulator, the second output node providing a second differential output signal to a second end of the load device; a current direction detection circuit coupled to the first output of the switched modulator and the second output of the switched modulator for determining a direction of an output current and providing a current direction signal indicative of whether the output current flows from the first output node to the second output node or the output current flows from the second output node to the first output node; first, second, third, and fourth slew control circuits responsive to the current direction signal and coupled to the first pull-up transistor, the first pull-down transistor, the second pull-up transistor, and the second pull-down transistor, respectively; Equipped with the first slew control circuit is activated only during a turn-off of the first pull-up transistor when the output current flows from the first output node to the second output node; the second slew control circuit is activated only during a turn-off of the first pull-down transistor when the output current flows from the second output node to the first output node; the third slew control circuit is activated only during a turn-off of the second pull-up transistor when the output current flows from the second output node to the first output node; the fourth slew control circuit is activated only during a turn-off of the second pull-down transistor when the output current flows from the first output node to the second output node; Switching amplifier circuit.

2. a given slew control circuit is coupled to the control terminal of the output transistor, the slew control circuit including a current source coupled in series with a first switch transistor and a second switch transistor connected in parallel; the first switch transistor having a control terminal coupled to a switching input signal; the second switch transistor having a control terminal coupled to either the switching input signal or a dynamically modulated switching signal that reduces slew rate depending on a current direction at an output node.

2. The switching amplifier circuit of claim 1.

3. 3. The switching amplifier circuit of claim 2, wherein a dynamically modulated switching input signal comprises the switching input signal and a first pulse signal determined by a high pass filter coupled to the output node.

4. 4. The switching amplifier circuit of claim 3, wherein the second switch transistor is characterized by an on-resistance that is 25% or less of the on-resistance of the first switch transistor.

5. 4. The switching amplifier circuit of claim 3, wherein the second switch transistor is characterized by an on-resistance that is 50% or less than the on-resistance of the first switch transistor.

6. the given slew control circuit is a PMOS slew control circuit, the first and second switch transistors are PMOS transistors, and the PMOS slew control circuit a first input node for receiving said switching input signal; a second input node for receiving the current sense signal; and having an output node, An OR circuit; a p-channel MOS transistor having a drain node coupled to the output node of the OR circuit through a resistor; a high pass filter coupled between an output node of the output transistor and a gate node of the p-channel MOS transistor, a high pass filter, the drain of which provides the dynamically modulated switching input signal; a multiplexer configured to select one of the switching input signal and the dynamically modulated switching input signal in response to the current direction signal.

4. The switching amplifier circuit of claim 3.

7. the first pull-up transistor is a PMOS transistor; the first slew control circuit is a PMOS slew control circuit; 7. The switching amplifier circuit of claim 6.

8. the second pull-up transistor is a PMOS transistor; the second slew control circuit is a PMOS slew control circuit; 7. The switching amplifier circuit of claim 6.

9. the given slew control circuit is an NMOS slew control circuit, the first and second switch transistors are NMOS transistors, and the NMOS slew control circuit a first input node for receiving said switching input signal; a second input node for receiving the current sense signal; and having an output node, An AND circuit; an n-channel MOS transistor having a drain node coupled to the output node of the AND circuit through a resistor; a high pass filter coupled between an output node of the output transistor and a gate node of the n-channel MOS transistor, a high pass filter, the drain of which provides the dynamically modulated switching input signal; a multiplexer configured to select one of the switching input signal and the dynamically modulated switching input signal in response to the current direction signal.

4. The switching amplifier circuit of claim 3.

10. the first pull-down transistor is an NMOS transistor; the third slew control circuit is an NMOS slew control circuit; 10. The switching amplifier circuit of claim 9.

11. the second pull-down transistor is an NMOS transistor; the fourth slew control circuit is an NMOS slew control circuit; 10. The switching amplifier circuit of claim 9.

12. a control terminal coupled to a switching input signal; a drain node coupled to the output node for coupling to a load device; and a source node coupled to a reference voltage; An output transistor; a slew control circuit including a current source coupled in series at a connection node of a first switch transistor and a second switch transistor connected in parallel, the connection node being coupled to the control terminal of the output transistor; Equipped with the first switch transistor having a control terminal coupled to the switching input signal; the second switch transistor having a control terminal coupled to either the switching input signal or a dynamically modulated switching input signal depending on a current direction at the output node. Output drivers with slew rate control.

13. 13. The output driver of claim 12, wherein the dynamically modulated switching input signal comprises a negative pulse signal determined by the switching input signal and a high pass filter coupled to the output node.

14. 14. The output driver of claim 13, wherein the dynamically modulated switching input signal is generated by adding a delay according to a sensed output signal using a delay cell.

15. the output transistor is an NMOS transistor, and the through control circuit is a first input node for receiving said switching input signal; a second input node for receiving the current detection signal IL-Dir; and having an output node, An AND circuit; an n-channel MOS transistor having a drain node coupled to the output node of the AND circuit through a resistor; a high pass filter coupled between the output node of the output transistor and a gate node of a switch transistor, a high pass filter, the drain node of the n-channel MOS transistor providing a dynamically modulated switching signal; a multiplexer circuit configured to select one of the switching input signal and the dynamically modulated switching input signal in response to a current direction signal.

13. An output driver as claimed in claim 12.

16. the output transistor is a PMOS transistor, and the through control circuit is a first input node for receiving said switching input signal; a second input node for receiving the current sense signal; and having an output node, An OR circuit; a p-channel MOS transistor having a drain node coupled to the output node of the OR circuit through a resistor; a high pass filter coupled between the output node of the output transistor and a gate node of a switch transistor, a high pass filter, the drain of which provides the dynamically modulated switching input signal; a multiplexer configured to select one of the switching input signal and the dynamically modulated switching input signal in response to the current direction signal.

13. An output driver as claimed in claim 12.

17. controlling an output transistor by a switching input signal at a control terminal of said output transistor; adjusting a turn-off current of the output transistor using a slew control circuit including a current source coupled in series at a connection node with a first switch transistor and a second switch transistor connected in parallel, the connection node being coupled to the control terminal of the output transistor; turning on the first switch transistor using the switching input signal; and and adjusting, depending on a current direction at an output node of the output transistor, to turn on the second switch transistor using either the switching input signal or a dynamically modulated switching input signal. A method for operating an output driver.

18. 20. The method of claim 17, further comprising forming the dynamically modulated switching input signal by modifying the switching input signal using a pulse signal determined by a high pass filter coupled to the output node.

19. 20. The method of claim 17, further comprising configuring the second switch transistor with an on-resistance that is 25% or less of an on-resistance of the first switch transistor.

20. 20. The method of claim 17, further comprising generating the dynamically modulated switching input signal by applying a delay according to a sensed output signal using a delay cell.

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