Small-loop delay clock and data recovery block for high-speed next-generation c-phy

Abstract

To provide a method and an apparatus for clock recovery of communication via a multi-wire, multi-phase interface.SOLUTION: The method includes generating a combinational signal that includes transition pulses. Each transition pulse is generated in response to a transition in a differential signal that represents a difference in the signaling state of a pair of wires in a three-wire bus. The method also provides a logic circuit with the combinational signal. The logic circuit provides a clock signal as its output. Here, a pulse in the combinational signal causes the clock signal to be driven to a first state. The method further receives a reset signal derived from the clock signal by the logic circuit delaying the transition to the first state and passing the transition from the first state without any additional delay. The clock signal is driven from the first state after passing the transition of the clock signal to the first state.SELECTED DRAWING: Figure 20

Description

Claiming priority

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of nonprovisional patent application No. 17 / 001,801, filed in the United States Patent and Trademark Office on August 25, 2020, and provisional patent application No. 62 / 925,916, filed in the United States Patent and Trademark Office on October 25, 2019, the contents of which are incorporated herein in their entireties as if fully set forth below and for all applicable purposes. [Technical field]

[0002] This disclosure relates generally to high speed data communication interfaces, and more particularly to clock generation in a receiver coupled to a multi-wire, multi-phase data communication link. [Background technology]

[0003]

[0003] A manufacturer of a mobile device, such as a cellular phone, may obtain parts of the mobile device from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, an imaging device or camera may be obtained from a second manufacturer, and a display may be obtained from a third manufacturer. The application processor, imaging device, display controller, or other types of devices may be interconnected using a standard-based or proprietary physical interface. In one example, an imaging device may be connected using a Camera Serial Interface (CSI) defined by the Mobile Industry Processor Interface (MIPI) Alliance. In another example, a display may include an interface that conforms to the Display Serial Interface (DSI) standard specified by the Mobile Industry Processor Interface (MIPI) Alliance.

[0004]

[0004] The C-PHY interface is a multiphase three-wire interface defined by the MIPI Alliance that uses a triplet of conductors to transmit information between devices. Each wire in the triplet can be in one of three signaling states during the transmission of a symbol. Clock information is encoded in the sequence of symbols transmitted, and the receiver generates a clock signal from the transitions between successive symbols. The ability of a clock and data recovery (CDR) circuit to recover the clock information may be limited by the maximum time variations associated with the transitions of signals transmitted on different wires of the communication link. The CDR circuit in the C-PHY receiver may employ a feedback loop to control a circuit that generates a pulse in the received clock signal. The feedback loop may be used to ensure that the pulse generation circuit does not generate additional pulses triggered by transients that may occur before the conductors in the triplet exhibit a stable signaling state before providing a sampling edge. The maximum symbol transmission rate may be limited by feedback loops, and there is a continuing need for optimized clock generation circuits that can function reliably at higher signaling frequencies. Summary of the Invention

[0005]

[0005] The embodiments disclosed herein provide systems, methods and apparatus that enable improved communication over multi-wire and / or multi-phase communication links that may be deployed in devices such as mobile terminals having multiple integrated circuit (IC) devices.

[0006] In various aspects of the disclosure, a clock recovery device includes a plurality of pulse generating circuits, a first logic circuit, a second logic circuit, and an asymmetric delay circuit. Each pulse generating circuit is configured to generate a transition pulse in response to a transition in a differential signal representing a difference between signaling states of a pair of wires in a three-wire bus. The first logic circuit is configured to provide a combination signal including a pulse corresponding to the transition pulse received from the plurality of pulse generating circuits. The second logic circuit is configured to output a clock signal in response to the pulse in the combination signal and used to decode information from the transition in the signaling state of the three-wire bus. The pulse in the combination signal causes the clock signal to be driven to a first state. The asymmetric delay circuit is configured to generate a reset signal from the clock signal. The reset signal may be generated by delaying a transition to the first state and passing a transition from the first state without an added delay, and the clock signal may be driven from the first state when the reset signal transitions to the first state.

[0007] In some aspects, each of the plurality of pulse generating circuits includes an exclusive-OR gate configured to receive as inputs an associated differential signal and a delayed version of the associated differential signal. The first logic circuit may include a logic gate configured to provide a combined signal by combining output signals received from the exclusive-OR gate of each pulse generating circuit. Each of the plurality of pulse generating circuits may be configured to generate a pulse having a duration configured based on a minimum clock pulse duration defined for the second logic circuit. The duration of the pulse generated by the delay circuit in each of the plurality of pulse generating circuits may be configurable. The duration of the delay applied by the asymmetric delay circuit to the transition to the first state may be configurable.

[0008] In one aspect, the asymmetric delay circuit is a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state. The rising edge delay circuit may be configured to pass a transition from a high logic state to a low logic state without added delay. In one aspect, a wire state decoder is configured to decode symbols from transitions in the signaling states of the three-wire bus based on timing information provided in a clock signal.

[0009] In various aspects of the disclosure, a clock recovery method includes generating a combined signal including a pulse corresponding to a transition pulse generated in response to a transition in a differential signal representing a difference between signaling states of pairs of wires in a three-wire bus. The clock recovery method further includes providing the combined signal to a logic circuit configured to provide a clock signal as an output thereof, where a pulse in the combined signal causes the clock signal to be driven to a first state. The clock recovery method further includes providing a reset signal to the logic circuit, where the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without an added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

[0010] In various aspects of the disclosure, a processor-readable storage medium has one or more instructions that, when executed by at least one processor of a processing circuit in a receiver, cause the at least one processor to generate a combined signal including a pulse corresponding to a transition pulse generated in response to a transition in a differential signal representing a difference in the signaling states of pairs of wires in a three-wire bus. The instructions cause the at least one processor to provide the combined signal to a logic circuit configured to provide a clock signal as an output thereof, where the pulse in the combined signal causes the clock signal to be driven to a first state. The instructions cause the at least one processor to provide a reset signal to the logic circuit, where the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without an added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

[0011] In various aspects of the disclosure, a clock recovery device includes a means for generating a combined signal including a pulse corresponding to a transition pulse generated in response to a transition in a differential signal representing a difference between signaling states of pairs of wires in a three-wire bus. The clock recovery device further includes a means for providing the combined signal to a logic circuit configured to provide a clock signal as an output thereof, where a pulse in the combined signal causes the clock signal to be driven to a first state. The clock recovery device further includes a means for providing a reset signal to the logic circuit, where the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without an added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state. [Brief description of the drawings]

[0012] [Figure 1]

[0012] FIG. 1 illustrates an apparatus employing a data link between IC devices that is selectively operated according to one of a number of available standards or protocols, which may include the C-PHY protocol. [Diagram 2]

[0013] 1 illustrates a system architecture for an apparatus employing a data link between IC devices that selectively operates according to one of several available standards. [Diagram 3]

[0014] A diagram showing a C-PHY three-phase transmitter. [Figure 4]

[0015] FIG. 1 illustrates signaling in a C-PHY three-phase encoded interface. [Diagram 5]

[0016] Diagram showing a C-PHY three-phase receiver. [Figure 6]

[0017] 1 is a state diagram illustrating the potential state transitions in the C-PHY three-phase encoded interface. [Figure 7]

[0018] 13 is an example of the effect of signal rise time on transition detection in a C-PHY decoder. [Figure 8]

[0019] FIG. 13 illustrates transition detection in a C-PHY decoder. [Figure 9]

[0020] 2 illustrates an example of signal transitions occurring between pairs of successive symbols transmitted on a C-PHY interface. [Figure 10]

[0021] FIG. 2 is a diagram showing the transition region and eye region in an eye pattern. [Figure 11]

[0022] FIG. 2 illustrates an example of an eye diagram generated for a C-PHY three-phase interface. [Figure 12]

[0023] FIG. 2 illustrates an example of a CDR circuit for a C-PHY three-phase interface. [Figure 13]

[0024] FIG. 13 is a timing diagram illustrating the CDR circuitry of FIG. 12. [Figure 14]

[0025] 13 is a diagram illustrating timing associated with a CDR circuit having a loop time that is shorter than the skew between signals transmitted on the C-PHY 3-phase signal. [Figure 15]

[0026] 1 illustrates a timing diagram associated with a CDR circuit having a loop time longer than the symbol interval of a C-PHY 3-phase signal. [Figure 16]

[0027] FIG. 2 illustrates a CDR circuit provided in accordance with certain aspects of the present disclosure. [Figure 17]

[0028] 17 is a timing diagram illustrating the CDR circuitry shown in FIG. 16. [Figure 18]

[0029] FIG. 2 illustrates an example of a rising edge delay circuit that can be used in accordance with some aspects disclosed herein. [Figure 19]

[0030] FIG. 1 is a block diagram illustrating an example of an apparatus employing processing circuitry that can be adapted in accordance with some aspects disclosed herein. [Figure 20]

[0031] 1 is a flowchart of a first method of calibration according to certain aspects disclosed herein. [Figure 21]

[0032] FIG. 1 illustrates a first example of a hardware implementation for an apparatus employing a processing circuit adapted in accordance with certain aspects disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0033] The detailed description of the embodiments of the invention described below with reference to the accompanying drawings illustrates various configurations and does not represent the only configurations in which the concepts described herein may be practiced. The detailed description of the embodiments of the invention includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0014]

[0034] Terms such as "component," "module," and "system" as used in this application are intended to include computer-related entities such as, but not limited to, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. As an example, both an application running on a computing device and that computing device may be a component. One or more components may reside within a process and / or thread of execution, and a component may be localized on one computer and / or distributed among two or more computers. Furthermore, these components may execute from various computer readable media having various data structures stored thereon. These components may communicate via signals with other components in a local system, a distributed system, and / or over a network such as the Internet, through local processes and / or remote processes, such as by following signals having one or more data packets, such as data from one component interacting with other systems over a network such as the Internet.

[0015]

[0035] Moreover, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, the phrase "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, the phrase "X employs A or B" is satisfied by either X employing A, X employing B, or X employing both A and B. Furthermore, the articles "a" and "an," as used in this application and the appended claims, should be construed generally to mean "one or more," unless otherwise specified or clear from the context that the singular form is intended. Overview

[0036] Some aspects of the present invention may be applicable to the C-PHY interface specified by the MIPI Alliance, which may be deployed to connect electronic devices that are subcomponents of mobile equipment, such as phones, mobile computing devices, appliances, automotive electronics, avionics systems, etc. Examples of mobile equipment include mobile computing devices, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, intelligent lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, gaming consoles, entertainment devices, vehicle components, avionics systems, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multicopters, or any other similarly functioning devices.

[0016]

[0037] The C-PHY interface is a high-speed serial interface capable of providing high throughput over bandwidth-limited channels. The C-PHY interface may be deployed to connect application processors to peripherals including displays and cameras. The C-PHY interface encodes data into symbols transmitted on a set of three wires, sometimes referred to as a triplet or a triplet of wires. For each symbol transmission interval, a three-phase signal is transmitted in different phases on the wires of the triplet, where the phase of the three-phase signal on each wire is defined by the symbol transmitted in the symbol transmission interval. Each triplet provides a lane on the communication link. A symbol transmission interval may be defined as a time interval during which a single symbol controls the signaling state of the triplet. In each symbol transmission interval, one wire of the triplet is undriven and the remaining two wires are differentially driven such that one of the two differentially driven wires exhibits a first voltage level and the other differentially driven wire exhibits a second voltage level different from the first voltage level. The undriven wire may be floated, driven, and / or terminated such that it assumes a third voltage level at or near a mid-level voltage between the first and second voltage levels. In one example, the driven voltage levels may be +V and -V and the undriven voltage is 0V. In another example, the driven voltage levels may be +V and 0V and the undriven voltage is +1 / 2V. A different symbol may be transmitted in each successively transmitted pair of symbols, and different pairs of wires may be differentially driven at different symbol intervals.

[0017]

[0038] More recent implementations and proposed specifications for C-PHY, including the C-PHY 1.2 and C-PHY 2.0 specifications, define frequencies of the symbol transmit clock signal that can exceed the capabilities of conventional CDR circuits to recover the clock signal at the receiver. The ability of the clock recovery circuit to recover the clock information may be limited by the maximum time variations associated with the transitions of the signals transmitted on different wires of the communication link. The clock recovery circuit in the C-PHY receiver typically employs a feedback loop that controls the generation of pulses in the receive clock signal. The feedback loop may be used to ensure that the pulse generation circuit does not generate additional pulses triggered by transients that may occur before the conductors in the triad exhibit a stable signaling state before providing a sampling edge. The maximum symbol transmission rate may be limited by the feedback loop, and there is a continuing need for an optimized clock generation circuit that can function reliably at the higher signaling frequencies defined by later generations of the C-PHY specification.

[0018]

[0039] Some aspects disclosed herein provide a clock recovery circuit in a C-PHY receiver circuit, where the loop time of the C-PHY receiver circuit is minimized so that the clock recovery circuit can operate at a next generation C-PHY clock rate. In one example, the clock recovery circuit generates a combined signal including one or more transition pulses, provides the combined signal to a logic circuit, the logic circuit configured to provide a clock signal as its output, and provides a reset signal to the logic circuit, where the reset signal is derived from the clock signal by delaying a transition to a first state and passing a transition from the first state without added delay. Each transition pulse is generated in response to a transition in a differential signal representing a difference between signaling states of a pair of wires in a three-wire bus. The pulse in the combined signal causes the clock signal to be driven to the first state, and the clock signal is driven from the first state after passing a transition of the clock signal to the first state.

[0019]

[0040] The clock recovery circuit may generate a transition pulse for the first differential signal by performing an exclusive OR gate function on the first differential signal and a delayed version of the first differential signal. The clock recovery circuit may configure the at least one pulse generating circuit to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for the logic circuit. The clock recovery circuit may calibrate the at least one pulse generating circuit based on an operating condition of the three-wire bus. The clock recovery circuit may configure an asymmetric delay circuit to select a duration of a delay applied to a transition to the first state. The asymmetric delay circuit may include a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without an added delay. The clock recovery circuit may provide the clock signal to a wire state decoder configured to decode symbols from transitions in the signaling states of the three-wire bus based on timing information provided in the clock signal. Examples of devices using the C-PHY interface

[0041] FIG. 1 illustrates an example of an apparatus 100 that may be adapted according to some aspects disclosed herein. The apparatus 100 may employ a C-PHY three-phase protocol to implement one or more communication links. The apparatus 100 may include a processing circuit 102 having multiple circuits or devices 104, 106, and / or 108. In some examples, the circuits or devices 104, 106, and / or 108 may be implemented in one or more ASICs or in a system-on-chip (SoC), where the SoC may include an integrated circuit that implements all or substantially all of the components of a processor, computer, or other electronic system. In one example, the apparatus 100 may be a communication device, and the processing circuit 102 may include a processor 112 provided in a first circuit or device 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network through an antenna 124.

[0020]

[0042] The first circuit or device 104 may have one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116, and / or other logic circuits or functions. The processing circuit 102 may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors 112 to execute software modules resident in the on-board memory 114 or processor-readable storage 122 provided on the processing circuit 102. The software modules may include instructions and data stored in the on-board memory 114 or other processor-readable storage 122. The first circuit or device 104 may access its on-board memory 114, processor-readable storage 122, and / or storage external to the processing circuit 102. The on-board memory 114 and / or processor-readable storage 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that may be used in processing systems and computing platforms. The processing circuit 102 may include, implement, or have access to a local database or other parameter storage capable of maintaining operational parameters and other information used to configure and operate the device 100 and / or the processing circuit 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, soft or hard disks, and the like. The processing circuit 102 may also be operatively coupled to external devices, such as an antenna 124, a display 126, operator controls such as switches or buttons 128, 130, and / or an integrated or external keypad 132, among other components. A user interface module may be configured to operate with the display 126, external keypad 132, and the like, through a dedicated communication link or through one or more serial data interconnects.

[0021]

[0043] The processing circuit 102 may provide one or more buses 118a, 118b, 120 that allow several circuits or devices 104, 106, and / or 108 to communicate. In one example, the first circuit or device 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a communication specification or protocol. The processing circuit 102 may include or control power management functions that configure and manage the operation of the apparatus 100.

[0022]

[0044] 2 illustrates some aspects of an apparatus 200 including multiple IC devices 202 and 230 that can exchange data and control information through a communication link 220. The communication link 220 can be used to connect a pair of IC devices 202 and 230 that are located in close proximity to each other or physically located in different parts of the apparatus 200. In one example, the communication link 220 can be provided on a chip carrier, substrate, or circuit board that carries the IC devices 202 and 230. In another example, the first IC device 202 can be located in a keypad section of a flip phone and the second IC device 230 can be located in a display section of the flip phone. In another example, a portion of the communication link 220 can include a cable or optical connection.

[0023]

[0045] The communication link 220 may include multiple channels 222, 224, and 226. One or more of the channels 226 may be bidirectional and may operate in half-duplex and / or full-duplex modes. One or more of the channels 222 and 224 may be unidirectional. The communication link 220 may be asymmetric, providing a higher bandwidth in one direction. In one example described herein, the first channel 222 may be referred to as a forward channel 222 and the second channel 224 may be referred to as a reverse channel 224. Even if both IC devices 202 and 230 are configured to transmit and receive on the channel 222, the first IC device 202 may be designated as a host system or transmitter and the second IC device 230 may be designated as a client system or receiver. In one example, the forward channel 222 may operate at a higher data rate when communicating data from the first IC device 202 to the second IC device 230, and the reverse channel 224 may operate at a lower data rate when communicating data from the second IC device 230 to the first IC device 202.

[0024]

[0046] The IC devices 202 and 230 may each include a processor 206, 236, a controller or other processing and / or computing circuitry or device. In one example, the first IC device 202 may perform the core functions of the apparatus 200, including establishing and maintaining wireless communications through the wireless transceiver 204 and antenna 214, and the second IC device 230 may support a user interface that manages or operates a display controller 232 and may control the operation of a camera or video input device using a camera controller 234. Other features supported by one or more of the IC devices 202 and 230 may include a keyboard, a voice recognition component, and other input or output devices. The display controller 232 may include circuitry and software drivers to support displays such as a liquid crystal display (LCD) panel, a touch screen display, indicators, and the like. The storage media 208 and 238 may include temporary and / or non-transitory storage devices adapted to maintain instructions and data used by the respective processors 206 and 236 and / or other components of the IC devices 202 and 230. Communications between each processor 206, 236 and its corresponding storage media 208 and 238 and other modules and circuits may be facilitated by one or more internal buses 212 and 242 and / or channels 222, 224 and / or 226 of the communication link 220.

[0025]

[0047] The reverse channel 224 may be operated in the same manner as the forward channel 222, and the forward channel 222 and the reverse channel 224 may be capable of transmitting at comparable or different rates, where the rates may be expressed as data transfer rates, symbol transmission rates, and / or clocking rates. The forward and reverse data rates may be substantially the same or may differ by several orders of magnitude, depending on the application. In some applications, a single bidirectional channel 226 may support communication between the first IC device 202 and the second IC device 230. The forward channel 222 and / or the reverse channel 224 may be configurable to operate in a bidirectional mode, for example, when the forward channel 222 and the reverse channel 224 share the same physical connection and operate in a half-duplex manner. In one example, the communication link 220 may be operated to communicate control, command, and other information between the first IC device 202 and the second IC device 230 in accordance with industry or other standards.

[0026]

[0048] The communication link 220 of FIG. 2 may be implemented according to the MIPI Alliance specification for C-PHY and may provide a wired bus including multiple signal wires (shown as M wires). The M wires may be configured to carry N-phase encoded data in a high-speed digital interface, such as a Mobile Display Digital Interface (MDDI). The M wires may facilitate N-phase polarity encoding on one or more of the channels 222, 224, and 226. The physical layer drivers 210 and 240 may be configured or adapted to generate the N-phase polarity encoded data for transmission on the communication link 220. The use of N-phase polarity encoding provides high-speed data transfer and may consume half or less power of other interfaces because fewer drivers are active in an N-phase polarity encoded data link.

[0027]

[0049] Physical layer drivers 210 and 240, when configured for N-phase polarity encoding, can generally encode multiple bits per transition on communication link 220. In one example, a combination of three-phase and polarity encoding can be used to support a wide video graphics array (WVGA) 80 frames per second LCD driver IC without a frame buffer, delivering pixel data at 810 Mbps for display refresh.

[0028]

[0050] Figure 3 is a diagram 300 illustrating a three-wire, three-phase polar encoder that may be used to implement some aspects of the communication link 220 shown in Figure 2. The three-wire, three-phase encoding example is chosen solely for the purpose of simplifying the description of some aspects of the invention. The principles and techniques disclosed for the three-wire, three-phase encoder may be applied in other configurations of M-wire, N-phase polar encoders.

[0029]

[0051] The signaling states defined for each of the three wires in the three-wire, three-phase polarity encoding scheme may include an undriven state, a positively driven state, and a negatively driven state. The positively driven state and the negatively driven state may be obtained by applying a voltage difference between two of the signal wires 318a, 318b, and / or 318c and / or by driving current through two of the signal wires 318a, 318b, and / or 318c connected through a termination resistor such that the current flows in different directions through the two of the signal wires 318a, 318b, and / or 318c. The undriven state may be achieved by putting the output of the driver of the signal wires 318a, 318b, or 318c into a high impedance mode. Alternatively or additionally, an undriven state may be obtained on a signal wire 318a, 318b or 318c by passively or actively reaching a voltage level on the "undriven" signal wire 318a, 318b or 318c that is substantially halfway between the positive and negative voltage levels provided on the driven signal wires 318a, 318b and / or 318c. Generally, there is no significant current flow through the undriven signal wire 318a, 318b or 318c. The signaling states defined for a three-wire, three-phase polarity encoding scheme may be indicated using three voltage or current states (+1, -1, and 0).

[0030]

[0052] A three-wire, three-phase polarity encoder may employ line drivers 308 to control the signaling states of the signal wires 318a, 318b, and 318c. The line drivers 308 may be implemented as unit-level current-mode or voltage-mode drivers. In some implementations, each line driver 308 may receive a set of signals 316a, 316b, and 316c that determine the output state of the corresponding signal wire 318a, 318b, and 318c. In one example, each of the sets of signals 316a, 316b, and 316c may include two or more signals, including a pull-up signal (PU signal) and a pull-down signal (PD signal), which, when high, activate pull-up and pull-down circuits that drive the signal wires 318a, 318b, and 318c toward higher or lower voltage levels, respectively. In this example, when both the PU and PD signals are low, the signal wires 318a, 318b and 318c may be terminated to a mid-level voltage.

[0031]

[0053] For each symbol transmission interval in an M-wire, N-phase polarity encoding scheme, at least one signal wire 318a, 318b or 318c is at a neutral level / undriven (0) voltage or current state, and the number of positively driven (+1 voltage or current state) signal wires 318a, 318b or 318c is equal to the number of negatively driven (-1 voltage or current state) signal wires 318a, 318b or 318c such that the sum of the currents flowing to the receiver is always 0. For each symbol transmission interval, the signaling state of at least one signal wire 318a, 318b or 318c is changed from the wire state transmitted in the preceding transmission interval.

[0032]

[0054] In operation, the mapper 302 may receive and map 16-bit data 310 into seven symbols 312. In a three-wire example, each of the seven symbols defines the state of signal wires 318a, 318b, and 318c for one symbol transmission interval. The seven symbols 312 may be serialized using a parallel-to-serial converter 304 that provides a timed sequence of symbols 314 for each signal wire 318a, 318b, and 318c. The sequence of symbols 314 is generally synchronized with a symbol clock (CLK SYM The symbol transmission interval is timed using a transmit clock, sometimes referred to as a symbol clock period. In one example, the period of the symbol clock defines the duration of a symbol transmission interval. A three-wire, three-phase encoder 306 receives the sequence of seven symbols 314 generated by the mapper, one symbol at a time, and calculates the state of each signal wire 318a, 318b, and 318c for each symbol transmission interval. The three-wire, three-phase encoder 306 selects the state of signal wires 318a, 318b, and 318c based on the current input symbol 314 and the previous states of signal wires 318a, 318b, and 318c.

[0033]

[0055] The use of M-wire, N-phase encoding allows some bits to be encoded in multiple symbols, where the bits per symbol are not an integer. In the example of a three-wire communication link, there are three available combinations of two wires that can be driven simultaneously, and two possible combinations of polarities on the pairs of driven wires, resulting in six possible states. Since each transition occurs from the current state, five of the six states are available in every transition. The state of at least one wire is required to change in each transition. For five states, log2(5) ≈ 2.32 bits can be encoded per symbol. Thus, seven symbols carrying 2.32 bits per symbol can encode 16.24 bits, so a mapper may accept a 16-bit word and convert it to seven symbols. In other words, the seven symbol combinations that encode five states are 5 7There are (78,125) possible permutations. Therefore, the seven symbols are 16 It can be used to encode (65,536) permutations.

[0034]

[0056] FIG. 4 includes an example of a timing diagram 400 for a signal encoded using a three-phase modulation data encoding scheme based on a circular state diagram 450. Information may be encoded in a sequence of signaling states, where, for example, a wire or connector is in one of three phase states S1, S2, and S3 defined by the circular state diagram 450. Each state may be separated from the other states by a 120° phase shift. In one example, data may be encoded in the direction of rotation of the phase states on the wire or connector. The phase states in the signal may rotate in a clockwise direction 452 and 452' or a counterclockwise direction 454 and 454'. For example, in the clockwise direction 452 and 452', the phase states may progress in a sequence that includes one or more of a transition from S1 to S2, a transition from S2 to S3, and a transition from S3 to S1. In the counterclockwise direction 454 and 454', the phase states may progress in a sequence including one or more of an S3 to S2 transition, an S2 to S1 transition, and an S1 to S3 transition. The three signal wires 318a, 318b, and 318c carry different versions of the same signal, where the versions may be phase shifted by 120° relative to each other. Each signaling state may be represented as a different voltage level on a wire or connector and / or a direction of current flow through the wire or connector. During each of the sequences of signaling states in the three-wire system, each signal wire 318a, 318b, and 318c is in a different signaling state than the other wires. When more than three signal wires 318a, 318b and 318c are used in a three-phase encoding system, two or more signal wires 318a, 318b and / or 318c may be in the same signaling state in each signaling interval, but each state is present on at least one signal wire 318a, 318b and / or 318c in every signaling interval.

[0035]

[0057] Information may be encoded in the direction of rotation at each phase transition 410, and the three-phase signal may change direction for each signaling state. The direction of rotation may be determined by considering which signal wires 318a, 318b and / or 318c are in the “0” state before and after a phase transition, since the non-driven signal wires 318a, 318b and / or 318c change at every signaling state in a rotating three-phase signal, regardless of the direction of rotation.

[0036]

[0058] The encoding scheme may also encode information in the polarity 408 of the two actively driven signal wires 318a, 318b and / or 318c. At any time in a three-wire implementation, exactly two of the signal wires 318a, 318b, 318c are driven with currents in opposite directions and / or with a voltage difference. In one implementation, data may be encoded using a two-bit value 412, where one bit is encoded in the direction of the phase transition 410 and a second bit is encoded in the polarity 408 for the current state.

[0037]

[0059] Timing diagram 400 illustrates data encoding using both phase rotation direction and polarity. Curves 402, 404, and 406 relate to signals carried on three signal wires 318a, 318b, and 318c, respectively, for multiple phase states. Initially, the phase transition 410 is clockwise and the most significant bit is set to a binary "1", after which the rotation of the phase transition 410 switches to a counterclockwise direction at time 414, as represented by a binary "0" in the most significant bit. The least significant bit reflects the polarity 408 of the signal in each state.

[0038]

[0060] According to some aspects disclosed herein, one bit of data may be encoded in the rotation or phase change in a three-wire, three-phase encoding system, and an additional bit may be encoded in the polarity of the two drive wires. Additional information may be encoded in each transition of the three-wire, three-phase encoding system by allowing a transition from the current state to any of the possible states. Assuming three rotation phases and two polarities for each phase, six states are available in a three-wire, three-phase encoding system. Thus, five states are available from the current state, and there may be log2(5)≈2.32 bits encoded per symbol (transition), which allows the mapper 302 to accept a 16-bit word and encode it in seven symbols.

[0039]

[0061] 5 illustrates some aspects of a three-wire, three-phase decoder 500. Differential receivers 502a, 502b, 502c and wire state decoder 504 are configured to provide a digital representation 522 of the state of three transmission lines (e.g., signal wires 318a, 318b, and 318c shown in FIG. 3) relative to one another and detect changes in the state of the three transmission lines compared to the state transmitted in the previous symbol period. Seven successive states are assembled by a serial-to-parallel converter 506 to obtain a set of seven symbols 516 to be processed by a demapper 508. The demapper 508 generates 16 bits of data 518 that can be buffered in a first-in-first-out (FIFO) register 510 to provide output data 520.

[0040]

[0062] The wire state decoder 504 may extract a sequence of symbols 514 from the phase-encoded signals received on the signal wires 318a, 318b, and 318c. The symbols 514 are encoded as a combination of phase rotation and polarity as disclosed herein. The wire state decoder may include a CDR circuit 524 that extracts a clock 526 that may be used to reliably capture the wire state from the signal wires 318a, 318b, and 318c. A transition occurs on at least one of the signal wires 318a, 318b, and 318c at each symbol boundary, and the CDR circuit 524 may be configured to generate the clock 526 based on the occurrence of one or more transitions. An edge of the clock may be delayed to allow time for all signal wires 318a, 318b, and 318c to stabilize, thereby ensuring that the current wire state is captured for decoding purposes.

[0041]

[0063] 6 is a state diagram 600 illustrating possible signaling states 602, 604, 606, 612, 614, 616 of three wires, with possible transitions from each state shown. In an example of a three-wire, three-phase communication link, six states and 30 state transitions are available. The possible signaling states 602, 604, 606, 612, 614, and 616 in the state diagram 600 include and expand upon the states shown in the circular state diagram 450 of FIG. 4. As shown in the sample of state element 628, each signaling state 602, 604, 606, 612, 614, and 616 in the state diagram 600 defines a voltage signaling state for the signal wires 318a, 318b, 318c, labeled A, B, and C, respectively. For example, in signaling state 602(+x), wire A=+1, wire B=-1 and wire C=0, which results in outputs of differential receiver 502a (AB)=+2, differential receiver 502b (BC)=-1 and differential receiver 502c (CA)=-1. The transition decision made by the phase change detection circuitry in the receivers is based on the five possible levels generated by differential receivers 502a, 502b, 502c, including -2, -1, 0, +1 and +2 voltage states.

[0042]

[0064] The transitions in the state diagram 600 may be represented by Flip, Rotate, Polarity symbols (e.g., FRP symbol 626) having one of three-bit binary values ​​in the set {000, 001, 010, 011, 100}. The Rotation bit 622 of the FRP symbol 626 indicates the direction of phase rotation associated with the transition to the next state. The Polarity bit 624 of the FRP symbol 626 is set to a binary 1 when the transition to the next state involves a change in polarity. When the Flip bit 620 of the FRP symbol 626 is set to a binary 1, the Rotation and Polarity values ​​may be ignored and / or zeroed out. A flip represents a state transition that involves only a change in polarity. Thus, the phase of the three-phase signal is not considered to be rotated when a flip occurs, and the Polarity bit is redundant when a flip occurs. The FRP symbol 626 corresponds to a wire state change for each transition. The state diagram 600 may be separated into an inner circle 608 that includes the positive signaling states 602 , 604 , 606 and an outer circle 618 that encompasses the negative signaling states 612 , 614 , 616 . Jitter in a 3-phase interface

[0065] A three-phase transmitter includes drivers that provide high, low and medium voltage levels on the transmission channel. This results in several varying transitions between successive symbol intervals. Low-to-high and high-to-low voltage transitions are sometimes called full-swing transitions, while low-to-medium and high-to-medium voltage transitions are sometimes called half-swing transitions. Different types of transitions may have different rise or fall times and may result in different zero crossings at the receiver. These differences may result in "coding jitter", which may affect link signal integrity performance.

[0043]

[0066] 7 is a timing diagram 700 illustrating some aspects of transition variability at the output of a C-PHY three-phase transmitter. The variability in signal transition times may be due to the presence of different voltage and / or current levels used in three-phase signaling. The timing diagram 700 illustrates transition times in a signal received from a single signal wire 310a, 310b or 310c. The first symbol Sym n 702 is transmitted in a first symbol interval, which ends at time 722, after which the second symbol Sym n+1 704 is transmitted in the second symbol interval. The second symbol interval may end at time 724, after which the third symbol, Sym n+2 706 is transmitted in a third symbol interval, which ends at time 726, after which a fourth symbol, Sym n+3708 is transmitted in the fourth symbol interval. A transition from a state determined by the first symbol 702 to a state corresponding to the second symbol 704 may be detectable after a delay 712 due to the time it takes for the voltage in the signal wires 310a, 310b or 310c to reach threshold voltages 718 and / or 720. The threshold voltages may be used to determine the state of the signal wires 310a, 310b or 310c. A transition from a state determined by the second symbol 704 to a state for the third symbol 706 may be detectable after a delay 714 due to the time it takes for the voltage in the signal wires 310a, 310b or 310c to reach one of the threshold voltages 718 and / or 720. A transition from the state determined by the third symbol 706 to the state for the fourth symbol 708 may be detectable after a delay 716 due to the time it takes for the voltage in the signal wires 310a, 310b or 310c to reach threshold voltages 718 and / or 720. The delays 712, 714 and 716 may have different durations, which may be due in part to variations in device manufacturing processes and operating conditions, which may result in unequal effects on the transitions between the different voltage or current levels associated with the three states and / or different transition magnitudes. These differences may cause jitter and other problems in the C-PHY three-phase receiver.

[0044]

[0067] 8 illustrates some aspects of CDR circuits that may be implemented in a receiver in a C-PHY interface 800. Differential receivers 802a, 802b, and 802c are configured to generate a set of differential signals 810a, 810b, 810c by comparing the signaling states of each different pair of signal wires 310a, 310b, and 310c in a triplet. In the illustrated example, the first differential receiver 802a provides an AB differential signal 810a representing the difference between the signaling states of the A signal wire 310a and the B signal wire 310b, the second differential receiver 802b provides a BC differential signal 810b representing the difference between the signaling states of the B signal wire 310b and the C signal wire 310c, and the third differential receiver 802c provides a CA differential signal 810c representing the difference between the signaling states of the C signal wire 310c and the A signal wire 310a. Thus, the transition detection circuit 804 may be configured to detect the occurrence of a phase change as the output of at least one of the differential receivers 802a, 802b, and 802c changes at the end of each symbol interval.

[0045]

[0068] Transitions between some consecutively transmitted pairs of symbols may be detectable by a single differential receiver 802a, 802b, or 802c, while other transitions may be detected by two or more of the differential receivers 802a, 802b, and 802c. In one example, the state, or relative state, of the two wires may be unchanged after a transition, and the output of the corresponding differential receiver 802a, 802b, or 802c may also be unchanged after a phase transition. Thus, the clock generation circuit 806 may include or cooperate with the transition detection circuit 804 and / or other logic to monitor the outputs of all the differential receivers 802a, 802b, and 802c to determine when a phase transition has occurred. The clock generation circuit may generate a receive clock signal 808 based on the detected phase transition.

[0046]

[0069] Changes in the signaling states of the three wires in the triad may be detected at different times, which may cause the differential signals 810a, 810b, 810c to assume stable states at different times. The states of the differential signals 810a, 810b, 810c may switch before stability is reached after the signaling state of each signal wire 310a, 310b and / or 310c transitions to its defined state for a symbol transmission interval. The result of such variability is shown in the timing diagram 820 of FIG. 8.

[0047]

[0070] The timing of the signaling state change detection may vary according to the type of signaling state change that occurs. Markers 822, 824, and 826 represent the occurrence of transitions in the differential signals 810a, 810b, 810c provided to the transition detection circuit 804. The markers 822, 824, and 826 are assigned different heights in the timing diagram 820 for clarity of illustration only, and the relative heights of the markers 822, 824, and 826 do not indicate any particular relationship to voltage or current levels, polarities, or weighting values ​​used for clock generation or data decoding. The timing diagram 820 illustrates the effect of the timing of the transitions relative to the transmitted symbols on the phase and polarity on the three signal wires 310a, 310b, and 310c. In timing diagram 820, the transitions between several symbols may result in variable acquisition windows 830a, 830b, 830c, 830d, 830e, 830f and / or 830g (collectively symbol acquisition windows 830) during which symbols may be reliably acquired. The number of state changes detected and their relative timing may result in jitter on the clock signal 808.

[0048]

[0071] The throughput of the C-PHY communication link may be affected by the duration and variability in signal transition times. For example, variability in the detection circuitry may be caused by manufacturing process tolerances, and variations and stability of voltage and current sources and operating temperature, as well as the electrical characteristics of the signal wires 310a, 310b, and 310c. Variability in the detection circuitry may limit the channel bandwidth.

[0049]

[0072] 9 includes timing diagrams 900 and 920 depicting several examples of transitions from a first signaling state to a second signaling state over several consecutive symbols. The signaling state transitions shown in timing diagrams 900 and 920 are selected for illustrative purposes, and other transitions and combinations of transitions may occur in a MIPI Alliance C-PHY interface. Timing diagrams 900 and 920 relate to an example of a three-wire, three-phase communication link in which multiple receiver output transitions may occur at each symbol interval boundary due to rise and fall time differences between signal levels on the three wires. 8, a first timing diagram 900 shows the signaling states of the triplet of signal wires 310a, 310b, and 310c (A, B, and C) before and after a transition, and a second timing diagram 920 shows the output of differential receivers 802a, 802b, and 802c providing differential signals 810a, 810b, 810c representing the difference between the signal wires 310a, 310b, and 310c. In many instances, the set of differential receivers 802a, 802b, and 802c can be configured to capture transitions by comparing different combinations for the two signal wires 310a, 310b, and 310c. In one example, these differential receivers 802a, 802b, and 802c can be configured to generate an output by determining the difference (e.g., by subtraction) of their respective input voltages.

[0050]

[0073] In each of the examples shown in timing diagrams 900 and 920, an initial symbol representing the -z state 616 (see FIG. 6) transitions to a different symbol. As shown in timing diagrams 902, 904, and 906, signal A is initially in a +1 state, signal B is in a 0 state, and signal C is in a -1 state. Thus, as shown in timing diagrams 922, 932, 938 for the differential receiver outputs, differential receivers 802a, 802b initially measure a +1 difference 924, and differential receiver 802c measures a -2 difference 926.

[0051]

[0074] In a first example corresponding to timing diagrams 902, 922, a transition occurs from a symbol representing a -z state 616 to a symbol representing a -x signaling state 612 (see FIG. 6), where signal A transitions to a -1 state, signal B transitions to a +1 state, signal C transitions to a 0 state, differential receiver 802a transitions from a +1 differential 924 to a -2 differential 930, differential receiver 802b remains at a +1 differential 924, 928, and differential receiver 802c transitions from a -2 differential 926 to a +1 differential 928.

[0052]

[0075] In a second example corresponding to timing diagrams 904, 932, a transition occurs from a symbol representing a -z state 616 to a symbol representing a +z signaling state 606, where signal A transitions to the -1 state, signal B remains in the 0 state, signal C transitions to the +1 state, the two differential receivers 802a and 802b transition from a +1 differential 924 to a -1 differential 936, and differential receiver 802c transitions from a -2 differential 926 to a +2 differential 934.

[0053]

[0076] In a third example corresponding to timing diagrams 906, 938, a transition occurs from a symbol representing a -z state 616 to a symbol representing a +x signaling state 602, where signal A remains in the +1 state, signal B transitions to the -1 state, signal C transitions to the 0 state, differential receiver 802a transitions from a +1 difference 924 to a +2 difference 940, differential receiver 802b transitions from a +1 difference 924 to a -1 difference 942, and differential receiver 802c transitions from a -2 difference 926 to a -1 difference 942.

[0054]

[0077] These examples show transitions in differential values ​​across 0, 1, 2, 3, 4 and 5 levels. Pre-emphasis techniques used for typical differential or single-ended serial transmitters are developed for 2-level transitions and may have some adverse effects when used on MIPI Alliance C-PHY 3-phase signals. In particular, pre-emphasis circuits that overdrive the signal during the transition may cause overshoot during transitions across one or two levels, causing false triggering in edge-sensitive circuits.

[0055]

[0078] FIG. 10 shows a binary eye pattern 1000 that is generated as a superposition of multiple symbol intervals, including a single symbol interval 1002. A signal transition region 1004 represents a period of uncertainty at the boundary between two symbols, where variable signal rise times prevent reliable decoding. State information can be reliably determined in a region defined by an eye mask 1006 within the "eye opening," which represents a period of time when symbols are stable and can be reliably received and decoded. The eye mask 1006 masks off regions where no zero crossings occur, and is used by the decoder to prevent multiple clocking due to the effects of subsequent zero crossings at symbol interval boundaries following the first signal zero crossing.

[0056]

[0079] The concept of periodic sampling and display of a signal is useful during the design, adaptation and construction of systems that use clock data recovery circuits that use frequent transitions present in the received data to regenerate a received data timing signal. A communication system based on serializer / deserializer (SERDES) technology is one example of a system in which the binary eye pattern 1000 may be utilized as a basis for determining the ability to reliably recover data based on the eye opening of the binary eye pattern 1000.

[0057]

[0080] An M-wire N-phase encoding system, such as a 3-wire, 3-phase encoder, may encode a signal with at least one transition at every symbol boundary, and the receiver may use those guaranteed transitions to recover the clock. The receiver may require reliable data just before the first signal transition at the symbol boundary, and must be able to reliably mask the occurrence of multiple transitions correlated to the same symbol boundary. Multiple receiver transitions may occur due to slight differences in rise and fall times between signals carried on the M wires (e.g., a triplet of wires), as well as slight differences in signal propagation times between combinations of received signal pairs (e.g., the AB, BC, and CA outputs of differential receivers 802a, 802b, and 802c in FIG. 8).

[0058]

[0081] FIG. 11 illustrates an example of a multilevel eye pattern 1100 generated for a C-PHY three-phase signal. The multilevel eye pattern 1100 may be generated from a superposition of multiple symbol intervals 1102. The multilevel eye pattern 1100 may be generated using a fixed and / or symbol-independent trigger 1110. The multilevel eye pattern 1100 includes an increased number of voltage levels 1120, 1122, 1124, 1126, 1128, which may result from multiple voltage levels measured by the differential receivers 802a, 802b, 802c and the N-phase receiver circuit (see FIG. 8). In this example, the multilevel eye pattern 1100 may correspond to possible transitions in a three-wire, three-phase encoded signal provided to the differential receivers 802a, 802b, and 802c. The three voltage levels may cause the differential receivers 802a, 802b, and 802c to generate strong voltage levels 1126, 1128 and weak voltage levels 1122, 1124 for both positive and negative polarities. In general, only one signal wire 310a, 310b, and 310c is undriven in a symbol, and the differential receivers 802a, 802b, and 802c do not generate a zero-state (here, 0 volts) output. The voltages associated with the strong and weak levels need not be evenly spaced relative to the 0 volt level. For example, the weak voltage levels 1122, 1124 represent a comparison of voltages that may include the voltage levels reached by the undriven signal wires 310a, 310b, and 310c. The multi-level eye pattern 1100 may overlap the waveforms generated by the differential receivers 802a, 802b, and 802c because when the data is captured at the receiving device, all three pairs of signals are considered to be simultaneous. The waveforms generated by the differential receivers 802a, 802b, and 802c represent differential signals 810a, 810b, 810c that represent a comparison of three pairs of signals (AB, BC, and CA).

[0059]

[0082] The drivers, receivers and other devices used in the C-PHY three-phase decoder may exhibit different switching characteristics that may result in relative delays between the signals received from the three wires. Due to slight differences in rise and fall times between the three signals of the triplet of signal wires 310a, 310b, 310c, and due to slight differences in signal propagation times between pair combinations of signals received from the signal wires 310a, 310b, 310c, multiple receiver output transitions may be observed at each symbol interval boundary 1108 and / or 1114. The multi-level eye pattern 1100 may capture the differences in rise and fall times as relative delays of transitions near each symbol interval boundary 1108 and 1114. The differences in rise and fall times may be due to different characteristics of the three-phase drivers. The differences in rise and fall times may also result in an effective shortening or lengthening of the duration of the symbol interval 1102 for a given symbol.

[0060]

[0083] The signal transition region 1104 represents a time, or period, of uncertainty where variable signal rise times prevent reliable decoding. State information may be reliably determined at an "eye opening" 1106, which represents a period of time when symbols are stable and can be reliably received and decoded. In one example, the eye opening 1106 may be determined to start at the end 1112 of the signal transition region 1104 and end at a symbol interval boundary 1114 of the symbol interval 1102. In the example shown in FIG. 11, the eye opening 1106 may be determined to start at the end 1112 of the signal transition region 1104 and end at a time 1116 when the signaling states of the signal wires 310a, 310b, 310c and / or the outputs of the three differential receivers 802a, 802b, and 802c begin to change to reflect the next symbol.

[0061]

[0084] The maximum speed of the communication link 220 configured for N-phase encoding may be limited by the duration of the signal transition region 1104 compared to the eye opening 1106 corresponding to the received signal. The minimum duration for the symbol interval 1102 may be constrained, for example, by tight design margins associated with the CDR circuit 524 in the decoder 500 shown in FIG. 5. Different signaling state transitions may be associated with different variations in signal transition times corresponding to two or more signal wires 310a, 310b and / or 310c, thereby causing the outputs of the differential receivers 802a, 802b and 802c in the receiving device to change at different times and / or rates relative to the symbol interval boundary 1108 at which the inputs of the differential receivers 802a, 802b and 802c begin to change. The difference between the signal transition times may result in a timing skew between the signaling transitions in the two or more differential signals 810a, 810b, 810c. The CDR circuitry may include delay and other circuits to accommodate timing skew between the differential signals 810a, 810b, and 810c.

[0062]

[0085] FIG. 12 provides an example of a CDR circuit 1200 for a three-wire, three-phase interface. The illustrated CDR circuit 1200 includes several features and functional elements that are common to many different types of clock recovery circuits. The CDR circuit 1200 receives differential signals 1202, 1204, 1206, which may be derived, for example, from differential signals 810a, 810b, 810c generated by differential receivers 802a, 802b and 802c of FIG. 8. In the CDR circuit 1200, each differential signal 1202, 1204, 1206 clocks a pair of D-type flip-flops 1210a, 1210b, 1210c to generate an output signal 1230a-1230f. The output signals 1230a-1230f carry a pulse when a transition is detected on the corresponding differential signal 1202, 1204, 1206. A rising edge provided to the clock input on the D-type flip-flop clocks a logic 1 through the D-type flip-flop. Inverters 1208a, 1208b, 1208c may be used to provide an inverted version of the differential signal 1202, 1204, 1206 to one of the D-type flip-flops in each corresponding pair of D-type flip-flops 1210a, 1210b, 1210c. Thus, each pair of D-type flip-flops 1210a, 1210b, 1210c generates a pulse in response to rising and falling edges detected in the corresponding differential signal 1202, 1204, 1206.

[0063]

[0086] For example, the AB differential signal 1202 is provided to a first D-type flip-flop 1232 of the first pair of D-type flip-flops 1210a, and an inverter 1208a provides an inverted version of the AB differential signal 1202 to a second D-type flip-flop 1234 of the first pair of D-type flip-flops 1210a. The D-type flip-flops are initially in a reset state. A rising edge on the AB differential signal 1202 clocks a logic one through the first D-type flip-flop 1232, transitioning the output of the first flip-flop (r_AB) 1230a to a logic one state. A falling edge on the AB differential signal 1202 clocks a logic one through the second D-type flip-flop 1234, transitioning the output of the second flip-flop (f_AB) 1230b to a logic one state.

[0064]

[0087] The output signals 1230a-1230f are provided to logic, such as an OR gate 1212, which generates an output signal that may serve as a receiver clock (RxCLK) signal 1222. The RxCLK signal 1222 transitions to a logic 1 state when a transition occurs in the signaling state of any of the differential signals 1202, 1204, 1206. The RxCLK signal 1222 is provided to a programmable delay circuit 1214, which drives a reset signal (rb signal 1228) that resets the D-type flip-flops in the pair of D-type flip-flops 1210a, 1210b, 1210c. In the illustrated example, an inverter 1216 may be included when the D-type flip-flops 1210a, 1210b, 1210c are reset by a low signal. When the D-type flip-flops 1210a, 1210b, 1210c are reset, the output of the OR gate 1212 returns to a logic 0 state and the pulse on the RxCLK signal 1222 is terminated. When this logic 0 state propagates through the programmable delay circuit 1214 and the inverter 1216, the reset condition on the D-type flip-flops 1210a, 1210b, 1210c is released. While the D-type flip-flops 1210a, 1210b, 1210c are in the reset condition, transitions on the differential signals 1202, 1204, 1206 are ignored.

[0065]

[0088] The programmable delay circuit 1214 is generally configured to generate a delay having a duration that exceeds the difference in timing skew between the occurrence of the first transition and the occurrence of the last transition on the differential signals 1202, 1204, 1206. The programmable delay circuit 1214 configures the duration (i.e., pulse width) of a pulse on the RxCLK signal 1222. The programmable delay circuit 1214 may be configured when a set signal 1226 is asserted by a processor or other control and / or configuration logic.

[0066]

[0089] The RxCLK signal 1222 may also be provided to a set of three flip-flops 1220 that capture the signaling states of the differential signals 1202, 1204, 1206 and provide a stable output symbol 1224 for each pulse occurring on the RxCLK signal 1222. The delay or alignment logic 1218 may adjust the timing of the set of differential signals 1202, 1204, 1206. For example, the delay or alignment logic 1218 may be used to adjust the timing of the differential signals 1202, 1204, 1206 relative to the pulses on the RxCLK signal 1222 to ensure that the flip-flops 1220 capture the signaling states of the differential signals 1202, 1204, 1206 when the differential signals 1202, 1204, 1206 are stable. The delay or matching logic 1218 may delay edges in the differential signals 1202 , 1204 , 1206 based on the delay configured for the programmable delay circuit 1214 .

[0067]

[0090] The programmable delay circuit 1214 may be configured in the CDR circuit 1200 to accommodate possible large variations in transition times in the differential signals 1202, 1204, 1206. In one example, the programmable delay circuit 1214 is configured to provide a minimum delay period that generally exceeds the duration of the timing skew between the occurrence of the first transition and the occurrence of the last transition on the differential signals 1202, 1204, 1206. The delay time provided by the programmable delay circuit 1214 is calculated to account for the number of logic gates in the delay loop of the CDR circuit 1200, and is constrained to a minimum delay time that accounts for expected or observed variations in the manufacturing process, circuit power supply voltage, and temperature (PVT) conditions that may affect the operation of the logic gates and / or the programmable delay circuit 1214. For reliable operation of the CDR circuit 1200, the maximum delay time provided by the programmable delay circuit 1214 may not be greater than a symbol interval. At faster data rates, the timing skew and delay time provided by the delay loop of the CDR circuit 1200 increases as a fraction of the symbol interval 1102. The eye opening 1106 may become small compared to the symbol interval 1102, and the eye opening 1106 may close at higher frequencies. The maximum symbol transmission rate may be limited when the delay time provided by the programmable delay circuit 1214 reduces the percentage of the symbol interval 1102 occupied by the eye opening 1106 below a threshold size that can support reliable capture of the symbols.

[0068]

[0091] FIG. 13 is a timing diagram 1300 illustrating some aspects of the operation of the CDR circuit 1200. The diagram relates to operation after the programmable delay circuit 1214 has been configured and the set signal 1226 is inactive. The CDR circuit 1200 operates as an edge detector. The C-PHY three-phase encoding provides a single signaling state transition per unit interval (UI) 1302. Differences in the state of each wire of a triplet and / or the transmission characteristics of the triplet can cause transitions to appear at different times on two or more wires. The maximum difference in time of occurrence of transitions in the differential signals 1202, 1204, 1206 is referred to as the skew time (t skew ) 1304. Another delay associated with the CDR circuit 1200 is the propagation delay (t ck2q ) 1314 and the propagation delay (t OR_0 ) 1306 and the propagation delay (t OR_1 ) 1308, which combines the delay provided by the programmable delay circuit 1214 and the driver and / or inverter 1216. pgm ) 1310 and a reset delay (t rst )1312.

[0069]

[0092] Loop delay (t loop 1320) can be defined as follows:

[0070]

number

[0071] t loopThe relationship between the programmable delay circuit 1214 and the UI 1302 may determine the reliability of the operation of the CDR circuit 1200. This relationship is affected by the clock frequency used for transmission and the variability in the operation of the programmable delay circuit 1214, which has a direct impact on the UI 1302.

[0072]

[0093] In some devices, the operation of the programmable delay circuit 1214 in FIG. 12 may suffer from variations in operating conditions, including variations in PVT conditions. The delay time provided by the programmable delay circuit 1214 about a configured value may vary significantly from device to device and / or from circuit to circuit within a device. In conventional systems, the nominal operating conditions of the CDR circuit 1200 are generally set by design to generate a clock edge somewhere in the middle of the eye opening 1106 under all PVT conditions to ensure that the clock edge occurs after the tail 1112 of the signal transition region 1104 and before the beginning of the transition region to the next symbol, even under worst-case PVT effects. When the transmission frequency increases and the timing skew of the differential signals 1202, 1204, 1206 is large compared to the UI 1302, difficulties may arise in designing the CDR circuit 1200 to guarantee a clock edge within the eye opening 1106. For example, a typical delay circuit may generate delay values ​​that vary by a factor of 2 across all PVT conditions.

[0073]

[0094] 14 is a timing diagram 1400 illustrating the effect of the programmable delay circuit 1214 (see FIG. 12) providing insufficient delay. In this example, t loop 1406 was observed t skew 1404, resulting in multiple clock pulses 1408, 1410 being generated within one UI 1402. loop 1406 is t skew1404 is not large enough to mask later occurring transitions on the differential signals 1202, 1204, 1206. In the illustrated example, a second transition 1414 in one of the differential signals 1206 may be detected after a pulse 1408 is generated in response to a first occurring transition 1412 in another one of the differential signals 1202. In this example, the recovered clock frequency may be twice the clock frequency used to transmit symbols on the three-phase interface.

[0074]

[0095] 15 is a timing diagram 1500 illustrating the effect of a programmable delay circuit 1214 providing too long a delay. In this example, the duration of the observed skew t skew There is 1504, t loop 1506 is greater than the UI 1502. The CDR circuit 1200 may generate a clock pulse 1508 in response to the first occurring transition 1514 in the first UI 1502, while the rb signal 1228 may be active when the transitions 1516, 1518 occur in the second UI 1512. In the illustrated example, the transitions 1516, 1518 in the second UI 1512 are masked and the expected pulse 1510 corresponding to the second UI 1512 is suppressed. In this example, the recovered clock frequency may be 1 / 2 the clock frequency used to transmit symbols on the three-phase interface.

[0075]

[0096] As illustrated by the examples of FIGS. 14 and 15, the CDR circuit 1200 may be subject to the following constraints.

[0076]

number

[0077] Empirical evidence shows that loop This suggests that the t loop 1320 can be rephrased as follows:

[0078]

number

[0079] The loop time is sensitive to PVT variations, which can affect reliability at higher symbol rates due to the large number of delays. pgm The delay, and the large delay associated with the six-input OR gate 1212, may limit the maximum frequency of the clock signal that can be restored by the CDR circuit 1200. Increasing the delay provided by the programmable delay circuit 1214 to accommodate the range of potential variations in the PVT serves to further limit the maximum frequency of the clock signal that can be restored by the CDR circuit 1200.

[0080]

[0097] More recent implementations and proposed specifications for C-PHY, including the C-PHY 1.2 and C-PHY 2.0 specifications, define a frequency of the symbol transmit clock signal that can exceed the capability of conventional CDR circuits to recover the clock signal at the receiver. The symbol transmit clock signal is used to control the rate of symbol transmission and determines the duration of the UI 1302. The duration of the UI 1302 is reduced when the frequency of the symbol transmit clock signal is increased. The constraints imposed by the loop delay in the CDR circuit 1200 limit the minimum duration of the UI 1302 that can be supported by the CDR circuit 1200, which limits the maximum frequency of the symbol transmit clock signal that can be supported by the CDR circuit 1200. Even with advanced device technology, the loop delay in the CDR circuit 1200 can exceed 300 picoseconds under some PVT conditions, which can limit conventional C-PHY applications to a maximum symbol transmission rate of 2.5 gigasymbols per second. In some implementations, constraints on the duration of the UI 1302 imposed by loop delays in the CDR circuit 1200 may render a conventional CDR circuit 1200 invalid for use in a C-PHY interface that should comply with later generations of the C-PHY specification.

[0081]

[0098] A clock recovery circuit implemented according to some aspects disclosed herein can support higher clock frequencies defined by later generation C-PHY specifications. FIG. 16 provides an example of a clock recovery circuit 1640 that may be configured according to some aspects of the present disclosure to support higher symbol transmission clock frequencies. The clock recovery circuit 1640 uses an optimized feedback loop that minimizes or reduces loop delays and allows the clock recovery circuit 1640 to generate a receive clock signal 1646 at a frequency of at least 8 GHz. The delay loop may be implemented using an asymmetric delay circuit that delays certain types of edges and passes other types of edges with minimal delay. In the illustrated example, the delay loop is implemented using a few logic gates and a PVT insensitive delay block that responds only to rising edges. The illustrated clock recovery circuit 1640 may be configured to optimize loop timing and support ultra-fast symbol transmission rates. A pulse generation and merging circuit 1600 generates and merges transition pulses that represent transitions detected in the differential signals 1602, 1604, 1606. FIG. 17 is a timing diagram 1700 illustrating the timing associated with the pulse generating and merging circuit 1600 and the clock recovery circuit 1640.

[0082]

[0099] The pulse generating and merging circuit 1600 receives differential signals 1602, 1604, 1606 that represent the difference between the signaling states of the pairs of wires of the triplet wires A, B, and C. The differential signals 1602, 1604, 1606 may be received from a differential receiver or comparator, such as differential receivers 802a, 802b, and 802c that generate differential signals 810a, 810b, 810c shown in Figure 8. The pulse generating and merging circuit 1600 uses three exclusive-OR gates 1608, 1610, 1612 and corresponding delay circuits 1616, 1618, and 1620 to generate limited-duration transition pulses 1704, 1706, 1708 in response to transitions occurring in the differential signals 1602, 1604, 1606. In the illustrated example of timing diagram 1700, transitions in the AB differential signal 1602, the BC differential signal 1604, and the CA differential signal 1606 occur at each of the illustrated symbol boundaries 1710a, 1710b, 1710c, 1710d. The transitions in the differential signals 1602, 1604, 1606 may occur at different times, and thus a skew 1702 may be observed between the first occurring transition and the last occurring transition. In the illustrated example, at the first illustrated symbol boundary 1710a, the first occurring transition is observed on the AB differential signal 1602, and the last occurring transition is observed on the CA differential signal 1606. The relationship between the transitions may be different at each symbol boundary 1710a, 1710b, 1710c, 1710d. During operation, a transition occurs on at least one differential signal 1602, 1604, 1606 at each symbol boundary 1710a, 1710b, 1710c, 1710d, and may occur on fewer than three differential signals 1602, 1604, 1606 at one or more symbol boundaries 1710a, 1710b, 1710c, 1710d.

[0083]

[0100] A first exclusive-OR gate 1608 receives the AB difference signal 1602 and a delayed version of the AB difference signal 1602 provided by an AB delay circuit 1616, and provides an AB_p signal 1622 that includes a transition pulse 1704 having a duration controlled by the duration of the delay provided by the AB delay circuit 1616. A second exclusive-OR gate 1610 receives the BC difference signal 1604 and a delayed version of the BC difference signal 1604 provided by a BC delay circuit 1618, and provides a BC_p signal 1624 that includes a transition pulse 1706 having a duration controlled by the duration of the delay provided by the BC delay circuit 1618. A third exclusive OR gate 1612 receives the CA difference signal 1606 and a delayed version of the CA difference signal 1606 provided by a CA delay circuit 1620 and provides a CA_p signal 1626 that includes a transition pulse 1708 having a duration controlled by the duration of the delay introduced by the CA delay circuit 1620. The AB_p signal 1622, the BC_p signal 1624 and the CA_p signal 1626 are provided to an OR gate 1614 which provides an eg_pulse signal 1630, sometimes referred to herein as a combined signal, that includes a pulse 1714 derived from and / or corresponding to the transition pulses 1704, 1706, 1708 in the AB_p signal 1622, the BC_p signal 1624 and the CA_p signal 1626. In some cases, two or more of the transition pulses 1704, 1706, 1708 may overlap in time and merge in a pulse 1714 of the combined signal.

[0084]

[0101] The eg_pulse signal 1630 clocks a delay flip-flop (DFF 1642) in the clock recovery circuit 1640. In some implementations, different types of flip-flops, latches, registers, or other sequential logic circuits may be configured for use as a replacement for DFF 1642. Each rising edge in the eg_pulse signal 1630 clocks a logic 1 from the D input to the output (Q) of DFF 1642. The output of DFF 1642 provides the receive clock signal 1646 (Rclk_q). The delay circuits 1616, 1618, and 1620 may be configured to provide transition pulses 1704, 1706, 1708 having a duration sufficient to clock DFF 1642 under expected or observed PVT conditions. For example, the duration of the transition pulses 1704, 1706, 1708 may be configured based on a minimum duration for a clock pulse. The receive clock signal 1646 transitions high from an initial state in which the receive clock signal 1646 is in a reset state (i.e., set to a logic 0 state). The receive clock signal 1646 transitions high in response to the first rising edge in the eg_pulse signal 1630 and after a delay caused by a gate propagation delay (clk_q 1716), which may correspond to the accumulated transition time of the OR gate 1614 and DFF 1642. The receive clock signal 1646 transitions high in response to the first rising edge in the eg_pulse signal 1630, and additional edges in the eg_pulse signal 1630 have no effect until DFF 1642 is reset.

[0085]

[0102] The DFF 1642 is reset when the output of the rising edge delay circuit 1644 (the Rclk_rst signal 1648) transitions high. The rising edge delay circuit 1644 is configured to pass a falling edge at its input with no delay or a minimum delay before causing the Rclk_rst signal 1648 to fall and to delay a rising edge at its input before causing the Rclk_rst signal 1648 to rise. In the illustrated example, the rising edge delay circuit 1644 receives the receive clock signal 1646 as its input and delays a rising edge in the receive clock signal 1646 by a selected delay duration (rise_dly 1718). The falling edge in the receive clock signal 1646 is delayed by a duration (fall_dly 1720) that may be attributable to transition times associated with the DFF 1642 and / or one or more logic gates in the rising edge delay circuit 1644. The rising edge delay circuit 1644 is one example of an asymmetric delay circuit. It should be appreciated that other types of asymmetric delay circuits may be used in various implementations, including, for example, a falling edge delay circuit.

[0086]

[0103] After the Rclk_rst signal 1648 rises, the output of the DFF 1642 is reset and the receive clock signal 1646 returns to logic 0 after a delay (rst_dly 1722) that may be due to gate transition time. The falling edge in the receive clock signal 1646 is delayed by the duration of fall_dly 1720 and the clock recovery circuit 1640 is returned to its initial state. In some implementations, the receive clock signal 1646 may be used to capture the differential signals 1602, 1604, 1606 and / or decode data from the differential signals 1602, 1604, 1606. In some implementations, a driver circuit 1652 is provided to buffer and / or delay the receive clock signal 1646 and provide a clock signal (RxCLK signal 1650) as an output of the clock recovery circuit 1640. The RxCLK signal 1650 may be used to capture and / or decode data from the differential signals 1602 , 1604 , 1606 .

[0087]

[0104] In one example, the data recovery circuit 1660 may include one or more latches, registers, or flip-flops 1664 that receive the RxCLK signal 1650. The latches, registers, or flip-flops 1664 may be configured to capture the signaling states of the differential signals 1602, 1604, 1606 and provide a stable output symbol 1670 for each pulse occurring on the RxCLK signal 1650. A delay or alignment logic 1662 may adjust the timing of the differential signals 1602, 1604, 1606. For example, the delay or alignment logic 1662 may be used to adjust the timing of the differential signals 1602, 1604, 1606 relative to the pulses on the RxCLK signal 1650 to ensure that the latches, registers, or flip-flops 1664 capture the signaling states of the differential signals 1602, 1604, 1606 when the differential signals 1602, 1604, 1606 are stable. The delay or alignment logic 1662 may provide a relative delay or advance of the edges in the differential signals 1602 , 1604 , 1606 .

[0088]

[0105] The maximum operating frequency of the clock recovery circuit 1640 and the corresponding minimum UI 1712 may be determined by timing constraints associated with the clock recovery circuit 1640 and the pulse generating and merging circuit 1600. The timing delays in the pulse generating and merging circuit 1600 are outside the timing loop of the clock recovery circuit 1640. The timing constraints may be stated as follows:

[0089]

number

[0090] The clk_q 1716, rst_dly 1722 and fall_dly 1720 parameters may be quantified as a small number of gating switching delays, and the rise_dly 1718 duration may be selected based on the skew time under expected PVT conditions with small gating switching delays due to the clk_q 1716.

[0091]

[0106] According to some aspects disclosed herein, the rising edge delay circuit 1644 and the delay circuits 1616, 1618, and 1620 may be configured during manufacturing, system configuration, and / or system initialization. In some implementations, the rising edge delay circuit 1644 and / or each of the delay circuits 1616, 1618, and 1620 may be programmable and dynamically reconfigured and / or calibrated during bus operation, for example, using initial line synchronization signaling transmitted over the C-PHY bus. The delay circuits 1616, 1618, and 1620 may be calibrated based on measured, observed, and / or expected operating conditions. A controller or processor may obtain a desired or required symbol transmission rate by optimizing the duration of rise_dly 1718 and / or the delay provided by the delay circuits 1616, 1618, and 1620 for PVT conditions.

[0092]

[0107] FIG. 18 illustrates an example of a rising edge delay circuit 1800 that may be used to delay a rising edge by a configured or configurable delay duration while passing a falling edge without added delay, according to some aspects disclosed herein. Other types of circuits may be employed to delay a rising edge while passing a falling edge without added delay. The illustrated rising edge delay circuit 1800 may be implemented using a set of unit delay elements 1804, where different delay paths 1806 include different numbers of unit delay elements 1804 concatenated to obtain selectable delay durations. In some instances, the different delay paths 1806 may be provided using a single multi-tap delay path. A signal received at an input 1802 of the rising edge delay circuit 1800 is routed through one or more delay paths 1806 under the control of a selection circuit 1808, which selects a signal output by one of the delay paths 1806 to drive an output 1812 of the selection circuit 1808. In one example, the selection circuit 1808 is implemented using a multiplexer. In another example, the selection circuit 1808 is implemented using a set of switches that direct the signal received at the input 1802 to the delay paths 1806 or use the signal that has traversed one of the delay paths 1806 to drive the output 1812 of the selection circuit 1808. The rising edge delay circuit 1800 may be configured by providing a selection signal 1814 to the selection circuit 1808, where the selection signal 1814 determines which of the delay paths 1806 drives the output 1812 of the selection circuit 1808.

[0093]

[0108] The output 1812 of the selection circuit 1808 is gated by the input 1802 of the rising edge delay circuit 1800 using an AND gate 1810. The AND gate 1810 drives the output 1816 of the rising edge delay circuit 1800. A low logic level at the input 1802 of the rising edge delay circuit 1800 forces the output 1816 of the rising edge delay circuit 1800 to a low logic level. A rising edge at the input 1802 of the rising edge delay circuit 1800 occurs when the input 1802 transitions from a low logic level to a high logic level. When the input 1802 is at a high logic level, the output 1816 of the rising edge delay circuit 1800 is controlled by the output 1812 of the selection circuit 1808. The output 1812 of the selection circuit 1808 is initially in a low logic state and remains low until a delayed version of the rising edge at the input 1802 of the rising edge delay circuit 1800 exits the selected delay path 1806, causing the output 1812 of the selection circuit 1808 to transition high. A falling edge at the input 1802 occurs when the input 1802 transitions from a high logic level to a low logic level. The low logic level at the input 1802 of the rising edge delay circuit 1800, which is coupled to the input of the AND gate 1810, forces the output 1816 of the rising edge delay circuit 1800 back to a low logic level.

[0094]

[0109] Other implementations of the rising edge delay circuit 1800 are contemplated. In some implementations, the AND gate 1810 may be omitted when each of the unit delay elements 1804 is implemented as a resettable delay element. In some implementations, each delay element in the rising edge delay circuit 1800 may be reset by a low logic level on the input 1802 of the rising edge delay circuit 1800, so that a falling edge is propagated immediately through the delay path 1806 (with a small delay due to the switching time of one or more logic gates) and a rising edge is propagated through each delay element in each delay path 1806. In another example, the type of selection circuit 1808 may be configured to obtain additional or minimal delay. Example Processing Circuits and Methods

[0110] 19 illustrates an example of a hardware implementation for an apparatus 1900 employing a processing circuit 1902 that may be configured to perform one or more functions disclosed herein. According to various aspects of the disclosure, the elements disclosed herein, or any portion of the elements, or any combination of the elements, may be implemented using the processing circuit 1902. The processing circuit 1902 may include a number of devices, circuits, and / or logic that support the clock recovery techniques disclosed herein.

[0095]

[0111] The processing circuit 1902 may include one or more processors 1904 controlled by some combination of hardware and software modules. Examples of the processor 1904 include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gate logic, discrete hardware circuits, and other suitable hardware configured to perform various functions described throughout this disclosure. The one or more processors 1904 may include special-purpose processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1916. The one or more processors 1904 may be configured through a combination of software modules 1916 loaded during initialization and may be further configured by loading or unloading one or more software modules 1916 during operation.

[0096]

[0112] In the depicted example, the processing circuit 1902 may be implemented with a bus architecture, represented diagrammatically by a bus 1910. The bus 1910 may include any number of interconnected buses and bridges, depending on the particular application and overall design constraints of the processing circuit 1902. In one example, the bus 1910 links together various circuits, including one or more processors 1904 and a processor-readable storage medium 1906. The processor-readable storage medium 1906 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. The bus 1910 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. The bus interface 1908 may provide an interface between the bus 1910 and one or more transceivers 1912. A transceiver 1912 may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in the transceiver 1912. Each transceiver 1912 provides a means for communicating with various other devices over a transmission medium. Depending on the nature of the device 1900, a user interface 1918 (e.g., keypad, display, speaker, microphone, joystick) may also be provided and may be communicatively coupled to the bus 1910 either directly or through the bus interface 1908.

[0097]

[0113] The processor 1904 may be responsible for managing the bus 1910 and for general processing, which may include executing software stored on a computer-readable medium, which may include a processor-readable storage medium 1906. In this regard, the processing circuitry 1902, including the processor 1904, may be used to implement any of the methods, functions, and techniques disclosed herein. The processor-readable storage medium 1906 may be used to store data that is manipulated by the processor 1904 when executing software, which may be configured to implement any one of the methods disclosed herein.

[0098]

[0114] One or more processors 1904 in the processing circuit 1902 may execute software. Software should be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the processor-readable storage medium 1906 or in another external processor-readable medium. The processor-readable storage medium 1906 may include a non-transitory computer-readable storage medium and / or a transitory processor-readable storage medium. The non-transitory processor-readable storage medium includes, by way of example, a magnetic storage device (e.g., a hard disk, a floppy disk, a magnetic strip), an optical disk (e.g., a compact disk (CD) or a digital versatile disk (DVD)), a smart card, a flash memory device (e.g., a "flash drive", a card, a stick, or a key drive), a random access memory (RAM), a ROM, a PROM, an erasable PROM (EPROM), an EEPROM, a register, a removable disk, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. The processor-readable storage medium 1906 may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. The processor-readable storage medium 1906 may be present in the processing circuitry 1902 in the processor 1904, external to the processing circuitry 1902, or distributed across multiple entities including the processing circuitry 1902. The processor-readable storage medium 1906 may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials.Those skilled in the art will recognize how to best implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0099]

[0115] The processor-readable storage medium 1906 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, etc., sometimes referred to herein as software modules 1916. Each of the software modules 1916 may include instructions and data that, when installed or loaded onto the processing circuitry 1902 and executed by one or more processors 1904, contribute to a runtime image 1914 that controls the operation of the one or more processors 1904. When executed, some instructions may cause the processing circuitry 1902 to perform functions in accordance with some methods, algorithms, and processes described herein.

[0100]

[0116] Some of the software modules 1916 may be loaded during initialization of the processing circuit 1902, and these software modules 1916 may configure the processing circuit 1902 to enable performance of various functions disclosed herein. For example, some software modules 1916 may configure the internal devices and / or logic circuits 1922 of the processor 1904 and may manage access to external devices, such as the transceiver 1912, the bus interface 1908, the user interface 1918, timers, mathematical co-processors, etc. The software modules 1916 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 1902. The resources may include memory, processing time, access to the transceiver 1912, the user interface 1918, etc.

[0101]

[0117] The one or more processors 1904 of the processing circuit 1902 may be multifunctional, whereby some of the software modules 1916 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1904 may be further adapted to manage background tasks initiated in response to inputs from, for example, the user interface 1918, the transceiver 1912, and device drivers. To support the performance of multiple functions, the one or more processors 1904 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks serviced by the one or more processors 1904 as needed or desired. In one example, the multitasking environment may be implemented using a time-sharing program 1920 that passes control of the processor 1904 between different tasks, whereby each task returns control of the one or more processors 1904 to the time-sharing program 1920 upon completion of outstanding operations and / or in response to inputs such as interrupts. When a task has control of one or more processors 1904, the processing circuitry is effectively dedicated to the purpose addressed by the function associated with the controlling task. The time-sharing program 1920 may include an operating system, a main loop that transfers control on a round-robin basis, a function that allocates control of one or more processors 1904 according to a prioritization of functions, and / or an interrupt-driven main loop that responds to external events by granting control of one or more processors 1904 to a processing function.

[0102]

[0118] The apparatus 1900 may be adapted, configured, and / or operated according to several aspects of the disclosure. In a first implementation, the resulting clock recovery apparatus may include a plurality of pulse generating circuits 1628 (see FIG. 16), where each pulse generating circuit is configured to generate a transition pulse in response to a transition in a differential signal representing a difference in the signaling states of a pair of wires in the three-wire bus. In the first implementation, the clock recovery apparatus may include a first logic circuit configured to provide a combined signal including a pulse corresponding to the transition pulse received from the plurality of pulse generating circuits 1628, and a second logic circuit responsive to the pulse in the combined signal and configured to output a clock signal used to decode information from the transition in the signaling state of the three-wire bus, where the pulse in the combined signal causes the clock signal to be driven to the first state. The second logic circuit may be implemented using a flip-flop (such as a delay flip-flop), a latch, a register, or other sequential logic circuit. In a first implementation, the clock recovery apparatus may include an asymmetric delay circuit configured to generate a reset signal from a clock signal, where the reset signal is generated by delaying a transition to a first state and passing a transition from the first state without an added delay, where the clock signal is driven from the first state after a transition of the clock signal to the first state has been passed by the asymmetric delay circuit.

[0103]

[0119] In a second implementation, each of the plurality of pulse generating circuits 1628 of the clock recovery device of the first implementation includes an exclusive-OR gate configured to receive as inputs an associated differential signal and a delayed version of the associated differential signal. In a third implementation, the first logic circuit of the second implementation includes a logic gate configured to provide a combined signal by combining output signals received from the exclusive-OR gates in each pulse generating circuit. In a fourth implementation, each of the plurality of pulse generating circuits 1628 of the second or third implementation is configured to generate a transition pulse having a duration configured based on a minimum clock pulse duration defined for the second logic circuit. In a fifth implementation, the duration of the pulse generated by each of the plurality of pulse generating circuits 1628 of the second, third, or fourth implementation is configurable.

[0104]

[0120] In a sixth implementation, a duration of the delay applied by the asymmetric delay circuit of the first, second, third, fourth, or fifth implementation to a transition to the first state is configurable. In a seventh implementation, the asymmetric delay circuit of the first, second, third, fourth, fifth, or sixth implementation includes a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without added delay. In an eighth implementation, the clock recovery device of the first, second, third, fourth, fifth, sixth, or seventh implementation includes a wire state decoder configured to decode a symbol from a transition in a signaling state of the three-wire bus based on timing information provided in the clock signal.

[0105]

[0121] The processing circuit 1902 may be configured to perform at least some of the methods disclosed herein. In a first example, a clock recovery method includes generating a combined signal including a pulse corresponding to a transition pulse generated in response to a transition in a differential signal representing a difference in the signaling states of a pair of wires in a three-wire bus, providing the combined signal to a logic circuit configured to provide a clock signal as an output thereof, where the pulse in the combined signal causes the clock signal to be driven to a first state, providing a reset signal to the logic circuit, where the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without an added delay, where the clock signal is driven from the first state after the transition of the clock signal to the first state is passed by the asymmetric delay circuit. The logic circuit may be implemented using flip-flops (such as delay flip-flops), latches, registers, or other sequential logic circuits.

[0106]

[0122] In a second example, the clock recovery method of the first example includes generating a transition pulse for the first differential signal by performing an exclusive OR gate function on the first differential signal and a delayed version of the first differential signal. In a third example, the clock recovery method of the first example or the second example includes configuring at least one pulse generating circuit to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for the logic circuit. In a fourth example, the clock recovery method of the first example, the second example or the third example includes calibrating the at least one pulse generating circuit based on an operating condition of the three-wire bus. In a fifth example, the clock recovery method of the first example, the second example, the third example or the fourth example includes configuring an asymmetric delay circuit to select a duration of a delay applied to a transition to a first state. In a sixth example, the asymmetric delay circuit of the first example, the second example, the third example, the fourth example or the fifth example includes a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without added delay. In a seventh example, the clock recovery method of the first example, the second example, the third example, the fourth example, the fifth example or the sixth example includes providing a clock signal to a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal.

[0107]

[0123] FIG. 20 is a flowchart 2000 of a clock recovery method that may be implemented in a receiving device coupled to a 3-wire C-PHY interface. In block 2002, the receiving device may generate a combined signal including a pulse corresponding to a transition pulse generated in response to a transition in a differential signal representing a difference in the signaling states of pairs of wires in the 3-wire bus. In block 2004, the receiving device may provide the combined signal to a logic circuit configured to provide a clock signal as its output. The logic circuit may be implemented using flip-flops (such as delay flip-flops), latches, registers or other sequential logic circuits. The pulse in the combined signal causes the clock signal to be driven to a first state. In block 2006, the receiving device may provide a reset signal to the logic circuit. The reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without an added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

[0108]

[0124] The receiving device may generate a transition pulse for the first differential signal by performing an exclusive OR gate function on the first differential signal and a delayed version of the first differential signal. The receiving device may configure at least one pulse generating circuit to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for the logic circuit. The receiving device may calibrate the at least one pulse generating circuit based on an operating condition of the three-wire bus. The receiving device may configure an asymmetric delay circuit to provide a desired duration of the delay applied to the transition to the first state. In one example, the asymmetric delay circuit is implemented as a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state. The rising edge delay circuit may be further configured to pass a transition from a high logic state to a low logic state without an added delay.

[0109]

[0125] In various implementations, the clock signal may be provided to a wire state decoder configured to decode symbols from transitions in the signaling states of the three-wire bus based on timing information provided in the clock signal.

[0110]

[0126] FIG. 21 illustrates an example of a hardware implementation for an apparatus 2100 employing a processing circuit 2102. The processing circuit 2102 has at least one processor 2116, which may generally include one or more of a microprocessor, a microcontroller, a digital signal processor, a sequencer, and a state machine. The processing circuit 2102 may be implemented using a bus architecture, represented generally by a bus 2120. The bus 2120 may include any number of interconnected buses and bridges, depending on the particular application and overall design constraints of the processing circuit 2102. The bus 2120 links together various circuits, including one or more processors and / or hardware modules, represented by the processor 2116, modules or circuits 2104, 2106 and 2108, a differential receiver circuit 2112 that generates a differential signal 2122 representing the difference in signaling states between different pairs of connectors or wires 2114, and a processor-readable storage medium 2118. The bus 2120 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0111]

[0127] The processor 2116 is responsible for general processing, including the execution of software stored in the processor-readable storage medium 2118. The software, when executed by the processor 2116, causes the processing circuit 2102 to perform various functions described above for a particular apparatus. The processor-readable storage medium 2118 may also be used to store data that is manipulated by the processor 2116 when executing the software, including data decoded from symbols transmitted over the connectors or wires 2114, which may be configured as a C-PHY bus. The processing circuit 2102 further includes at least one of modules 2104, 2106, and 2108. The modules 2104, 2106, and 2108 may be software modules that operate in the processor 2116, residing / stored in the processor-readable storage medium 2118, one or more hardware modules coupled to the processor 2116, or some combination thereof. Modules 2104, 2106 and / or 2108 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0112]

[0128] In one configuration, the apparatus 2100 may be configured for data communication according to a C-PHY interface protocol. The apparatus 2100 may include a module and / or circuit 2108 configured to generate transition pulses in response to transitions in the signaling states of the differential signal 2122, a module and / or circuit 2106 configured to generate a clock signal usable to decode symbols from transitions in the signaling states of the three-wire bus, and a configuration module and / or circuit 2104 for configuring delay durations used in generating the transition pulses and / or receive clocks.

[0113]

[0129] In one example, the device 2100 has a plurality of pulse generating circuits 1628 (see FIG. 16), one or more combinational logic circuits, and a clock recovery circuit. Each of the pulse generating circuits 1628 is configured to generate a transition pulse in response to a transition in a differential signal 2122 representing a difference between the signaling states of a pair of wires in a three-wire bus. One combinational logic circuit is configured to provide a combined signal including a pulse corresponding to the transition pulses received from the plurality of pulse generating circuits 1628. In one example, the three difference signals 2122 are combined using a logic OR gate such that a high logic level of a transition pulse in any of the difference signals 2122 causes a high logic level in the combined signal, where the state of the combined signal returns to a low logic level when the three difference signals 2122 are at a low logic level. The clock recovery circuit may be implemented using a flip-flop (such as a delay flip-flop), a latch, a register, or other sequential logic circuit. The clock recovery circuit may be responsive to a pulse in the combination signal and configured to output a clock signal used to decode information from a transition in the signaling state of the three-wire bus. The pulse in the combination signal causes the clock signal to be driven to a first state. The clock recovery circuit may include an asymmetric delay circuit configured to generate a reset signal from the clock signal. The reset signal is generated by delaying a transition to the first state and passing a transition from the first state without an added delay. The clock signal is driven from the first state after the transition of the clock signal to the first state has been passed by the asymmetric delay circuit.

[0114]

[0130] Each pulse generating circuit includes an exclusive-OR gate configured to receive as inputs an associated differential signal and a delayed version of the associated differential signal. The combinational logic circuit may include a logic gate configured to provide a combination signal by combining the output signals received from the exclusive-OR gate of each pulse generating circuit. Each pulse generating circuit is configured to generate a pulse with a duration configured based on a minimum clock pulse duration defined for the clock recovery circuit. The duration of the pulse generated by the delay circuits 1616, 1618, 1620 in each of the plurality of pulse generating circuits 1628 may be configurable. The duration of the delay applied by the asymmetric delay circuit to the transition to the first state may be configurable.

[0115]

[0131] In one example, the asymmetric delay circuit is implemented as a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without added delay. In one example, the apparatus 2100 includes a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in a clock signal.

[0116]

[0132] The processor-readable storage medium 2118 may be a non-transitory storage medium and may store instructions and / or code that, when executed by the processor 2116, cause the processing circuit 2102 to generate a combination signal including one or more transition pulses, where each transition pulse is generated in response to a transition in a differential signal 2122 representing a difference in the signaling states of a pair of wires in the three-wire bus. The instructions and / or code cause the processing circuit 2102 to provide the combination signal to a logic circuit, the logic circuit configured to provide a clock signal as its output, where a pulse in the combination signal causes the clock signal to be driven to a first state. The logic circuit may be implemented using flip-flops (such as delay flip-flops), latches, registers, or other sequential logic circuits. The instructions and / or code cause the processing circuit 2102 to provide a reset signal to the logic circuit, where the reset signal is derived from the clock signal by delaying a transition to a first state and passing a transition from the first state without an added delay, and the clock signal is driven from the first state after passing a transition of the clock signal to the first state.

[0117]

[0133] The instructions and / or code may cause the processing circuit 2102 to generate a transition pulse for the first differential signal by performing an exclusive OR gate function on the first differential signal and a delayed version of the first differential signal. The instructions and / or code may cause the processing circuit 2102 to configure at least one pulse generating circuit to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for the logic circuit. The instructions and / or code may cause the processing circuit 2102 to calibrate the at least one pulse generating circuit based on an operating condition of the three-wire bus. The instructions and / or code may cause the processing circuit 2102 to configure an asymmetric delay circuit to provide a desired duration of the delay applied to the transition to the first state. The asymmetric delay circuit may be implemented using a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from a high logic state to a low logic state without an added delay. The instructions and / or code may cause the processing circuit 2102 to provide a clock signal to a wire state decoder configured to decode symbols from transitions in the signaling states of the three-wire bus based on timing information provided in the clock signal.

[0118]

[0134] It is understood that the specific order or hierarchy of steps in the processes disclosed is an example of an example approach. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Additionally, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in an example order, and are not limited to the specific order or hierarchy presented. The above description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects set forth herein, but are to be accorded the widest scope consistent with claim language, where reference to an element in the singular does not mean "one and only," unless expressly stated as such, but rather means "one or more." Unless expressly stated otherwise, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various embodiments described throughout this disclosure that are known or later become known to those skilled in the art are expressly incorporated herein by reference and are encompassed by the claims. Moreover, nothing disclosed herein is made publicly available, regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase "means for."

Claims

1. 1. A clock recovery device comprising: a plurality of pulse generating circuits, each pulse generating circuit configured to generate a transition pulse in response to a transition in a differential signal representing a difference in the signaling states of a pair of wires in the three-wire bus; a first logic circuit configured to provide a combined signal including pulses corresponding to the transition pulses received from the plurality of pulse generating circuits; a second logic circuit responsive to a pulse in the combined signal and configured to output a clock signal used to decode information from the three-wire bus, where the pulse in the combined signal causes the clock signal to be driven to a first state; an asymmetric delay circuit configured to generate a reset signal from the clock signal, wherein the reset signal is generated by delaying a transition to the first state and passing a transition from the first state without additional delay, and the clock signal is driven from the first state after a transition of the clock signal to the first state has been passed by the asymmetric delay circuit; A clock recovery device comprising:

2. Each of the plurality of pulse generating circuits an exclusive-OR gate configured to receive as inputs an associated difference signal and a delayed version of said associated difference signal; 2. The clock recovery device of claim 1, comprising:

3. The first logic circuit comprises: a logic gate configured to provide said combined signal by combining output signals received from said exclusive-OR gates in each pulse generating circuit; 3. The clock recovery device of claim 2, comprising:

4. 3. The clock recovery apparatus of claim 2, wherein each of the plurality of pulse generating circuits is configured to generate a transition pulse having a duration configured based on a minimum clock pulse duration defined for the second logic circuit.

5. 3. The clock recovery apparatus of claim 2, wherein the duration of the pulses generated by each of the plurality of pulse generating circuits is configurable.

6. 2. The clock recovery apparatus of claim 1, wherein a duration of the delay applied by the asymmetric delay circuit to the transition to the first state is configurable.

7. 2. The clock recovery apparatus of claim 1, wherein the asymmetric delay circuit comprises a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from the high logic state to the low logic state without additional delay.

8. a wire state decoder configured to decode symbols from transitions in the signaling states of the three-wire bus based on timing information provided in the clock signal; The clock recovery device of claim 1 further comprising:

9. 1. A clock recovery method comprising: generating a combination signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in signaling states of pairs of wires in the three-wire bus; providing the combined signal to a logic circuit configured to provide a clock signal as an output, wherein a pulse in the combined signal causes the clock signal to be driven to a first state; providing a reset signal to the logic circuit, wherein the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without additional delay, and the clock signal is driven from the first state after passing a transition of the clock signal to the first state; A clock recovery method comprising:

10. generating a transition pulse for the first differential signal by performing an exclusive-OR gate function on a first differential signal and a delayed version of the first differential signal; The clock recovery method of claim 9 further comprising:

11. 10. The method of claim 9, further comprising: configuring at least one pulse generating circuit to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for the logic circuit.

12. calibrating at least one pulse generating circuit based on an operating condition of the three-wire bus; The clock recovery method of claim 9 further comprising:

13. configuring an asymmetric delay circuit to select a duration of a delay applied to a transition to said first state; The clock recovery method of claim 9 further comprising:

14. 14. The clock recovery method of claim 13, wherein the asymmetric delay circuit comprises a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from the high logic state to the low logic state without additional delay.

15. providing said clock signal to a wire state decoder configured to decode symbols from transitions in signaling states of said three-wire bus based on timing information provided in said clock signal; The clock recovery method of claim 9 further comprising:

16. A non-transitory processor-readable storage medium having one or more instructions that, when executed by at least one processor of a processing circuit in a receiver, cause the at least one processor to: generating a combination signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in signaling states of pairs of wires in the three-wire bus; providing the combined signal to a logic circuit, the logic circuit configured to provide a clock signal as an output thereof, wherein a pulse in the combined signal causes the clock signal to be driven to a first state; providing a reset signal to the logic circuit, wherein the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without additional delay, and the clock signal is driven from the first state after passing a transition of the clock signal to the first state; A non-transitory processor-readable storage medium that causes

17. The at least one processor, generating a transition pulse for the first differential signal by performing an exclusive-OR gate function on a first differential signal and a delayed version of the first differential signal; The storage medium of claim 16 , further comprising instructions to:

18. The at least one processor, configuring at least one pulse generating circuit to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for said logic circuit; The storage medium of claim 16 , further comprising instructions to:

19. The at least one processor, calibrating at least one pulse generating circuit based on an operating condition of the three-wire bus; The storage medium of claim 16 , further comprising instructions to:

20. The at least one processor, configuring an asymmetric delay circuit to select a duration of a delay applied to a transition to said first state; The storage medium of claim 16 , further comprising instructions to:

21. 21. The storage medium of claim 20, wherein the asymmetric delay circuit comprises a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from the high logic state to the low logic state without additional delay.

22. The at least one processor, providing said clock signal to a wire state decoder configured to decode symbols from transitions in signaling states of said three-wire bus based on timing information provided in said clock signal; The storage medium of claim 16 , further comprising instructions to:

23. 1. A clock recovery device comprising: means for generating a combination signal including pulses corresponding to transition pulses generated in response to transitions in a differential signal representing differences in the signaling states of pairs of wires in the three-wire bus; a means for providing a clock signal, the logic circuit being responsive to a pulse in the combined signal, wherein the pulse in the combined signal causes the clock signal to be driven to a first state; means for providing a reset signal to the logic circuit, wherein the reset signal is derived from the clock signal by delaying a transition to the first state and passing a transition from the first state without additional delay, and the clock signal is driven from the first state after passing a transition of the clock signal to the first state; A clock recovery device comprising:

24. 24. The clock recovery apparatus of claim 23, further comprising: means for generating the one or more transition pulses, each transition pulse being generated using a corresponding differential signal and a delayed version of the corresponding differential signal.

25. 24. The clock recovery apparatus of claim 23, wherein at least one pulse generating circuit is configured to provide a corresponding transition pulse having a duration based on a minimum clock pulse duration defined for the logic circuit.

26. 24. The clock recovery apparatus of claim 23, wherein one or more pulse generation circuits are calibrated based on operating conditions of the three-wire bus.

27. 24. The clock recovery apparatus of claim 23, wherein the means for providing the reset signal is configurable to select a duration of a delay applied to the transition to the first state.

28. 28. The clock recovery apparatus of claim 27, wherein the means for providing the reset signal comprises a rising edge delay circuit configured to delay a transition from a low logic state to a high logic state and further configured to pass a transition from the high logic state to the low logic state without additional delay.

29. 24. The clock recovery apparatus of claim 23, wherein the clock signal is provided to a wire state decoder configured to decode symbols from transitions in signaling states of the three-wire bus based on timing information provided in the clock signal.

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