Simulation method, program, and storage medium

Abstract

To improve accuracy while minimizing an increase in cost.SOLUTION: A simulation method according to an embodiment comprises correcting a layout of a laminated structure based on the shape of the laminated structure, deriving a first feature quantity of the corrected layout, and simulating a polishing step for the corrected layout on the basis of the first feature quantity.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The embodiments relate to a simulation method, a program, and a storage medium. [Background technology]

[0002] There is known a technique for simulating a manufacturing process of a semiconductor device. The simulation process makes it possible to predict the layout of a pattern in the manufacturing process of the semiconductor device. However, as the integration density of semiconductor devices increases, the cost required for the simulation process increases. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-103634 A Summary of the Invention [Problem to be solved by the invention]

[0004] Improve accuracy while suppressing increases in costs. [Means for solving the problem]

[0005] A simulation method of one embodiment includes correcting a layout of a laminated structure based on a shape of the laminated structure, calculating a first characteristic amount of the corrected layout, and simulating a polishing process for the corrected layout based on the first characteristic amount. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of a hardware configuration of a simulation device according to a first embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of a functional configuration of a simulation device according to a first embodiment. [Diagram 3]FIG. 2 is a view showing an example of a data structure of layout data stored in the simulation apparatus according to the first embodiment. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of a cross-sectional structure of a stacked structure corresponding to layout data stored in the simulation apparatus according to the first embodiment. [Diagram 5] 4 is a diagram showing an example of a rule table stored in the simulation device according to the first embodiment. [Figure 6] 5 is a flowchart showing an example of a simulation process involving a layout correction process in the simulation apparatus according to the first embodiment. [Figure 7] 4 is a cross-sectional view showing an example of a simulation process of a film formation process in the simulation apparatus according to the first embodiment. [Figure 8] 4 is a cross-sectional view showing an example of a layout correction process in the simulation apparatus according to the first embodiment. [Figure 9] 3 is a cross-sectional view showing an example of a simulation process of a polishing process in the simulation device according to the first embodiment. FIG. [Figure 10] 13 is a cross-sectional view showing an example of a cross-sectional structure of a laminated structure that is a target of a simulation process of a polishing process in the simulation device according to the second embodiment. FIG. [Figure 11] 13 is a diagram showing an example of a rule table stored in a simulation device according to a second embodiment. [Figure 12] 10 is a flowchart showing an example of a simulation process involving a layout correction process in the simulation apparatus according to the second embodiment. [Figure 13] 13 is a cross-sectional view showing a first example of a first layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. [Figure 14] 13 is a cross-sectional view showing a first example of a second layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. [Figure 15]13 is a cross-sectional view showing a first example of a third layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. [Figure 16] 13 is a cross-sectional view showing a second example of a first layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. FIG. [Figure 17] 13 is a cross-sectional view showing a second example of a second layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. FIG. [Figure 18] 13 is a cross-sectional view showing a second example of a third layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In the following description, components having the same functions and configurations are denoted by the same reference numerals.

[0008] 1. First embodiment 1.1 Configuration of the simulation device 1.1.1 Hardware Configuration Fig. 1 is a block diagram showing an example of a hardware configuration of the simulation device according to the first embodiment. As shown in Fig. 1, the simulation device 1 includes a control unit 11, a user interface 12, a storage 13, a drive 14, and a storage medium 15.

[0009] The simulation device 1 is an information processing device configured to execute a simulation process for predicting a three-dimensional shape of a stacked structure in a manufacturing process of a semiconductor device. The manufacturing process simulated by the simulation device includes, for example, a film formation process and a polishing process. The film formation process includes a film formation process by any film formation method, such as, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and sputtering. The polishing process includes, for example, chemical mechanical polishing (CMP). The simulation device 1 is configured to correct layout data of a pattern obtained by a simulation process of the film formation process. Then, the simulation device 1 is configured to execute a simulation process of the polishing process based on the corrected layout data.

[0010] The control unit 11 is a circuit that controls the overall components of the simulation device 1. The control unit 11 includes a CPU (Central Processing Unit), a RAM (Random Access Memory), and a ROM (Read Only Memory), etc. The ROM of the control unit 11 stores programs and the like used in various processes in the simulation device 1. The CPU of the control unit 11 controls the entire simulation device 1 in accordance with the programs stored in the ROM of the control unit 11. The RAM of the control unit 11 is used as a working area for the CPU of the control unit 11.

[0011] The user interface 12 is an interface that handles communication between the user and the control unit 11. The user interface 12 includes input devices and output devices. The input devices include, for example, a touch panel and an operation button. The output devices include, for example, an LCD (Liquid Crystal Display) or an EL (Electroluminescence) display. The user interface 12 converts input from the user into an electrical signal and then transmits it to the control unit 11. The user interface 12 outputs the results of various processes based on the input from the user to the user.

[0012] The storage 13 includes, for example, a hard disk drive (HDD) or a solid state drive (SSD). The storage 13 stores data used in various processes in the simulation device 1.

[0013] The drive 14 is a device for reading software stored in a storage medium 15. The drive 14 includes, for example, a CD (Compact Disk) drive, a DVD (Digital Versatile Disk) drive, and the like.

[0014] The storage medium 15 is a medium that stores software by electrical, magnetic, optical, mechanical, or chemical action. The storage medium 15 may store programs for executing various processes in the simulation device 1.

[0015] 1.1.2 Functional Configuration FIG. 2 is a block diagram illustrating an example of a functional configuration of the simulation apparatus according to the first embodiment. As shown in FIG.

[0016] 2, the CPU of the control unit 11 loads a program stored in the ROM of the control unit 11 or the storage medium 15 into the RAM of the control unit 11. Then, the CPU of the control unit 11 interprets and executes the program loaded into the RAM of the control unit 11. In this way, the simulation device 1 functions as a computer including a feature amount calculation unit 23, a bias amount calculation unit 24, a layout correction unit 25, a film formation process simulation unit 26, and a polishing process simulation unit 27. In addition, the simulation device 1 stores layout data 21 and a rule table 22.

[0017] The layout data 21 is data that indicates a two-dimensional layout of a laminated structure in a manufacturing process of a semiconductor device that is the subject of a simulation process.

[0018] Fig. 3 is a diagram showing an example of a data structure of layout data stored in the simulation device according to the first embodiment. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3, showing an example of a cross-sectional structure of a stacked structure corresponding to the layout data stored in the simulation device according to the first embodiment. As shown in Figs. 3 and 4, the layout data 21 is data corresponding to a two-dimensional distribution of a pattern P formed on a substrate 30 during the manufacture of a semiconductor device.

[0019] In the example of Fig. 3 and Fig. 4, nine rectangular patterns P1 to P9 are distributed on a substrate 30. Each of the patterns P1 to P9 is, for example, a transistor in the middle of manufacture. More specifically, each of the patterns P1 to P9 is a laminated structure of an insulating film 31 and a conductive film 32 formed on the substrate 30. Each of the patterns P1 to P9 is not limited to a transistor, and may be any laminated structure. In this case, the laminated structure forming each of the patterns P1 to P9 may be a plurality of films of different film types (for example, materials). The patterns P1 and P2 are provided in parallel with a space W12 in between. The patterns P2 and P3 are provided in parallel with a space W23 in between.

[0020] The pattern P in the layout data 21 is managed, for example, for each of a plurality of sub-regions R obtained by dividing an area on the substrate 30 in a matrix shape. Specifically, the pattern P1 distributed across four sub-regions R is managed for each of the four sub-regions R.

[0021] The feature amount calculation unit 23 is a functional block that calculates feature amounts related to the pattern P in the layout data 21 for each sub-region R. The feature amounts are parameters applied to the simulation processing of the film forming process and the simulation processing of the polishing process. The feature amounts include, for example, the area ratio, width, and perimeter of the pattern P in the sub-region R.

[0022] The area ratio is the ratio of the area of ​​the pattern P to the area of ​​the sub-region R. Specifically, for example, no pattern is formed in the sub-region R1. Therefore, the area ratio in the sub-region R1 is 0%. A part of the pattern P6 is formed over the entire sub-region R2. Therefore, the area ratio in the sub-region R2 is 100%.

[0023] The width is the length of the minor axis of the pattern P in the sub-region R. The perimeter is the length of the outer perimeter of the pattern P in the sub-region R. Specifically, for example, the width and perimeter of the sub-region R1 are both 0. The width and perimeter of the sub-region R2 are the length of the side of the sub-region R2 and the length of the outer perimeter of the sub-region R2, respectively.

[0024] The above-described feature amounts of the layout data 21 are updated in response to the execution of the simulation process of the film forming process and the simulation process of the polishing process.

[0025] The bias amount calculation unit 24 is a functional block that calculates the bias amount B. The bias amount B is a parameter that is applied to the layout correction process. The layout correction process is a process that corrects the layout data 21 that is applied to the simulation process of the polishing process prior to the execution of the simulation process of the polishing process. The bias amount calculation unit 24 calculates the bias amount B for each pair of two adjacent patterns P based on the rule table 22.

[0026] FIG. 5 is a diagram showing an example of a data structure of a rule table stored in the simulation device according to the first embodiment.

[0027] As shown in FIG. 5, the rule table 22 is data that defines the relationship between the space W between two adjacent patterns P and the bias amount B. In the example of FIG. 5, the relationship between the space W and the bias amount B is represented by a line La. According to the line La, when the space W is less than a value W0, the bias amount B increases linearly as the space W increases. Also, when the space W is equal to or greater than the value W0, the bias amount B becomes approximately constant at a value B0. Note that the rule table 22 shown in FIG. 5 is only an example, and the relationship between the space W and the bias amount B can be defined by a line of any shape other than the line La.

[0028] The layout correction unit 25 is a functional block that executes a layout correction process based on the bias amount B and corrects the layout data 21. Specifically, the layout correction unit 25 widens the width of each of two adjacent patterns P so that the space W between the two patterns P is narrowed in accordance with the corresponding bias amount B.

[0029] The film formation process simulation unit 26 is a functional block that executes a simulation process of the film formation process. The simulation process of the film formation process executed by the film formation process simulation unit 26 is a simple simulation process. Therefore, the shape of the pattern P is almost maintained before and after the simulation process of the film formation process executed by the film formation process simulation unit 26.

[0030] Polishing process simulation unit 27 is a functional block that executes a simulation process of the polishing process. The simulation process of the polishing process executed by polishing process simulation unit 27 is a simple simulation process. Therefore, the shape of pattern P is almost maintained before and after the simulation process of the polishing process executed by polishing process simulation unit 27.

[0031] 1.2 Simulation process with layout correction process A simulation process involving a layout correction process in the simulation apparatus according to the first embodiment will be described.

[0032] 1.2.1 Flowchart Fig. 6 is a flowchart showing an example of a simulation process involving a layout correction process in the simulation apparatus according to the first embodiment. Fig. 6 shows a series of processes in simulating the shape of a laminated structure in a case where a film forming process and a polishing process are performed in this order in a manufacturing process of a semiconductor device.

[0033] When an instruction to start a simulation process of a film formation process is received from a user (START), the feature amount calculation unit 23 calculates feature amounts related to the layout data 21 before the film formation process (S11). Specifically, the feature amount calculation unit 23 calculates parameters including an area ratio, a width, and a perimeter related to the pattern P in the layout data 21 for each sub-region R.

[0034] The film formation process simulation unit 26 executes a simulation process of the film formation process based on the feature amount calculated in the process of S11 (S12). As a result, a new film is formed on the pattern P in the layout data 21, thereby forming a new pattern P. After the process of S12, the layout data 21 is updated according to the pattern P after the film formation.

[0035] The bias amount calculation unit 24 calculates the bias amount B based on the layout data 21 updated in the process of S12 by referring to the rule table 22 (S13). Specifically, the bias amount calculation unit 24 calculates the bias amount B based on the space W between adjacent patterns P.

[0036] The layout correction unit 25 corrects the layout data 21 based on the bias amount B calculated in the process of S13 (S14). Specifically, the layout correction unit 25 widens the width of each of the two adjacent patterns P so that the space W between the two patterns P is narrowed in accordance with the bias amount B.

[0037] The feature amount calculation unit 23 calculates the feature amount for the layout data 21 corrected by the process of S14 (S15).

[0038] Polishing process simulation unit 27 executes a simulation process of the polishing process based on the feature amount calculated in the process of S15 (S16). This executes a simulation process of the polishing process based on pattern P taking into account bias amount B. After the process of S16, layout data 21 is updated according to pattern P after polishing.

[0039] When the process of S16 ends, the simulation process involving the layout correction process ends (END).

[0040] 1.2.2 Specific examples Next, a specific example of a simulation process involving a layout correction process in the simulation apparatus according to the first embodiment will be described.

[0041] Fig. 7 is a cross-sectional view showing an example of a simulation process of a film formation process in the simulation apparatus according to the first embodiment. Fig. 8 is a cross-sectional view showing an example of a layout correction process in the simulation apparatus according to the first embodiment. Fig. 9 is a cross-sectional view showing an example of a simulation process of a polishing process in the simulation apparatus according to the first embodiment. The cross-sectional views shown in Figs. 7, 8, and 9 correspond to cross-sectional views of a stacked structure after the process of S12, the process of S14, and the process of S16, respectively, when the process shown in Fig. 6 is performed on the cross-sectional view shown in Fig. 4.

[0042] First, the simulation process of the film formation process will be described.

[0043] 7, an insulating film 33 is provided over the entire surface by a simulation process of the film formation process. The insulating film 33 forms patterns P1-0, P2-0, and P3-0.

[0044] As described above, the shape of the pattern P is almost maintained before and after the simulation process of the film formation process. Therefore, the width of the insulator film 33 forming the pattern P1-0 is approximately equal to the width of the conductor film 32 below the insulator film 33 forming the pattern P1-0. The width of the insulator film 33 forming the pattern P2-0 is approximately equal to the width of the conductor film 32 below the insulator film 33 forming the pattern P2-0. The width of the insulator film 33 forming the pattern P3-0 is approximately equal to the width of the conductor film 32 below the insulator film 33 forming the pattern P3-0. The space W12-0 between the pattern P1-0 and the pattern P2-0 is approximately equal to the space W12 between the pattern P1 and the pattern P2. The space W23-0 between the pattern P2-0 and the pattern P3-0 is approximately equal to the space W23 between the pattern P2 and the pattern P3.

[0045] Next, the layout correction process will be described.

[0046] The bias amount calculation section 24 calculates the bias amount B12 based on the space W12-0. The bias amount calculation section 24 calculates the bias amount B23 based on the space W23-0.

[0047] 8, the layout correction unit 25 widens the width of the pattern P1-0 and the width of the pattern P2-0 so that the space W12-0 narrows according to the bias amount B12. Specifically, the layout correction unit 25 adds a virtual insulator film 34 having a width of the bias amount B12 to the sidewall of the insulator film 33 corresponding to the pattern P1-0 on the pattern P2-0 side, and adds a virtual insulator film 34 having a width of the bias amount B12 to the sidewall of the insulator film 33 corresponding to the pattern P2-0 on the pattern P1-0 side. In addition, the layout correction unit 25 widens the width of the pattern P2-0 and the width of the pattern P3-0 so that the space W23-0 narrows according to the bias amount B23. Specifically, the layout correction unit 25 adds a virtual insulator film 34 having a width of the bias amount B23 to the sidewall of the insulator film 33 corresponding to the pattern P2-0 on the pattern P3-0 side, and also adds a virtual insulator film 34 having a width of the bias amount B23 to the sidewall of the insulator film 33 corresponding to the pattern P3-0 on the pattern P2-0 side. The insulator film 34 is, for example, an insulator having the same characteristics as the insulator film 33.

[0048] As a result, the patterns P1-0, P2-0, and P3-0 are corrected to patterns P1-1, P2-1, and P3-1, respectively. The spaces W12-0 and W23-0 are corrected to spaces W12-1 and W23-1, respectively.

[0049] Next, the simulation process of the polishing process will be described.

[0050] 9, the simulation process of the polishing process removes the insulator film 33 and the insulator film 34 on the upper surface of the conductor film 32. Accordingly, a small amount of the insulator film 33 provided on the side of the conductor film 32 that is not protected by the insulator film 34 is also removed. As a result, the conductor film 32 and the insulator film 33 form patterns P1-2, P2-2, and P3-2.

[0051] As described above, the shape of the pattern P is almost maintained before and after the simulation process of the polishing process. Therefore, the width of the conductor film 32 and the insulator film 33 forming the pattern P1-2 is almost equal to the width of the conductor film 32 and the insulator film 34 forming the pattern P1-1. The width of the conductor film 32 and the insulator film 33 forming the pattern P2-2 is almost equal to the width of the conductor film 32 and the insulator film 34 forming the pattern P2-1. The width of the conductor film 32 and the insulator film 33 forming the pattern P3-2 is almost equal to the width of the conductor film 32 and the insulator film 34 forming the pattern P3-1. The space W12-2 between the pattern P1-2 and the pattern P2-2 is almost equal to the space W12-1. The space W23-2 between the pattern P2-2 and the pattern P3-2 is almost equal to the space W23-1.

[0052] 1.3 Effects of the First Embodiment According to the first embodiment, the bias amount calculation unit 24 calculates the bias amount B12 based on the space W12 between two adjacent patterns P1 and P2. The layout correction unit 25 widens the width of the pattern P2 toward the pattern P1 side and the width of the pattern P1 toward the pattern P2 side by the bias amount B12. That is, the layout correction unit 25 corrects the layout data 21 based on the space W12. The feature amount calculation unit 23 calculates the feature amount of the corrected layout data 21. The polishing process simulation unit 27 simulates the polishing process for the corrected layout data 21 based on the feature amount. This makes it possible to reproduce the effective widths of the patterns P1 and P2 even after a simplified simulation process of a film formation process in which the widths of the patterns P1 and P2 do not change before and after the simulation process.

[0053] Supplementally, the simulation process of the film forming process and the polishing process is performed on a large amount of patterns P formed on a wafer. As a result, if the simulation process of the film forming process and the polishing process is performed using a detailed model, it becomes difficult to complete the process within a realistic time. For this reason, a simplified simulation process of the film forming process and the polishing process in which the width of the pattern P does not change before and after the simulation process may be applied. In the simplified simulation process of the film forming process and the polishing process, for example, the area ratio, width, and perimeter of the pattern P are used as feature amounts (parameters). In this case, the area ratio of the pattern P formed in the actual film forming process cannot be reproduced in the simulation process of the polishing process.

[0054] On the other hand, the tendency of the step of the laminated structure after the actual polishing process may be strongly correlated with the area ratio of the pattern P formed in the actual film formation process. For this reason, if the simulation process of the simplified polishing process is executed as it is after the simulation process of the simplified film formation process, there is a possibility that the tendency of the step of the laminated structure after the actual polishing process cannot be simulated.

[0055] According to the first embodiment, the bias amount calculation unit 24 calculates the bias amount B corresponding to the amount of change in the width of the pattern P before and after the actual film formation process based on the shape (geometry) of the pattern P, in particular the space W between two adjacent patterns P. This makes it possible to reproduce the area ratio of the pattern P formed in the actual film formation process in the simulation processing of the polishing process. Therefore, it is possible to improve the accuracy of the step shape after the polishing process while suppressing an increase in simulation cost.

[0056] Moreover, the bias amount calculation unit 24 calculates a bias amount B23 based on a space W23 between the pattern P2 and the pattern P3 adjacent to the pattern P2 on the opposite side of the pattern P1. The layout correction unit 25 widens the width of the pattern P2 toward the pattern P3 side and the width of the pattern P3 toward the pattern P2 side by the bias amount B23. This makes it possible to apply different bias amounts B12 and B23 to the pattern P1 side and the pattern P3 side of the pattern P2. Therefore, in the simulation processing of the polishing process, it is possible to improve the reproducibility of the area ratio of the pattern P formed in the actual film formation process.

[0057] 2. Second embodiment Next, a simulation device according to a second embodiment will be described. The second embodiment differs from the first embodiment in that the bias amount is updated during the simulation process of the polishing process. The following mainly describes configurations and operations that are different from the first embodiment. Descriptions of configurations and operations equivalent to those of the first embodiment will be omitted as appropriate.

[0058] 2.1 Cross-sectional structure of the laminated structure to be simulated during the polishing process Fig. 10 is a cross-sectional view showing an example of a cross-sectional structure of an actual laminated structure that is the subject of a simulation process of a polishing process in a simulation device according to the second embodiment. In Fig. 10, the cross-sectional structure after a film formation process is shown classified into three cases (A), (B), and (C) according to the magnitude of the sidewall angle θ. The sidewall angle θ is the inclination of the sidewall of the pattern P formed by the actual film formation process.

[0059] Case (A) shown in the upper part of FIG. 10 is a case where the sidewall angle θ is 90°. In case (A), an insulating film 33a is provided by a film formation process. The width of the pattern Pa formed by the insulating film 33a has a bias amount Ba with respect to the width of the conductive film 32. The bias amount Ba can be considered to be equivalent to the bias amount B in the first embodiment. That is, case (A) corresponds to the case of the first embodiment.

[0060] Case (B) shown in the center of Fig. 10 is a case where the sidewall angle θ is smaller than 90°. In case (B), an insulating film 33b is provided by a film forming process. A bias amount Bb of the width of the pattern Pb formed by the insulating film 33b relative to the width of the conductive film 32 is equal to the bias amount Ba on the upper surface, but gradually becomes narrower toward the conductive film 32. In other words, the pattern Pb has an inverse tapered shape.

[0061] Case (C) shown in the lower part of Fig. 10 is a case where the sidewall angle θ is greater than 90°. In case (C), an insulating film 33c is provided by a film forming process. The bias amount Bc of the width of the pattern Pc formed by the insulating film 33c relative to the width of the conductive film 32 is equal to the bias amount Ba on the upper surface, but gradually becomes wider toward the conductive film 32. In other words, the pattern Pc has a forward tapered shape.

[0062] Of the above three cases, the results of performing the polishing process for cases (B) and (C) may differ from the results of performing the polishing process for case (A). In the second embodiment, the difference between the cases (B) and (C) and the case (A) is taken into consideration in the simulation process. Specifically, the polishing process simulation unit 27 divides the simulation process of the polishing process into multiple times and executes it. Then, the polishing process simulation unit 27 applies a different bias amount B to each of the multiple polishing process simulation processes that are divided and executed.

[0063] 2.2 Bias amount FIG. 11 is a diagram showing an example of a bias amount applied to the simulation apparatus according to the second embodiment.

[0064] As described above, the width of the pattern P formed by the film formation process can vary depending on the sidewall angle θ. In the second embodiment, bias amounts Ba, Bb, and Bc are defined for three cases (A), (B), and (C) based on the sidewall angle, respectively.

[0065] 11, when the sidewall angle θ is 90° (case (A)), the bias amount Ba does not change regardless of the polishing amount t. In contrast, when the sidewall angle θ is smaller than 90° (case (B)), the bias amount Bb decreases according to the polishing amount t. Also, when the sidewall angle θ is larger than 90° (case (C)), the bias amount Bc increases according to the polishing amount t.

[0066] 2.3 Flowchart Fig. 12 is a flowchart showing an example of a simulation process involving a layout correction process in the simulation apparatus according to the second embodiment, which corresponds to Fig. 6 in the first embodiment.

[0067] When an instruction to start a simulation process of a film formation process is received from a user (START), the feature amount calculation unit 23 calculates feature amounts related to the layout data 21 before the film formation process (S21).

[0068] The film forming process simulation unit 26 executes a simulation process of the film forming process based on the feature amount calculated in the process of S21 (S22).

[0069] Bias amount calculation unit 24 sets a sidewall angle θ for pattern P formed in the process of S22, and a division number N for the simulation process of the polishing process. In addition, polishing process simulation unit 27 initializes a variable i to 0 (S23). The variable i corresponds to the number of polishing processes, and is an integer between 0 and N.

[0070] The bias amount calculation unit 24 refers to the rule table 22 to calculate the bias amount B_i (=B_0) based on the layout data 21 updated in the process of S22 (S24). Specifically, the bias amount calculation unit 24 calculates the bias amount B_0 based on the space W between adjacent patterns P. Here, when the sidewall angle θ is 90°, the bias amount calculation unit 24 calculates the bias amount Ba_0. When the sidewall angle θ is smaller than 90°, the bias amount calculation unit 24 calculates the bias amount Bb_0. When the sidewall angle θ is larger than 90°, the bias amount calculation unit 24 calculates the bias amount Bc_0. As shown in FIG. 10, after the film formation process, the bias amount B_0 is expected to be equal regardless of the sidewall angle θ. For this reason, the bias amounts Ba_0, Bb_0, and Bc_0 are set to equal values.

[0071] The layout correction unit 25 corrects the layout data 21 based on the bias amount B_0 calculated in the process of S24 (S25). Specifically, the layout correction unit 25 widens the width of each of the two patterns P so that the space W between the two adjacent patterns P is narrowed according to the bias amount B_0.

[0072] The feature amount calculation section 23 calculates the feature amount for the layout data 21 corrected by the process of S25 (S26).

[0073] The polishing process simulation unit 27 increments the variable i (S27). That is, when the variable i=1, the bias amount B_0=B_(i-1).

[0074] The polishing process simulation unit 27 executes a simulation process of the i-th polishing process based on the feature amount calculated in the process of S26 (S28). This executes a simulation process of the polishing process based on the pattern P taking into account the bias amount B_(i-1). After the process of S28, the layout data 21 is updated according to the pattern P after polishing. In the simulation process of the i-th polishing process, the pattern P is removed in the stacking direction by a polishing amount t_i that is smaller than the final polishing amount.

[0075] After the process of S28, polishing process simulation unit 27 determines whether or not variable i has reached division number N of the polishing process (S29).

[0076] If the variable i has not reached the division number N of the polishing process (S29; no), the bias amount calculation unit 24 calculates the bias amount B_i based on the layout data 21 after the i-th polishing process, based on the sidewall angle θ set in the process of S23 and the i-th polishing amount t_i (S30). Specifically, the bias amount calculation unit 24 calculates the bias amount B_i based on the following formula (1). B_i = B_(i-1) - t_i / tan(θ) … (1) The layout correction unit 25 corrects the layout data 21 after the i-th polishing step based on the bias amount B_i calculated in the process of S30 (S31).

[0077] The feature amount calculation section 23 calculates the feature amount for the layout data 21 corrected by the process of S31 (S32).

[0078] The polishing process simulation unit 27 increments the variable i (S33). That is, when the variable i=2, the bias amount B_1=B_(i-1).

[0079] After the process of S33, polishing process simulation unit 27 executes a simulation process of the i-th polishing process based on the feature amount calculated in the process of S32 (S28). Then, the subsequent process of S29 is executed. In this manner, the processes of S30 to S33, S28, and S29 are repeatedly executed until variable i reaches the division number N of the polishing process.

[0080] When the variable i reaches the division number N of the polishing process (S29; yes), the simulation process involving the layout correction process ends (end).

[0081] 2.4 Specific examples Next, a specific example of a simulation process involving a layout correction process in the simulation apparatus according to the second embodiment will be described. For convenience of explanation, the following will describe a case where the number of divisions N of the polishing process is 3.

[0082] 2.4.1 Case (B) Fig. 13 is a cross-sectional view showing a first example of a first layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. Fig. 14 is a cross-sectional view showing a first example of a second layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. Fig. 15 is a cross-sectional view showing a first example of a third layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. The first example corresponds to case (B).

[0083] First, the first layout correction process and the polishing process simulation process in case (B) will be described with reference to Fig. 13. The cross-sectional structures shown in parts (A), (B), and (C) of Fig. 13 correspond to the state after the simulation process of the film formation process (S22(i=0)), the state after the first layout correction process (S25(i=0)), and the state after the simulation process of the first polishing process (S28(i=1)), respectively.

[0084] As shown in part (A) of FIG. 13, the insulating film 33b is provided over the entire surface by the simulation process of the film formation process. As described above, the shape of the pattern Pb is almost maintained before and after the simulation process of the film formation process. Therefore, the width of the insulating film 33b forming the pattern Pb-0 is almost equal to the width of the conductive film 32 portion.

[0085] Therefore, the bias amount calculation unit 24 calculates, based on the rule table 22, a bias amount Bb_0 that is equal to the case where the sidewall angle θ is 90°.

[0086] 13B, the layout correction unit 25 corrects the layout data 21 based on the bias amount Bb_0. Specifically, the layout correction unit 25 adds a virtual insulator film 34b-1 having a width of the bias amount Bb_0 to the sidewall of the insulator film 33b on the upper surface of the conductor film 32. As a result, the pattern Pb-0 is corrected to a pattern Pb-1.

[0087] 13C, the insulator film 33b on the upper surface of the conductor film 32 and the insulator film 34b-1 are removed by a first polishing amount tb_1 by a simulation process of the first polishing step. Accordingly, a region of the insulator film 33b provided on the side of the conductor film 32 that is not protected by the insulator film 34b-1 is also slightly removed.

[0088] Next, the second layout correction process and the polishing process simulation process in case (B) will be described with reference to Fig. 14. The cross-sectional structures shown in parts (A), (B), and (C) of Fig. 14 correspond to the state after the first simulation process of the polishing process (S28(i=1)), the state after the second layout correction process (S31(i=1)), and the state after the second simulation process of the polishing process (S28(i=2)), respectively.

[0089] As shown in portion (A) of FIG. 14, the width of pattern Pb-1 after the simulation process of the first polishing process is approximately equal to the width of pattern Pb-1 before the simulation process of the first polishing process.

[0090] However, in case (B), the width of the actual insulating film 33b is narrower after the first polishing process than before the first polishing process. Therefore, the bias amount calculation unit 24 substitutes the first polishing amount tb_1, the bias amount Bb_0, and the sidewall angle θ into the above-mentioned formula (1) to calculate the bias amount Bb_1 that is smaller than the bias amount Bb_0.

[0091] 14B, the layout correction unit 25 corrects the layout data 21 based on the bias amount Bb_1. Specifically, the layout correction unit 25 adds a virtual insulator film 34b-2 having a width of the bias amount Bb_1 to the sidewall of the insulator film 33b on the upper surface of the conductor film 32. As a result, the pattern Pb-1 is corrected to a pattern Pb-2.

[0092] 14C, the insulator film 33b on the upper surface of the conductor film 32 and the insulator film 34b-2 are removed by a second polishing amount tb_2 by a simulation process of the second polishing step. Accordingly, a region of the insulator film 33b provided on the side of the conductor film 32 that is not protected by the insulator film 34b-2 is also slightly removed.

[0093] Next, the third layout correction process and the polishing process simulation process in case (B) will be described with reference to Fig. 15. The cross-sectional structures shown in parts (A), (B), and (C) of Fig. 15 correspond to the state after the second polishing process simulation process (S28(i=2)), the state after the third layout correction process (S31(i=2)), and the state after the third polishing process simulation process (S28(i=3=N)), respectively.

[0094] As shown in portion (A) of FIG. 15, the width of pattern Pb-2 after the simulation process of the second polishing process is approximately equal to the width of pattern Pb-2 before the simulation process of the second polishing process.

[0095] However, in case (B), the width of the actual insulating film 33b is narrower after the second polishing process than before the second polishing process. Therefore, the bias amount calculation unit 24 substitutes the second polishing amount tb_2, the bias amount Bb_1, and the sidewall angle θ into the above-mentioned formula (1) to calculate the bias amount Bb_2 smaller than the bias amount Bb_1.

[0096] 15B, the layout correction unit 25 corrects the layout data 21 based on the bias amount Bb_2. Specifically, the layout correction unit 25 adds a virtual insulator film 34b-3 having a width of the bias amount Bb_2 on the upper surface of the insulator film 33b on the side of the conductor film 32. As a result, the pattern Pb-2 is corrected to a pattern Pb-3.

[0097] Next, as shown in part (C) of FIG. 15, a region of the insulator film 33b that is not protected by the insulator film 34b-3 is slightly removed by the simulation process of the third polishing step.

[0098] By the above-mentioned process, a step shape of the insulating film 33b can be obtained that takes into consideration the sidewall angle θ smaller than 90°.

[0099] 2.4.2 Case (C) Fig. 16 is a cross-sectional view showing a first layout correction process and a second example of a polishing process simulation process in the simulation apparatus according to the second embodiment. Fig. 17 is a cross-sectional view showing a second example of a second layout correction process and a polishing process simulation process in the simulation apparatus according to the second embodiment. Fig. 18 is a cross-sectional view showing a third layout correction process and a second example of a polishing process simulation process in the simulation apparatus according to the second embodiment. The second example corresponds to case (C).

[0100] First, the first layout correction process and the polishing process simulation process in case (C) will be described with reference to Fig. 16. The cross-sectional structures shown in parts (A), (B), and (C) of Fig. 16 correspond to the state after the simulation process of the film formation process (S22(i=0)), the state after the first layout correction process (S25(i=0)), and the state after the simulation process of the first polishing process (S28(i=1)), respectively.

[0101] As shown in part (A) of FIG. 16, the insulating film 33c is provided over the entire surface by the simulation process of the film formation process. As described above, the shape of the pattern Pc is almost maintained before and after the simulation process of the film formation process. Therefore, the width of the insulating film 33c forming the pattern Pc-0 is almost equal to the width of the conductive film 32 portion.

[0102] Therefore, the bias amount calculation unit 24 calculates, based on the rule table 22, a bias amount Bc_0 that is equal to the amount when the sidewall angle θ is 90°.

[0103] 16B, the layout correction unit 25 corrects the layout data 21 based on the bias amount Bc_0. Specifically, the layout correction unit 25 adds a virtual insulator film 34c-1 having a width of the bias amount Bc_0 to the sidewall of the insulator film 33c on the upper surface of the conductor film 32. As a result, the pattern Pc-0 is corrected to a pattern Pc-1.

[0104] 16C, the insulator film 33c on the upper surface of the conductor film 32 and the insulator film 34c-1 are removed by a first polishing amount tc_1 by a simulation process of the first polishing step. Accordingly, a region of the insulator film 33c provided on the side of the conductor film 32 that is not protected by the insulator film 34c-1 is also slightly removed.

[0105] Next, the second layout correction process and the polishing process simulation process in case (C) will be described with reference to Fig. 17. The cross-sectional structures shown in parts (A), (B), and (C) of Fig. 17 correspond to the state after the first polishing process simulation process (S28(i=1)), the state after the second layout correction process (S31(i=1)), and the state after the second polishing process simulation process (S28(i=2)), respectively.

[0106] As shown in portion (A) of FIG. 17, the width of pattern Pc-1 after the simulation process of the first polishing process is approximately equal to the width of pattern Pc-1 before the simulation process of the first polishing process.

[0107] However, in case (C), the width of the actual insulating film 33c is wider after the first polishing process than before the first polishing process. Therefore, the bias amount calculation unit 24 substitutes the first polishing amount tc_1, the bias amount Bc_0, and the sidewall angle θ into the above-mentioned formula (1) to calculate the bias amount Bc_1 that is larger than the bias amount Bc_0.

[0108] 17B, ​​the layout correction unit 25 corrects the layout data 21 based on the bias amount Bc_1. Specifically, the layout correction unit 25 adds a virtual insulator film 34c-2 having a width of the bias amount Bc_1 to the sidewall of the insulator film 33c on the upper surface of the conductor film 32. As a result, the pattern Pc-1 is corrected to a pattern Pc-2.

[0109] 17C, the insulator film 33c on the upper surface of the conductor film 32 and the insulator film 34c-2 are removed by a second polishing amount tc_2 by a simulation process of the second polishing step. Accordingly, a region of the insulator film 33c provided on the side of the conductor film 32 that is not protected by the insulator film 34c-2 is also slightly removed.

[0110] Next, the third layout correction process and the polishing process simulation process in case (C) will be described with reference to Fig. 18. The cross-sectional structures shown in parts (A), (B), and (C) of Fig. 18 correspond to the state after the second polishing process simulation process (S28(i=2)), the state after the third layout correction process (S31(i=2)), and the state after the third polishing process simulation process (S28(i=3=N)), respectively.

[0111] As shown in portion (A) of FIG. 18, the width of pattern Pc-2 after the simulation process of the second polishing process is approximately equal to the width of pattern Pc-2 before the simulation process of the second polishing process.

[0112] However, in case (C), the width of the actual insulating film 33c is wider after the second polishing process than before the second polishing process. Therefore, the bias amount calculation unit 24 substitutes the second polishing amount tc_2, the bias amount Bc_1, and the sidewall angle θ into the above-mentioned formula (1) to calculate the bias amount Bc_2 that is larger than the bias amount Bc_1.

[0113] 18B, the layout correction unit 25 corrects the layout data 21 based on the bias amount Bc_2. Specifically, the layout correction unit 25 adds a virtual insulator film 34c-3 having a width of the bias amount Bc_2 on the upper surface of the insulator film 33c on the side of the conductor film 32. As a result, the pattern Pc-2 is corrected to a pattern Pc-3.

[0114] Next, as shown in part (C) of FIG. 18, a region of the insulator film 33c that is not protected by the insulator film 34c-3 is slightly removed by the simulation process of the third polishing step.

[0115] By the above-mentioned process, a step shape of the insulating film 33c can be obtained that takes into consideration the sidewall angle θ larger than 90°.

[0116] 2.5 Effects of the Second Embodiment According to the second embodiment, the polishing process simulation unit 27 executes a simulation process of the first polishing process based on the feature amount of the layout data 21 corrected after the simulation process of the film formation process. The bias amount calculation unit 24 calculates a bias amount B_1 based on the bias amount B_0 applied to the simulation process of the first polishing process, the polishing amount t_1 by the simulation process of the first polishing process, and the sidewall angle θ of the pattern P after the actual film formation process. The layout correction unit 25 corrects the bias amount B applied to the layout data 21 from the bias amount B_0 to the bias amount B_1. The feature amount calculation unit 23 calculates the feature amount of the layout data 21 to which the bias amount B_1 is applied. The polishing process simulation unit 27 executes a simulation process of the second polishing process based on the feature amount of the layout data 21 corrected after the simulation process of the first polishing process. This makes it possible to execute the simulation process while applying different bias amounts B according to the progress of the polishing process. Therefore, even when the pattern P has a forward tapered shape or an inverse tapered shape, the step shape of the laminated structure after the polishing process can be simulated while taking these shapes into consideration, thereby improving the accuracy of the step shape after the polishing process.

[0117] 3. Modifications Various modifications can be applied to the first and second embodiments described above.

[0118] In the above-described second embodiment, the case where the simulation process of the polishing process is divided into multiple times and executed for one layer of the insulator film 33 has been described, but the present invention is not limited to this. For example, the simulation process of the polishing process may be executed for multiple laminated layers of films. In this case, the simulation process of the polishing process may be divided so as to correspond to each of the multiple layers of films. This allows further consideration of the film quality of each of the multiple layers of films. Therefore, the step shape generated in the insulator film 33 after the simulation process of the polishing process can be made closer to the actual shape.

[0119] In the above-described first and second embodiments, the case where the planar shape of the pattern P, such as the space W, is applied as a parameter for determining the bias amount B has been described, but the present invention is not limited to this. For example, in addition to the space W, the three-dimensional shape of the pattern P, including the conductive film 32 (i.e., the dimensions of the transistor gate), the thickness of the conductive film 32, and the thickness of the insulating film 33 provided above the conductive film 32 by a film formation process, may be applied as a parameter for determining the bias amount B.

[0120] In the above-described first and second embodiments, the case where the program for executing the simulation process involving the layout correction process is executed by the simulation device 1 has been described, but this is not limiting. For example, the program for executing the simulation process involving the layout correction process may be executed by computational resources on a cloud.

[0121] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0122] 1. Simulation device 11...Control section 12...User Interface 13. Storage 14. Drive 15...Storage medium 21...Layout data 22…Rule table 23...Feature calculation unit 24...Bias amount calculation section 25…Layout correction section 26…Deposition process simulation section 27…Polishing process simulation section 30...Substrate 31, 33...Insulating film 32...Conductive film

Claims

1. correcting a layout of a stacked structure based on a shape of the stacked structure; Calculating a first feature of the corrected layout; simulating a polishing process for the corrected layout based on the first feature amount; The simulation method includes:

2. The laminated structure includes a first pattern and a second pattern adjacent to each other, The correction is Calculating a first bias amount based on a first space between the first pattern and the second pattern; widening a width of the second pattern toward the first pattern by the first bias amount; Including, The simulation method according to claim 1 .

3. The correcting step further includes increasing a width of the first pattern toward the second pattern by the first bias amount. The simulation method according to claim 2.

4. the laminate structure further includes a third pattern having a third width, located on an opposite side of the second pattern from the first pattern, and adjacent to the second pattern; The correcting includes correcting the layout based on the first space and a second space between the second pattern and the third pattern. The simulation method according to claim 2.

5. The correction is calculating a first bias amount based on the first space; widening a width of the second pattern toward the first pattern by the first bias amount; calculating a second bias amount based on the second space; widening a width of the second pattern toward the third pattern by the second bias amount; Including, The simulation method according to claim 4.

6. The correction is widening a width of the first pattern toward the second pattern by the first bias amount; widening a width of the third pattern toward the second pattern by the second bias amount; Further comprising: The simulation method according to claim 5.

7. the first feature amount includes an area ratio, a width, and a perimeter of a pattern included in the layout; The simulation method according to claim 1 .

8. The simulating step comprises: simulating a first polishing step for the corrected layout based on the first feature amount; calculating a second bias amount based on the first bias amount, a polishing amount of the stacked structure in the first polishing step, and a sidewall angle related to the second pattern; correcting a width of the second pattern to be expanded toward the first pattern from the first bias amount to the second bias amount; Calculating a second feature amount of the corrected layout after simulating the first polishing process; simulating a second polishing process for a layout corrected after the simulation of the first polishing process based on the second feature amount; Including, The simulation method according to claim 2.

9. The second bias amount is smaller than the first bias amount. The simulation method according to claim 8.

10. The second bias amount is greater than the first bias amount. The simulation method according to claim 8.

11. On the computer, correcting a layout of a stacked structure based on a shape of the stacked structure; Calculating a first feature of the corrected layout; simulating a polishing process for the corrected layout based on the first feature amount; A program for executing the above.

12. On the computer, correcting a layout of a stacked structure based on a shape of the stacked structure; Calculating a first feature of the corrected layout; simulating a polishing process for the corrected layout based on the first feature amount; A non-transitory computer-readable storage medium having a program stored therein for executing the above.

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