Optical device, light receiver, and light transceiver

Abstract

To provide an optical device in which the coupling loss between a second EC and an edge surface on a local light-emission port side due to the tolerance deviation of dicing can be reduced.SOLUTION: The optical device includes: a first edge coupler connected to a polarization beam combiner-splitter and in contact with an edge surface; and a second edge coupler connected to an optical hybrid circuit and in contact with the edge surface. The optical device has a first tapered part included in the first edge coupler, which guides light from the edge surface, and a second tapered part included in the second edge coupler, which guides light from the edge surface. The second tapered part has a configuration in which the tapered angle to the edge surface of the second tapered part is smaller than the tapered angle to the edge surface of the first tapered part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an optical device, an optical receiver, and an optical transceiver. [Background technology]

[0002] Fig. 11 is an explanatory diagram showing an example of a conventional optical chip 100. The optical chip 100 shown in Fig. 11 is, for example, an optical IC chip having an optical receiver 110 with a digital coherent function. The optical receiver 110 has a first EC (Edge Coupler) 111 arranged at a signal light port for inputting a signal light, a second EC 112 arranged at a local light port for inputting a local light, and a PBS (Polarization Beam Splitter) 113. The optical receiver 110 has a PR (Polarization Rotator) 114, a first optical hybrid circuit 115A, a second optical hybrid circuit 115B, first to fourth PD (Photo Diodes) 116A to 116D, and first to fourth output ports 117A to 117D. For example, the second EC 112 and the first optical hybrid circuit 115A, the second EC 112 and the second optical hybrid circuit 115B, and the first EC 111 and the PBS 113 are connected by optical waveguides such as Si waveguides.

[0003] The first EC111 of the signal light port is formed on a chip end face D11, which is a side end in the optical chip 100, and is, for example, an EC of a port that connects to a first optical fiber F11 that inputs signal light. The signal light port is exposed to the chip end face D11 of the optical chip 100 by forming the wafer into a chip. The second EC112 of the local light port is formed on the chip end face D11 in the optical chip 100, and is, for example, an EC of a port that connects to a second optical fiber F12 that inputs local light from a light source. The local light port is exposed to the chip end face D11 of the optical chip 100 by forming the wafer into a chip.

[0004] The PBS 113 separates the received light, which is the signal light input from the first EC 111, into two orthogonal polarization states, for example, an X-polarized component which is TE (Transverse Electric) polarization and a Y-polarized component which is TM (Transverse Magnetic) polarization. The PBS 113 outputs the received light of the X-polarized component to the first optical hybrid circuit 115A. Furthermore, the PR 114 rotates the polarization of the received light of the Y-polarized component from the PBS 113 by 90 degrees, converts it into the received light of the Y-polarized component after the polarization rotation, and outputs it to the second optical hybrid circuit 115B.

[0005] The first optical hybrid circuit 115A causes the local light to interfere with the received light of the X-polarized component to obtain optical signals of I and Q components. The I component is an in-phase axis component, and the Q component is an orthogonal axis component. The first optical hybrid circuit 115A outputs the optical signal of the I component of the received light of the X-polarized component to the first PD 116A. The first optical hybrid circuit 115A outputs the optical signal of the Q component of the received light of the X-polarized component to the second PD 116B.

[0006] The second optical hybrid circuit 115B causes the local light to interfere with the received Y-polarized light to obtain I- and Q-component optical signals. The second optical hybrid circuit 115B outputs the I-component optical signal of the received Y-polarized light to the third PD 116C. The second optical hybrid circuit 115B outputs the Q-component optical signal of the received Y-polarized light to the fourth PD 116D.

[0007] The first PD 116A converts the optical signal of the I component of the X polarization component from the first optical hybrid circuit 115A into an electric signal, adjusts the gain, and outputs the gain-adjusted electric signal to the first output port 117A. The second PD 116B converts the optical signal of the Q component of the X polarization component from the first optical hybrid circuit 115A into an electric signal, adjusts the gain, and outputs the gain-adjusted electric signal to the second output port 117B.

[0008] The third PD 116C converts the optical signal of the I component of the Y polarization component from the second optical hybrid circuit 115B into an electric signal, adjusts the gain, and outputs the gain-adjusted electric signal to the third output port 117C. The fourth PD 116D converts the optical signal of the Q component of the Y polarization component from the second optical hybrid circuit 115B into an electric signal, adjusts the gain, and outputs the gain-adjusted electric signal to the fourth output port 117D.

[0009] FIG. 12 is a schematic plan view showing an example of an EC section in an optical chip 100. The EC section shown in FIG. 12 is a section of a substrate-type optical waveguide element that is optically coupled to a core C of an optical fiber. The EC section has a first EC 111 which is a signal light port, and a second EC 112 which is a local light port. Since the received light includes TE light and TM light, the first EC 111 guides the TE light and TM light. Since the local light is TE light, the second EC 112 guides the TE light. Since the second EC 112 has the same configuration as the first EC 111, the same reference numerals are used, and explanations of the overlapping configurations and operations will be omitted.

[0010] The first EC 111 has a clad 121 made of SiO2 or the like, and a first waveguide 122 made of, for example, Si3N4 (hereinafter, simply referred to as SiN (Silicon Nitride)) or the like, which is covered with the clad 121. The first EC 111 has a second waveguide 123 made of, for example, Si, which is covered with the clad 121, and an adiabatic conversion section 124 where light adiabatically transitions between the first waveguide 122 and the second waveguide 123. Furthermore, the first EC 111 has an inverted taper section 125 having a structure in which the waveguide width to the chip end face D11 of the first waveguide 122 gradually narrows.

[0011] The first waveguide 122 has a first tapered waveguide 122A and a second tapered waveguide 122B connected to the first tapered waveguide 122A. The first tapered waveguide 122A has a structure in which the waveguide width gradually increases from the optical input / output portion near the chip end face D11 toward the starting point. The second tapered waveguide 122B has a structure in which the waveguide width gradually decreases from the point connected to the starting point of the first tapered waveguide 122A toward the starting point of the first tapered waveguide 122A.

[0012] The second waveguide 123 has a third tapered waveguide 123A arranged at a position where at least a part of the second tapered waveguide 122B overlaps in the planar direction, and a straight waveguide 123B connected to the third tapered waveguide 123A. The third tapered waveguide 123A has a structure in which the waveguide width gradually increases with increasing distance from the starting point of the second tapered waveguide 122B. The straight waveguide 123B is a waveguide connected to the side of the third tapered waveguide 123A where the waveguide width is wider.

[0013] Fig. 13A is an explanatory diagram showing an example of a schematic cross-sectional portion of the first EC 111 shown in Fig. 12 along the line AA. The first EC 111 shown in Fig. 13A has a Si substrate 131, a clad 121, a first assembly layer 141A arranged on the side farther from the Si substrate 131, and a second assembly layer 141B arranged on the side closer to the Si substrate 131. The schematic cross-sectional portion of the line AA shown in Fig. 13A is a cross-sectional portion of the first EC 111 in which the straight waveguide 123B is arranged. The straight waveguide 123B in the second waveguide 123 is arranged in the second assembly layer 141B.

[0014] FIG. 13B is an explanatory diagram showing an example of a schematic cross-sectional portion of the first EC 111 shown in FIG. 12 along the line BB. The first EC 111 shown in FIG. 13B has a Si substrate 131, a clad 121, a first assembly layer 141A, and a second assembly layer 141B. The schematic cross-sectional portion of the line BB shown in FIG. 13B is a cross-sectional portion of the first EC 111 in which the adiabatic conversion section 124 is arranged. The third tapered waveguide 123A in the second waveguide 123 is arranged in the second assembly layer 141B. The second tapered waveguide 122B in the first waveguide 122 is arranged in the first assembly layer 141A.

[0015] 13C is an explanatory diagram showing an example of a schematic cross-sectional portion of the CC line of the first EC 111 shown in FIG. 12. The first EC 111 shown in FIG. 13C has a Si substrate 131 and a clad 121 laminated on the Si substrate 131. The schematic cross-sectional portion of the CC line shown in FIG. 13C is a cross-sectional portion of the first EC 111 where the reverse taper portion 125 is arranged. Furthermore, the first EC 111 has a first assembly layer 141A and a second assembly layer 141B. The first tapered waveguide 122A in the first waveguide 122 is arranged in the first assembly layer 141A.

[0016] The configurations of the adiabatic conversion section 124 and the inverse taper section 125 of the first EC 111 are the same as those of the adiabatic conversion section 124 and the inverse taper section 125 of the second EC 112, and the waveguide width, the waveguide length, and the waveguide thickness are also the same.

[0017] 12 uses an inverse taper section 125 to guide received light from a first optical fiber F11 to an adiabatic conversion section 124. In the adiabatic conversion section 124, the waveguide widths of a first waveguide 122 and a second waveguide 123 change in a tapered shape. Since the first waveguide 122 has a lower refractive index than the second waveguide 123, the mode field of the received light can be increased and the coupling loss with the first optical fiber F11 can be reduced.

[0018] Moreover, the second EC 112 guides the local light from the second optical fiber F12 to the adiabatic conversion section 124 using the inverse taper section 125. In the adiabatic conversion section 124, the waveguide widths of the first waveguide 122 and the second waveguide 123 change in a tapered shape. Since the first waveguide 122 has a lower refractive index than the second waveguide 123, the mode field of the local light can be increased and the coupling loss with the second optical fiber F12 can be reduced. [Prior art documents] [Patent documents]

[0019] [Patent Document 1] US Patent Application Publication No. 2005 / 0185893 [Patent Document 2] US Patent Application Publication No. 2018 / 0321445 [Patent Document 3] Special Publication No. 2008-530615 [Patent Document 4] Special Publication No. 2006-517673 Summary of the Invention [Problem to be solved by the invention]

[0020] However, in an EC, in order to reduce the coupling loss with an optical fiber, it is required that the waveguide has an appropriate width at the chip end face D11. In Fig. 12, if the waveguide width of the inverted taper portion 125 widens in a tapered shape from the chip end face D11, the waveguide width of the first waveguide 122 at the chip end face D11 will vary from the design value due to tolerance deviation from the dicing line DL when the wafer is diced or polished. As a result, in an EC, the coupling loss with the optical fiber will increase due to tolerance deviations in dicing, polishing, etc.

[0021] 12, if the dicing position is shifted to the left in the drawing due to a tolerance deviation from the dicing line DL and the waveguide length of the inverse taper portion 125 of the second EC 112 is shortened, the waveguide width on the chip end face D11 side of the inverse taper portion 125 becomes wider. As a result, the coupling loss with the core C of the second optical fiber F12 becomes large, and the loss of the TE light guided through the second EC 112 becomes large. In particular, since the local light guided through the second EC 112 of the local light port is TE light, the loss of the TE light is more remarkable than that of the first EC 111.

[0022] One aspect of the present invention provides an optical device etc. capable of reducing coupling loss between a second EC on the local light source port side and a second optical fiber due to dicing tolerance deviation. [Means for solving the problem]

[0023] An optical device according to one embodiment includes a first edge coupler connected to a polarization multiplexer / demultiplexer and in contact with an end face, and a second edge coupler connected to an optical hybrid circuit and in contact with the end face. The optical device includes a first tapered portion included in the first edge coupler and guiding light from the end face, and a second tapered portion included in the second edge coupler and guiding light from the end face. The second tapered portion has a structure in which a taper angle of the second tapered portion with respect to the end face is smaller than a taper angle of the first tapered portion with respect to the end face. Effect of the Invention

[0024] According to one aspect, it is possible to reduce the coupling loss between the second edge coupler on the local light source port side and the end face due to dicing tolerance deviation. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is an explanatory diagram showing an example of an optical chip according to this embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of an EC portion in the optical chip according to the first embodiment. [Figure 3A]FIG. 3A is an explanatory diagram showing an example of a schematic cross-sectional portion taken along line AA of the second EC shown in FIG. [Figure 3B] 3B is an explanatory diagram showing an example of a schematic cross-sectional portion of the second EC shown in FIG. 2 taken along line BB. [Figure 3C] 3C is an explanatory diagram showing an example of a schematic cross-sectional portion taken along line CC of the second EC shown in FIG. 2. FIG. [Figure 4A] FIG. 4A is an explanatory diagram showing an example of the relationship between the dicing position for each taper length of the second inverse taper portion and the optical loss. [Figure 4B] FIG. 4B is an explanatory diagram showing an example of the relationship between the dicing position for each taper length of the first reverse taper portion and the optical loss. [Diagram 5] FIG. 5 is a schematic plan view showing an example of an EC portion in the optical chip according to the second embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an example of an EC portion in the optical chip according to the third embodiment. [Figure 7] FIG. 7 is a schematic plan view showing an example of an EC portion in the optical chip according to the fourth embodiment. [Figure 8A] FIG. 8A is an explanatory diagram showing an example of a schematic cross-sectional portion taken along line AA of the second EC shown in FIG. [Figure 8B] 8B is an explanatory diagram showing an example of a schematic cross-sectional portion of the second EC shown in FIG. 7 taken along the line BB. [Figure 8C] 8C is an explanatory diagram showing an example of a schematic cross-sectional portion taken along line CC of the second EC shown in FIG. [Figure 9] FIG. 9 is a schematic plan view showing an example of an EC portion in the optical chip according to the fifth embodiment. [Figure 10] FIG. 10 is an explanatory diagram illustrating an example of an optical transceiver according to this embodiment. [Figure 11] FIG. 11 is an explanatory diagram showing an example of a conventional optical chip. [Figure 12] FIG. 12 is a schematic plan view showing an example of an EC portion in an optical chip. [Figure 13A] FIG. 13A is an explanatory diagram showing an example of a schematic cross-sectional portion taken along line AA of the first EC shown in FIG. [Figure 13B] 13B is an explanatory diagram showing an example of a schematic cross-sectional portion of the first EC shown in FIG. 12 along the line BB. [Figure 13C] 13C is an explanatory diagram showing an example of a schematic cross-sectional portion taken along line CC of the first EC shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiments of the optical device and the like disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments. In addition, the following examples may be appropriately combined as long as no contradiction occurs. EXAMPLES

[0027] FIG. 1 is an explanatory diagram showing an example of an optical chip 1 of the present embodiment. The optical chip 1 shown in FIG. 1 is, for example, an optical IC chip having an optical receiver 10 with a digital coherent function. The optical receiver 10 has a first EC (Edge Coupler) 11 arranged at a signal light port for inputting a signal light, a second EC 12 arranged at a local light port for inputting a local light, a PBS (Polarization Beam Splitter) 13, and a PR (Polarization Rotator) 14. The optical receiver 10 has a first optical hybrid circuit 15A, a second optical hybrid circuit 15B, first to fourth PDs (Photo Diodes) 16A to 16D, and first to fourth output ports 17A to 17D. For example, the second EC 12 and the first optical hybrid circuit 15A, the second EC 12 and the second optical hybrid circuit 15B, and the first EC 11 and the PBS 13 are connected by optical waveguides such as Si waveguides.

[0028] The first EC11 of the signal light port is formed on chip end face D1, which is a side end in the optical chip 1, and is, for example, an EC of a port that connects to a first optical fiber F1 that inputs received light that is signal light. The signal light port is exposed to the chip end face D1 of the optical chip 1 when the wafer is made into a chip. The second EC12 of the local light port is formed on chip end face D1 in the optical chip 1, and is, for example, an EC of a port that connects to a second optical fiber F2 that inputs local light from a light source. The local light port is exposed to the chip end face D1 of the optical chip 1 when the wafer is made into a chip.

[0029] The PBS 13 is a polarization multiplexer / demultiplexer that separates the received light input from the first EC 11 into two orthogonal polarization states, for example, an X-polarized component which is TE (Transverse Electric) polarization and a Y-polarized component which is TM (Transverse Magnetic) polarization. The PBS 13 outputs the X-polarized component of the received light to the first optical hybrid circuit 15A. Furthermore, the PR 14 rotates the Y-polarized component of the received light from the PBS 13 by 90 degrees, converts it into a Y-polarized component of the received light after polarization rotation, and outputs it to the second optical hybrid circuit 15B.

[0030] The first optical hybrid circuit 15A causes the local light to interfere with the received light of the X-polarized component to obtain optical signals of I and Q components. The I component is an in-phase axis component, and the Q component is an orthogonal axis component. The first optical hybrid circuit 15A outputs the optical signal of the I component of the received light of the X-polarized component to the first PD 16A. The first optical hybrid circuit 15A outputs the optical signal of the Q component of the received light of the X-polarized component to the second PD 16B.

[0031] The second optical hybrid circuit 15B causes the local light to interfere with the received Y-polarized light to obtain I- and Q-component optical signals. The second optical hybrid circuit 15B outputs the I-component optical signal of the received Y-polarized light to the third PD 16C. The second optical hybrid circuit 15B outputs the Q-component optical signal of the received Y-polarized light to the fourth PD 16D.

[0032] The first PD 16A electrically converts the optical signal of the I component of the X polarization component from the first optical hybrid circuit 15A, adjusts the gain, and outputs the gain-adjusted electrical signal to the first output port 17A. The second PD 16B electrically converts the optical signal of the Q component of the X polarization component from the first optical hybrid circuit 15A, adjusts the gain, and outputs the gain-adjusted electrical signal to the second output port 17B.

[0033] The third PD 16C electrically converts the optical signal of the I component of the Y polarization component from the second optical hybrid circuit 15B, adjusts the gain, and outputs the gain-adjusted electrical signal to the third output port 17C. The fourth PD 16D electrically converts the optical signal of the Q component of the Y polarization component from the second optical hybrid circuit 15B, adjusts the gain, and outputs the gain-adjusted electrical signal to the fourth output port 17D.

[0034] Fig. 2 is a schematic plan view showing an example of an EC section in the optical chip 1 of the first embodiment. The EC section shown in Fig. 2 is an EC such as a substrate-type optical waveguide element optically coupled to a core C of an optical fiber. The EC section has a first EC 11 at a signal light port and a second EC 12 at a local light port. Since the received light includes TE light and TM light, the first EC 11 guides the TE light and TM light. Since the local light is TE light, the second EC 12 guides the TE light.

[0035] The first EC 11 has a clad 21 made of SiO2 or the like, and a first waveguide 22 made of, for example, Si3N4 (hereinafter, simply referred to as SiN (Silicon Nitride)) or the like, which is covered with the clad 21. The first EC 11 has a second waveguide 23 made of, for example, Si, which is covered with the clad 21, and a first adiabatic conversion section 24 where light adiabatically transitions between the first waveguide 22 and the second waveguide 23. Furthermore, the first EC 11 has a first reverse taper section 25 having a structure in which the waveguide width of the first waveguide 22 to the chip end face D1 gradually narrows. The first reverse taper section 25 is a first taper section included in the first EC 11 that guides the received light from the first optical fiber F1 connected to the chip end face D1.

[0036] The first waveguide 22 has a first tapered waveguide 22A and a second tapered waveguide 22B connected to the first tapered waveguide 22A. The first tapered waveguide 22A has a structure in which the waveguide width gradually increases from the optical input / output portion near the chip end face D1 toward the starting point. The second tapered waveguide 22B has a structure in which the waveguide width gradually decreases from the point connected to the starting point of the first tapered waveguide 22A toward the starting point of the first tapered waveguide 22A.

[0037] The second waveguide 23 has a third tapered waveguide 23A arranged at a position where at least a part of the second tapered waveguide 22B overlaps in the planar direction, and a straight waveguide 23B connected to the third tapered waveguide 23A. The third tapered waveguide 23A has a structure in which the waveguide width gradually increases with increasing distance from the starting point of the second tapered waveguide 22B. The straight waveguide 23B is a waveguide connected to the side of the third tapered waveguide 23A where the waveguide width is wider.

[0038] The second EC 12 has a cladding 21 made of SiO2 or the like, and a third waveguide 32 made of, for example, SiN or the like, covered with the cladding 21. The second EC 12 has a fourth waveguide 33 made of, for example, Si or the like, covered with the cladding 21, and a second adiabatic conversion section 34 in which light adiabatically transitions between the third waveguide 32 and the fourth waveguide 33. Furthermore, the second EC 12 has a second inverted taper section 35 having a structure in which the waveguide width to the chip end face D1 of the third waveguide 32 gradually narrows. The second inverted taper section 35 is a second taper section included in the second EC 12 that guides local light from a second optical fiber F2 connected to the chip end face D1.

[0039] The third waveguide 32 has a fourth tapered waveguide 32A and a fifth tapered waveguide 32B connected to the fourth tapered waveguide 32A. The fourth tapered waveguide 32A has a structure in which the width of the waveguide gradually increases from the optical input / output portion near the chip end face D1 toward the starting point. The fifth tapered waveguide 32B has a structure in which the width of the waveguide gradually decreases from the point where the fifth tapered waveguide 32B is connected to the starting point of the fourth tapered waveguide 32A toward the starting point of the fourth tapered waveguide 32A.

[0040] The fourth waveguide 33 has a sixth tapered waveguide 33A arranged at a position where at least a part of the fifth tapered waveguide 32B overlaps in the planar direction, and a straight waveguide 33B connected to the sixth tapered waveguide 33A. The sixth tapered waveguide 33A has a structure in which the waveguide width gradually increases with increasing distance from the starting point of the fifth tapered waveguide 32B. The straight waveguide 33B is a waveguide connected to the side of the sixth tapered waveguide 33A where the waveguide width is wider.

[0041] Fig. 3A is an explanatory diagram showing an example of a schematic cross-sectional portion of the second EC 12 shown in Fig. 2 taken along the line AA. The second EC 12 shown in Fig. 3A has a Si substrate 41, a clad 21, a first assembly layer 42A arranged on the side farther from the Si substrate 41, and a second assembly layer 42B arranged on the side closer to the Si substrate 41. The schematic cross-sectional portion of the line AA shown in Fig. 3A is a cross-sectional portion of the second EC 12 in which the straight waveguide 33B is arranged. The straight waveguide 33B in the fourth waveguide 33 is arranged in the second assembly layer 42B.

[0042] 3B is an explanatory diagram showing an example of a schematic cross-sectional portion of the second EC 12 shown in FIG. 2 along the line BB. The second EC 12 shown in FIG. 3B has a Si substrate 41, a clad 21, a first assembly layer 42A, and a second assembly layer 42B. The schematic cross-sectional portion of the line BB shown in FIG. 3B is a cross-sectional portion of the second EC 12 in which the second adiabatic conversion section 34 is arranged. The sixth tapered waveguide 33A in the fourth waveguide 33 is arranged in the second assembly layer 42B. The fifth tapered waveguide 32B in the third waveguide 32 is arranged in the first assembly layer 42A.

[0043] 3C is an explanatory diagram showing an example of a schematic cross-sectional portion of the CC line of the second EC 12 shown in FIG. 2. The second EC 12 shown in FIG. 3C has a Si substrate 41 and a clad 21 laminated on the Si substrate 41. The schematic cross-sectional portion of the CC line shown in FIG. 3C is a cross-sectional portion of the second EC 12 in which the second reverse taper portion 35 is arranged. Furthermore, the second EC 12 has a first assembly layer 42A and a second assembly layer 42B. The fourth tapered waveguide 32A in the third waveguide 32 is arranged in the first assembly layer 42A.

[0044] The dimension of the waveguide length of the second adiabatic conversion section 34 of the second EC 12 that guides only the TE light is the same as the dimension of the waveguide length of the first adiabatic conversion section 24 of the first EC 11 that guides the TE light and the TM light. However, the taper angle of the second reverse taper section 35 of the second EC 12 with respect to the chip end face D1 is smaller than the taper angle of the first reverse taper section 25 of the first EC 11 with respect to the chip end face D1. The waveguide length (taper length) of the second reverse taper section 35 is longer than the waveguide length (taper length) of the first reverse taper section 25. The waveguide width on the chip end face D1 side of the second reverse taper section 35 is narrower than the waveguide width on the chip end face D1 side of the first reverse taper section 25.

[0045] 4A is an explanatory diagram showing an example of the relationship between the dicing position for each taper length of the second reverse taper portion 35 and the optical loss. When the dicing position between the wafer and the optical chip 1 is 0 (no misalignment), the loss of the TE light is 0.8 dB, but when the dicing position is misaligned 20 μm to the left in FIG. 2 and the taper length of the second reverse taper portion 35 becomes shorter and the taper length becomes 60 μm, the loss of the TE light increases to 1.2 dB. In contrast, when the dicing position is misaligned to the right in FIG. 2 and the taper length of the second reverse taper portion 35 becomes longer and the taper length becomes 120 μm, the increase in the loss of the TE light increases slightly.

[0046] FIG. 4B is an explanatory diagram showing an example of the relationship between the dicing position for each taper length of the first reverse taper portion 25 and the optical loss. When the dicing position between the wafer and the optical chip 1 is shifted to the right in FIG. 2 and the taper length of the first reverse taper portion 25 is increased to 120 μm, the loss of the TM light increases to 1.5 dB. In contrast, when the dicing position is shifted to the left in FIG. 2 and the taper length of the first reverse taper portion 25 is decreased to 60 μm, the loss of the TM light can be suppressed to 1.1 dB. Therefore, since the taper length of the second reverse taper portion 35 is set to 120 μm and the taper length of the first reverse taper portion 25 is set to 60 μm, which is shorter than the taper length of the second reverse taper portion 35, the increase in the optical loss due to the dicing shift can be suppressed.

[0047] 2 uses the first inverted taper section 25 to guide the received light from the first optical fiber F1 to the first adiabatic conversion section 24. In the first adiabatic conversion section 24, the waveguide widths of the first waveguide 22 and the second waveguide 23 change in a tapered shape. Since the first waveguide 22 has a lower refractive index than the second waveguide 23, the mode field of the received light can be increased and the coupling loss with the first optical fiber F1 can be reduced.

[0048] The second EC 12 guides the local light from the second optical fiber F2 to the second adiabatic conversion section 34 using the second inverted taper section 35. In the second adiabatic conversion section 34, the waveguide widths of the third waveguide 32 and the fourth waveguide 33 change in a tapered shape. Since the third waveguide 32 has a lower refractive index than the fourth waveguide 33, the mode field of the local light can be increased and the coupling loss with the second optical fiber F2 can be reduced.

[0049] The taper angle of the second reverse taper portion 35 of the second EC 12 with respect to the chip end face D1 is smaller than the taper angle of the first reverse taper portion 25 of the first EC 11 with respect to the chip end face D1. The waveguide length (taper length) of the second reverse taper portion 35 is longer than the waveguide length (taper length) of the first reverse taper portion 25. The waveguide width on the chip end face D1 side of the second reverse taper portion 35 is narrower than the waveguide width on the chip end face D1 side of the first reverse taper portion 25. As a result, the coupling loss between the second EC 12 and the second optical fiber F2 due to the dicing tolerance deviation is reduced, and an EC with high tolerance to the dicing tolerance deviation can be realized.

[0050] In the first embodiment, the taper angle of the second inverse taper portion 35 with respect to the chip end face D1 is smaller than the taper angle of the first inverse taper portion 25 with respect to the chip end face D1, and the taper length of the second inverse taper portion 35 is longer than the taper length of the first inverse taper portion 25. However, regardless of the taper length of the second inverse taper portion 35, the same effect can be obtained by simply making the taper angle of the second inverse taper portion 35 with respect to the chip end face D1 smaller than the taper angle of the first inverse taper portion 25 with respect to the chip end face D1. Even in this case, the waveguide width on the chip end face D1 side of the second inverse taper portion 35 is narrower than the waveguide width on the chip end face D1 side of the first inverse taper portion 25, so that the coupling loss with the core C of the second optical fiber F2 is reduced, and the loss of the TE light guided through the second EC12 can be reduced. Therefore, the coupling loss between the second EC 12 and the second optical fiber F2 due to the dicing tolerance deviation can be reduced, and an EC with high tolerance to the dicing tolerance deviation can be realized.

[0051] 2 due to a tolerance deviation from the dicing line DL, and the waveguide length of the first reverse taper portion 25 of the first EC 11 becomes longer, the portion where the waveguide width is narrow on the chip end face D1 side of the first reverse taper portion 25 will continue for a long time. The TM light guided through the first EC 11 has weaker light confinement than the TE light, and the portion where the waveguide width is narrow on the chip end face D1 side of the first reverse taper portion 25 will continue for a long time, resulting in a large loss of the TM light. Therefore, an embodiment for dealing with such a situation will be described below as Example 2. EXAMPLES

[0052] 5 is a schematic plan view showing an example of an EC part in the optical chip 1A of the second embodiment. The same components as those in the optical chip 1 of the first embodiment are given the same reference numerals, and the description of the overlapping components and operations is omitted. The optical chip 1A of the second embodiment differs from the optical chip 1 of the first embodiment in that the end point of the second reverse taper portion 35 is not the chip end face D1, but a second excess portion 52 is arranged between the end point of the second reverse taper portion 35 and the chip end face D1. Another difference is that the end point of the first reverse taper portion 25 is not the chip end face D1, but a first excess portion 51 is arranged between the end point of the first reverse taper portion 25 and the chip end face D1.

[0053] The first excess length portion 51 is a straight waveguide that optically couples the first inverted taper portion 25 and the core C of the first optical fiber F1 and guides the received light from the core C of the first optical fiber F1, and is a part of the first waveguide 22. The waveguide width of the first excess length portion 51 is the same as the waveguide width on the end side of the first inverted taper portion 25. Even if the dicing position is shifted, the first excess length portion 51 allows the dicing position to shift within the range of the waveguide length of the first excess length portion 51. And, if the dicing shift occurs within the first excess length portion 51, it does not affect the waveguide width at the end point of the first inverted taper portion 25.

[0054] The second excess portion 52 is a straight waveguide that optically couples the second inverted taper portion 35 and the core C of the second optical fiber F2 and guides the local light from the core C of the second optical fiber F2, and is a part of the third waveguide 32. The waveguide width of the second excess portion 52 is the same as the waveguide width on the end side of the second inverted taper portion 35. Even if the dicing position is shifted, the second excess portion 52 allows the dicing position to be shifted within the range of the waveguide length of the second excess portion 52. And, if the dicing is shifted within the second excess portion 52, it does not affect the waveguide width at the end of the second inverted taper portion 35. The waveguide length of the first excess portion 51 is the same as the waveguide length of the second excess portion 52.

[0055] 5 guides the received light from the first optical fiber F1 to the first inverse taper section 25 using the first extra length section 51, and guides the received light to the first adiabatic conversion section 24 using the first inverse taper section 25. In the first adiabatic conversion section 24, the waveguide widths of the first waveguide 22 and the second waveguide 23 change in a tapered shape. Since the first waveguide 22 has a lower refractive index than the second waveguide 23, the mode field of the received light can be increased and the coupling loss with the first optical fiber F1 can be reduced.

[0056] The second EC 12A guides the local light from the second optical fiber F2 to the second inverse taper portion 35 using the second extra length portion 52, and guides the local light from the second optical fiber F2 to the second adiabatic conversion portion 34 using the second inverse taper portion 35. In the second adiabatic conversion portion 34, the waveguide widths of the third waveguide 32 and the fourth waveguide 33 change in a tapered shape. Since the third waveguide 32 has a lower refractive index than the fourth waveguide 33, the mode field of the local light can be increased and the coupling loss with the second optical fiber F2 can be reduced.

[0057] The taper angle of the second reverse taper portion 35 of the second EC 12 with respect to the chip end face D1 is smaller than the taper angle of the first reverse taper portion 25 of the first EC 11 with respect to the chip end face D1. The waveguide length (taper length) of the second reverse taper portion 35 is longer than the waveguide length (taper length) of the first reverse taper portion 25. As a result, the waveguide width on the chip end face D1 side of the second reverse taper portion 35 is narrower than the waveguide width on the chip end face D1 side of the first reverse taper portion 25, so that the coupling loss with the core C of the second optical fiber F2 is reduced, and the loss of the TE light guided through the second EC 11A can be reduced.

[0058] Moreover, the waveguide width of the second excess portion 52 is the same as the waveguide width on the chip end face D1 side of the second reverse taper portion 35, and the first excess portion 51 is the same as the waveguide width on the chip end face D1 side of the first reverse taper portion 25. As a result, even if a dicing position shift occurs within the range of the waveguide lengths of the first excess portion 51 and the second excess portion 52, the waveguide width on the chip end face D1 side of the first reverse taper portion 25 and the waveguide width on the chip end face D1 side of the second reverse taper portion 35 are prevented from changing due to the dicing position shift. As a result, the coupling loss between the second EC 11A and the second optical fiber F2 due to the dicing tolerance shift can be reduced, and an EC with high tolerance to the dicing tolerance shift can be realized.

[0059] The second excess length portion 52 of the second embodiment illustrates a case in which the waveguide width on the chip end face D1 side of the second reverse taper portion 35 is narrower than the waveguide width on the chip end face D1 side of the first reverse taper portion 25. However, the waveguide width on the chip end face D1 side of the second reverse taper portion 35 may be the same as the waveguide width on the chip end face D1 side of the first reverse taper portion 25, and can be changed as appropriate.

[0060] In the optical chip 1A of the second embodiment, a case where the dicing position is shifted and the waveguide lengths of the first and second excess parts 51 and 52 are shortened has been exemplified, but a case where the dicing position is shifted and the waveguide lengths of the first and second excess parts 51 and 52 are lengthened is also conceivable. When the dicing position is shifted and the waveguide lengths of the first and second excess parts 51 and 52 are lengthened, the optical loss in the first excess part 51 that guides the TM light increases. This is because the waveguide width of the first excess part 51 is narrower than the waveguide width of the first reverse taper part 25, so that the optical confinement is weaker and the propagation loss of the TM light increases.

[0061] Therefore, an embodiment for dealing with such a situation will be described below as a third embodiment. EXAMPLES

[0062] 6 is a schematic plan view showing an example of an EC portion in the optical chip 1B of the third embodiment. The same components as those in the optical chip 1A of the second embodiment are given the same reference numerals, and the description of the overlapping components and operations will be omitted. The optical chip 1B of the third embodiment differs from the optical chip 1A of the second embodiment in that the waveguide length of the first extra length portion 51A is shorter than the waveguide length of the second extra length portion 52.

[0063] In the optical chip 1B of the third embodiment, even if the dicing position is shifted toward the wafer side and the waveguide lengths of the first and second excess parts 51A and 52 are increased, the waveguide length of the first excess part 51A that guides the TM light can be made shorter than the waveguide length of the second excess part 52. As a result, the loss of the TM light in the first excess part 51A that guides the TM light can be suppressed.

[0064] In addition, in the optical chip 1 of Example 1, an example is given in which the taper length of the second inverted taper portion 35 is longer than the taper length of the first inverted taper portion 25, but this is not limited to this, and an embodiment of this embodiment will be described below as Example 4. EXAMPLES

[0065] 7 is a schematic plan view showing an example of an EC portion in an optical chip 1C of Example 4. The same components as those in the optical chip 1 of Example 1 are given the same reference numerals, and the description of the overlapping components and operations is omitted. The optical chip 1C of Example 4 differs from the optical chip 1 of Example 1 in that the optical chip 1C of Example 4 includes a third inverse taper portion 35A composed of an eighth taper waveguide 32A11 and a ninth taper waveguide 32A12 having different taper angles, instead of the second inverse taper portion 35.

[0066] The third inverted taper section 35A has an eighth taper waveguide 32A11 and a ninth taper waveguide 32A12 connected to the eighth taper waveguide 32A11. The eighth taper waveguide 32A11 has a structure in which the width of the waveguide gradually increases from the chip end face D1 toward the starting point of the eighth taper waveguide 32A11. The ninth taper waveguide 32A12 has a structure in which the width of the waveguide gradually increases from the starting point of the eighth taper waveguide 32A11 to the starting point of the ninth taper waveguide 32A12 at a point connected to the starting point of the eighth taper waveguide 32A11, and increases away from the starting point of the eighth taper waveguide 32A11. The ninth tapered waveguide 32A12 connects the end point of the ninth tapered waveguide 32A12 to the fifth tapered waveguide 32B in the second adiabatic conversion section 34. The taper angle of the eighth tapered waveguide 32A11 with respect to the chip end face D1 is smaller than the taper angle of the ninth tapered waveguide 32A12 with respect to the chip end face D1 of the start point of the eighth tapered waveguide 32A11. As a result, the taper length (waveguide length) of the third inverse taper section 35A can be made shorter than the taper length (waveguide length) of the second inverse taper section 35 shown in FIG.

[0067] Fig. 8A is an explanatory diagram showing an example of a schematic cross-sectional portion of the second EC 12C shown in Fig. 7 along the line AA. The second EC 12C shown in Fig. 8A has a Si substrate 41, a clad 21, a first assembly layer 42A, and a second assembly layer 42B. The schematic cross-sectional portion of the line AA shown in Fig. 8A is a cross-sectional portion of the second EC 12C in which the straight waveguide 33B is arranged. The straight waveguide 33B in the fourth waveguide 33 is arranged in the second assembly layer 42B.

[0068] 8B is an explanatory diagram showing an example of a schematic cross-sectional portion of the second EC 12C shown in FIG. 7 along the line BB. The second EC 12C shown in FIG. 8B has a Si substrate 41, a clad 21, a first assembly layer 42A, and a second assembly layer 42B. The schematic cross-sectional portion of the line BB shown in FIG. 8B is a cross-sectional portion of the second EC 12C in which the second adiabatic conversion section 34 is arranged. The sixth tapered waveguide 33A in the fourth waveguide 33 is arranged in the second assembly layer 42B. The fifth tapered waveguide 32B in the third waveguide 32 is arranged in the first assembly layer 42A.

[0069] 8C is an explanatory diagram showing an example of a schematic cross-sectional portion of the CC line of the second EC 12C shown in FIG. 7. The second EC 12C shown in FIG. 8C has a Si substrate 41 and a clad 21 laminated on the Si substrate 41. The schematic cross-sectional portion of the CC line shown in FIG. 8C is a cross-sectional portion of the second EC 12C in which the third inverted taper portion 35A is arranged. Furthermore, the second EC 12C has a first assembly layer 42A and a second assembly layer 42B. The ninth tapered waveguide 32A12 in the third waveguide 32 is arranged in the first assembly layer 42A.

[0070] The waveguide length of the second adiabatic conversion section 34 that guides only the TE light is the same as the waveguide length of the first adiabatic conversion section 24 that guides the TE light and the TM light. However, the waveguide width at the start point of the third inverse taper section 35A is the same as the waveguide width at the start point of the first inverse taper section 25. Furthermore, the taper angle of the third inverse taper section 35A with respect to the chip end face D1 is made smaller than the taper angle of the first inverse taper section 25 with respect to the chip end face D1. As a result, even if the taper length of the third inverse taper section 35A is kept the same as the taper length of the first inverse taper section 25, the waveguide width on the chip end face D1 side of the third inverse taper section 35A is narrower than the waveguide width on the chip end face D1 side of the first inverse taper section 25. As a result, the coupling loss between the second optical fiber F2 and the core C is reduced, and the loss of the TE light guided through the second EC 12C can be reduced. Therefore, the coupling loss between the second EC 12C and the second optical fiber F2 due to the dicing tolerance deviation can be reduced, and an EC with high tolerance to the dicing tolerance deviation can be realized.

[0071] The waveguide length of the third inverse taper portion 35A can be made shorter than the waveguide length of the second inverse taper portion 35 shown in FIG. 2, which can contribute to miniaturization of optical devices.

[0072] In addition, in the optical chip 1 of Example 1, the taper length of the second inverted taper portion 35 is longer than the taper length of the first inverted taper portion 25, but this is not limited to this, and an embodiment of this embodiment will be described below as Example 5. EXAMPLES

[0073] 9 is a schematic plan view showing an example of an EC portion in the optical chip 1D of the fifth embodiment. The same components as those in the optical chip 1 of the first embodiment are given the same reference numerals, and the description of the overlapping components and operations is omitted. The optical chip 1D of the fifth embodiment differs from the optical chip 1 of the first embodiment in that the optical chip 1D of the fifth embodiment includes a fourth inverted taper portion 35C instead of the second inverted taper portion 35.

[0074] The fourth inverse taper portion 35C is made shorter than the taper length of the second inverse taper portion 35 shown in FIG. 2, while the waveguide width on the chip end face D1 side of the fourth inverse taper portion 35C is made narrower than the waveguide width on the chip end face D1 side of the first inverse taper portion 25. The waveguide width on the chip end face D1 side is the width of the tip of the inverse taper portion. As a result, the coupling loss with the core C of the second optical fiber F2 is reduced, and the loss of the TE light guided through the second EC12D can be reduced. Therefore, the coupling loss between the second EC12D and the second optical fiber F2 due to the tolerance deviation of dicing is reduced, and an EC with high tolerance to the tolerance deviation of dicing can be realized.

[0075] In addition, the first waveguide 22, the second waveguide 23, the third waveguide 32 and the fourth waveguide 33 are illustrated as channel waveguides, but are not limited thereto, and may be, for example, a rib waveguide, a ridge waveguide, a slab waveguide, or the like, and can be appropriately changed.

[0076] FIG. 10 is an explanatory diagram showing an example of an optical transceiver 70 according to the present embodiment. The optical transceiver 70 shown in FIG. 10 is connected to an output optical fiber and an input optical fiber. The optical transceiver 70 includes a light source 71, a DSP (Digital Signal Processor) 72, and an optical transmitter / receiver 73. The optical transmitter / receiver 73 includes an optical transmitter 73A and an optical receiver 73B. The DSP 72 is an electrical component that performs digital signal processing. For example, the DSP 72 performs processing such as encoding transmission data, generates an electrical signal including the transmission data, and outputs the generated electrical signal to the optical transmitter 73A. The DSP 72 also obtains an electrical signal including reception data from the optical receiver 73B, and obtains reception data by performing processing such as decoding the obtained electrical signal.

[0077] The light source 71 includes, for example, a laser diode, and generates light of a predetermined wavelength and supplies it to the optical transmitter 73A and the optical receiver 73B. The optical transmitter 73A modulates the light supplied from the light source 71 with an electrical signal output from the DSP 72, and outputs the obtained transmission light to an optical fiber. The optical transmitter 73A includes an optical modulator element 73A1 that generates transmission light by modulating the light supplied from the light source 71 with an electrical signal input to the optical modulator when the light propagates through the waveguide.

[0078] The optical receiver 73B has an optical receiver element 73B1 that receives an optical signal from an optical fiber and demodulates the received light using light supplied from the light source 71. The optical receiver 73B then converts the demodulated received light into an electrical signal and outputs the converted electrical signal to the DSP 72. The optical receiver 73B incorporates an optical device that is a planar optical waveguide element that guides light.

[0079] The optical device in the optical transceiver 70 includes a first EC connected to the polarization multiplexer / demultiplexer and in contact with the chip end face, and a second EC connected to the optical hybrid circuit and in contact with the chip end face. The optical device includes a first taper portion included in the first EC that guides light from an input optical fiber connected to the chip end face, and a second taper portion included in the second edge coupler that guides light from an optical fiber connected to a light source 71 connected to the chip end face. The second taper portion has a structure in which the taper angle of the second taper portion with respect to the chip end face is smaller than the taper angle of the first taper portion with respect to the chip end face. As a result, the waveguide width on the chip end face side of the second reverse taper portion is narrower than the waveguide width on the chip end face side of the first reverse taper portion, so that the coupling loss with the light source is reduced, and the loss of the TE light guided through the second EC can be reduced. Therefore, the coupling loss between the second EC 12 and the optical fiber of the light source 71 due to the dicing tolerance deviation can be reduced, and an EC with high tolerance to the dicing tolerance deviation can be realized.

[0080] For convenience of explanation, the optical transceiver 70 has been illustrated as having the optical transmitter 73A and the optical receiver 73B built in, but the optical transceiver 70 may have either the optical transmitter 73A or the optical receiver 73B built in. For example, an optical device may be applied to the optical transceiver 70 having the optical receiver 73B built in, and modifications can be made as appropriate.

[0081] Furthermore, each component of each unit shown in the figure does not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each unit is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0082] Furthermore, the various processing functions performed by each device may be executed in whole or in part on a CPU (Central Processing Unit) (or a microcomputer such as an MPU (Micro Processing Unit) or an MCU (Micro Controller Unit)). It goes without saying that the various processing functions may be executed in whole or in part on a program analyzed and executed by a CPU (or a microcomputer such as an MPU or an MCU), or on hardware using wired logic. [Explanation of symbols]

[0083] 1 Optical chip 11 The First EC 12 The Second EC 13 PBS 15A First Optical Hybrid Circuit 15B Second optical hybrid circuit 25 First inverted taper section 35 Second reverse taper section 51 First extra length 52 Second extra length 70 Optical Transceiver 72 DSP 73 Optical Transmitter / Receiver 73A Optical Transmitter 73A1 Optical modulator element 73B Optical Receiver 73B1 Optical receiver element D1 Chip end face F1 First Optical Fiber F2 Second optical fiber

Claims

1. a first edge coupler connected to the polarization multiplexer / demultiplexer and in contact with the end face; a second edge coupler connected to the optical hybrid circuit and in contact with the end face; a first tapered portion included in the first edge coupler, the first tapered portion guiding light from the end face; a second tapered portion included in the second edge coupler, the second tapered portion guiding light from the end face; The second tapered portion is 1. An optical device comprising: a first tapered portion having a first end surface and a second tapered portion having a second end surface; a second tapered portion having a second end surface and a second end surface;

2. The second tapered portion is 2. The optical device according to claim 1, wherein the second tapered portion has a longer taper length than the first tapered portion.

3. a first excess portion on the end face side connected to the first tapered portion; a second excess portion on the end face side connected to the second tapered portion, The second excess portion is 2. The optical device according to claim 1, wherein the second tapered portion has a waveguide width on the end face side that is narrower than a waveguide width on the end face side of the first tapered portion.

4. The first excess length portion is 4. The optical device according to claim 3, wherein the first extra length portion has a waveguide length shorter than a waveguide length of the second extra length portion.

5. The second tapered portion is A third tapered portion disposed on the end surface side; a fourth tapered portion optically connected to the third tapered portion; The third tapered portion is 2. The optical device according to claim 1, wherein the third tapered portion has a taper angle with respect to the end face smaller than a taper angle with respect to the end face of the fourth tapered portion.

6. The first edge coupler comprises: The light from the end face is input as a signal light, The second edge coupler comprises:

2. The optical device according to claim 1, wherein light from said end face is input as local light.

7. The second edge coupler comprises:

2. The optical device according to claim 1, wherein light having a transverse electric (TE) polarization state is input from said end face.

8. An optical receiver including an optical receiver element that converts a received signal light into an electrical signal, The optical receiver element comprises: a first edge coupler connected to the polarization multiplexer / demultiplexer and in contact with the end face; a second edge coupler connected to the optical hybrid circuit and in contact with the end face; a first tapered portion included in the first edge coupler, the first tapered portion guiding light from the end face; a second tapered portion included in the second edge coupler, the second tapered portion guiding light from the end face; The second tapered portion is 1. An optical receiver having a structure in which a taper angle of said second taper portion with respect to said end face is smaller than a taper angle of said first taper portion with respect to said end face.

9. an optical modulator element that modulates guided light in response to an electrical signal; an optical receiver element that converts received light into an electrical signal; a signal processing unit that generates an electrical signal to the optical modulator element and acquires the electrical signal from the optical receiver element, The optical receiver element comprises: a first edge coupler connected to the polarization multiplexer / demultiplexer and in contact with the end face; a second edge coupler connected to the optical hybrid circuit and in contact with the end face; a first tapered portion included in the first edge coupler, the first tapered portion guiding light from the end face; a second tapered portion included in the second edge coupler, the second tapered portion guiding light from the end face; The second tapered portion is 1. An optical transceiver having a structure in which a taper angle of said second taper portion with respect to said end face is smaller than a taper angle of said first taper portion with respect to said end face.

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