Gate drive circuit, power converter, and motor unit

Abstract

To compatibly achieve reduction of switching loss and suppression of noise and surge.SOLUTION: A gate drive circuit GDA comprises: a first terminal P1 to which a first electric potential is applied; a second terminal P2 to which a second electric potential lower than the first electric potential is applied; a third terminal P3 connected to a gate terminal of a switching element TR; a first switch SW1 connected between the first terminal and a first node N1; a first diode D1 comprising an anode terminal connected to the first node, and a cathode terminal connected to a second node N2; an inductor L1 connected between the first node and a third node N3; a second switch SW2 connected between the second node and the third node; a third switch SW3 connected between the second terminal and the third node; and a fourth switch SW4 connected between the second terminal and a fourth node N4. The second node is directly or indirectly connected to the fourth node, and the fourth node is directly or indirectly connected to the third terminal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a gate drive circuit, a power conversion device, and a motor unit. [Background technology]

[0002] In recent years, silicon carbide (SiC) switching elements have been attracting attention as power semiconductor switching elements that can withstand high voltages, high heat resistance, and high-speed switching. In the case of SiC switching elements, because the transconductance is low, the conduction resistance does not decrease until a sufficiently high voltage is applied to the gate terminal, resulting in conduction loss.

[0003] By switching the switching element at high speed, losses are reduced, but noise and surges become worse. When the switching element is turned on, a reverse recovery current generated by a body diode parasitic to the switching element is superimposed on the current waveform of the switching element. When the switching element is switched at high speed, the reverse recovery current becomes steep, which leads to an increase in noise and surges. When the switching element is turned off, a surge voltage is generated due to the parasitic inductance component of the current path of the switching element.

[0004] For example, Patent Document 1 discloses a gate drive circuit for driving a switching element, the gate drive circuit having a circuit configuration for reducing switching loss and noise. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2005-039988 A Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, there has been a demand for the development of a gate drive circuit that can simultaneously reduce the switching loss of the switching element to be driven and suppress the noise and surges that occur during switching.

[0007] The present invention has been proposed in consideration of the above circumstances, and aims to provide a gate drive circuit that can achieve both reduction in switching loss of the switching element to be driven and suppression of noise and surges generated during switching, and a power conversion device and a motor unit that are equipped with the gate drive circuit. [Means for solving the problem]

[0008] One aspect of the gate drive circuit of the present invention is a gate drive circuit for driving a switching element, comprising: a first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, a third terminal connected to a gate terminal of the switching element, a first switch connected between the first terminal and a first node, a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node, an inductor connected between the first node and a third node, a second switch connected between the second node and the third node, a third switch connected between the second terminal and the third node, and a fourth switch connected between the second terminal and a fourth node, wherein the second node is directly or indirectly connected to the fourth node, and the fourth node is directly or indirectly connected to the third terminal.

[0009] One aspect of the power conversion device of the present invention includes a bridge circuit having a plurality of switching elements, a plurality of gate drive circuits provided corresponding to each of the plurality of switching elements and driving the corresponding switching elements, and a control unit controlling the plurality of gate drive circuits, each of the plurality of gate drive circuits including a first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, a third terminal connected to a gate terminal of the corresponding switching element, a first switch connected between the first terminal and a first node, a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node, an inductor connected between the first node and a third node, a second switch connected between the second node and the third node, a third switch connected between the second terminal and the third node, and a fourth switch connected between the second terminal and a fourth node, the second node being directly or indirectly connected to the fourth node, and the fourth node being directly or indirectly connected to the third terminal.

[0010] A motor unit according to one aspect of the present invention includes a motor and the power conversion device according to the above aspect that supplies power to the motor. Effect of the Invention

[0011] According to the above aspects of the present invention, it is possible to provide a gate drive circuit that can achieve both reduction in switching loss of the switching element to be driven and suppression of noise and surges generated during switching, and a power conversion device and a motor unit that are equipped with the gate drive circuit. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a motor unit 1 according to the first embodiment. [Diagram 2] FIG. 2 is a circuit configuration diagram of the gate drive circuit GDA in the first embodiment. [Diagram 3]FIG. 3 is a first diagram showing a path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. [Figure 4] FIG. 4 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned on. [Diagram 5] FIG. 5 is a third diagram showing a path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. [Figure 6] FIG. 6 is a diagram showing an example of waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned on. [Figure 7] FIG. 7 is a first diagram showing a path of a current flowing through the gate drive circuit GDA when the switching element TR is turned off. [Figure 8] FIG. 8 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned off. [Figure 9] FIG. 9 is a diagram showing an example of waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned off. [Figure 10] FIG. 10 is a circuit configuration diagram of the gate drive circuit GDB in the second embodiment. [Figure 11] FIG. 11 is a first diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. [Figure 12] FIG. 12 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned on. [Figure 13] FIG. 13 is a third diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. [Figure 14] FIG. 14 is a fourth diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. [Figure 15]FIG. 15 is a first diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned off. [Figure 16] FIG. 16 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned off. [Figure 17] FIG. 17 is a circuit diagram showing a first modified example of the gate drive circuit GDA. [Figure 18] FIG. 18 is a circuit diagram showing a first modified example of the gate drive circuit GDB. [Figure 19] FIG. 19 is a circuit diagram showing a second modified example of the gate drive circuit GDA. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0014] [First embodiment] First, a first embodiment of the present invention will be described. FIG. 1 is a diagram that shows a schematic configuration of a motor unit 1 in the first embodiment. As shown in FIG. 1, the motor unit 1 includes a motor 10 and a power conversion device 20. For example, the motor unit 1 is a driving motor unit mounted on an electric vehicle. Electric vehicles include electric vehicles, hybrid vehicles, plug-in hybrid vehicles, and fuel cell vehicles. For example, the motor 10 is a three-phase AC motor. The power conversion device 20 supplies power to the motor 10.

[0015] The power conversion device 20 is connected to the motor 10 and the first DC power source 2, and performs mutual conversion between DC power and three-phase AC power. For example, when the power conversion device 20 functions as an inverter, the power conversion device 20 converts the DC power supplied from the first DC power source 2 into three-phase AC power and outputs it to the motor 10. For example, the first DC power source 2 is a drive battery that outputs a relatively high DC voltage among multiple batteries mounted on the electric vehicle.

[0016] The power conversion device 20 includes a bridge circuit 21, six gate drive circuits GD1 to GD6, a control unit 22, a smoothing capacitor 23, and a power supply circuit 24. In this embodiment, the bridge circuit 21 is a three-phase full bridge circuit having six switching elements TR1 to TR6. In this embodiment, the switching elements TR1 to TR6 included in the bridge circuit 21 are, for example, N-channel MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The switching elements TR1 to TR6 may be IGBTs (Insulated-Gate Bipolar Transistors). In addition, the switching elements TR1 to TR6 may be SiC switching elements or Si switching elements.

[0017] The switching elements TR1, TR3, and TR5 are high-side switches of the bridge circuit 21. The drain terminals of the switching elements TR1, TR3, and TR5 are connected to the positive terminal of the first DC power supply 2. The switching elements TR2, TR4, and TR6 are low-side switches of the bridge circuit 21. The source terminals of the switching elements TR2, TR4, and TR6 are connected to the negative terminal of the first DC power supply 2.

[0018] The source terminal of switching element TR1 is connected to the drain terminal of switching element TR2 and to the U-phase terminal of the motor 10. The source terminal of switching element TR3 is connected to the drain terminal of switching element TR4 and to the V-phase terminal of the motor 10. The source terminal of switching element TR5 is connected to the drain terminal of switching element TR6 and to the W-phase terminal of the motor 10.

[0019] The switching element TR1 has a body diode BD1 parasitic between the drain and source of the switching element TR1. In an equivalent circuit, the anode terminal of the body diode BD1 is connected to the source terminal of the switching element TR1, and the cathode terminal of the body diode BD1 is connected to the drain terminal of the switching element TR1.

[0020] Like the switching element TR1, the switching element TR2 has a body diode BD2. The switching element TR3 has a body diode BD3. The switching element TR4 has a body diode BD4. The switching element TR5 has a body diode BD5. The switching element TR6 has a body diode BD6.

[0021] The six gate drive circuits GD1-GD6 are provided corresponding to the six switching elements TR1-TR6, respectively, and drive the corresponding switching elements. Note that "driving a switching element" includes turning on the switching element by charging the input capacitance of the switching element, and turning off the switching element by discharging the input capacitance of the switching element.

[0022] The gate drive circuit GD1 is provided corresponding to the switching element TR1, and drives the switching element TR1 in accordance with a control signal input from the control unit 22. The gate drive circuit GD1 is connected to the gate terminal and source terminal of the switching element TR1. The gate drive circuit GD2 is provided corresponding to the switching element TR2, and drives the switching element TR2 in accordance with a control signal input from the control unit 22. The gate drive circuit GD2 is connected to the gate terminal and source terminal of the switching element TR2.

[0023] The gate drive circuit GD3 is provided corresponding to the switching element TR3, and drives the switching element TR3 in accordance with a control signal input from the control unit 22. The gate drive circuit GD3 is connected to the gate terminal and source terminal of the switching element TR3. The gate drive circuit GD4 is provided corresponding to the switching element TR4, and drives the switching element TR4 in accordance with a control signal input from the control unit 22. The gate drive circuit GD4 is connected to the gate terminal and source terminal of the switching element TR4.

[0024] The gate drive circuit GD5 is provided corresponding to the switching element TR5, and drives the switching element TR5 in accordance with a control signal input from the control unit 22. The gate drive circuit GD5 is connected to the gate terminal and source terminal of the switching element TR5. The gate drive circuit GD6 is provided corresponding to the switching element TR6, and drives the switching element TR6 in accordance with a control signal input from the control unit 22. The gate drive circuit GD6 is connected to the gate terminal and source terminal of the switching element TR6.

[0025] Although details will be described later, the six gate drive circuits GD1 to GD6 each have the same circuit configuration. In the following description, when there is no need to distinguish between the gate drive circuits GD1 to GD6, the gate drive circuits GD1 to GD6 are collectively referred to as the gate drive circuit GDA. In the following description, the switching elements TR1 to TR6 may be collectively referred to as the switching elements TR, and the body diodes BD1 to BD6 may be collectively referred to as the body diode BD.

[0026] The control unit 22 controls each of the gate drive circuits GD1 to GD6 by outputting a control signal to each of the gate drive circuits GD1 to GD6. As will be described in detail later, the control signal output from the control unit 22 controls the on and off timings of the first switch SW1, second switch SW2, third switch SW3, and fourth switch SW4 included in each of the gate drive circuits GD1 to GD6.

[0027] For example, the control unit 22 has a function of communicating with an ECU (Electronic Control Unit) mounted on the electric vehicle. The control unit 22 receives a rotation speed command signal from the ECU, which is a higher-level control device, and outputs a control signal to each of the gate drive circuits GD1 to GD6 for rotating the motor 10 at a target rotation speed instructed by the rotation speed command signal. For example, the control unit 22 is a processor with a built-in memory (not shown). As an example, the control unit 22 is an MCU (Microcontroller Unit). The control unit 22 controls the gate drive circuits GD1 to GD6 according to a program previously stored in the memory.

[0028] The smoothing capacitor 23 is a capacitor connected in parallel to the first DC power source 2. Note that the smoothing capacitor 23 does not necessarily have to be disposed inside the power conversion device 20, and may be disposed outside the power conversion device 20.

[0029] The power supply circuit 24 is connected to the second DC power supply 3. For example, the second DC power supply 3 is a battery that outputs a relatively low DC voltage among a plurality of batteries mounted on the electric vehicle. The power supply circuit 24 generates, from the DC voltage supplied from the second DC power supply 3, a first power supply voltage Vdd used as a power supply voltage for each of the gate drive circuits GD1 to GD6 and a second power supply voltage Vc used as a power supply voltage for the control unit 22.

[0030] The power supply circuit 24 outputs a first power supply voltage Vdd to each of the gate drive circuits GD1 to GD6, and outputs a second power supply voltage Vc to the control unit 22. For example, the power supply circuit 24 is a regulator or a DC-DC converter. Note that the DC voltage output from the first DC power supply 2 may be used as the first power supply voltage Vdd supplied to each of the gate drive circuits GD1 to GD6.

[0031] The configuration of the gate drive circuit GDA in the first embodiment will be described in detail below with reference to Fig. 2. Fig. 2 is a circuit configuration diagram of the gate drive circuit GDA. As shown in Fig. 2, the gate drive circuit GDA includes a first terminal P1, a second terminal P2, a third terminal P3, a fourth terminal P4, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, an inductor L1, a first diode D1, and a resistive element Rg.

[0032] The first terminal P1 is a terminal to which a first potential V1 is applied. The second terminal P2 is a terminal to which a second potential V2 lower than the first potential V1 is applied. The potential difference between the first potential V1 and the second potential V2 is equal to the first power supply voltage Vdd output from the power supply circuit 24. In other words, the first power supply voltage Vdd output from the power supply circuit 24 is input to the gate drive circuit GDA via the first terminal P1 and the second terminal P2.

[0033] The third terminal P3 is a terminal connected to a gate terminal of the switching element TR corresponding to the gate drive circuit GDA. The fourth terminal P4 is a terminal connected to a source terminal of the switching element TR. For example, when the switching element TR is an IGBT, the fourth terminal P4 is connected to an emitter terminal of the switching element TR. The fourth terminal P4 is also directly connected to the second terminal P2.

[0034] The first switch SW1 is connected between the first terminal P1 and the first node N1. The first diode D1 has an anode terminal connected to the first node N1 and a cathode terminal connected to the second node N2. The inductor L1 is connected between the first node N1 and the third node N3. The second switch SW2 is connected between the second node N2 and the third node N3. The third switch SW3 is connected between the second terminal P2 and the third node N3. The fourth switch SW4 is connected between the second terminal P2 and the fourth node N4.

[0035] The second node N2 is directly connected to the fourth node N4. Although details will be described later, the second node N2 may be indirectly connected to the fourth node N4 via the fifth switch SW5. In this manner, the second node N2 is directly or indirectly connected to the fourth node N4.

[0036] The resistance element Rg is connected between the fourth node N4 and the third terminal P3. That is, the fourth node N4 is indirectly connected to the third terminal P3 via the resistance element Rg. The resistance element Rg serves as a gate resistor that limits a current flowing through the gate terminal of the switching element TR. The resistance element Rg may be connected between the gate terminal of the switching element TR and the third terminal P3. In this case, the fourth node N4 is directly connected to the third terminal P3. In this way, the fourth node N4 is directly or indirectly connected to the third terminal P3.

[0037] In this embodiment, the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 may be composed of a single switching element such as a MOS-FET, or may be composed of a switching element and a resistive element connected in series. When each switch is composed of a single switching element, the switching element itself may have a conductive resistance.

[0038] Hereinafter, the operation of the gate drive circuit GDA when the switching element TR is turned on will be described with reference to FIGS.

[0039] Fig. 3 is a first diagram showing a path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in Fig. 3, when the control unit 22 turns on the switching element TR, at a first timing, the control unit 22 turns on the first switch SW1 and turns off the second switch SW2, the third switch SW3, and the fourth switch SW4. As a result, after the first timing, a current flows through the path shown by the dotted arrow in Fig. 3.

[0040] That is, after the first timing, a current flows through the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fourth node N4, and the resistor Rg in that order, and flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd.

[0041] Fig. 6 is a diagram showing an example of waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned on. In Fig. 6, time t1 corresponds to the first timing. As shown in Fig. 6, after time t1 corresponding to the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and the conductive resistance of the switching element TR decreases over time, so that the drain current Id increases over time.

[0042] 4 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in FIG. 4, the control unit 22 turns on the third switch SW3 at a second timing after the first timing. As a result, after the second timing, the current flows through the path shown by the dotted arrow in FIG. 4.

[0043] That is, after the second timing, in addition to the current flowing through the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fourth node N4, and the resistor element Rg, the current also flows through the first node N1, the inductor L1, and the third switch SW3 in this order. As a result, after the second timing, the input capacitance of the switching element TR is charged by the first power supply voltage Vdd, and at the same time, energy is stored in the inductor L1.

[0044] 6, the second timing is a point in time between the first timing (time t1) and the point in time when the peak of the reverse recovery current appears in the drain current Id. In other words, the second timing is preset as a point in time between the first timing and the point in time when the peak of the reverse recovery current appears in the drain current Id, and the control unit 22 turns on the third switch SW3 at the second timing thus preset. The second timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0045] In the above description, an example has been described in which the control unit 22 turns on the third switch SW3 at the second timing, but the present invention is not limited to this. The control unit 22 may turn on the third switch SW3 at the same time as the first switch SW1 at the first timing. Alternatively, the control unit 22 may turn on the third switch SW3 in advance before the first timing. In these cases, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and at the same time, energy is stored in the inductor L1.

[0046] Fig. 5 is a third diagram showing the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in Fig. 5, at a third timing after the second timing, the control unit 22 turns on the second switch SW2 and turns off the third switch SW3. As a result, after the third timing, a current flows through the path shown by the dotted arrow in Fig. 5.

[0047] That is, after the third timing, a current flows in the order of the first terminal P1, the first switch SW1, the first node N1, the inductor L1, the third node N3, the second switch SW2, the second node N2, the fourth node N4, and the resistor Rg, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the third timing, the energy stored in the inductor L1 is released as a current, and the potential of the second node N2 becomes higher than the first power supply voltage Vdd, and the current flowing into the gate terminal of the switching element TR increases. As a result, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, and the charging speed of the input capacitance of the switching element TR increases.

[0048] In Fig. 6, time t2 corresponds to the third timing. As shown in Fig. 6, the third timing (time t2) is a time point later than the time point at which the peak of the reverse recovery current appears in the drain current Id. In other words, the third timing is preset as a time point later than the time point at which the peak of the reverse recovery current appears in the drain current Id, and the control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at the third timing thus preset. The third timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0049] 3, that is, through the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fourth node N4, and the resistor Rg, and then flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after all the energy stored in the inductor L1 is released as a current, the input capacitance of the switching element TR is charged again by the first power supply voltage Vdd.

[0050] In Fig. 6, time t3 corresponds to the time when all the energy stored in inductor L1 is released as a current. As shown in Fig. 6, for example, when switching element TR is completely turned on at time t3, drain-source voltage Vds becomes approximately 0 V at time t3, and drain current Id is maintained at a constant value after time t3.

[0051] As described above, when the switching element TR is turned on, the gate drive circuit GDA is controlled so that the charging speed of the input capacitance of the switching element TR increases from the third timing, which is a time point after the time point when the reverse recovery current peaks in the drain current Id, thereby making it possible to reduce switching loss at the time of turn-on while suppressing the generation of noise and surges caused by the reverse recovery current. In particular, since the charging speed increases in the latter half of the turn-on operation, it is possible to quickly apply an overdrive voltage to the gate terminal of the switching element TR. As a result, it is possible to suppress the conduction loss in the latter half of the turn-on operation.

[0052] Next, the operation of the gate drive circuit GDA when the switching element TR is turned off will be described with reference to FIGS.

[0053] Fig. 7 is a first diagram showing a path of a current flowing through the gate drive circuit GDA when the switching element TR is turned off. As shown in Fig. 7, when the control unit 22 turns off the switching element TR, at a fourth timing, the control unit 22 turns off the first switch SW1 and turns on the second switch SW2, the third switch SW3, and the fourth switch SW4. As a result, after the fourth timing, a current flows through the path shown by the dotted arrow in Fig. 7.

[0054] That is, after the fourth timing, current flows in the order of the third terminal P3, the resistive element Rg, the fourth node N4, and the fourth switch SW4, and at the same time, current flows in the order of the fourth node N4, the second node N2, the second switch SW2, the third node N3, and the third switch SW3, and the current is discharged to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4.

[0055] Fig. 9 is a diagram showing an example of waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned off. In Fig. 9, time t4 corresponds to the fourth timing. As shown in Fig. 9, after time t4 corresponding to the fourth timing, a discharge current flows through the path shown in Fig. 7, so that the conductive resistance of the switching element TR increases over time, and therefore the drain-source voltage Vds increases over time.

[0056] Fig. 8 is a second diagram showing the path of the current flowing through the gate drive circuit GDA when the switching element TR is turned off. As shown in Fig. 8, the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at a fifth timing after the fourth timing. As a result, after the fifth timing, the current flows through the path shown by the dotted arrow in Fig. 8. Note that Fig. 8 shows an example in which both the second switch SW2 and the third switch SW3 are turned off.

[0057] That is, after the fifth timing, current flows through the third terminal P3, the resistive element Rg, the fourth node N4, and the fourth switch SW4 in that order, and is discharged via the fourth terminal P4 to the wiring connected to the source terminal of the switching element TR.

[0058] In Fig. 9, time t5 corresponds to the fifth timing. As shown in Fig. 9, the fifth timing (time t5) is a time point before the time point at which the peak of the surge voltage appears in the drain-source voltage Vds. In other words, the fifth timing is preset as a time point before the time point at which the peak of the surge voltage appears in the drain-source voltage Vds, and the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing thus preset. The fifth timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0059] As described above, when the switching element TR is turned off, the input capacitance of the switching element TR is discharged through two discharge paths, the discharge path including the second switch SW2 and the third switch SW3 and the discharge path including the fourth switch SW4, at the beginning of the turn-off operation. This increases the discharge speed of the input capacitance of the switching element TR, thereby reducing the switching loss at the time of turn-off. In addition, from the fifth timing, which is a time point before the peak of the surge voltage appears in the drain-source voltage Vds, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4. This reduces the discharge speed before the peak of the surge voltage appears in the drain-source voltage Vds, thereby reducing the height of the peak of the surge voltage. As a result, it is possible to suppress noise and surges generated at the time of turn-off.

[0060] As described above, the gate drive circuit GDA of the first embodiment can reduce the switching loss of the switching element TR to be driven, while suppressing noise and surges that occur during switching.

[0061] [Second embodiment] Next, a second embodiment of the present invention will be described. The second embodiment differs from the first embodiment in that the power conversion device 20 includes a gate drive circuit GDB having a different configuration from the gate drive circuit GDA. In other words, in the second embodiment, the configuration of the power conversion device 20 other than the gate drive circuit GDB and the configuration of the motor unit 1 are the same as those in the first embodiment, so hereinafter, only the configuration and operation of the gate drive circuit GDB will be described.

[0062] Fig. 10 is a circuit configuration diagram of the gate drive circuit GDB in the second embodiment. As can be understood by comparing Fig. 10 with Fig. 2, the gate drive circuit GDB in the second embodiment differs from the gate drive circuit GDA in the first embodiment in that it further includes a fifth switch SW5 connected between the second node N2 and the fourth node N4. That is, in the gate drive circuit GDB, the second node N2 is indirectly connected to the fourth node N4 via the fifth switch SW5.

[0063] Hereinafter, the operation of the gate drive circuit GDB when the switching element TR is turned on will be described with reference to FIGS.

[0064] Fig. 11 is a first diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in Fig. 11, when the control unit 22 turns on the switching element TR, at a first timing, the control unit 22 turns on the first switch SW1 and the third switch SW3 and turns off the second switch SW2 and the fifth switch SW5. As a result, after the first timing, a current flows through the path indicated by the dotted arrow in Fig. 11.

[0065] That is, after the first timing, a current flows through the first terminal P1, the first switch SW1, the first node N1, the inductor L1, and the third switch SW3 in that order, whereby energy is stored in the inductor L1 after the first timing. In addition, in FIG. 11, the fourth switch SW4 is turned off. However, in order to prevent the gate voltage of the switching element TR from becoming unstable, it is desirable that the fourth switch SW4 is turned on at the first timing.

[0066] Fig. 12 is a second diagram showing the path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in Fig. 12, the control unit 22 turns off the fourth switch SW4 and turns on the fifth switch SW5 at a second timing after the first timing. As a result, after the second timing, a current flows through the path indicated by the dotted arrow in Fig. 12.

[0067] That is, after the second timing, in addition to the current flowing through the first terminal P1, the first switch SW1, the first node N1, the inductor L1, and the third switch SW3 in this order, the current also flows through the first node N1, the first diode D1, the second node N2, the fifth switch SW5, the fourth node N4, and the resistor Rg in this order, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the second timing, the input capacitance of the switching element TR is charged by the first power supply voltage Vdd, and at the same time, energy is stored in the inductor L1.

[0068] In the second embodiment, the second timing is set to a predetermined point in time after the first timing as the time for storing energy in the inductor L1, and the control unit 22 turns off the fourth switch SW4 and turns on the fifth switch SW5 at the second timing thus preset.

[0069] In the above description, the control unit 22 turns on the first switch SW1 and the third switch SW3 and turns off the second switch SW2 and the fifth switch SW5 at the first timing, and turns off the fourth switch SW4 and turns on the fifth switch SW5 at the second timing, but the present invention is not limited to this. For example, the control unit 22 may turn on the first switch SW1, the third switch SW3, and the fifth switch SW5 at the first timing and turns off the second switch SW2 and the fourth switch SW4. In this case, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and energy is stored in the inductor L1.

[0070] Alternatively, the control unit 22 may turn on the first switch SW1 and the fifth switch SW5 at the first timing, turn off the second switch SW2, the third switch SW3, and the fourth switch SW4, and turn on the third switch SW3 at the second timing. In this case, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd after the first timing, and energy is stored in the inductor L1 at the same time as the input capacitance of the switching element TR is charged with the first power supply voltage Vdd after the second timing.

[0071] Fig. 13 is a third diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in Fig. 13, the control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at a third timing after the second timing. As a result, after the third timing, a current flows through the path indicated by the dotted arrow in Fig. 13.

[0072] That is, after the third timing, a current flows through the first terminal P1, the first switch SW1, the first node N1, the inductor L1, the third node N3, the second switch SW2, the second node N2, the fifth switch SW5, the fourth node N4, and the resistor Rg in that order, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the third timing, the energy stored in the inductor L1 is released as a current, and the potential of the second node N2 becomes higher than the first power supply voltage Vdd, and the current flowing into the gate terminal of the switching element TR increases. As a result, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, and the charging speed of the input capacitance of the switching element TR increases.

[0073] As in the first embodiment, in the second embodiment, the third timing is preset as a point in time after the point in time when the peak of the reverse recovery current appears in the drain current Id, and the control unit 22 turns on the second switch SW2 and turns off the third switch SW3 at the third timing thus preset. Note that the third timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0074] Fig. 14 is a fourth diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned on. After all the energy stored in the inductor L1 is released as a current, the current flows through the path shown in Fig. 14, that is, the first terminal P1, the first switch SW1, the first node N1, the first diode D1, the second node N2, the fifth switch SW5, the fourth node N4, and the resistor Rg, in that order, and flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after all the energy stored in the inductor L1 is released as a current, the input capacitance of the switching element TR is charged again with the first power supply voltage Vdd.

[0075] As described above, when the switching element TR is turned on, the gate drive circuit GDB is controlled so that the charging speed of the input capacitance of the switching element TR increases from the third timing, which is a time point after the time point when the reverse recovery current peaks in the drain current Id, thereby making it possible to reduce switching loss at the time of turn-on while suppressing the generation of noise and surges caused by the reverse recovery current. In particular, since the charging speed increases in the latter half of the turn-on operation, it is possible to quickly apply an overdrive voltage to the gate terminal of the switching element TR. As a result, it is possible to suppress the conduction loss in the latter half of the turn-on operation.

[0076] Next, the operation of the gate drive circuit GDB when the switching element TR is turned off will be described with reference to FIGS.

[0077] Fig. 15 is a first diagram showing a path of a current flowing through the gate drive circuit GDB when the switching element TR is turned off. As shown in Fig. 15, when the control unit 22 turns off the switching element TR, at a fourth timing, the control unit 22 turns off the first switch SW1 and turns on the second switch SW2, the third switch SW3, the fourth switch SW4, and the fifth switch SW5. As a result, after the fourth timing, a current flows through the path indicated by the dotted arrow in Fig. 15.

[0078] That is, after the fourth timing, current flows in the order of the third terminal P3, the resistive element Rg, the fourth node N4, and the fourth switch SW4, and at the same time, current flows in the order of the fourth node N4, the fifth switch SW5, the second node N2, the second switch SW2, the third node N3, and the third switch SW3, and the current is discharged via the fourth terminal P4 to the wiring connected to the source terminal of the switching element TR.

[0079] Fig. 16 is a second diagram showing the path of the current flowing through the gate drive circuit GDB when the switching element TR is turned off. As shown in Fig. 16, the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at a fifth timing after the fourth timing. As a result, after the fifth timing, the current flows through the path indicated by the dotted arrow in Fig. 16. Note that Fig. 16 shows an example in which both the second switch SW2 and the third switch SW3 are turned off.

[0080] That is, after the fifth timing, current flows through the third terminal P3, the resistive element Rg, the fourth node N4, and the fourth switch SW4 in that order, and is discharged via the fourth terminal P4 to the wiring connected to the source terminal of the switching element TR.

[0081] As in the first embodiment, in the second embodiment, the fifth timing is preset as a time point before the time point at which the peak of the surge voltage appears in the drain-source voltage Vds, and the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3 at the fifth timing thus preset. Note that the fifth timing is appropriately set according to the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0082] As described above, when the switching element TR is turned off, the input capacitance of the switching element TR is discharged through two discharge paths, the discharge path including the second switch SW2, the third switch SW3, and the fifth switch SW5, and the discharge path including the fourth switch SW4, at the beginning of the turn-off operation. This increases the discharge speed of the input capacitance of the switching element TR, thereby reducing the switching loss at the time of turn-off. In addition, from the fifth timing, which is a time point before the peak of the surge voltage appears in the drain-source voltage Vds, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4. This reduces the discharge speed before the peak of the surge voltage appears in the drain-source voltage Vds, thereby reducing the height of the peak of the surge voltage. As a result, it is possible to suppress noise and surges generated at the time of turn-off.

[0083] As described above, the gate drive circuit GDB of the second embodiment can reduce the switching loss of the switching element TR to be driven and suppress the noise and surge generated during switching, similar to the gate drive circuit GDA of the first embodiment. In addition, the configuration of the gate drive circuit GDA of the first embodiment has a restriction that the input capacitance of the switching element TR is charged with the first power supply voltage Vdd at the first timing, and then the inductor L1 is charged with energy at the second timing, or both are simultaneously started at the first timing. On the other hand, the configuration of the gate drive circuit GDB of the second embodiment does not have such a restriction. Therefore, the second embodiment has a higher degree of freedom in circuit design compared to the first embodiment.

[0084] [Variations] The present invention is not limited to the above-described embodiment, and the configurations described in this specification can be appropriately combined within a range that does not contradict each other. For example, the following modifications can be made.

[0085] (1) Fig. 17 is a circuit diagram showing a first modified example of the gate drive circuit GDA. As shown in Fig. 17, the gate drive circuit GDA may further include a second diode D2 having an anode terminal connected to the third node N3 and a cathode terminal connected to the second node N2. The second diode D2 may be a body diode parasitic to the second switch SW2.

[0086] In a first modified example of the gate drive circuit GDA, when the control unit 22 turns on the switching element TR, it turns on the first switch SW1 and turns off the second switch SW2 and the fourth switch SW4 at a first timing. The control unit 22 also turns on the third switch SW3 at a second timing before the first timing, at the first timing, or after the first timing. Furthermore, the control unit 22 turns off the third switch SW3 at a third timing after the second timing.

[0087] In this way, when the first modified example of the gate drive circuit GDA is adopted, it is not necessary to turn on the second switch SW2 at the third timing, because after the third timing, the current passing through the inductor L1 flows through the second node N2, the fourth node N4, the resistive element Rg, and the third terminal P3 via the second diode D2.

[0088] (2) FIG. 18 is a circuit diagram showing a first modified example of the gate drive circuit GDB. As shown in FIG. 18, the gate drive circuit GDB may further include a second diode D2 and a third diode D3. The second diode D2 has an anode terminal connected to the third node N3 and a cathode terminal connected to the second node N2. The third diode D3 has an anode terminal connected to the fourth node N4 and a cathode terminal connected to the second node N2. The second diode D2 may be a body diode parasitic to the second switch SW2. The third diode D3 may be a body diode parasitic to the fifth switch SW5.

[0089] In a first modified example of the gate drive circuit GDB, when the control unit 22 turns on the switching element TR, it turns on the first switch SW1 and the third switch SW3 and turns off the second switch SW2 and the fifth switch SW5 at a first timing. Also, the control unit 22 turns off the fourth switch SW4 and turns on the fifth switch SW5 at a second timing after the first timing. Furthermore, the control unit 22 turns off the third switch SW3 at a third timing after the second timing.

[0090] In this way, when the first modified example of the gate drive circuit GDB is adopted, it is not necessary to turn on the second switch SW2 at the third timing, because after the third timing, the current passing through the inductor L1 flows through the second node N2, the fifth switch SW5, the fourth node N4, the resistive element Rg, and the third terminal P3 via the second diode D2.

[0091] In the first modified example of the gate drive circuit GDB, when the control unit 22 turns off the switching element TR, at a fourth timing, the control unit 22 turns off the first switch SW1 and the fifth switch SW5 and turns on the second switch SW2, the third switch SW3, and the fourth switch SW4. In addition, at a fifth timing after the fourth timing, the control unit 22 turns off at least one of the second switch SW2 and the third switch SW3.

[0092] In this way, when the first modified example of the gate drive circuit GDB is adopted, it is not necessary to turn on the fifth switch SW5 at the fourth timing, because after the fourth timing, the current flowing from the third terminal P3 to the fourth node N4 flows through the third diode D3 to the second node N2, the second switch SW2, the third node N3, and the third switch SW3.

[0093] (3) In the gate drive circuit GDA of the first embodiment, when the sum of the conductive resistance value of the second switch SW2 and the conductive resistance value of the third switch SW3 is smaller than the conductive resistance value of the fourth switch SW4, the control unit 22 may control the gate drive circuit GDA as follows. That is, when turning off the switching element TR, the control unit 22 turns off the first switch SW1 and the fourth switch SW4 and turns on the second switch SW2 and the third switch SW3 at a fourth timing. Furthermore, the control unit 22 turns on the fourth switch SW4 and turns off at least one of the second switch SW2 and the third switch SW3 at a fifth timing after the fourth timing.

[0094] In the above case, after the fourth timing, a current flows through the third terminal P3, the resistive element Rg, the fourth node N4, the second node N2, the second switch SW2, the third node N3, and the third switch SW3 in this order, but no current flows through the fourth switch SW4. After the fifth timing, a current flows through the third terminal P3, the resistive element Rg, the fourth node N4, and the fourth switch SW4 in this order.

[0095] (4) In the gate drive circuit GDB of the second embodiment, when the sum of the on-resistance values ​​of the second switch SW2, the third switch SW3, and the fifth switch SW5 is smaller than the on-resistance value of the fourth switch SW4, the control unit 22 may control the gate drive circuit GDB as follows. That is, when turning off the switching element TR, the control unit 22 turns off the first switch SW1 and the fourth switch SW4 at a fourth timing, and turns on the second switch SW2, the third switch SW3, and the fifth switch SW5. Furthermore, at a fifth timing after the fourth timing, the control unit 22 turns on the fourth switch SW4, and turns off at least one of the second switch SW2 and the third switch SW3.

[0096] In the above case, after the fourth timing, a current flows in the order of the third terminal P3, the resistive element Rg, the fourth node N4, the fifth switch SW5, the second node N2, the second switch SW2, the third node N3, and the third switch SW3, but no current flows in the fourth switch SW4. After the fifth timing, a current flows in the order of the third terminal P3, the resistive element Rg, the fourth node N4, and the fourth switch SW4.

[0097] (5) Fig. 19 is a circuit diagram showing a second modified example of the gate drive circuit GDA. As shown in Fig. 19, the gate drive circuit GDA may include a fifth terminal P5 to which a third potential V3 lower than the first potential V1 and higher than the second potential V2 is applied. In this case, the fourth terminal P4 is directly connected to the fifth terminal P5.

[0098] The sum of the potential difference Vdd1 between the first potential V1 and the third potential V3 and the potential difference Vdd2 between the third potential V3 and the second potential V2 is equal to the first power supply voltage Vdd. When the second modified example of the gate drive circuit GDA is adopted, the power supply circuit 24 generates a DC voltage equivalent to the potential difference Vdd1 and a DC voltage equivalent to the potential difference Vdd2 and outputs them to the gate drive circuit GDA.

[0099] As described above, by adopting a configuration in which the second terminal P2 to which the third switch SW3 and the fourth switch SW4 are connected becomes a negative voltage with respect to the source terminal of the switching element TR, the turn-off operation of the switching element TR can be accelerated, and the switching loss at the time of turn-off can be further reduced. In addition, when adopting a configuration using a high-side switching element TR and a low-side switching element TR as in the bridge circuit 21, the occurrence of erroneous arcing can be suppressed. The configuration shown in FIG. 19 may be applied to the gate drive circuit GDB of the second embodiment.

[0100] The present technology can be configured as follows. (1) A gate drive circuit for driving a switching element, comprising: a first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, a third terminal connected to a gate terminal of the switching element, a first switch connected between the first terminal and a first node, a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node, an inductor connected between the first node and a third node, a second switch connected between the second node and the third node, a third switch connected between the second terminal and the third node, and a fourth switch connected between the second terminal and a fourth node, wherein the second node is directly or indirectly connected to the fourth node, and the fourth node is directly or indirectly connected to the third terminal. (2) The gate drive circuit according to (1), further comprising a fifth switch connected between the second node and the fourth node. (3) The gate drive circuit according to (1) or (2), further comprising a resistive element connected between the fourth node and the third terminal. (4) A gate drive circuit according to any one of (1) to (3), further comprising a fourth terminal connected to a source terminal or an emitter terminal of the switching element, the fourth terminal being directly connected to the second terminal. (5) The gate drive circuit according to any one of (1) to (3), further comprising a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, the fourth terminal being directly connected to the fifth terminal. (6) A power conversion device comprising: a bridge circuit having a plurality of switching elements; a plurality of gate drive circuits provided corresponding to the plurality of switching elements, the plurality of gate drive circuits driving the corresponding switching elements; and a control unit controlling the plurality of gate drive circuits, each of the plurality of gate drive circuits comprising: a first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, a third terminal connected to a gate terminal of the corresponding switching element, a first switch connected between the first terminal and a first node, a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node, an inductor connected between the first node and a third node, a second switch connected between the second node and the third node, a third switch connected between the second terminal and the third node, and a fourth switch connected between the second terminal and a fourth node, the second node being directly or indirectly connected to the fourth node, and the fourth node being directly or indirectly connected to the third terminal. (7) The power conversion device described in (6), wherein the second node is directly connected to the fourth node, and the control unit, when turning on the switching element, turns on the first switch and turns off the second switch and the fourth switch at a first timing, turns on the third switch at a second timing before the first timing, at the first timing, or after the first timing, and turns on the second switch and turns off the third switch at a third timing after the second timing. (8) The power conversion device described in (6), wherein the second node is directly connected to the fourth node, and the gate drive circuit further includes a second diode having an anode terminal connected to the third node and a cathode terminal connected to the second node, and when turning on the switching element, the control unit turns on the first switch and turns off the second switch and the fourth switch at a first timing, turns on the third switch at a second timing before the first timing, at the first timing, or after the first timing, and turns off the third switch at a third timing after the second timing. (9) The power conversion device described in (6), wherein the second node is directly connected to the fourth node, and the control unit, when turning off the switching element, turns off the first switch and turns on the second switch, the third switch, and the fourth switch at a fourth timing, and turns off at least one of the second switch and the third switch at a fifth timing after the fourth timing. (10) The power conversion device described in (6), wherein the gate drive circuit further includes a fifth switch connected between the second node and the fourth node, and the control unit, when turning on the switching element, turns on the first switch and the third switch and turns off the second switch and the fifth switch at a first timing, turns off the fourth switch and turns on the fifth switch at a second timing after the first timing, and turns on the second switch and turns off the third switch at a third timing after the second timing. (11) The power conversion device described in (6), wherein the gate drive circuit further includes a fifth switch connected between the second node and the fourth node, and a second diode having an anode terminal connected to the third node and a cathode terminal connected to the second node, and the control unit, when turning on the switching element, turns on the first switch and the third switch and turns off the second switch and the fifth switch at a first timing, turns off the fourth switch and turns on the fifth switch at a second timing after the first timing, and turns off the third switch at a third timing after the second timing. (12) The power conversion device described in (6), wherein the gate drive circuit further includes a fifth switch connected between the second node and the fourth node, and when the control unit turns off the switching element, at a fourth timing, it turns off the first switch and turns on the second switch, the third switch, the fourth switch, and the fifth switch, and at a fifth timing after the fourth timing, it turns off at least one of the second switch and the third switch. (13) The power conversion device described in (6), wherein the gate drive circuit further includes a fifth switch connected between the second node and the fourth node, and a third diode having an anode terminal connected to the fourth node and a cathode terminal connected to the second node, and when turning off the switching element, the control unit turns off the first switch and the fifth switch and turns on the second switch, the third switch, and the fourth switch at a fourth timing, and turns off at least one of the second switch and the third switch at a fifth timing after the fourth timing. (14) The power conversion device according to any one of (6) to (13), wherein the gate drive circuit further includes a resistive element connected between the fourth node and the third terminal. (15) A power conversion device described in any one of (6) to (14), wherein the gate drive circuit further includes a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and the fourth terminal is directly connected to the second terminal. (16) A power conversion device described in any one of (6) to (14), wherein the gate drive circuit further includes a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, and the fourth terminal is directly connected to the fifth terminal. (17) A motor unit comprising: a motor; and a power conversion device according to any one of (6) to (16) that supplies power to the motor. [Explanation of symbols]

[0101] Reference Signs List 1...motor unit, 2...first DC power supply, 3...second DC power supply, 10...motor, 20...power conversion device, 21...bridge circuit, 22...control unit, 23...smoothing capacitor, 24...power supply circuit, GD1 to GD6, GDA, GDB...gate drive circuit, TR1 to TR6, TR...switching element, P1...first terminal, P2...second terminal, P3...third terminal, P4...fourth terminal, P5...fifth terminal, SW1...first switch, SW2...second switch, SW3...third switch, SW4...fourth switch, SW5...fifth switch, L1...inductor, D1...first diode, D2...second diode, D3...third diode, Rg...resistance element, N1...first node, N2...second node, N3...third node, N4...fourth node

Claims

1. A gate drive circuit for driving a switching element, a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; a third terminal connected to a gate terminal of the switching element; a first switch connected between the first terminal and a first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node; an inductor connected between the first node and a third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; a fourth switch connected between the second terminal and a fourth node; Equipped with the second node is directly or indirectly connected to the fourth node; the fourth node is directly or indirectly connected to the third terminal; Gate drive circuit.

2. The gate drive circuit of claim 1 , further comprising a fifth switch connected between the second node and the fourth node.

3. The gate drive circuit according to claim 1 , further comprising a resistive element connected between the fourth node and the third terminal.

4. a fourth terminal connected to the source terminal or the emitter terminal of the switching element; The fourth terminal is directly connected to the second terminal. A gate drive circuit according to any one of claims 1 to 3.

5. a fourth terminal connected to the source terminal or the emitter terminal of the switching element; a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied; Further equipped with The fourth terminal is directly connected to the fifth terminal. A gate drive circuit according to any one of claims 1 to 3.

6. a bridge circuit having a plurality of switching elements; a plurality of gate drive circuits provided corresponding to the plurality of switching elements, respectively, for driving the corresponding switching elements; A control unit that controls the plurality of gate drive circuits; Equipped with Each of the plurality of gate drive circuits a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; a third terminal connected to a gate terminal of the corresponding switching element; a first switch connected between the first terminal and a first node; a first diode having an anode terminal connected to the first node and a cathode terminal connected to a second node; an inductor connected between the first node and a third node; a second switch connected between the second node and the third node; a third switch connected between the second terminal and the third node; a fourth switch connected between the second terminal and a fourth node; Equipped with the second node is directly or indirectly connected to the fourth node; the fourth node is directly or indirectly connected to the third terminal; Power conversion equipment.

7. the second node is directly connected to the fourth node; When the control unit turns on the switching element, At a first timing, the first switch is turned on and the second switch and the fourth switch are turned off; turning on the third switch at a second timing before the first timing, at the first timing, or at a second timing after the first timing; At a third timing after the second timing, the second switch is turned on and the third switch is turned off. The power converter according to claim 6.

8. the second node is directly connected to the fourth node; the gate drive circuit further includes a second diode having an anode terminal connected to the third node and a cathode terminal connected to the second node; When the control unit turns on the switching element, At a first timing, the first switch is turned on, and the second switch and the fourth switch are turned off; turning on the third switch at a second timing before the first timing, at the first timing, or at a second timing after the first timing; At a third timing after the second timing, the third switch is turned off. The power converter according to claim 6.

9. the second node is directly connected to the fourth node; When the control unit turns off the switching element, At a fourth timing, the first switch is turned off, and the second switch, the third switch, and the fourth switch are turned on; At a fifth timing after the fourth timing, at least one of the second switch and the third switch is turned off. The power converter according to claim 6.

10. the gate drive circuit further includes a fifth switch connected between the second node and the fourth node; When the control unit turns on the switching element, At a first timing, the first switch and the third switch are turned on, and the second switch and the fifth switch are turned off; At a second timing after the first timing, the fourth switch is turned off and the fifth switch is turned on; At a third timing after the second timing, the second switch is turned on and the third switch is turned off. The power converter according to claim 6.

11. The gate drive circuit includes: a fifth switch connected between the second node and the fourth node; a second diode having an anode terminal connected to the third node and a cathode terminal connected to the second node; Further equipped with When the control unit turns on the switching element, At a first timing, the first switch and the third switch are turned on, and the second switch and the fifth switch are turned off; At a second timing after the first timing, the fourth switch is turned off and the fifth switch is turned on; At a third timing after the second timing, the third switch is turned off. The power converter according to claim 6.

12. the gate drive circuit further includes a fifth switch connected between the second node and the fourth node; When the control unit turns off the switching element, At a fourth timing, the first switch is turned off, and the second switch, the third switch, the fourth switch, and the fifth switch are turned on; At a fifth timing after the fourth timing, at least one of the second switch and the third switch is turned off. The power converter according to claim 6.

13. The gate drive circuit includes: a fifth switch connected between the second node and the fourth node; a third diode having an anode terminal connected to the fourth node and a cathode terminal connected to the second node; Further equipped with When the control unit turns off the switching element, At a fourth timing, the first switch and the fifth switch are turned off, and the second switch, the third switch, and the fourth switch are turned on; At a fifth timing after the fourth timing, at least one of the second switch and the third switch is turned off. The power converter according to claim 6.

14. The power conversion device according to claim 6 , wherein the gate drive circuit further comprises a resistive element connected between the fourth node and the third terminal.

15. the gate drive circuit further includes a fourth terminal connected to a source terminal or an emitter terminal of the switching element; The fourth terminal is directly connected to the second terminal. The power converter according to claim 6.

16. The gate drive circuit includes: a fourth terminal connected to the source terminal or the emitter terminal of the switching element; a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied; Further equipped with The fourth terminal is directly connected to the fifth terminal. The power converter according to claim 6.

17. A motor; The power conversion device according to any one of claims 6 to 16, which supplies power to the motor; A motor unit comprising:

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