Semiconductor device and manufacturing method of the same

Abstract

To provide a semiconductor device capable of improving a write characteristic and a manufacturing method of the same.SOLUTION: A semiconductor device according to the present embodiment includes a stacked body, a semiconductor layer, a first insulating film, a first charge storage film, a second charge storage film, and a second insulating film. In the stacked body, electrode layers and insulating layers are alternately stacked in a first direction. The semiconductor layer is disposed in the stacked body along the first direction. The first insulating film is disposed between the stacked body and the semiconductor layer along the first direction. The first charge storage film is disposed between the stacked body and the first insulating film along the first direction. The second charge storage film is disposed between the electrode layers and the first charge storage film and in contact with insulating films in the first direction. The second insulating film is disposed between the electrode layers and the second charge storage film. The second charge storage film is an oxide film, a nitride film, or an oxynitride film, containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr).SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A NAND flash memory, which has memory cells arranged in three dimensions, is known as a semiconductor device. In this NAND flash memory, a stack of multiple electrode layers and insulating layers is alternately stacked, and a memory hole is provided through the stack. A charge storage layer and a semiconductor layer are provided in the memory hole, forming a memory string in which multiple memory cells are connected in series. Data is stored in the memory cell by controlling the amount of charge held in the charge storage layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0265381 [Patent Document 2] US Patent Application Publication No. 2021 / 0327898 [Patent Document 3] US Patent Application Publication No. 2021 / 0399011 [Patent Document 4] US Patent Application Publication No. 2021 / 0035801 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of improving writing characteristics and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] The semiconductor device according to the present embodiment includes a stacked body, a semiconductor layer, a first insulating film, a first charge storage film, a second charge storage film, and a second insulating film. The stacked body includes electrode layers and insulating layers alternately stacked in a first direction. The semiconductor layer is disposed in the stacked body along the first direction. The first insulating film is disposed between the stacked body and the semiconductor layer along the first direction. The first charge storage film is disposed between the stacked body and the first insulating film along the first direction. The second charge storage film is disposed between the electrode layer and the first charge storage film, and contacts the insulating film in the first direction. The second insulating film is disposed between the electrode layer and the second charge storage film. The second charge storage film is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr). [Brief description of the drawings]

[0006] [Figure 1A] 1 is a schematic cross-sectional view of a memory cell of the semiconductor device according to the first embodiment. [Figure 1B] 1 is a schematic cross-sectional view of a memory cell of the semiconductor device according to the first embodiment. [Diagram 2] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 3] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 5] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second comparative example. [Figure 13] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second comparative example. [Figure 14] FIG. 11 is a schematic cross-sectional view of a memory cell of a semiconductor device according to a second embodiment. [Figure 15] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 16] 6A to 6C are cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 17] 6A to 6C are cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 18] 6A to 6C are cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 19] 6A to 6C are cross-sectional views showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 20] 13A to 13C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first modified example of the second embodiment. [Figure 21] 13A to 13C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first modified example of the second embodiment. [Figure 22] FIG. 13 is a schematic cross-sectional view of a memory cell of a semiconductor device according to a second modification of the second embodiment. [Diagram 23] FIG. 13 is a schematic cross-sectional view of a memory cell of a semiconductor device according to a third modification of the second embodiment. [Figure 24] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Diagram 25] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 26] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 27] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 28] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 29] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. [Diagram 30] 10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to this embodiment. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0008] (First embodiment) The semiconductor device of the first embodiment is a three-dimensional NAND flash memory.

[0009] 1A and 1B are schematic cross-sectional views of a memory cell array 100 of a semiconductor device according to a first embodiment. 1A and 1B show cross sections of a plurality of memory cells MC in one memory string in the memory cell array 100.

[0010] Fig. 1A is a yz cross-sectional view of the memory cell array 100. Fig. 1A is a BB' cross-sectional view of Fig. 1B. Fig. 1B is an xy cross-sectional view of the memory cell array 100. Fig. 1B is an AA' cross-sectional view of Fig. 1A. In Fig. 1A, the area surrounded by a dashed line is one memory cell MC.

[0011] 1A and 1B, the memory cell array 100 includes a plurality of word lines 40, a semiconductor layer 32, a plurality of insulating layers 21, a tunnel insulating film 30, a charge storage film 28, a plurality of charge storage films 29, a plurality of block films 37a, a plurality of block films 37, a core insulating film 33, and a cover film 26. The plurality of word lines 40 and the plurality of insulating layers 21 form a stacked body 20.

[0012] The memory cell array 100 is provided, for example, on a semiconductor substrate (not shown). The semiconductor substrate has a surface parallel to the x-direction and the y-direction.

[0013] The word lines 40 and the insulating layers 21 are alternately stacked in the z direction (first direction) on the semiconductor substrate. The word lines 40 are arranged at intervals in the z direction. The word lines 40 are repeatedly arranged at intervals in the z direction. The multiple word lines 40 and the multiple insulating layers 21 form a stacked body 20. The word lines 40 function as control electrodes of the memory cell transistors.

[0014] The word line 40 is a plate-shaped conductor. The word line 40 is, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. The word line 40 is, for example, tungsten (W). The thickness of the word line 40 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0015] The insulating layer 21 separates the word lines 40 from each other. The insulating layer 21 electrically separates the word lines 40 from each other.

[0016] The insulating layer 21 is, for example, an oxide, an oxynitride, or a nitride. The insulating layer 21 is, for example, silicon oxide. The thickness of the insulating layer 21 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0017] The semiconductor layer 32 is provided in the stack 20. The semiconductor layer 32 extends in the z direction. The semiconductor layer 32 extends in a direction perpendicular to the surface of the semiconductor substrate.

[0018] The semiconductor layer 32 is provided to penetrate the stacked body 20. The semiconductor layer 32 is surrounded by a plurality of word lines 40. The semiconductor layer 32 has, for example, a cylindrical shape. The semiconductor layer 32 functions as a channel of the memory cell transistor.

[0019] The semiconductor layer 32 is, for example, a polycrystalline semiconductor. The semiconductor layer 32 is, for example, polycrystalline silicon.

[0020] The tunnel insulating film 30 is provided between the semiconductor layer 32 and the word line 40. The tunnel insulating film 30 is provided between the semiconductor layer 32 and the plurality of word lines 40. The tunnel insulating film 30 is provided between the semiconductor layer 32 and the charge storage film 29. The tunnel insulating film 30 is provided between the semiconductor layer 32 and the charge storage film 28.

[0021] The tunnel insulating film 30 has a function of passing electric charges in response to a voltage applied between the word line 40 and the semiconductor layer 32 .

[0022] The tunnel insulating film 30 includes, for example, silicon (Si) and oxygen (O). The tunnel insulating film 30 includes, for example, silicon (Si), oxygen (O), and nitrogen (N).

[0023] The tunnel insulating film 30 includes, for example, silicon oxide or silicon oxynitride, and is, for example, a stacked film of a silicon oxide film, a silicon oxynitride film, and a silicon oxide film.

[0024] The thickness of the tunnel insulating film 30 in the y direction is, for example, not less than 3 nm and not more than 8 nm.

[0025] The charge storage film 28 is provided between the tunnel insulating film 30 and the charge storage film 29. The charge storage film 28 is provided between the tunnel insulating film 30 and the insulating layer 21. The charge storage film 28 is in contact with the charge storage film 29.

[0026] The charge storage film 28 functions as a seed film when the charge storage film 29 is formed by vapor phase growth.

[0027] The charge storage film 28 includes silicon (Si) and nitrogen (N). The charge storage film 28 includes, for example, silicon nitride. The charge storage film 28 is, for example, a silicon nitride film.

[0028] The charge storage film 28 includes, for example, silicon (Si), nitrogen (N), and oxygen (O). The charge storage film 28 includes, for example, silicon oxynitride.

[0029] The thickness of the charge storage film 28 in the y direction is, for example, not less than 1 nm and not more than 5 nm.

[0030] The charge storage film 29 is provided between the tunnel insulating film 30 and the word line 40. The charge storage film 29 is provided between the tunnel insulating film 30 and the block film 37. The multiple charge storage films 29 are separated from each other. Between two charge storage films 29 adjacent to each other in the z direction, the insulating layer 21 or the cover film 26 is sandwiched.

[0031] The charge storage film 29 has a function of trapping and storing electric charges. The electric charges are, for example, electrons. The threshold voltage of the memory cell transistor changes depending on the amount of electric charges stored in the charge storage film 29. By utilizing this change in threshold voltage, it becomes possible for one memory cell MC to store data.

[0032] For example, a change in the threshold voltage of a memory cell transistor changes the voltage at which the memory cell transistor turns on. If a high threshold voltage state is defined as data "0" and a low threshold voltage state is defined as data "1," then the memory cell MC can store one bit of data, either "0" or "1."

[0033] The charge storage film 29 has a higher relative dielectric constant than the charge storage film 28. The charge storage film 29 is, for example, a high-k film including a high-k material.

[0034] The charge storage film 29 is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr). The charge storage film 29 may be an oxide film, a nitride film, or an oxynitride film containing two or more of hafnium (Hf), aluminum (Al), and zirconium (Zr). A film having such a composition may be called a "high-k film." The oxynitride film contains, for example, 1% to 20% nitrogen (N).

[0035] The blocking film 37 a is provided between the charge storage film 29 and the blocking film 37 .

[0036] The blocking film 37 a has a function of blocking a current flowing between the charge storage film 29 and the word line 40 .

[0037] The blocking film 37a includes, for example, silicon oxide, and is, for example, a silicon oxide film.

[0038] The blocking film 37 is provided between the blocking film 37a and the word line 40. The blocking film 37 is in contact with the insulating layer 21 in the z direction.

[0039] The block film 37 has a function of blocking a current flowing between the charge storage film 29 and the word line 40 .

[0040] The blocking film 37 includes, for example, aluminum oxide. The blocking film 37 is, for example, an aluminum oxide layer.

[0041] The core insulating film 33 is provided in the stacked body 20. The core insulating film 33 extends in the z direction. The core insulating film 33 is provided to penetrate the stacked body 20. The core insulating film 33 is surrounded by the semiconductor layer 32. The core insulating film 33 is surrounded by a plurality of word lines 40. The core insulating film 33 is columnar. The core insulating film 33 is, for example, cylindrical.

[0042] The core insulating film 33 is, for example, an oxide, an oxynitride, or a nitride. The core insulating film 33 includes, for example, silicon oxide. The core insulating film 33 is, for example, a silicon oxide layer.

[0043] The cover film 26 is provided between the charge storage film 28 and the insulating layer 21. The cover film 26 is in contact with the charge storage film 28 and the insulating layer 21. The cover film 26 contains, for example, silicon and oxygen. The cover film 26 is, for example, a silicon oxide film.

[0044] The thickness of the cover film 26 in the y direction is, for example, not less than 3 nm and not more than 8 nm.

[0045] The detailed structure of the charge storage film 29 will be described later with reference to Fig. 11. The detailed composition of the charge storage film 29 will be described later.

[0046] A semiconductor device according to a first embodiment will be described with reference to Figs. 2 to 11. The semiconductor device of this embodiment is manufactured, for example, by the method described below. First, as shown in Fig. 2, insulating layers 21 and sacrificial layers 22 are alternately laminated on a semiconductor substrate 10. This forms a laminate 20 in which layers are laminated in the z direction (the vertical direction in the figure). The insulating layers 21 are, for example, silicon oxide layers. The sacrificial layers 22 are, for example, silicon nitride layers.

[0047] The insulating layer 21 and the sacrificial layer 22 are formed by, for example, a chemical vapor deposition (CVD) method. A part of the insulating layer 21 becomes an interlayer insulating layer.

[0048] Next, a memory hole 24 is formed in the stack 20 along the z direction as shown in Fig. 3. The semiconductor substrate 10 is omitted from Fig. 3 and subsequent figures. This memory hole 24 penetrates the stack 20 that constitutes the insulating layer 21 and the sacrificial layer 22. This memory hole 24 is formed by using, for example, a lithography method and a RIE (Reactive Ion Etching) method.

[0049] Next, as shown in FIG. 4, a silicon oxide film is formed as a stopper film (cover film) 26 on the inner wall of the memory hole 24. On the cover film 26, a silicon nitride film having a thickness of, for example, 2 nm is formed as a charge storage film 28 that becomes a part of the charge storage film. On the charge storage film 28, a silicon oxynitride film having a thickness of, for example, 5 nm is formed as a tunnel insulating film 30. On the tunnel insulating film 30, a semiconductor layer 32 having a thickness of, for example, 7 nm is formed. The cover film 26, the charge storage film 28, and the tunnel insulating film 30 are formed by, for example, a CVD method. Polysilicon is typically used as the material of the semiconductor layer 32. However, from the viewpoint of surface roughness, a method is used in which amorphous silicon is formed at a low temperature (for example, about 500° C.) and then heat-treated at, for example, 800° C. or higher to crystallize the material. Note that the materials of the cover film 26, the charge storage film 28, and the tunnel insulating film 30 are only examples, and are not particularly limited as long as they are materials capable of realizing the structure of the semiconductor device of the embodiment described in FIG. 1A, FIG. 1B, and FIG. 11 below.

[0050] Next, as shown in Fig. 5, the memory hole 24 is filled with a core insulating film 33. The core insulating film 33 is, for example, a silicon oxide film. In the following description, the cross section is symmetrical with respect to the center line CC shown in Fig. 5, so the cross section on the left side of the center line CC will be described. Note that the tunnel insulating film 30, the semiconductor layer 32, and the core insulating film 33 are not shown in the following drawings.

[0051] Thereafter, a groove penetrating the stack 20 is opened around the memory hole 24, and the sacrificial layer 22 is removed from this groove. By removing the sacrificial layer 22, the cover film 26 is exposed. A heated phosphoric acid chemical is usually used to remove the sacrificial layer 22. This chemical process creates a void 22a in the place where the removed silicon nitride layer was. The void 22a is created so as to trace the shape of the original sacrificial layer 22 (see FIG. 6).

[0052] The insulating layer 21 has a thickness T21 in the z direction of, for example, 20 nm. The cover film 26 has a thickness T26a in the y direction of, for example, 7.0 nm.

[0053] 7, the cover film 26 is partially removed by a hydrofluoric acid (HF) solution diluted to about 0.5%, so that a part of the charge storage film 28 is exposed in the gap 22a.

[0054] The diluted hydrofluoric acid (HF) chemical also removes a portion of the surface of the insulating layer 21. Since the etching rate of the cover film 26 is lower than that of the insulating layer 21, a skirt portion 26h that contacts the charge storage film 28 is formed in the cover film 26.

[0055] Next, as shown in FIG. 8, an inhibitor IN is supplied. The inhibitor IN terminates the surfaces of the insulating layer 21 and the cover film 26. The inhibitor IN inhibits the adsorption of a precursor of the charge storage film 29 to the insulating layer 21 and the cover film 26 for the subsequent selective growth of the charge storage film 29. Note that the inhibitor IN is omitted from FIG. 9 onwards. Also, a step of removing the inhibitor IN may be added, or if the charge storage film 29 can be selectively formed on the surface of the charge storage film 28 in a subsequent step, the inhibitor does not necessarily have to be used.

[0056] 9, a charge storage film 29 is selectively grown using the exposed surface of the charge storage film 28 as a base point. The charge storage film 29 has a higher relative dielectric constant than the charge storage film 28. The charge storage film 29 is, for example, the high-k film described above. In this example, the charge storage film 29 is, for example, HfN, HfO2, or HfON.

[0057] The deposition (selective growth) of HfN as the charge storage film 29 is performed by ALD (Atomic Layer Deposition) method, which consists of one cycle of supplying HfCl4, evacuation / purging, and supplying NH3. HfCl4 is supplied at a processing temperature of, for example, 200°C to 450°C. NH3 is supplied at a processing temperature of, for example, 200°C to 450°C.

[0058] In addition, HfO2 may be formed as the charge storage film 29 by oxidizing HfN after its formation. The oxidation process may be, for example, dry oxidation, wet oxidation, or radical oxidation. In addition, HfON may be formed as the charge storage film 29. When HfON is formed from HfN, for example, the temperature and / or time of the oxidation process may be appropriately changed as parameters so as to obtain a desired N concentration. In addition, the composition of the charge storage film 29 is not limited to HfN, HfO2, or HfON, as will be described later.

[0059] The charge storage film of the embodiment includes a charge storage film 28 and a charge storage film 29. This process forms the charge storage film 29, which is a part of the charge storage layer, with a thickness in the y direction of about 1 nm to about 2 nm. As a result, in the y direction of the gap 22a, the thickness of the charge storage film in the y direction is the sum of the thickness of the charge storage film 28 (about 1 nm to about 3 nm) and the thickness of the charge storage film 29 (about 1 nm to about 2 nm). However, the charge storage film in the region where the charge storage film 29 is not provided becomes the charge storage film 28, and the thickness thereof is about 1 nm to about 3 nm. That is, the charge storage film 28 constituting the charge storage film is continuous in the extending direction (z direction) of the semiconductor layer 32, but the charge storage film 29 is divided in the z direction by the cover film 26. Therefore, a pseudo-divided structure of the charge storage film is formed.

[0060] 9, the upper and lower ends of the charge storage film 29 may be less likely to be formed thicker than the central portion. This is because, for example, when an inhibitor IN is used to inhibit the adsorption of the precursor to the insulating layer 21 and the cover film 26 during selective growth of the charge storage film 29, the inhibitor IN may slightly adhere to the surface of the charge storage film 28 near the cover film 26. Even if the inhibitor IN is not used, the upper and lower ends of the charge storage film 29 may be less likely to adsorb the silicon raw material than the central portion.

[0061] The surface of the charge storage film 29 facing the laminated body 20 has a convex shape facing the laminated body 20. The thickness T29 of the charge storage film 29 in the y direction is, for example, 1 nm to 2 nm. The width W29 indicates the width of the charge storage film 29 in the z direction.

[0062] Moreover, the charge storage film 29 is disposed so as to protrude in the y direction from the charge storage film 28 towards the stacked body 20. Therefore, the charge storage film 28 has no irregularities on the surface facing the semiconductor layer 32. That is, the surface of the charge storage film 28 facing the semiconductor layer 32 is approximately flat. The thickness of the charge storage film 28 in the y direction is approximately constant along the z direction. In the region where the charge storage film 29 is provided, the charge storage film is thicker in the y direction.

[0063] 10, a block film 37a is selectively formed on the charge storage film 29. When the charge storage film 29 is made of, for example, HfON or HfAlON, the surface OH groups are dissociated by crystallization (the H concentration in the film is, for example, 1.0×10 19 ~1.0×10 21 atoms / cm 3 As a result, a silicon nitride film can be formed on the charge storage film 29 by a process using an inhibitor in the same manner as in the case of forming a silicon nitride film on a silicon nitride film. Thereafter, the formed silicon nitride film is oxidized to convert the formed silicon nitride film into a silicon oxide film. As a result, a block film 37a including a silicon nitride film is selectively formed on the charge storage film 29.

[0064] The thickness of the blocking film 37a in the y direction is, for example, 5 nm to 7 nm.

[0065] 11, a block film 37 containing, for example, aluminum oxide is formed so as to cover the bottom and side surfaces of the gap 22a. A barrier metal containing, for example, TiN may be formed so as to cover the block film 37.

[0066] Next, the gap 22a is filled with a wiring material, for example, W (tungsten), to form a word line (electrode) 40, thereby completing the semiconductor device.

[0067] As described above with respect to the pseudo-divided structure of the charge storage film, the sum of the thicknesses of the charge storage film 28 and the charge storage film 29 in the y direction is greater than the thickness of the charge storage film 28 in the y direction.

[0068] As described above, in the first embodiment, the sum of the thicknesses in the y direction of the charge storage film 28 and the charge storage film 29 is greater than the thickness in the y direction of the charge storage film 28. This can improve the write characteristics.

[0069] In addition, the charge storage film 28 is continuous along the direction in which the semiconductor layer 32 serving as the channel extends (z direction), but the charge storage film 29 is divided in the direction in which the semiconductor layer 32 serving as the channel extends (z direction) by the insulating layer 21 and the cover film 26, so that it is possible to suppress the escape of charges in the direction in which the semiconductor layer 32 serving as the channel extends (z direction). As a result, according to this embodiment, it is possible to suppress the deterioration of the charge retention characteristics.

[0070] In addition, the charge storage film 29 is a high-k film. This improves the function of the charge storage film itself. As a result, the charge storage film can be made thinner and the write / erase characteristics (W / E characteristics) can be improved.

[0071] Another example of the composition of the charge storage film 29 will be described.

[0072] 9, the supply of HfCl4 may be changed or added. AlCl3 and / or ZrCl4, etc. may be supplied or added to HfCl4. As a result, for example, a charge storage film 29 containing Hf and Al, a charge storage film 29 containing Hf and Zr, a charge storage film 29 containing Hf, Al and Zr, or a charge storage film 29 containing Al and Zr may be formed.

[0073] The formation of the charge storage film 29 containing HfAlN will be described. The charge storage film 29 is formed by the ALD method in which HfCl4 is supplied, vacuuming / purging is performed, NH3 is supplied, vacuuming / purging is performed, AlCl3 is supplied, vacuuming / purging is performed, and NH3 is supplied in this order, forming one cycle. The charge storage film 29 containing HfAlN may also be formed by the ALD method in which HfCl4 is supplied, vacuuming / purging is performed, AlCl3 is supplied, vacuuming / purging is performed, and NH3 is supplied in this cycle. In the above two flow examples, the ALD method may be performed in which the order of supplying HfCl4 and AlCl3 is reversed. In addition, the ALD method may be performed using N2H4 as a nitriding agent instead of NH3.

[0074] Incidentally, after the formation of HfAlN, HfAlO2 may be formed as the charge storage film 29 by oxidizing the HfAlN. Also, for example, HfAlON may be formed as the charge storage film 29 by changing the parameters of the oxidation process.

[0075] The formation of the charge storage film 29 containing HfZrN will be described below. The charge storage film 29 is formed by the ALD method using ZrCl4 instead of AlCl3 in the above four film formation flows for the charge storage film 29 containing HfAlN.

[0076] Incidentally, after the formation of HfZrN, HfZrN may be oxidized to form HfZrO2 as the charge storage film 29. Also, for example, HfZrON may be formed as the charge storage film 29 by changing the parameters of the oxidation process.

[0077] The formation of the charge storage film 29 containing HfAlZrN will be described. The charge storage film 29 is formed by the ALD method in which steps of supplying ZrCl4, performing evacuation / purging, and supplying NH3 are inserted into the above four film formation flows of the charge storage film 29 containing HfAlN. The above steps may be inserted at any timing as long as they are after supplying NH3 and performing evacuation / purging.

[0078] Incidentally, after the formation of HfAlZrN, HfAlZrN may be oxidized to form HfAlZrO2 as the charge storage film 29. Also, for example, HfAlZrON may be formed as the charge storage film 29 by changing the parameters of the oxidation process.

[0079] The formation of the charge storage film 29 containing AlZrN will be described below. The charge storage film 29 is formed by the ALD method using ZrCl4 instead of HfCl3 in the above four film formation flows for the charge storage film 29 containing HfAlN.

[0080] Incidentally, after the formation of AlZrN, AlZrN may be oxidized to form AlZrO2 as the charge storage film 29. In addition, for example, AlZrON may be formed as the charge storage film 29 by changing the parameters of the oxidation process.

[0081] (First Comparative Example of the First Embodiment) In the first comparative example, the charge storage film 29 is not provided. The first comparative example differs from the first embodiment in that the charge storage film does not have a pseudo-divided structure and is flat. In the first comparative example, when the charge storage film, which is a silicon nitride film, has a thickness of 5 nm, the ISPP (write efficiency) is 0.77.

[0082] In contrast, in the first embodiment, when the charge storage film 29 is HfAlO (containing, for example, 75% or less Al) and the sum of the thicknesses of the charge storage film 28, which is a silicon nitride film, and the charge storage film 29 is 3 nm, the ISPP (write efficiency) is 0.90 V / V or more. Therefore, the thickness of the charge storage film including the charge storage films 28 and 29 can be reduced, and the characteristics such as ISPP can be improved.

[0083] (Second Comparative Example of the First Embodiment) A semiconductor device according to a second comparative example will be described with reference to Figures 12 and 13. The second comparative example differs from the first embodiment in that a charge storage film 29a, which is a silicon nitride film, is provided instead of the charge storage film 29.

[0084] First, in substantially the same manner as in FIGS. 2 to 5 of the first embodiment, a stacked body 20 and a memory hole 24 are formed, and in the memory hole 24, a cover film 26, a charge storage film 28, a tunnel insulating film 30, a semiconductor layer 32, and a core insulating film 33 are formed.

[0085] Next, as shown in FIG. 12, which corresponds to FIG. 6 of the first embodiment, the sacrificial layer 22 is removed.

[0086] The cover film 26 has a thickness T26b in the y direction of, for example, 9.5 nm. The charge storage film 28 has a thickness T28 in the y direction of, for example, 2.0 nm.

[0087] Next, as shown in Fig. 13, the cover film 26 is partially removed (similar to Fig. 7 of the first embodiment), and a charge storage film 29a is selectively grown using the surface of the exposed charge storage film 28 (seed film) as a base point. The charge storage film 29a is, for example, a silicon nitride film. In the example shown in Fig. 13, the cross-sectional shape of the charge storage film 29 is a convex lens shape. This leads to deterioration of the write / erase characteristics (W / E characteristics).

[0088] The thickness T29a of the charge storage film 29a in the y direction is, for example, 3.5 nm. The width W29a indicates the width of the charge storage film 29a in the z direction.

[0089] Thereafter, a semiconductor device is completed through steps similar to those shown in FIG. 11 in the first embodiment.

[0090] The charge storage film 29 is a high-k film and has a high charge trapping property, which allows the charge storage film 29 to be thinner than the charge storage film 29a.

[0091] In Fig. 13, when the thickness T28 of the charge storage film 28 is 2 nm, the thickness T26b of the cover film 26 shown in Fig. 12 needs to be 9.5 nm. Since the cover film 26 is required to function as a stopper for the phosphoric acid chemical solution, the cover film 26 is required to have a film quality similar to that of a thermal oxide film, and a selectivity ratio of the hydrofluoric acid (HF) chemical solution with the insulating layer 21 occurs. The insulating layer 21 is, for example, TEOS (Tetra-ethoxy silane). Therefore, the amount of tailing increases in proportion to the thickness T26b of the cover film 26 (the tail portion 26h becomes longer in the z direction), and the width W29a is reduced.

[0092] When the charge storage film 29 having a thickness T29 of 1 nm shown in FIG. 9 has charge trapping properties equivalent to the charge storage film 29a having a thickness T29a of 3.5 nm shown in FIG. 13, the thickness T26a of the cover film 26 shown in FIG. 6 can be reduced from the thickness T26b of 9.5 nm to 7.0 nm. This allows the bottom portion 26h of the cover film 26 shown in FIG. 9 to be shortened in the z direction, and the width W29 can be increased, for example, by 1.2 times the width W29a. As a result, the convex lens-like cross-sectional shape of the charge storage film 29 is suppressed, and the write / erase characteristics (W / E characteristics) can be improved. In addition, since the thickness T26 of the cover film 26 can be reduced, there is no need to increase the interval (margin) between the memory holes 24 during design.

[0093] In addition, since the charge storage film 29 has a high charge trapping property, there is a high possibility that charges will pass through laterally toward the adjacent cell via the levels in the charge storage film 29. Therefore, it is desirable to use the charge storage film 29 in combination with a divided structure (pseudo-divided structure or completely divided structure) of the charge storage film.

[0094] Second embodiment 14 is a schematic cross-sectional view of a memory cell array 100 of a semiconductor device according to a second embodiment. The second embodiment is different from the first embodiment in that a pseudo-divided structure of a charge storage film is formed from the memory hole 24 side, not from the stack 20 side.

[0095] In the following description, the cross section is symmetrical with respect to the center line CC shown in Fig. 5, so the cross section on the left side of the center line CC will be described. Note that the core insulating film 33 is not shown in the following drawings.

[0096] In the example shown in FIG. 14, unlike the first embodiment described with reference to FIG. 1A, a cover film 26 is not provided.

[0097] The blocking film 37a is provided so as to extend continuously along the charge storage film 28 and the charge storage film 29 in the z direction.

[0098] The memory cell array 100 further includes an insulating film 41. The insulating film 41 is provided between the insulating layer 21 and the block film 37a. The insulating film 41 includes, for example, silicon oxide.

[0099] A semiconductor device according to the second embodiment will be described with reference to Figures 15 to 19. The process shown in Figure 15 is carried out after the same processes as those shown in Figures 2 and 3.

[0100] After the memory hole 24 is formed (see FIG. 3), an insulating film 41 is selectively formed on the insulating layer 21 on the inner surface of the memory hole 24, as shown in FIG. 15. More specifically, the insulating film 41 is selectively grown from the insulating layer 21 (using the surface of the insulating layer 21 as a base point). As a result, an opening of the insulating film 41 is formed in a region corresponding to the sacrificial layer 22.

[0101] Next, as shown in FIG. 16, a block film 37a is formed on the sacrificial layer 22 and the insulating film 41.

[0102] Next, as shown in FIG. 17, the charge storage film 29 is formed on the block film 37a. The charge storage film 29 is formed by repeatedly depositing and etching the charge storage film 29. More specifically, the charge storage film 29 is formed by repeatedly depositing and etching the charge storage film 29 in-situ (in the same furnace). As a result, the charge storage film 29 is formed so that its surface is approximately flat. The charge storage film 29 is deposited by, for example, the ALD method. The charge storage film 29 is etched by, for example, atomic layer etching (ALE).

[0103] 18, the charge storage film 29 is removed until the block film 37a is exposed in a region corresponding to the insulating film 41. The charge storage film 29 is removed by, for example, wet etching using a mixed acid.

[0104] Next, as shown in FIG. 19, the charge storage film 28 is formed on the block film 37a and the charge storage film 29, the tunnel insulating film 30 is formed on the charge storage film 28, and the semiconductor layer 32 is formed on the tunnel insulating film 30.

[0105] Thereafter, the sacrificial layer 22 is removed in the same manner as in the process shown in Fig. 6, and the block film 37 and the word lines 40 are formed in the same manner as in the process shown in Fig. 11, thereby completing the semiconductor device shown in Fig. 14. Note that a barrier metal containing, for example, TiN may be formed so as to cover the block film 37.

[0106] As in the second embodiment, a pseudo-divided structure of the charge storage film may be formed from the side of the memory hole 24. The semiconductor device according to the second embodiment can obtain the same effects as the first embodiment.

[0107] 14, the surface of the charge storage film 29 facing the stacked body 20 is approximately flat along the z direction. The surface of the charge storage film 29 facing the semiconductor layer 32 is approximately flat along the z direction.

[0108] Furthermore, the roughness of the surface of the charge storage film 29 facing the semiconductor layer 32, and the charge storage film 28, the tunnel insulating film 30, and the semiconductor layer 32 in the region corresponding to the charge storage film 29 is 0.5 nm or less.

[0109] (First modified example of the second embodiment) A semiconductor device according to a first modified example of the second embodiment will be described with reference to Figures 20 and 21. The first modified example of the second embodiment differs from the second embodiment in that the frontage (edge) of the opening of the insulating film 41 is not rectangular.

[0110] The process shown in Fig. 20 corresponds to the process shown in Fig. 16 in the second embodiment. As shown in Fig. 20, due to the footing of the insulating film 41, it may be difficult to form the opening of the insulating film 41 into a rectangular shape.

[0111] The process shown in Fig. 21 corresponds to the process shown in Fig. 18 in the second embodiment. As shown in Fig. 21, the charge storage film 29 is formed so as to have a substantially flat surface, that is, so as to be flush with the surface of the block film 37a.

[0112] As in the first modification of the second embodiment, the frontage (edge) of the opening of the insulating film 41 does not have to be rectangular. The semiconductor device according to the first modification of the second embodiment can obtain the same effects as the second embodiment.

[0113] (Second modified example of the second embodiment) 22 is a schematic cross-sectional view of a memory cell array 100 of a semiconductor device according to a second modification of the second embodiment. The second modification of the second embodiment differs from the second embodiment in that the charge storage film 28 is a high-k film.

[0114] The charge storage film 28 is a high-k film. The charge storage film 28 is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr). The charge storage film 28 may be an oxide film, a nitride film, or an oxynitride film containing two or more of hafnium (Hf), aluminum (Al), and zirconium (Zr). The composition of the charge storage film 28 is the same as the composition of the charge storage film 29, but may be different.

[0115] As in the second modification of the second embodiment, the charge storage film 28 may be a high-k film. The semiconductor device according to the second modification of the second embodiment can obtain the same effects as the second embodiment.

[0116] (Third modified example of the second embodiment) 23 is a schematic cross-sectional view of a memory cell array 100 of a semiconductor device according to a third modification of the second embodiment. The third modification of the second embodiment differs from the second embodiment in that the charge storage film 28 is not provided.

[0117] Since the charge storage film 28 is not provided, a completely separated structure of the charge storage film is formed. This makes it possible to further suppress the escape of charges in the direction in which the semiconductor layer 32, which becomes the channel, extends (z direction). Therefore, the charge retention characteristics can be further improved.

[0118] As in the third modification of the second embodiment, it is not necessary to provide the charge storage film 28. The semiconductor device according to the third modification of the second embodiment can obtain the same effects as the second embodiment.

[0119] Third embodiment A semiconductor device according to the third embodiment will be described with reference to Figures 24 to 30. The third embodiment differs from the second embodiment in the method of forming the insulating film 41. The steps shown in Figures 24 to 30 are performed after the same steps as those shown in Figures 2 and 3.

[0120] After the memory hole 24 is formed (see FIG. 3), an insulating film 42 is selectively formed on the sacrificial layer 22 on the inner surface of the memory hole 24, as shown in FIG. The insulating film 42 includes, for example, silicon oxide. The insulating film 42 is formed by selectively forming a silicon nitride film on the sacrificial layer 22 and oxidizing the silicon nitride film.

[0121] 25, an insulating film 43 is formed on the insulating layer 21 and the insulating film 42. The insulating film 43 includes, for example, silicon nitride. The insulating film 43 is formed by, for example, an ALD method.

[0122] 26, the insulating film 43 is removed until the insulating film 42 is exposed. The insulating film 43 is removed by wet etching using a heated phosphoric acid solution.

[0123] 27, the insulating film 42 is selectively removed. The insulating film 42 is removed by wet etching using a diluted hydrofluoric acid (HF) chemical solution. As a result, the insulating film 43 remains on the insulating layer 21.

[0124] 28, the insulating film 43 is oxidized to form the insulating film 41. The oxidation is, for example, radical oxidation.

[0125] Next, as shown in FIG. 29, a block film 37a is formed on the sacrificial layer 22 and the insulating film 41 (similar to the process shown in FIG. 16 in the second embodiment).

[0126] Next, as shown in FIG. 30, the charge storage film 29 is formed on the block film 37a (similar to the process shown in FIG. 17 in the second embodiment).

[0127] Thereafter, the semiconductor device is completed through steps similar to those in the second embodiment shown in FIG.

[0128] As in the third embodiment, a different method may be used for forming the insulating film 41. The semiconductor device according to the third embodiment can achieve the same effects as the second embodiment.

[0129] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0130] 10 semiconductor substrate, 20 laminate, 21 insulating layer, 21a impurity, 21b impurity-containing layer, 22 sacrificial layer, 22a void, 24 memory hole, 26 cover film, 28 charge storage film, 29 charge storage film, 37 block film, 37a block film, 41 insulating film, 42 insulating film, 42 insulating film

Claims

1. a laminate in which electrode layers and insulating layers are alternately laminated in a first direction; a semiconductor layer disposed in the stack along the first direction; a first insulating film disposed between the stack and the semiconductor layer along the first direction; a first charge storage film disposed between the stack and the first insulating film along the first direction; a second charge storage film disposed between the electrode layer and the first charge storage film and in contact with an insulating film in the first direction; a second insulating film disposed between the electrode layer and the second charge storage film; Equipped with The semiconductor device, wherein the second charge storage film is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr).

2. 2. The semiconductor device according to claim 1, wherein said oxynitride film contains nitrogen (N) in an amount of 1% to 20%.

3. The semiconductor device according to claim 1 , wherein a first surface of said second charge storage film facing said stacked body has a convex shape facing said stacked body.

4. a first surface of the second charge storage film facing the stack is flat along the first direction; The semiconductor device according to claim 1 , wherein a second surface of said second charge storage film facing said semiconductor layer is flat along said first direction.

5. 2. The semiconductor device according to claim 1, wherein a roughness of the first charge storage film, the first insulating film, and the semiconductor layer in a second surface of the second charge storage film facing the semiconductor layer and in a region corresponding to the second charge storage film is 0.5 nm or less.

6. The semiconductor device according to claim 1 , wherein the first charge storage film includes SiN.

7. 2. The semiconductor device according to claim 1, wherein the first charge storage film is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr).

8. forming a laminate in which sacrificial layers and insulating layers are alternately laminated in a first direction; forming a hole penetrating the laminate in the first direction; forming a first film of an insulator on an inner surface of the hole; forming a first charge storage film on the first film; forming a second film of an insulator on the first charge storage film; forming a semiconductor layer on the second film; removing the sacrificial layer to expose the first film; removing the first film in the region where the sacrificial layer has been removed to expose the first charge storage film; selectively forming a second charge storage film on the exposed first charge storage film; forming a third film of an insulator on the second charge storage film; It is provided with The method for manufacturing a semiconductor device, wherein the second charge storage film is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr).

9. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of: oxidizing the second charge storage film after selectively forming the second charge storage film.

10. forming a laminate in which sacrificial layers and insulating layers are alternately laminated in a first direction; forming a hole penetrating the laminate in the first direction; selectively forming a third film of an insulator on the insulating layer on the inner surface of the hole; forming a fourth film of an insulator on the sacrificial layer and the third film; forming a third charge storage film on the fourth film by repeating deposition and etching of the third charge storage film; removing the third charge storage film until the fourth film in a region corresponding to the third film is exposed; forming a fourth charge storage film on the fourth film and the third charge storage film; forming a fifth film of an insulator on the fourth charge storage film; forming a semiconductor layer on the fifth film; It is provided with The method for manufacturing a semiconductor device, wherein the third charge storage film is an oxide film, a nitride film, or an oxynitride film containing at least one of hafnium (Hf), aluminum (Al), and zirconium (Zr).

11. The method for manufacturing a semiconductor device according to claim 10, wherein the etching is atomic layer etching.

12. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising: forming the third charge storage film on the fourth film by repeating deposition and etching of the third charge storage film in-situ.

13. The method of claim 10 , wherein selectively forming the third film on the insulating layer comprises selectively growing the third film from the insulating layer.

14. Selectively forming the third film on the insulating layer includes: selectively forming a sixth film of an insulator on the sacrificial layer on the inner surface of the hole; forming a seventh film of an insulator on the insulating layer and the sixth film; removing the seventh film until the sixth film is exposed; Selectively removing the sixth film; forming the third film by oxidizing the seventh film; The method for manufacturing a semiconductor device according to claim 10, comprising:

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