Display device

Abstract

To reduce manufacturing costs of a semiconductor device, to improve the aperture ratio of a semiconductor device, to make a display portion of a semiconductor device display a higher-definition image, and to provide a semiconductor device which can be operated at high speed.SOLUTION: A display device is provided that includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Metal oxides having light transmitting properties are used in semiconductor devices. For example, indium oxide Conductive metal oxides such as indium tin oxide (ITO) (hereafter referred to as oxide conductors) are used in liquid crystal displays. It is used as a transparent electrode material required for display devices such as displays.

[0004] In addition, metal oxides that have light-transmitting properties are attracting attention as materials that exhibit semiconductor properties. For example, In-Ga-Zn-O oxides are required for display devices such as liquid crystal displays. It is expected that this technology will be applied to semiconductor materials that are used in thin film transistors (TFTs). It is expected that this technology will be applied to the channel layer of a FT (fiber-transistor-transistor).

[0005] TFTs that use metal oxides with semiconducting properties (hereinafter referred to as oxide semiconductors) can be used at low temperatures. Therefore, it is possible to manufacture alumina, which is used in display devices, etc. There is growing expectation that this material will replace or surpass rufus silicon.

[0006] In addition, both the oxide conductor and the oxide semiconductor have light-transmitting properties. By constructing a TFT using this, it is possible to fabricate a TFT having light-transmitting properties (for example, For example, see Non-Patent Document 1.

[0007] In addition, the TFT using an oxide semiconductor has a high field effect mobility. It is also possible to configure a driving circuit for a display device or the like using the above (for example, see Non-Patent Document 2). ). [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Tetsuo Nozawa, "Transparent Circuits," Nikkei Electronics, 2007.8.27 (no.959), pp.39-52 [Non-Patent Document 2] T.Osada, and 8 others, SID '09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to reduce manufacturing costs of a semiconductor device.

[0010] An object of one embodiment of the present invention is to improve the aperture ratio of a semiconductor device.

[0011] An object of one embodiment of the present invention is to improve the resolution of a display portion of a semiconductor device.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed operation. [Means for solving the problem]

[0013] One embodiment of the present invention is a display device having a driver circuit portion and a display portion over the same substrate. The source electrode (also called the source electrode layer) and the drain electrode (also called the drain electrode layer) are made of metal. and a driver circuit TFT having a channel layer made of an oxide semiconductor. The display section has a source electrode and a drain electrode, and a driving circuit wiring made of metal. The doped electrode is made of an oxide conductor and the semiconductor layer is made of an oxide semiconductor. A display device having a pixel TFT and a display wiring made of an oxide conductor. be.

[0014] In addition, Non-Patent Document 1 describes a specific process for manufacturing a TFT and other elements ( For example, the structure of the capacitor element is not disclosed. There is also no description of fabricating a TFT having light-transmitting properties.

[0015] The semiconductor device according to one embodiment of the present invention includes a driver circuit having a TFT for a driver circuit on the same substrate. A display section having a path section and a pixel TFT is manufactured. Costs can be reduced.

[0016] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of an oxide A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and a display wiring made of an oxide conductor. Therefore, the area where the pixel TFT and the pixel wiring are formed can be used as the opening. This makes it possible to improve the aperture ratio of the semiconductor device.

[0017] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of an oxide A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and a display wiring made of an oxide conductor. Therefore, the pixel size can be designed without being limited by the size of the pixel TFT. Therefore, the resolution of the display portion of the semiconductor device can be increased.

[0018] In the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode are formed of gold in a driver circuit portion. A TFT for a driving circuit, the TFT being made of a metal and the channel layer being made of an oxide semiconductor. and a driver circuit wiring made of metal. The driving circuit is composed of a TFT that exhibits high field effect mobility and low resistance wiring. Therefore, the semiconductor device can be a semiconductor device capable of high speed operation.

[0019] The oxide semiconductor used in this specification is InMO 3 (ZnO) m (m>0) A thin film is formed on the oxide semiconductor layer, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. In addition, M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. Indicates a metal element. For example, M can be Ga, Ga and Ni, or Ga and Ni. In some cases, the oxide semiconductor may contain the above-mentioned metal elements other than Ga, such as Fe. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In the present specification, the term "In" refers to a transition metal oxide. MO 3 (ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), M is Ga The oxide semiconductor with the structure containing In-Ga-Zn-O is called the In-Ga-Zn-O oxide semiconductor, and the thin film of the In-Ga-Zn-O oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor. It is also called n-Ga-Zn-O type non-single crystal film.

[0020] In addition to the above, In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In In addition, the above-mentioned oxide semiconductors can be used. The oxide semiconductor layer may contain silicon oxide. By including SiOx (X>0), the formation of an oxide semiconductor layer during the manufacturing process When the oxide semiconductor is subsequently subjected to a heat treatment, crystallization can be suppressed. The conductor layer is preferably in an amorphous state, and may be partially crystallized.

[0021] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), Hydrogenation or dehydrogenation is effective.

[0022] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. , that is, N-type (N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer. By carrying out the above process, the oxide semiconductor layer is made into an oxygen-excessive state, and thus the resistance is increased, that is, the oxide semiconductor layer is made into an I-type. This allows the production of semiconductor devices having thin film transistors with good electrical characteristics and high reliability. It becomes possible to manufacture and provide the device.

[0023] Dehydration or dehydrogenation is performed using inert gases such as nitrogen or noble gases (argon, helium, etc.). At 350° C. or higher, preferably 400° C. or higher but lower than the distortion point of the substrate, in an atmosphere or under reduced pressure. Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer.

[0024] The dehydration or dehydrogenation conditions are as follows: a temperature rise Desorption gas analysis (TDS: Thermal Desorption Spectroscopy) Even when measurements were taken up to 450°C using the 100°C (opy), two peaks for water were observed at least around 300°C. The heat treatment conditions should be such that no single peak is detected. Thin-film transistors using oxide semiconductor layers that have been annealed are measured up to 450℃ using TDS. Even if the temperature is measured, the water peak that appears around 300°C is not detected.

[0025] The heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is changed to The oxide semi-conductor is then cooled without exposure to air in the same furnace where it was dehydrogenated or dehydrated. It is important not to reintroduce water or hydrogen into the conductor layer. The oxide semiconductor layer is made low-resistance, that is, made N-type (N - , N + After that, the resistance is increased. When a thin film transistor is manufactured using an oxide semiconductor layer that is an i-type, The threshold voltage value of the switching element can be set to positive, so that the switching element is a normally-off switching element. This can be achieved by setting the gate voltage of the thin film transistor to a positive threshold voltage as close as possible to 0V. It is desirable for a semiconductor device (display device) to have a channel formed. If the threshold voltage of the transistor is negative, the source and drain electrodes will Current flows between the electrodes, which is called normally-on. In display devices, the electrical characteristics of the thin-film transistors that make up the circuits are important. The electrical characteristics of thin film transistors affect the performance of display devices. The threshold voltage (Vth) is important. If the threshold voltage is negative, it is difficult to control the circuit. In the case of a thin-film transistor with a high voltage value and a large absolute value of the threshold voltage, the driving voltage If the voltage is too low, the TFT will not be able to perform its switching function and may become a load. In the case of an n-channel thin film transistor, a positive voltage is applied to the gate voltage. A transistor in which a channel is formed and a drain current flows out is desirable. There are transistors in which a channel does not form unless the voltage is increased, and transistors in which a channel forms even under negative voltage conditions. A transistor in which a drain current flows due to a bias current is not suitable for use as a thin-film transistor in a circuit. It is the direction.

[0026] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. A gas atmosphere may be switched to, for example, air in the same furnace where dehydration or dehydrogenation was performed. The furnace is filled with high-purity oxygen gas or N 2 O gas, ultra-dry air (dew point Cooling is performed by filling the container with water at a temperature of -40°C or less, preferably -60°C or less.

[0027] The moisture content in the film is reduced by a heat treatment for dehydration or dehydrogenation, and then the film is Cool slowly (or cool) in an atmosphere that is not prone to dew (dew point is -40°C or less, preferably -60°C or less). The oxide semiconductor film is used to improve the electrical characteristics of thin film transistors and to facilitate mass production. This will realize thin-film transistors that are both reliable and high performance.

[0028] In this specification, under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), Alternatively, the heat treatment under reduced pressure is called a heat treatment for dehydration or dehydrogenation. This heat treatment causes H 2 Dehydrogenation is the process of removing hydrogen from the water. For convenience, this term is used to refer to the elimination of H, OH, etc. Let us assume that.

[0029] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. , that is, N-type (N - After that, the area overlapping with the drain electrode layer is converted to an oxygen-deficient type. The drain region is formed as a high-resistance drain region (also called an HRD region).

[0030] Specifically, the carrier concentration in the high-resistance drain region is 1×10 17 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least (1×10 17 / cm 3 Less than The carrier concentration in this specification is calculated from Hall effect measurements at room temperature. This refers to the carrier concentration value measured.

[0031] In addition, a low-resistance drain region (L Specifically, the carrier concentration of the low-resistance drain region may be is larger than the high resistance drain region (HRD region), for example, 1×10 20 / cm 3 End 1×10 21 / cm 3 It is within the following range.

[0032] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state. By this, the resistance is increased, that is, the I-type is formed, and a channel formation region is formed. The treatment for bringing the dehydrogenated oxide semiconductor layer into an oxygen-excess state is to perform dehydration or dehydrogenation. The oxide insulating film in contact with the hydrogenated oxide semiconductor layer is formed by a sputtering method or Heat treatment after the formation of an insulating film, or heat treatment in an atmosphere containing oxygen after the formation of an oxide insulating film, or a process of heating in an inert gas atmosphere after forming an oxide insulating film and then cooling in an oxygen atmosphere. Or, after forming the oxide insulating film, it is heated in an inert gas atmosphere and then dried with ultra-dry air (dew point is - This is carried out by cooling the mixture to a temperature of 40° C. or less, preferably −60° C. or less.

[0033] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (which overlaps with the gate electrode layer) is In order to make the channel formation region in the region where the oxygen is present, a high resistance is achieved by selectively creating an oxygen-excess state. The oxide semiconductor layer may be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. The source electrode layer and the drain electrode layer are formed of a metal electrode such as Ti. The exposed area that does not overlap with the drain electrode layer is selectively made into an oxygen-excessive state to form a channel formation area. When the oxygen-excess state is selectively created, the first layer overlapping the source electrode layer can be formed. A first high-resistance drain region and a second high-resistance drain region overlapping the drain electrode layer are formed. A region between the first high-resistance drain region and the second high-resistance drain region has a channel shape. That is, the channel forming region is self-aligned between the source electrode layer and the drain electrode layer. It is formed synthetically.

[0034] This allows the fabrication of a semiconductor device having thin film transistors with good electrical characteristics and high reliability. It will be possible to provide such information.

[0035] In addition, in the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer), By forming a drain region, it is possible to improve the reliability when forming a drive circuit. Specifically, by forming a high-resistance drain region, the high-resistance drain can be The structure is such that the conductivity can be changed stepwise from the drain region to the channel formation region. Therefore, the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated with a high resistance, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, The drain region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible to adopt a configuration in which

[0036] In addition, between the drain electrode layer (and source electrode layer) made of a metal material and the oxide semiconductor layer A low-resistance drain region (also called an LRN region) may be formed. By forming a junction region (also called an RN region), the breakdown voltage of the transistor is improved. It can be said that:

[0037] In addition, a high resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region, leakage in the channel formation region when forming a driver circuit is prevented. Specifically, the drain current can be reduced by forming a high-resistance drain region. The drain electrode layer and the source electrode layer are connected to each other as a leakage current path of the transistor. Drain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The high-resistance drain region on the side of the gate electrode is followed by the source electrode layer. The leakage current flowing from the low-resistance N-type region on the drain electrode layer side to the channel region is The gate insulating layer and the channel formation region are concentrated near the interface, which has high resistance when the transistors are turned off. The back channel portion (a part of the surface of the channel formation region that is separated from the gate electrode layer) is formed. ) can reduce the leakage current.

[0038] A first high-resistance drain region overlapping the source electrode layer and a second high-resistance drain region overlapping the drain electrode layer. The high resistance drain region is formed by a part of the gate electrode layer and the gate insulator, depending on the width of the gate electrode layer. The drain electrode layer is overlapped with the edge layer to more effectively reduce the electric field strength in the vicinity of the edge of the drain electrode layer. This can be done.

[0039] That is, the semiconductor device according to one embodiment of the present invention includes a first thin film transistor and a second thin film transistor over the same substrate. The pixel portion has a driver circuit having a second thin film transistor. The transistor has a bottom gate electrode on a substrate, a gate insulating layer on the bottom gate electrode, and a gate an oxide semiconductor layer on the insulating layer; and a second channel protection layer in contact with a part of the oxide semiconductor layer. A source electrode and a drain electrode are formed on the second channel protection layer and the oxide semiconductor layer, and a second A pixel electrode layer is provided on the channel protection layer. A gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, a drain electrode, a second channel The pixel electrode layer and the protective layer are light-transmitting. The source electrode and the drain electrode of the second thin film transistor are made of the same material as the source electrode and the drain electrode of the second thin film transistor. The material is different from that of the source electrode and the drain electrode of the second thin film transistor, and the resistance of the source electrode and the drain electrode of the second thin film transistor is lower than that of the drain electrode of the second thin film transistor. It is characterized by being made of a conductive material.

[0040] Further, one embodiment of the present invention is a semiconductor device comprising: a first channel protection layer in contact with a part of the oxide semiconductor layer of the thin film transistor; The semiconductor device is characterized in that a source electrode and a drain electrode are provided on the channel protective layer and the oxide semiconductor layer. It is a semiconductor device.

[0041] Further, one embodiment of the present invention is a semiconductor device comprising: a first channel protection layer in contact with a part of the oxide semiconductor layer of the thin film transistor; A source electrode and a drain electrode are provided on the channel protective layer and the oxide semiconductor layer. The back gate electrode is provided on the channel forming region via the first channel protection layer. The semiconductor device is as follows.

[0042] Further, one embodiment of the present invention is a semiconductor device comprising: a first channel protection layer and a second channel protection layer; The channel protection layer is made of an insulating material having the same light-transmitting property. .

[0043] Further, one embodiment of the present invention is a semiconductor device comprising: The electrodes and drain electrodes are made of elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The present invention is characterized by being made up of a laminated film that combines a film having the main component thereof or an alloy film thereof. It is a semiconductor device.

[0044] Further, one aspect of the present invention is a semiconductor device comprising: The source electrode layer, the drain electrode layer, and the pixel electrode layer are made of indium oxide, indium oxide oxide, A semiconductor characterized in that it is a tin alloy, an indium oxide zinc oxide alloy, or zinc oxide. It is a device.

[0045] Further, one embodiment of the present invention is a semiconductor device further comprising a capacitor portion on the same substrate. The capacitance section has a capacitance wiring and a capacitance electrode overlapping the capacitance wiring, and the capacitance wiring and the capacitance electrode are The semiconductor device has light-transmitting properties. Effect of the Invention

[0046] A thin film transistor having stable electrical characteristics can be manufactured and provided. It is possible to provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Cut. [Brief description of the drawings]

[0047] [Figure 1] 1A to 1C are diagrams illustrating thin film transistors. [Diagram 2] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Diagram 3] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 4] 1A to 1C are diagrams illustrating thin film transistors. [Diagram 5] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 6] 1A to 1C illustrate a method for manufacturing a thin film transistor. [Figure 7] 1A to 1C are diagrams illustrating thin film transistors. [Figure 8]1A to 1C are diagrams illustrating thin film transistors. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating a display device. [Figure 13] 1A and 1B are diagrams illustrating a display device. [Figure 14] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 15] 1A and 1B are diagrams illustrating a display device. [Figure 16] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 17] 1A and 1B are diagrams illustrating a display device. [Figure 18] 1A and 1B are diagrams illustrating a display device. [Figure 19] 1A and 1B are diagrams illustrating a display device. [Figure 20] 1A and 1B are diagrams illustrating a display device. [Figure 21] 1A and 1B are diagrams illustrating a display device. [Figure 22] FIG. 1 is an external view showing an example of an electronic book. [Figure 23] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 24] FIG. 1 is an external view showing an example of a gaming machine. [Diagram 25] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33]1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 38] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 39] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 40] 1A to 1C are diagrams illustrating a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. In addition, the present invention is not limited to the above embodiment. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The repeated explanation will be omitted.

[0049] (Embodiment 1) This embodiment describes a thin film transistor according to one embodiment of the present invention and a manufacturing method thereof. Reveal.

[0050] FIG. 1A illustrates a cross-sectional view of thin film transistors 141 and 142 which are embodiments of the present invention. The thin film transistors 141 and 142 are formed on the same substrate 100. The thin film transistor 141 is disposed in the driving circuit and The film transistors 142 are arranged in pixels.

[0051] FIG. 1C1 shows a plan view of a channel stop type thin film transistor 141 arranged in a driving circuit. 1(C1) is a cross-sectional view taken along line C1-C2 in FIG. 1(B) is a cross-sectional view taken along line C3-C4 of FIG. 1(C1).

[0052] FIG. 1C2 shows a channel stop type thin film transistor 142 arranged in a pixel. FIG. 1(A) is a cross-sectional view taken along line D1-D2 in FIG. 1(C2). FIG. 1B is a cross-sectional view taken along line D3-D4 in FIG. 1C2.

[0053] The thin film transistor 141 includes a first bottom gate electrode 111 provided on a substrate 100, The gate insulating film 102, the third oxide semiconductor layer 113c, and the fourth oxide semiconductor region 113 d), a first channel protection layer 116, a source electrode, and The source electrode and the drain electrode are made of a first transparent material that transmits visible light. A conductive layer in which a second conductive layer 115a is laminated on the first conductive layer 114a, and a first conductive layer 115b that transmits visible light The conductive layer 115 is formed by laminating a first conductive layer 114b and a second conductive layer 115b on the first conductive layer 114b. Furthermore, a first protective insulating film 107 and a second protective insulating film 108 are formed in contact with and cover the first channel protective layer 116. a second protective insulating film 108 and a third oxide semiconductor layer 109 provided on the second protective insulating film 108; A back gate electrode 129 is provided so as to overlap with 113c.

[0054] The fourth oxide semiconductor region 1 having low resistance and in contact with the lower surfaces of the source electrode and the drain electrode 13d is formed in a self-aligned manner with respect to the channel protection layer. The thin film transistor 141 to be described is one mode of a channel stop type.

[0055] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this paper, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. The thin-film transistors that make up the MOSFET, as well as the analog components such as the sense amplifier, constant voltage generator, and VCO The thin-film transistors that make up the gate circuits have only positive polarity between the source and drain electrodes. Therefore, only the fourth oxide semiconductor region, which is required to have a high withstand voltage, is applied. The width of the fourth oxide semiconductor region 113d may be designed to be wider than the width of the other fourth oxide semiconductor region 113d. In addition, even if the width of the portion where the fourth oxide semiconductor region 113d overlaps with the bottom gate electrode is increased, good.

[0056] The thin film transistor 141 disposed in the driving circuit is a thin film transistor having a single gate structure. Although the above description is based on a transistor, a multi-gate transistor having multiple channel formation regions may be used as necessary. A thin film transistor having the above structure can also be formed.

[0057] In addition, a backgate electrode 129 is provided so as to overlap with the oxide semiconductor layer 113. The top electrode 129 is electrically connected to the bottom gate electrode 111 and is at the same potential. The oxide semiconductor layer 113 disposed between the main gate electrode 111 and the back gate electrode 129 A gate voltage can be applied from above and below. When the gate electrode 129 is set to a different potential, for example, a fixed potential, GND, or 0V, Electrical properties, such as threshold voltage, can be controlled. The conductive layer formed above and overlapping the nitride semiconductor layer 113 is backed up regardless of its potential. The back gate electrode 129 is called the gate electrode 129. Therefore, the back gate electrode 129 is in a floating state. It's fine.

[0058] In addition, the first protective insulating film 107 is provided between the back gate electrode 129 and the oxide semiconductor layer 113. Then, a second protective insulating film 108 is laminated.

[0059] The thin film transistor 142 includes a second bottom gate electrode 211 provided over the substrate 100, The gate insulating film 102, the third oxide semiconductor layer 213c, and the fourth oxide semiconductor region 213 d), a second channel protection layer 216, a source electrode, and Drain electrodes (214a, 214b) are provided. In addition, the second channel protection layer 216 is provided with A first protective insulating film 107 and a second protective insulating film 108 are provided to cover these. .

[0060] The fourth oxide semiconductor region 2 having low resistance in contact with the lower surfaces of the source electrode and the drain electrode 13d is formed in a self-aligned manner. The transistor 142 is a type of channel stop type. A pixel electrode 128 is provided that overlaps the film transistor 142 .

[0061] However, liquid crystal display devices are driven by alternating current to prevent deterioration of the liquid crystal. By this operation, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternate between the source electrode and the drain electrode. In this specification, for convenience, one of the electrodes of the thin film transistor of the pixel is One is called the source electrode and the other is called the drain electrode, but in reality, only one is used during AC drive. The electrodes alternately function as source and drain electrodes. In order to achieve this, the width of the second bottom gate electrode of the thin film transistor 142 disposed in the pixel is set to be smaller than that of the driving circuit. The width of the first bottom gate electrode of the thin film transistor 141 may be narrower than that of the first bottom gate electrode of the thin film transistor 141. In order to reduce leakage current, the bottom gate of the thin film transistor 142 disposed in the pixel is The electrodes may be designed so that they do not overlap the source or drain electrodes.

[0062] In addition, the thin film transistor 142 disposed in the pixel is a thin film transistor having a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. A thin film transistor having the above structure can also be formed.

[0063] The thin film transistor 142 includes a third oxide semiconductor layer 213c that transmits visible light and A second bottom gate electrode 211 and a source electrode and a second bottom gate electrode 212 are formed using a conductive film that transmits visible light. Drain electrodes (214a, 214b), a substrate 100 that transmits visible light, and a The second channel protection layer 216, the first protection insulating film 107, and the second protection insulating film 10 Therefore, the thin film transistor 142 is a so-called transparent transistor that transmits visible light. It is a ninja.

[0064] 2A to 3C are cross-sectional views showing manufacturing steps of the thin film transistors 141 and 142. FIG.

[0065] The substrate 100 is transparent to visible light and has an insulating surface. Glass used in the electronics industry such as aluminoborosilicate glass and barium borosilicate glass Glass substrates that can withstand the processing temperatures of this manufacturing process (also called "alkali-free glass substrates"). A substrate having an insulating surface such as a plastic substrate having heat resistance can be used. If 100 is the mother glass, the first generation (320mm x 400mm), the second generation (400 mm×500mm), 3rd generation (550mm×650mm), 4th generation (680mm×8 80mm, or 730mm x 920mm), 5th generation (up to 1000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800mm, 2450mm x 3050mm), 10th generation (2950 Sizes such as 3400 mm x 3,400 mm can be used.

[0066] In addition, a base insulating layer is provided between the substrate 100 and the first bottom gate electrode 111 and between the substrate 100 and the The insulating base layer may be provided between the second bottom gate electrodes 211. An insulating film that prevents elements (such as sodium) from diffusing into thin-film transistors. For example, silicon nitride, silicon oxide, silicon nitride oxide, or oxide may be used. The insulating film can be formed by laminating one or more films selected from silicon nitride films.

[0067] A first bottom gate electrode 111 and a second bottom gate electrode 112 are formed on a substrate 100 having an insulating surface. The electrode 211 is provided. The first bottom gate electrode 111 and the second bottom gate electrode 211 is formed using a conductive film that transmits visible light.

[0068] The first bottom gate electrode 111 and the second bottom gate electrode 211 are made of a conductive material having light transmitting properties. Conductive materials, such as indium oxide, including tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, Indium tin oxide with silicon dioxide added, In-Sn-Zn-O system, In-Al-Zn- O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, S Translucency of n-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. The thickness of the film is appropriately selected within the range of 50 nm to 300 nm. Complete.

[0069] In addition, for example, In (indium), Ga ( Gallium) and Zn (zinc)-containing oxide semiconductor targets (In 2 O 3 :Ga 2 O 3 Indium, gallium, and zinc obtained using ZnO = 1:1:1 (molar ratio) Nitrogen-containing oxynitride films, Al-Zn-O non-single crystal films, and nitrogen-containing Al-Zn-O films A non-single crystal film, i.e., an Al-Zn-ON type non-single crystal film (also called an AZON film), may be used. stomach.

[0070] The deposition method of the conductive film with light transmission is sputtering method or vacuum deposition method (electron beam deposition method, etc.). The arc discharge ion plating method and the spray method are used. Also, the sputtering method is used. If so, SiO 2 A film is formed using a target containing 2% by weight or more and 10% by weight or less of The transparent conductive film is made to contain SiOx (X>0), which inhibits crystallization, and is then processed in a later step. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. It is.

[0071] The wiring layer including the first bottom gate electrode 111 is the same as the second bottom gate electrode 211. The insulating layer 11 may be formed using a conductive material that transmits visible light, but is preferably formed using a material that transmits visible light, such as molybdenum or tungsten. Using metal materials having any heat resistance or alloy materials mainly composed of these, may be formed by laminating.

[0072] The wiring layer including the first bottom gate electrode 111 is made of the same conductive material as the second bottom gate electrode 211. It is preferable to form the first bottom gate electrode using a thin film because the number of steps can be reduced. The wiring layer including the electrode 111 is made of a heat-resistant metal material or an alloy material mainly composed of the metal material. It is preferable to use such a material since it is possible to reduce the wiring resistance.

[0073] For example, when the wiring layer including the first bottom gate electrode 111 has a two-layer laminated structure, Two-layer structure with a molybdenum layer laminated on an aluminum layer, or a molybdenum layer laminated on a copper layer Two-layer structure with a copper layer and a titanium nitride layer or a tantalum nitride layer laminated on the copper layer Preferably, the titanium nitride layer and the molybdenum layer are laminated to form a two-layer structure. In the case of a layered structure, a tungsten layer or a tungsten nitride layer and an aluminum and silicon layer are used. A layer of titanium nitride or titanium alloy is laminated with a layer of titanium nitride or titanium. It is preferable that the laminate has a three-layer structure.

[0074] In this embodiment, a conductive film that transmits visible light is formed on the entire surface of the substrate 100, and then the first film is A photolithography process is performed, a resist mask is formed on the conductive film, and the conductive film is By removing unnecessary portions, wiring and electrodes (the first bottom gate electrode 111 and the second A gate wiring including a bottom gate electrode 211, a capacitance wiring, a terminal electrode, and the like are formed. .

[0075] Next, a gate insulating film is formed on the first bottom gate electrode 111 and the second bottom gate electrode 211. In this embodiment, the gate insulating film 102 is formed by a single layer of silicon nitride. Complete.

[0076] The gate insulating film 102 is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon can be formed in a single layer or a multilayer structure. It was used in layers.

[0077] The gate insulating film 102 may be formed by, for example, a plasma CVD method or a sputtering method. When using the plasma CVD method, the source gas is S iH 4 and either or both of oxygen and nitrogen by plasma CVD. Alternatively, instead of oxygen and nitrogen, a silicon oxynitride layer may be formed. Either may be used.

[0078] Next, an oxide semiconductor film is formed over the gate insulating film 102.

[0079] The oxide semiconductor film is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O film, or an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S In this embodiment, an In-Ga-Zn The film is formed by sputtering using a -O-based oxide semiconductor target. The film is heated under a rare gas (typically argon) atmosphere, under oxygen atmosphere, or under a rare gas (typically The film can be formed by sputtering under an atmosphere of argon and oxygen. When using the sputtering method, SiO 2 Using a target containing 2% by weight or more and 10% by weight or less The oxide semiconductor film is then formed to contain SiOx (X>0), which inhibits crystallization, and the oxide semiconductor film is then processed in the following steps. In order to prevent crystallization during the heat treatment for dehydration or dehydrogenation, is preferred.

[0080] Next, the oxide semiconductor film is subjected to a second photolithography process to form a first oxide semiconductor island. The oxide semiconductor layer is then processed into island-shaped oxide semiconductor layers 113a and 213a (see FIG. 2A). A resist mask for forming the layer may be formed by an ink-jet method. When the inkjet method is used to form the film, no photomask is used, reducing manufacturing costs. Cut.

[0081] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The sputtering is performed by generating a gas to remove dust and other foreign matter adhering to the surface of the gate insulating film 102. It is preferable to remove it.

[0082] Reverse sputtering is a method in which RF voltage is applied to the substrate side in an argon atmosphere without applying voltage to the target side. This method uses a voltage source to generate plasma near the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, or the like may be used.

[0083] Next, the first oxide semiconductor layers 113a and 213a are dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydration or dehydrogenation is 350° C. or higher than the distortion point of the substrate. The temperature is set to less than 400° C., preferably 400° C. or more. The oxide semiconductor layer was subjected to heat treatment in a nitrogen atmosphere. By cooling the semiconductor layer without exposing it to the air, water and hydrogen are prevented from being reabsorbed into the oxide semiconductor layer. In this manner, the second oxide semiconductor layers 113b and 213b are obtained (FIG. 2). (See (B)).

[0084] In this embodiment, the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is changed to Use the same furnace until the temperature is high enough that water does not enter, specifically, 100°C higher than the heating temperature T. The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops to 100° C. The atmosphere is not limited to nitrogen, and may be helium, neodymium, etc. Dehydration or dehydrogenation is performed under an inert gas atmosphere such as argon or under reduced pressure. cormorant.

[0085] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0086] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. In some cases, the film may be a crystalline or polycrystalline film.

[0087] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. It is then removed and subjected to a second photolithography process.

[0088] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400℃ or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) 100 ℃) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0089] Next, an insulating film which is in contact with the second oxide semiconductor layers 113b and 213b and serves as a channel protective layer is formed. A channel is formed in contact with the second oxide semiconductor layers 113b and 213b. The insulating film that serves as the protective layer must be made of an oxide insulating film and have a thickness of at least 1 nm. Further, the oxide insulating film can be formed by a method such as a sputtering method, in which water or water is added to the oxide insulating film. The insulating layer can be formed by appropriately using a method that does not mix with impurities such as silicon.

[0090] In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the oxide insulating film by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. In this example, the temperature is set to 100°C. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically In the case of argon, oxygen, or rare gas (typically argon) and oxygen The reaction can be carried out in an atmosphere. The target is a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and nitrogen. Silicon oxide can be formed by sputtering in a nitrogen atmosphere. The channel protection layer formed in contact with the nitride semiconductor layer is resistant to moisture, hydrogen ions, and OH - etc. It uses an inorganic insulating film that does not contain impurities and blocks the intrusion of these substances from the outside. Typically, the film is a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film. A membrane or the like is used.

[0091] Next, a third photolithography process is performed to form a resist on the insulating film that will become the channel protection layer. A mask is formed, and unnecessary portions are removed by etching to form the first channel protection layer 116. And the second channel protection layer 216 is formed.

[0092] Next, a second heat treatment is performed in an inert gas atmosphere (preferably at 200° C. or higher and 400° C. or lower, For example, the temperature is 250°C or higher and 350°C or lower (see FIG. 2(C)). For example, the heating is performed under a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour. The second heat treatment results in the formation of a second oxide semiconductor. A part of the conductor layer 113b is heated in a state where the part is in contact with the first channel protection layer 116, and the second oxide is formed. A portion of the compound semiconductor layer 213b is heated in a state where the portion is in contact with the second channel protection layer 216. In addition, in a region of the second oxide semiconductor layer 113b that is not in contact with the first channel protection layer 116, The region of the second oxide semiconductor layer 213b that is not in contact with the first channel protection layer 216 is The material is heated while exposed to an inert gas atmosphere.

[0093] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, the channel protection film in contact with a part of the oxide semiconductor film A layer is formed using an oxide insulating film, and a region overlapping with the channel protective layer is selectively treated with an oxygen-excess As a result, the channel formation region overlapping with the channel protection layer becomes an I-type. In the text, this I-type oxide semiconductor is called the third oxide semiconductor. The second oxide semiconductor layer 113b that is in contact with the oxide semiconductor protective layer 116 and is subjected to the second heat treatment is The third oxide semiconductor layer 113c is in contact with the second channel protective layer 216. The second oxide semiconductor layer 213b subjected to the heat treatment becomes a third oxide semiconductor layer 213c.

[0094] On the other hand, in a region of the second oxide semiconductor layer 113b that is not in contact with the first channel protection layer 116, In a region of the second oxide semiconductor layer 213b that is not in contact with the first channel protection layer 216, In this specification, the high resistance drain region is formed in a self-aligned manner. The region in contact with the first channel protection layer 116 is called a fourth oxide semiconductor region. The remaining second oxide semiconductor layer 113b becomes a fourth oxide semiconductor region 113d. The second oxide semiconductor layer 213b not in contact with the channel protection layer 216 is a fourth oxide semiconductor This becomes area 213d.

[0095] Next, visible light is applied to the gate insulating film 102 and the fourth oxide semiconductor regions 113d and 213d. A conductive film that is transparent to the light is formed.

[0096] The deposition method of the conductive film with light transmission is sputtering method or vacuum deposition method (electron beam deposition method, etc.). The conductive film is made of the following materials: , conductive materials having transparency to visible light, such as In-Sn-Zn-O, In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O The metal oxide of Zn-O system can be applied, and the film thickness is 50 nm to 300 nm. In addition, when the sputtering method is used, SiO 2 2% by weight or more The film is formed using a target containing 0.01 wt % or less of a substance that inhibits crystallization of the light-transmitting conductive film. The inclusion of SiOx (x>0) prevents crystallization during the heat treatment in the subsequent process. It is preferable to control

[0097] Next, a metal conductive film is formed on the conductive film that transmits visible light. Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or elements containing the above elements The titanium layer may be an aluminum layer on a titanium layer, or an alloy of the above elements. and a three-layer laminate structure in which a titanium layer is laminated on the aluminum layer, or a molybdenum layer The aluminum layer is then laminated on the molybdenum layer to form a three-layer laminate structure. Of course, the metal conductive film may be a single layer, a two-layer structure, or a stack of four or more layers. It may also have a layered structure.

[0098] Next, a resist mask 134 is formed by a fourth photolithography process, and selectively etched. The conductive film that transmits visible light is etched away, and the unnecessary parts of the metal conductive film are etched away. The conductive film that transmits visible light and the metal conductive film are laminated to form an electrode layer (Figure 3(A)). reference).

[0099] In this etching, the first channel protection layer 116 and the second channel protection layer The third oxide semiconductor layers 113c and 213c function as an etching stopper. Therefore, the third oxide semiconductor layers 113c and 213c are not etched.

[0100] A first channel protection layer 116 is provided on a channel formation region of the third oxide semiconductor layer 113c. A second channel protection layer 216 is formed on a channel formation region of the third oxide semiconductor layer 213c. Since the third oxide semiconductor layers 113c and 213c are provided with the above-mentioned structure, The area is protected from damage during the process (film loss due to plasma or etching agents during etching, Therefore, the reliability of the thin film transistors 141 and 142 is improved. It can be done.

[0101] The resist mask may be formed by an ink-jet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0102] Next, after removing the resist mask 134, a fifth photolithography process is performed to form a A wiring layer including a source electrode and a drain electrode (115a and 115b), and a thin film transistor A resist mask 135 is formed to cover the etched portion 141. Next, the resist mask 135 is used to The unnecessary conductive layers (215a, 215b) are removed by etching to form a light-transmitting source. The drain and gate electrodes (214a and 214b) are formed. The capacitors 141 and 142 are formed (see FIG. 3(B)).

[0103] Note that a high-resistance drain electrode layer or a high-resistance oxide semiconductor layer overlapping with the drain electrode layer or the source electrode layer may be formed. By forming the fourth oxide semiconductor region, which is a gate region, Specifically, the drain electrode layer to the fourth oxide semiconductor The structure is such that the conductivity can be changed stepwise from the gate region to the channel formation region. Therefore, it is possible to operate the device by connecting it to a wiring that supplies a high power supply potential VDD to the drain electrode layer. When a high electric field is applied between the gate electrode layer and the drain electrode layer, a high resistance drain is formed. The fourth oxide semiconductor region, which is a transistor region, serves as a buffer to prevent a local high electric field from being applied. In addition, the drain electrode layer may be overlapped with the transistor. In the oxide semiconductor layer, a fourth oxide semiconductor region serving as a high-resistance drain region is formed. This reduces the leakage current in the channel formation region when the driver circuit is formed. It is possible.

[0104] Specifically, the thin film transistor 141 is formed of a metal conductive film having a low wiring resistance. The conductive layer 115b serving as the drain electrode is a light-transmitting conductive layer 114b and a high-resistance drain The third oxide semiconductor region 113d is a channel formation region, and the fourth oxide semiconductor region 113c is a gate region. Therefore, the conductive layer 114 having the light transmitting property is electrically connected to the conductive semiconductor layer 113c. b can be called the low-resistance drain region (also called the LRN region). In the transistor 142, a conductive film having a light transmitting property and a fourth oxide film which is a high resistance drain region are formed. A third oxide semiconductor layer 213c serving as a channel formation region is formed through the oxide semiconductor region 213d. is connected to

[0105] Next, the resist mask 135 is removed, and the first channel protection layer 116 and the second channel A first protective insulating film 107 is formed on the film protective layer 216. The first protective insulating film 107 is a film Water, hydrogen ions, and OH -These external intrusions are reduced. Blocking. It is formed using an insulating inorganic material. Specifically, silicon oxide, oxynitride, Silicon or silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride The above may be formed as a single layer or a laminate.

[0106] Here, first, a first protective insulating film in contact with the gate insulating film 102 is formed using a silicon nitride film. The gate insulating film 102 and the first protective insulating film 107a are formed using a silicon nitride film. By forming 107a, the thin film transistors 141 and 142 are surrounded by the same insulating layer. This allows the insulating layers to be in contact with each other, improving the sealing of the thin film transistor. A protective insulating film having a different composition, for example, silicon oxynitride, is laminated on the silicon nitride to form the first insulating film. The protective insulating film 107 may be formed of the above-mentioned material.

[0107] Another example of the first protective insulating film 107 is a 300 nm thick film formed by sputtering. A silicon oxide film having a thickness of 100 nm may be formed, and then a silicon nitride film may be laminated on the silicon oxide film. The temperature is set to be equal to or higher than room temperature and equal to or lower than 300° C., and is set to 100° C. in this embodiment. The formation of silicon films by sputtering is done under a rare gas (typically argon) atmosphere or an oxygen atmosphere. Alternatively, the reaction can be carried out under a mixed gas atmosphere of rare gas (typically argon) and oxygen. In addition, a silicon oxide target can be used as the target. For example, a silicon target may be used in a sputtering process under an atmosphere containing oxygen. More silicon oxide can be formed.

[0108] Next, the second protective insulating film 108 covering the thin film transistors 141 and 142 is It is formed on the velum 107.

[0109] The second protective insulating film 108 is connected to the first channel protective layer 1 through the first protective insulating film 107. 16 and the second channel protection layer 216, and the source electrode and the drain electrode (115a, 11 5b, 214a, 214b).

[0110] The second protective insulating film 108 is, for example, a photosensitive or non-photosensitive film having a thickness of 0.5 μm to 3 μm. A photosensitive organic material can be used for the second protective insulating film 108. Photosensitive or non-photosensitive organic materials include polyimide, acrylic, polyamide, polyimide, Amidoamide, resist, benzocyclobutene, or a laminate of these In addition to the above organic materials, low-k materials are also available. ), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, A protective insulating film 108 may be formed.

[0111] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0112] The method for forming the second protective insulating film 108 is not particularly limited. Depending on the material, the method may be a sputtering method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, spin Clean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A coater, knife coater, etc. can be used.

[0113] In this embodiment, the second protective insulating film 108 is formed by coating photosensitive polyimide. After polyimide is applied to the entire surface, it is exposed to light, developed, and baked to form a flat surface. A second protective insulating film 108 made of flat polyimide having a thickness of 1.5 μm is formed.

[0114] By providing the second protective insulating film 108, the thin film transistors 141 and 142 are The unevenness caused by the resin layer can be reduced and the upper surface can be made flat. The surface must be formed using a method that results in a flat surface (such as spin coating or reflow). It would be good if it could be done.

[0115] Next, the first protective insulating film 107 is opened by etching, and the thin film transistor 142 is A contact hole 125 reaching the drain electrode 214b is formed.

[0116] In the thin film transistor 141, the back gate electrode 129 is connected to the first bottom gate In the case of connecting to the electrode 111, before forming a conductive film to be the back gate electrode 129, The second protective insulating film 108, the first protective insulating film 107 and the gate insulating film 102 are shown in the figure. An opening is provided at a predetermined location where there is no opening.

[0117] Next, a conductive film that transmits visible light is formed on the second protective insulating film 108. The conductive film includes a first bottom gate electrode 111 and a second bottom gate electrode 211. In addition, the back gate electrode 129 and the pixel electrode 12 The process can be simplified by using the same material for 8.

[0118] Next, a sixth photolithography step is performed to form a resist mask over the conductive film, The unnecessary parts are removed by etching to form the back gate electrode 129 and the pixel electrode 128. A wiring layer is formed. The wiring layer including the back gate electrode 129 and the pixel electrode 128 is selectively formed. When etching is performed to obtain a desired top surface shape, the second protective insulating film 108 acts as an etching stopper. It functions as a par.

[0119] The back gate electrode 129 is a third oxide semiconductor between the source electrode and the drain electrode. The layer 113c may be disposed to cover the area overlapping with the first channel protection layer 116. By shortening the width of the back gate electrode 129, the parasitic capacitance can be reduced.

[0120] The pixel electrode 128 is connected to the drain electrode 214b of the thin film transistor 142 through a contact hole. The connection is made via a cable 125 (see FIG. 3(C)).

[0121] In addition, the thin film transistor 141 and Heat treatment may be performed on 142. The heat treatment is preferably performed at a temperature of 350° C. or less. This may be done at any time after the insulating film that will become the first protective insulating film 107 is formed. For example, The heat treatment is performed at 350° C. for 1 hour in a 350° C. atmosphere. This can reduce the variation in electrical characteristics of 41 and 142.

[0122] By going through the above steps, thin film transistors 141 and 142 shown in FIG. 1(A) are formed. It can be achieved.

[0123] In addition, in FIG. 2(A) and FIG. 2(B), before forming the insulating film to be the channel protection layer, Then, exposed portions of the second oxide semiconductor layers 113b and 213b are subjected to oxygen radical treatment. By performing oxygen radical treatment, the vicinity of an exposed surface of the oxide semiconductor layer may be improved. Oxygen radicals can be generated by using a gas containing oxygen to create an oxygen-excess region. It may be supplied by a Zuma generator or an ozone generator. The second oxide semiconductor is formed by irradiating the thin film with the supplied oxygen radicals or oxygen. The surfaces of the layers 113b and 213b (surfaces of the back channel portion) can be modified. In addition, the radical treatment is not limited to oxygen radical treatment, and radical treatment using argon and oxygen may be performed. The argon and oxygen radical treatment is a process in which argon gas and oxygen gas are introduced to generate plasma. The aim of this study is to modify the thin film surface by using a fluorine-containing solution.

[0124] In addition, a two-layered film consisting of a silicon oxide film formed on a silicon nitride film is used as a gate insulating film. The configurations of the thin film transistor 210 and the thin film transistor 220 used in the device 102 are shown in FIG. When the gate insulating film 102b in contact with the oxide semiconductor layer is a silicon oxide film, the channel When the protective layer is formed from a silicon oxide film, the gate insulating film 102b is etched, and the gate The thickness of the gate insulating film 102b in the region overlapping the island-shaped oxide semiconductor layer is The thickness of the region not overlapping with the island-shaped oxide semiconductor layer of b is thin.

[0125] The thin film transistors 210 and 220 have a gate insulating film 102 and a first protective insulating film 107 alternately. The gate insulating film 102 and the first protective insulating film 107 are made of the same inorganic insulating film material. The thin film transistors 210 and 220 can be surrounded by the same insulating layer. By using a structure in which the insulating layers are in contact with each other, the sealing of the thin film transistors is improved. In the case of a structure in which the same type of inorganic insulating film is in contact with each other, the above-mentioned inorganic insulating film can be used. However, a silicon nitride film is particularly preferable because of its excellent barrier properties against impurities.

[0126] In addition, the resist mask for forming the pixel electrode 128 may be formed by the inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used, Manufacturing costs can be reduced.

[0127] Through the above steps, the thin film transistor 141 is formed on the same substrate using seven photomasks. and thin film transistor 142, or thin film transistor 210 and thin film transistor 2 20 can be made and formed separately.

[0128] The back gate electrode 129 is disposed at a position overlapping with a channel formation region of the third oxide semiconductor layer 113c. By installing the device in a position, it is possible to carry out bias-thermal stress tests to examine the reliability of thin-film transistors. In the BT test, the thin film transistor 14 In addition, the amount of change in the threshold voltage of the back gate electrode 129 can be reduced. The position of the back gate electrode 111 may be the same as or different from that of the bottom gate electrode 111. The potential of the port electrode 129 may be GND, 0 V, or may be in a floating state.

[0129] The semiconductor layer in the channel formation region of the thin film transistor of this embodiment is a high resistance region. Therefore, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained. It is possible to provide a device.

[0130] In addition, the thin film transistors 141 and 142 and the thin film transistors 210 and 220 In the present invention, a fourth oxide is formed in the source region and the drain region where the source electrode and the drain electrode are in contact with each other. Since a solid semiconductor region is formed, the contact resistance is suppressed and a high on-current is obtained. do.

[0131] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0132] (Embodiment 2) The present embodiment is one aspect of the present invention and is different from the first embodiment in that a thin film transistor and The method for producing the same will be described.

[0133] FIG. 4A shows a cross-sectional view of thin film transistors 143 and 144 which are embodiments of the present invention. The thin film transistors 143 and 144 are formed on the same substrate 100. The thin film transistor 143 is disposed in the driving circuit and The film transistor 144 is arranged in a pixel.

[0134] FIG. 4(C1) shows a plan view of a channel stop type thin film transistor 143 arranged in a driving circuit. 4(C1) is a cross-sectional view taken along line C1-C2 in FIG. 4(B) is a cross-sectional view taken along line C3-C4 in FIG. 4(C1).

[0135] FIG. 4C2 shows a channel stop type thin film transistor 144 arranged in a pixel. 4(C2) is a cross-sectional view taken along line D1-D2 in FIG. FIG. 4B is a cross-sectional view taken along line D3-D4 in FIG. 4C2.

[0136] The thin film transistor 143 includes a first bottom gate electrode 111 provided on a substrate 100 and The gate insulating film 102, the third oxide semiconductor layer 113c, and the first channel protection layer 116 and a source electrode and a drain electrode. The source electrode and the drain electrode are A conductive layer in which a second conductive layer 115a is laminated on a first conductive layer 114a, and a first conductive layer 11 The first conductive layer 115b is formed on the second conductive layer 115b. A first protective insulating film 107 and a second protective insulating film 108 are in contact with and cover the channel protective layer 116. a second protective insulating film 108 and a third oxide semiconductor layer 113c provided on the second protective insulating film 108 and overlapping the third oxide semiconductor layer 113c; A back gate electrode 129 is provided to overlap the thin film 121. The transistor 143 is one embodiment of a channel-stop type.

[0137] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this paper, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. The thin-film transistors that make up the MOSFET, as well as the analog components such as the sense amplifier, constant voltage generator, and VCO The thin-film transistors that make up the gate circuits have only positive polarity between the source and drain electrodes. Therefore, the third oxide semiconductor layer 113c is required to have a withstand voltage. The width of either the source electrode or the drain electrode may be designed to be wider than the other. In addition, the width of the third oxide semiconductor layer 113c overlapping with the bottom gate electrode may be increased. stomach.

[0138] The thin film transistor 143 disposed in the driving circuit is a thin film transistor with a single gate structure. Although the above description is based on a transistor, a multi-gate transistor having multiple channel formation regions may be used as necessary. A thin film transistor having the above structure can also be formed.

[0139] In addition, a backgate electrode 129 is provided above and overlapping with the third oxide semiconductor layer 113c. The back gate electrode 129 is electrically connected to the bottom gate electrode 111 to have the same potential. The third oxide semiconductor layer is disposed between the bottom gate electrode 111 and the back gate electrode 129. A gate voltage can be applied to the conductor layer 113c from above and below. When the back gate electrode 111 and the back gate electrode 129 are set to different potentials, for example, a fixed potential, GND, or 0V, In this case, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled. In the specification, a conductive layer formed above and overlapping the third oxide semiconductor layer 113c is referred to as a Regardless of the potential of the back gate electrode 129, the back gate electrode 12 9 may be in a floating state.

[0140] In addition, a first protective insulating film is provided between the back gate electrode 129 and the third oxide semiconductor layer 113c. The film 107 and the second protective insulating film 108 are laminated.

[0141] The thin film transistor 144 includes a second bottom gate electrode 211 provided on the substrate 100, The gate insulating film 102, the third oxide semiconductor layer 213c, and the second channel protection layer 216 and a source electrode and a drain electrode (214a, 214b). The first protective insulating film 107 and the second protective insulating film 108 are in contact with and cover the channel protective layer 216. 08 is provided. Therefore, the thin film transistor 144 described in this embodiment is This is one embodiment of a channel stop type. A pixel electrode 128 is provided so as to overlap with the capacitor 144 .

[0142] However, liquid crystal display devices are driven by alternating current to prevent deterioration of the liquid crystal. By this operation, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternate between the source electrode and the drain electrode. In this specification, for convenience, one of the thin film transistors of the pixel is referred to as a source electrode. The first electrode is called the drain electrode and the second electrode is called the drain electrode. In addition, in order to reduce leakage current, The width of the second bottom gate electrode of the thin film transistor 144 disposed in the driving circuit is set to The width of the first bottom gate electrode of the transistor 143 may be narrower than that of the first bottom gate electrode of the transistor 143. In order to reduce the number of pixels, the bottom gate electrode of the thin film transistor 144 disposed in the pixel is The gate electrode may be designed so as not to overlap with the drain electrode.

[0143] In addition, the thin film transistor 144 disposed in the pixel is a thin film transistor having a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. A thin film transistor having the above structure can also be formed.

[0144] The thin film transistor 144 includes a third oxide semiconductor layer 213c that transmits visible light, The second bottom gate electrode 211 and the source and drain electrodes are formed using a conductive film that transmits visible light. A rain electrode (214a, 214b), a substrate 100 that transmits visible light, and a The second channel protection layer 216, the first protection insulating film 107, and the second protection insulating film 108 are Therefore, the thin film transistor 144 is a so-called transparent transistor that transmits visible light. It's Jista.

[0145] The material of the oxide semiconductor layer including the channel formation region is an oxide material having semiconductor characteristics. Specifically, the oxide semiconductor material described in Embodiment 1 can be used. Cut.

[0146] In addition, in the thin film transistor of this embodiment, the third oxide semiconductor layer (113c, 213c ) in the channel formation region.

[0147] 5 and 6 are cross-sectional views showing the manufacturing process of the thin film transistors 143 and 144. A first bottom gate electrode 111 and a second bottom gate electrode 112 are formed on a substrate 100 having an edge surface. The electrode 211 is formed, and the first bottom gate electrode 111 and the second bottom gate electrode 211 are A gate insulating film 102 is formed to cover the gate insulating film 102, and an oxide semiconductor film is formed to cover the gate insulating film 102. Since the steps are the same as those in the first embodiment, detailed explanations are omitted here. The same parts will be described using the same reference numerals.

[0148] A first oxide semiconductor film is formed over the gate insulating film 102 in a manner similar to that of Embodiment 1.

[0149] Next, a second photolithography step is performed to form a resist mask on the first oxide semiconductor film. The first oxide semiconductor film is etched to form an island-shaped oxide semiconductor layer 113a and The etching method here is not limited to wet etching. Dry etching may also be used (see FIG. 5(A)).

[0150] Next, the first oxide semiconductor layers 113a and 213a are subjected to a first heating process in a manner similar to that of the first embodiment. The first oxide semiconductor layers 113a and 213a are subjected to treatment under an inert gas atmosphere or The resistance was reduced by heat treatment under reduced pressure and slow cooling. The oxide semiconductor layers 113b and 213b can be formed as two oxide semiconductor layers (see FIG. 5B).

[0151] Next, in a manner similar to that of Embodiment 1, a thimble was formed in contact with the second oxide semiconductor layers 113b and 213b. An insulating film that will serve as a channel protection layer is formed.

[0152] In this embodiment, a 300 nm thick insulating film is formed as a channel protection layer by sputtering. A silicon oxide film having a thickness of m is formed.

[0153] Next, a third photolithography process is performed to form a resist on the insulating film that will become the channel protection layer. A mask is formed, and unnecessary portions are removed by etching to form the first channel protection layer 116. And the second channel protection layer 216 is formed.

[0154] In this embodiment, oxygen gas, N 2 O gas atmosphere or ultra-dry air (dew point -40℃ 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower The second heat treatment is performed under conditions of 00° C. or less. For example, the second heat treatment is performed under an oxygen atmosphere at 250° C. for 1 hour. The second heat treatment is carried out.

[0155] The second oxide semiconductor layers 113b and 213b are entirely made to have high resistance (see FIG. 5C). .

[0156] Next, in the same manner as in Embodiment 1, the gate insulating film 102, the third oxide semiconductor layer 113c, and A conductive film that transmits visible light is formed on 213c, and a metal conductive film is laminated on top of that. .

[0157] Next, a fourth photolithography process is performed to form a resist mask 134 on the conductive film. and removing unnecessary portions of the conductive film and the conductive film that transmits visible light by etching. Conductive layers including source and drain electrodes (114a, 114b, 115a, 115b, 214a, 214b, 215a, and 215b) are formed (see FIG. 6(A)).

[0158] In this etching, the first channel protection layer 116 and the second channel protection layer 216 The insulating layer 213 functions as an etching stopper for the third oxide semiconductor layers 113c and 213c. Therefore, the third oxide semiconductor layers 113c and 213c are not etched.

[0159] The first channel region is formed on and in contact with the channel formation regions of the third oxide semiconductor layers 113c and 213c. Since the structure includes the channel protection layer 116 and the second channel protection layer 216, the third oxide The channel formation regions of the semiconductor layers 113c and 213c are damaged during the process (etching, This protects the thin film from damage caused by plasma and etching agents during cleaning, oxidation, etc. The reliability of the film transistors 143 and 144 can be improved.

[0160] After removing the resist mask 134, a fifth photolithography process is performed to form a source electrode and a wiring layer including drain electrodes (115a and 115b), and a thin film transistor 143. A resist mask 135 is then formed to cover the resist film 135. Next, etching is performed using the resist mask 135. The unnecessary conductive layers (215a, 215b) are removed by Drain electrodes (214a and 214b) are formed.

[0161] Next, the resist mask 135 is removed, and at this stage, the thin film transistors 143 and 14 4 is formed (see FIG. 6(B)).

[0162] Next, the first channel protection layer 116 and the second channel protection layer 216 are covered with the same material as in the first embodiment. Similarly, a first protective insulating film 107 is formed. and form.

[0163] In this embodiment, the first protective insulating film 107 is formed by sputtering to a thickness of 300 nm. A silicon oxide film is formed, and then silicon nitride is laminated on it.

[0164] Next, a second protective insulating film is formed to cover the thin film transistors 143 and 144 in the same manner as in the first embodiment. 108 is formed on the first protective insulating film 107 .

[0165] The second protective insulating film 108 is connected to the first channel protective layer 1 through the first protective insulating film 107. 16 and the second channel protection layer 216, and the source electrode and the drain electrode (115a, 11 5b, 214a, 214b).

[0166] Next, the first protective insulating film 107 is opened by etching, and the thin film transistor 144 is A contact hole 125 reaching the drain electrode 214b is formed.

[0167] In addition, in the thin film transistor 143, the back gate electrode 129 is connected to the first bottom gate In the case of connecting to the electrode 111, before forming a conductive film to be the back gate electrode 129, The second protective insulating film 108, the first protective insulating film 107 and the gate insulating film 102 are shown in the figure. An opening is provided at a predetermined location where there is no opening.

[0168] Next, in the same manner as in the first embodiment, a conductive film that transmits visible light is formed on the second protective insulating film 108. Then, unnecessary portions are removed by etching to form the back gate electrode 129 and the pixel electrode 12 A wiring layer including 8 is formed.

[0169] The back gate electrode 129 is a third oxide semiconductor between the source electrode and the drain electrode. The backplane layer 113c may be disposed to cover the area where the backplane layer 113c overlaps with the first channel protection layer 116. By shortening the width of the gate electrode 129, the parasitic capacitance can be reduced.

[0170] The pixel electrode 128 is connected to the drain electrode 214b of the thin film transistor 144 through a contact hole. The connection is made via a cable 125 (see FIG. 6(C)).

[0171] In addition, the thin film transistor 143 and Heat treatment may be performed on 144. The heat treatment is preferably performed at a temperature of 350° C. or less. This may be done at any time after the insulating film that will become the first protective insulating film 107 is formed. For example, The heat treatment is performed at 350° C. for 1 hour in a 350° C. atmosphere. This can reduce the variation in electrical characteristics of 43 and 144.

[0172] By going through the above steps, thin film transistors 143 and 144 shown in FIG. 4(A) are formed. It can be achieved.

[0173] In addition, in FIG. 5(A) and FIG. 5(B), before forming the insulating film to be the channel protection layer, Similarly to the first embodiment, the exposed second oxide semiconductor layers 113b and 213b are Alternatively, oxygen radical treatment may be performed.

[0174] In addition, a thin-film transistor using a gate insulating film 102 in which a silicon nitride film and a silicon oxide film are laminated is The configuration of the transistors 145 and 146 is shown in FIG. When forming the gate insulating film 102 and the gate insulating film 216, the silicon oxide film of the gate insulating film 102 is etched. Therefore, the thickness of the silicon oxide film in other regions is thinner than the thickness of the silicon oxide film overlapping the island-shaped oxide semiconductor layer. become.

[0175] In addition, the resist mask for forming the pixel electrode 128 may be formed by the inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used, Manufacturing costs can be reduced.

[0176] Through the above steps, the thin film transistor 143 is formed on the same substrate using seven photomasks. and thin film transistor 144, or thin film transistor 145 and thin film transistor 1 46 can be made and formed separately.

[0177] The back gate electrode 129 is disposed at a position overlapping with a channel formation region of the third oxide semiconductor layer 113c. By installing the device in a position, it is possible to carry out bias-thermal stress tests to examine the reliability of thin-film transistors. In the BT test, the thin film transistor 14 In addition, the amount of change in the threshold voltage of the back gate electrode 129 can be reduced. The position of the back gate electrode 111 may be the same as or different from that of the bottom gate electrode 111. The potential of the port electrode 129 may be GND, 0 V, or may be in a floating state.

[0178] The semiconductor layer in the channel formation region of the thin film transistor of this embodiment is a high resistance region. Therefore, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained. It is possible to provide a device.

[0179] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0180] (Embodiment 3) In this embodiment mode, the active matrix substrate shown in Embodiment 1 is used to An example of manufacturing a liquid crystal display device of a matrix type will be described.

[0181] FIG. 9A shows an example of a cross-sectional structure of an active matrix substrate.

[0182] In the first embodiment, the thin film transistors of the driver circuit and the thin film transistors of the pixel section are formed on the same substrate. In the present embodiment, in addition to the thin film transistors, a storage capacitor, a gate The terminals of the wiring (also called the gate wiring layer) and the source wiring (also called the source wiring layer) are also shown. The capacitor, the gate wiring, and the terminal portion of the source wiring are manufactured in the same manner as in the embodiment mode 1. It can be formed in the same process, without increasing the number of photomasks or processes. In addition, in the portion that becomes the display region of the pixel portion, the gate wiring, The source wiring and the capacitance wiring layer are all formed of a conductive film having light transmitting properties, and a high aperture ratio is achieved. In addition, the source wiring layer in the non-display area is made of Therefore, metal wiring can be used.

[0183] In FIG. 9A, a thin film transistor 210 is a channel stop provided in a driving circuit. A thin film transistor that is a flip-type thin film transistor and is electrically connected to the pixel electrode layer 227. Reference numeral 220 denotes a channel stop type thin film transistor provided in a pixel portion.

[0184] In this embodiment, the thin film transistor 220 formed above the substrate 200 is The same structure as that of the thin film transistor 220 of the first embodiment is used. It may be a single layer or a multilayer.

[0185] A layer formed of the same material and process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is made of a first gate insulating layer 202a and a second gate insulating layer 202b, which are dielectrics. The insulating layer 202b overlaps with the capacitance electrode 231 to form a storage capacitor. The thin film transistor 220 has a source electrode layer or a drain electrode layer having the same light-transmitting property as the thin film transistor 220. Therefore, the thin film transistor 220 has a light-transmitting property. In addition, each storage capacitor is transparent, which improves the aperture ratio. can be done.

[0186] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is reduced to achieve high resolution, a high aperture ratio can be achieved. By using a film having light transmitting properties as the constituent members of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a high density group of thin film transistors is arranged, a large aperture ratio can be obtained. For example, two to four pixels can be arranged in one pixel, and a sufficient area can be secured for the display area. When the device has four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is transparent, so that the aperture ratio can be improved. do.

[0187] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is disposed below the pixel electrode layer 227. 27.

[0188] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. For example, The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the first gate insulating layer and the second gate insulating layer therebetween.

[0189] In addition, the gate wiring, source wiring, and capacitance wiring layer are provided in multiple lines according to the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate line, a source line a second terminal electrode having the same potential as the capacitance wiring layer, a third terminal electrode having the same potential as the capacitance wiring layer, etc. are arranged in a row. The number of each terminal electrode may be any number. The implementer should make the appropriate decision.

[0190] In the terminal portion, the first terminal electrode having the same potential as the gate line is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good thermal conductivity. The contact hole is electrically connected to the gate wiring. The pin electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The second protective insulating layer 204 and the first The first protective insulating layer 203, the second gate insulating layer 202b, and the first gate insulating layer 202a is selectively etched to form.

[0191] The gate electrode layer of the thin film transistor 210 disposed in the driving circuit is an oxide semiconductor layer Alternatively, the conductive layer 217 may be electrically connected to the conductive layer 217 provided above the conductive layer 217. , electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227 The same photomask as that for the contact holes for the second protective insulating layer 204 and the first protective insulating layer 205 are used. The protective insulating layer 203, the second gate insulating layer 202b, and the first gate insulating layer 202a are selected. A contact hole is formed by selectively etching the conductive layer through the contact hole. 217 and the gate electrode layer of the thin film transistor 210 arranged in the driving circuit are electrically connected. do.

[0192] In addition, the second terminal electrode 235, which has the same potential as the source line 234 of the driving circuit, is connected to the pixel electrode layer 22. The second terminal electrode 235 can be formed of the same light-transmitting material as the source electrode 7. The source line is electrically connected to the source electrode via a contact hole that reaches the line 234. The wiring is a metal wiring, and is made of the same material and in the same process as the source electrode layer of the thin film transistor 210. are formed and are at the same potential.

[0193] The third terminal electrode having the same potential as the capacitance wiring layer 230 has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitance wiring layer 230 can be formed of a material having the above-mentioned properties. The contact hole 22 is for electrically connecting the capacitance electrode 231 to the pixel electrode layer 227. It can be formed using the same photomask and process as in 4.

[0194] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between a substrate and a counter substrate on which a counter electrode (also called a counter electrode layer) is provided. The active matrix substrate and the opposing substrate are fixed together. A common electrode electrically connected to the electrode is provided on the active matrix substrate. A fourth terminal electrode is provided on the terminal portion for connecting the common electrode to the The fourth terminal electrode is a terminal for setting the potential, for example, GND, 0V, etc. It can be made of the same light-transmitting material as the pole layer 227 .

[0195] In addition, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 The configuration for electrically connecting the source of the thin film transistor 220 is not particularly limited. A connection electrode that connects the electrode layer and the source electrode layer of the thin film transistor 210 is formed on the pixel electrode layer 227. In addition, in the portion other than the display region, the thin film transistor 2 may be formed in the same process. The source electrode layer of the thin film transistor 20 and the source electrode layer of the thin film transistor 210 are overlapped in contact with each other. This is also fine.

[0196] The cross-sectional structure of the gate wiring layer 232 of the driving circuit is shown in FIG. Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer of the driving circuit is The gate electrode layer 232 is made of the same light-transmitting material as the gate electrode layer of the thin film transistor 220. do.

[0197] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the layers and other wiring layers, common sputter targets and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gas, resulting in reduced manufacturing costs. It is possible.

[0198] In the structure of FIG. 9(A), a photosensitive resin material is used as the second protective insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0199] FIG. 9B shows a cross-sectional structure that is partially different from that shown in FIG. A) is the same as A) except that the second protective insulating layer 204 is not present, so the same In FIG. 9B, the first protective insulating layer 20 A pixel electrode layer 227, a conductive layer 217, and a second terminal electrode 235 are formed on and in contact with the pixel electrode 227, the conductive layer 217, and the second terminal electrode 235.

[0200] When the structure in FIG. 9B is used, the process of forming the second protective insulating layer 204 can be omitted.

[0201] This embodiment mode can be freely combined with other embodiment modes.

[0202] (Embodiment 4) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch display, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce the wiring resistance will be shown.

[0203] In FIG. 10(A), the same reference numerals are used for the same parts as in FIG. 9(A), and detailed explanations of the same parts will be omitted. is omitted.

[0204] FIG. 10A shows a thin film transistor 210 in which a part of the gate wiring of the driving circuit is made of metal wiring. In this example, the gate electrode layer is formed in contact with a wiring having the same light-transmitting property as the gate electrode layer. Therefore, the number of photomasks increases compared to the third embodiment.

[0205] First, a layer capable of withstanding a first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0206] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a laminate of a tantalum nitride film and a tungsten film. It is not limited, and an element selected from Ta, W, Ti, Mo, Al, Cu, or the above-mentioned elements An alloy film having the above-mentioned elements as components, an alloy film having the above-mentioned elements as components, The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and may be a bilayer. A stack of more than one layer may be used.

[0207] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The metal wiring layer 237 is formed. The tungsten film and the tantalum nitride film are etched using I CP (Inductively Coupled Plasma) It is recommended to use the etching method. The ICP etching method is used, and the etching conditions (coil type The amount of power applied to the electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc. By appropriately adjusting the thickness, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are tapered to be in contact with each other. This can reduce defects in the formation of a light-transmitting conductive film.

[0208] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. a gate wiring layer 238, a gate electrode layer of the thin film transistor 210, a gate A gate electrode layer and a capacitor wiring layer 230 are formed. A conductive material that is transparent to the above-described visible light is used.

[0209] Depending on the material of the conductive film having light transmitting properties, for example, the gate wiring layer 238 may be a first gold If there is an interface in contact with the metal wiring layer 236 or the second metal wiring layer 237, it may be difficult to perform subsequent heat treatment, etc. Therefore, an oxide film is formed, which may increase the contact resistance. Therefore, the second metal wiring layer 237 It is preferable to use a metal nitride film that prevents the first metal wiring layer 236 from being oxidized.

[0210] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in the first embodiment. In this process, an active matrix substrate is manufactured according to the first embodiment.

[0211] In this embodiment, after the second protective insulating layer 204 is formed, a photomask is used to An example of selectively removing the planarizing insulating layer in the terminal area is shown. Its absence is preferable in terms of achieving a good connection with the FPC.

[0212] In FIG. 10A, the second terminal electrode 235 is formed on the first protective insulating layer 203 . In FIG. 10A, the gate wiring layer 238 overlapping a part of the second metal wiring layer 237 is As shown in FIG. 1, the gate wiring covers the entire first metal wiring layer 236 and the second metal wiring layer 237. That is, the first metal wiring layer 236 and the second metal wiring layer 237 may be a gate The wiring layer 238 can be called an auxiliary wiring for reducing the resistance.

[0213] In addition, in the terminal portion, the first terminal electrode having the same potential as the gate wiring is formed on the first protective insulating layer 20. 3 and electrically connected to the second metal wiring layer 237. Also formed of metal wiring.

[0214] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are made to have low wiring resistance. Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0215] FIG. 10B shows a cross-sectional structure that is partially different from that shown in FIG. The same as in FIG. 10(A) except that the material of the gate electrode layer of the thin film transistor of the driver circuit is different. Therefore, the same parts are designated by the same reference numerals, and detailed descriptions of the same parts are omitted.

[0216] FIG. 10B shows an example in which the gate electrode layer of the thin film transistor of the driver circuit is made of metal wiring. In the driver circuit, the material for the gate electrode layer is not limited to a light-transmitting material.

[0217] In FIG. 10B, a thin film transistor 240 of the driving circuit is formed on a first metal wiring layer 242. The gate electrode layer is formed by laminating a second metal wiring layer 241 on the first metal wiring layer 242. 42 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed of the same material and in the same process as the second metal wiring layer 237. This can be done.

[0218] In addition, when the first metal wiring layer 242 is electrically connected to the conductive layer 217, the first metal wiring The second metal wiring layer 241 is preferably a metal nitride film to prevent oxidation of the layer 242. .

[0219] In this embodiment, the wiring resistance is reduced by partially using metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is increased to 60 inches or even 120 inches, It is possible to achieve high definition and a high aperture ratio.

[0220] This embodiment mode can be freely combined with other embodiment modes.

[0221] (Embodiment 5) In this embodiment, a configuration of a storage capacitor different from that of the third embodiment is shown in FIG. FIG. 11(A) is the same as FIG. 9(A) except for the configuration of the storage capacitor. Since the two are the same, the same reference numerals are used for the same parts, and detailed explanations of the same parts will be omitted. FIG. 11A shows a cross-sectional structure of a thin film transistor 220 and a storage capacitor arranged in a pixel. vinegar.

[0222] FIG. 11A shows a channel protection layer 216 made of an oxide insulating layer as a dielectric, a first protective insulating layer a second protective insulating layer 204; a pixel electrode layer 227; This is an example in which a storage capacitor is formed by the overlapping capacitance wiring layer 250. The source electrode layer of the thin film transistor 220 is made of a material having the same light-transmitting property as that of the source electrode layer of the thin film transistor 220 disposed in the Since the thin film transistor 220 is formed in the same process, the wiring layer 220 is not overlapped with the source wiring layer. The layout will be done.

[0223] The storage capacitor shown in FIG. 11A has a pair of electrodes and a dielectric material that are transparent. The entire film is translucent.

[0224] FIG. 11B shows an example of a storage capacitor having a different configuration from that shown in FIG. 11A. Since this is the same as FIG. 11(A) except for the difference in the configuration of the storage capacitor, the same parts are Reference numerals will be used and detailed explanations of the same parts will be omitted.

[0225] FIG. 11B shows a structure in which the dielectric is a first gate insulating layer 202a and a second gate insulating layer 202b. The capacitance wiring layer 230 and the oxide semiconductor layer 251 and the capacitance wiring layer 230 overlap each other. This is an example in which a storage capacitor is formed by laminating with the electrode 231. The capacitor electrode 231 is an oxide semiconductor. The oxide layer 251 is laminated in contact with the oxide layer 251 and functions as one electrode of the storage capacitor. The semiconductor layer 251 has the same transparent property as the source electrode or the drain electrode of the thin film transistor 220. The capacitor wiring layer 230 is formed of a material having optical properties in the same process as the thin film transistor. Since the gate electrode 220 is formed of the same material and in the same process, The layout is such that it does not overlap with the gate wiring layer of the resistor 220.

[0226] In addition, the capacitance electrode 231 is electrically connected to the pixel electrode layer 227 .

[0227] The storage capacitor shown in FIG. 11B also has a pair of electrodes and a dielectric material that are transparent. The entire film is translucent.

[0228] The storage capacitor shown in FIG. 11(A) and FIG. 11(B) has a light-transmitting property and is connected to the main gate wiring. In order to increase the resolution of the displayed image by increasing the number of pixels, the size of the pixels is reduced, but this is not enough. A large amount of light can be obtained and a high aperture ratio can be realized.

[0229] This embodiment mode can be freely combined with other embodiment modes.

[0230] (Embodiment 6) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0231] The thin film transistor disposed in the pixel portion is formed according to the embodiment 1 or 2. Since the thin film transistor shown in the first or second embodiment is an n-channel TFT, the driving circuit Of these, a part of the driver circuit that can be configured with n-channel TFTs is a thin-film transistor in the pixel area. The transistor is formed on the same substrate.

[0232] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the display elements, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is a flexible printed circuit (FPC). A timing control circuit 5305 (controller, control I / F) is connected to the timing control circuit 5305 via a connection part such as a C).

[0233] In FIG. 16A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability and yield can be improved.

[0234] The timing control circuit 5305 is, for example, A start signal (GSP1) for the first scanning line driver circuit (also called a start pulse) A clock signal (GCK1) for the scan line driver circuit is supplied to the timing control circuit 530. 5 is a second scanning line driver circuit 5303, for example, a second scanning line driver circuit The signal line supplies the clock signal (GSP2) for the scanning line driver circuit and the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit and a clock for the signal line driver circuit are input to the driver circuit 5304. Clock signal (SCK), data for video signal (DATA) (also simply called video signal), Each clock signal is a multiple of the clock signal (LAT) with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0235] In FIG. 16B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The driving circuit formed on the substrate 5300 can be configured by the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce costs, or improve yields. It is possible to plan this.

[0236] The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT. 7(A) and 17(B) show the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given below.

[0237] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0238] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0239] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0240] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0241] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0242] Next, the operation of the signal line driver circuit of FIG. 17(A) will be described with reference to the timing chart of FIG. 17(B). FIG. 17B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0243] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0244] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written more quickly. This can prevent under-crowding.

[0245] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use a circuit composed of thin film transistors as shown in FIG. The polarity of all the transistors in the soft resistor 5601 is set to N-channel or P-channel. The polarity of the casing can be either one of the polarities.

[0246] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 18 and FIG.

[0247] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. A selection signal is generated by inputting a clock (CK) and a start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on at the same time, a buffer The resistor used is capable of passing a large current.

[0248] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 18(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage (called the previous stage signal OUT(n-1)) (n is a natural number greater than or equal to 2) is input. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages behind, Similarly, in the second or subsequent n-th pulse output circuit 10_n, a signal from the second or subsequent stage is input. The signal from the (n+2)th pulse output circuit 10_(n+2) in the latter stage (the latter stage signal OUT(n Therefore, the pulse output circuit of each stage outputs the following stage and / or The first output signal (OUT(1)(SR) to OU T(N)(SR)), the second output signal (OUT(1) to OUT( As shown in FIG. 18(A), the last two stages of the shift register are Since the next stage signal OUT(n+2) is not input to this stage, for example, a second stage A start pulse SP2 and a third start pulse SP3 may be input. .

[0249] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use the term CK for explanation.

[0250] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to The fourth wiring 14 is electrically connected to the fourth wiring 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0251] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 18(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0252] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to TFTs (also called Thin Film Transistors), The four-terminal thin film transistor described in the above embodiment can be used. In the document, when a thin film transistor has two gate electrodes via a semiconductor layer, The gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. It is also called the gate electrode.

[0253] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage can be adjusted to the desired value by controlling the potential of the upper and / or lower gate electrodes. The value can be controlled.

[0254] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. This is explained in (C).

[0255] The pulse output circuit shown in FIG. 18C includes a first transistor 31 to a thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied is provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is supplied to the first transistor 31 to the thirteenth transistor 43 from a power supply line 53 connected to the The power supply potential is supplied to each of the power supply lines. The magnitude relationship of the power supply potential of each of the power supply lines in FIG. The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC. The potential of the first clock signal (CK1) to the third power supply potential VSS is set to be higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H and L levels at regular intervals. When the power supply line 51 is at the H level, it is VDD, and when the power supply line 51 is at the L level, it is VSS. By making the potential VDD higher than the potential VCC of the power supply line 52, the operation is not affected. Therefore, the potential applied to the gate electrode of the transistor can be kept low, and the transistor This reduces the threshold shift of the first transistor and suppresses deterioration. Among the transistors 31 to 43, the first transistor 31 and the sixth transistor It is preferable to use four-terminal thin film transistors for the transistors 36 to 39. The first transistor 31 and the sixth to ninth transistors 36 to 39 In operation, the potential of the node to which one of the electrodes, which is the source or drain, is connected is set to the gate voltage. A transistor that requires switching by a control signal input to the gate electrode. The response to the input control signal is fast (the rise of the on-current is steep), so the This is a transistor that can reduce malfunctions in the output circuit. By using transistors, the threshold voltage can be controlled, reducing malfunctions. It is possible to provide a pulse output circuit that can

[0256] In FIG. 18C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; is electrically connected to the fourth input terminal 24. The second transistor 32 is is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. a gate electrode electrically connected to the gate electrode of the fourth transistor 34; The third transistor 33 has a first terminal electrically connected to the first input terminal 21, The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 of No. 6 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second Electrically connected to the gate electrode of the transistor 32 and the gate electrode of the fourth transistor 34 The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode electrically connected to a third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and The fourth transistor 34 is electrically connected to a gate electrode thereof, the gate electrode of which is connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The tenth transistor is electrically connected to the power supply line 52, and the gate electrode is electrically connected to the power supply line 52. The resistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the second output terminal 22. a gate electrode electrically connected to the second terminal of the ninth transistor 39; The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. the second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal The seventh transistor 37 has a gate electrode electrically connected to the second output terminal 27 and a gate The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37 .

[0257] In FIG. 18C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let us assume that.

[0258] FIG. 19(A) shows the pulse output circuit described in FIG. 18(C) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0259] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a clock signal CK3 is input to the fifth input terminal The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0260] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device has a terminal and a channel region formed in a region overlapping with the gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source and which is the drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be written as terminal or second terminal.

[0261] In FIG. 18(C) and FIG. 19(A), node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0262] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 19(B) corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0263] As shown in FIG. 19A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0264] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 is increased, but the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, It is possible to reduce the value of the negative bias voltage applied between the gate and source of the transistor 31. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0265] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0266] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor including an oxide semiconductor can be Compared to transistors using amorphous silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power lines to be routed can be reduced, the circuit can be made more compact.

[0267] The gate electrode of the seventh transistor 37 is connected to the third input terminal 23. A lock signal is supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38. The clock signal to be generated is input to the gate electrode of the seventh transistor 37 by the second input terminal 22. a clock signal provided by the third input terminal 23 to the gate electrode of the eighth transistor 38; The same effect can be obtained by swapping the wiring so that the clock signal is supplied by In the shift register shown in FIG. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 are The voltage drop at node B is generated by the gate of the seventh transistor 37. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, when the shift register shown in FIG. 19(A) is As described above, the seventh transistor 37 and the eighth transistor 38 are both in an on state, and The seventh transistor 37 is on and the eighth transistor 38 is off. Then, the seventh By turning off the transistor 37 and the eighth transistor 38, The potential of the node B caused by the potential of the second input terminal 22 and the third input terminal 23 decreasing The decrease in the potential of the gate electrode of the eighth transistor 38 is reduced to one time. Therefore, the gate electrode of the seventh transistor 37 is connected to the third input terminal 23. a clock signal provided by the second input terminal 22 to the eighth gate electrode; By reducing the fluctuation of the potential of node B as a clock signal, noise can be reduced. This is preferable because it is possible to

[0268] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0269] (Embodiment 7) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. A part or the whole of the driver circuit is formed on the same substrate as the pixel portion by using transistors, A stem-on panel can be formed.

[0270] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0271] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. Alternatively, only the pixel electrode (also called pixel electrode layer) of the display element may be formed. After forming the conductive film to be the pixel electrode and before etching to form the pixel electrode, It can be a state, or it can take any form.

[0272] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0273] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 12(A1) and 12(A2) show thin film transistors 4010 and 4011 and a liquid crystal display device. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. FIG. 12(B) is a plan view of the panel sealed by the above method, and FIG. 12(A1) and (A2) are the same as FIG. Equivalent to the cross-sectional view at -N.

[0274] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0275] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 12A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0276] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 12B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The protective insulating layer 4020 and the protective insulating layer 4021 are formed on the thin film transistors 4010 and 4011. 021 is provided.

[0277] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in Embodiment 1 or 2. Thin film transistors with high reliability, including thin film transistors for driving circuits, can be used. The transistor 4011 may be the thin film transistor 141 or 143 shown in the first or second embodiment. Thin film transistors 142 and 144 are used as the thin film transistor 4010 for the pixel. In this embodiment, the thin film transistors 4010 and 4011 are n-channel It is a thin film transistor.

[0278] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A back gate electrode 4040 is provided at a position overlapping with the channel forming region. By providing the gate electrode 4040 in a position overlapping with a channel formation region of the oxide semiconductor layer, In this way, the change in the threshold voltage of the thin film transistor 4011 before and after the BT test is reduced. In addition, the back gate electrode 4040 can be electrically connected to the thin film transistor 4011. The gate electrode layer may be the same as or different from the gate electrode layer, and serves as a second gate electrode layer. In addition, the potential of the back gate electrode 4040 can be set to GND, 0 V, or The device may be in a loading state.

[0279] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0280] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0281] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is incorporated into material 4005.

[0282] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0283] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0284] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the substrate in the order of the filter and the electrode layer used for the display element. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and may be provided on the polarizing side. The setting may be appropriately determined depending on the materials of the plate and the colored layer and the manufacturing process conditions. A light-shielding film that functions as a rack matrix may be provided.

[0285] The thin film transistor 4011 has an insulating layer 4042 formed thereon as a channel protection layer. 042 is formed by the same material and method as the channel protection layers 116 and 216 shown in the first embodiment. In addition, the film functions as a planarizing insulating film to reduce the surface irregularities of the thin film transistor. The insulating layer 4021 covers the insulating layer 4041 and 4042. Then, a silicon oxide film is formed by the sputtering method exemplified in the first embodiment.

[0286] In addition, a protective insulating layer 4020 is formed over the insulating layers 4041 and 4042. The protective insulating film 4020 may be formed using a material and a method similar to those of the protective insulating film 107 described in the first embodiment. Here, a silicon nitride film is formed as the insulating layer 4020 by a PCVD method.

[0287] In addition, an insulating layer 4021 is formed as a planarization insulating film. The protective insulating film 108 may be formed of the same material and by the same method as in the first embodiment. Heat-resistant organic materials such as acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials, white materials, etc. Xanthane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. In addition, by stacking a plurality of insulating films made of these materials, the insulating layer 402 can be formed. 1 may be formed.

[0288] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0289] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a fcoater or the like. By using both, a semiconductor device can be manufactured efficiently.

[0290] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0291] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0292] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0293] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0294] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed of the same conductive film.

[0295] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0296] In FIG. 12, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0297] FIG. 21 shows a semiconductor device using a TFT substrate 2600 produced by the production method disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0298] FIG. 21 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0299] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0300] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0301] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0302] (Embodiment 8)

[0303] An example of electronic paper will be shown as one mode of a semiconductor device.

[0304] Electronic paper that uses switching elements and elements electrically connected to drive electronic ink Electronic paper is also called an electrophoretic display. It is known to be as easy to read as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0305] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0306] Thus, electrophoretic displays operate in a manner such that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Therefore, no polarizing plate, which is necessary for a liquid crystal display device, is required.

[0307] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0308] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using transistors can be used.

[0309] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0310] FIG. 20 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor can be fabricated in the same manner as the conventional thin film transistor, and is highly reliable, including an oxide semiconductor layer. The thin film transistors shown in any of the embodiments 2 to 4 may be used as the thin film transistor 581 in this embodiment. It can also be applied.

[0311] The electronic paper in FIG. 20 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0312] The thin film transistor 581 formed on the substrate 580 is a bottom-gate thin film transistor. The thin film transistor 581 is covered with an insulating layer 583. The rain electrode layer is a first electrode layer 587 and an opening formed in the insulating layer 583 and the insulating layer 585. The first electrode layer 587 and the second electrode layer 596 formed on the substrate 596 are in contact with each other and are electrically connected to each other. Between the electrode layer 588 and the black area 590a and the white area 590b, the liquid A spherical particle 589 is provided that includes a cavity 594 that is filled with The periphery of the first electrode layer 587 is filled with a filler 595 such as resin. The second electrode layer 588 corresponds to a thin film transistor. The common connection portion is electrically connected to a common potential line provided on the same substrate as the resistor 581. By using the conductive particles disposed between the pair of substrates, the second electrode layer 588 and the common potential line are connected to each other. and can be electrically connected.

[0313] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is the electrophoretic display element, and the device that uses the electrophoretic display element The electrophoretic display element is generally called electronic paper. High reflectance means no auxiliary light is required, and the low power consumption means it can be displayed even in dimly lit areas. Even if the display unit is not powered, Since it is possible to hold the image displayed at any one time, it is possible to easily transmit the image from the source of the radio wave to a semiconductor device with a display function. (also simply referred to as a display device or a semiconductor device equipped with a display device) is moved away. It is also possible to store the displayed image.

[0314] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0315] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0316] (Embodiment 9) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0317] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0318] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0319] FIG. 14 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0320] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0321] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6 The transistor 402 has a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) One of the electrodes) is connected to a signal line 6405, and the second electrode (the source electrode and the drain electrode) is connected to a signal line 6405. The other end of the transistor 6402 is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 via a capacitor element 6403. The first electrode is connected to a power line 6407, and the second electrode is the first electrode (pixel The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0322] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. A high power supply potential is applied to the common electrode 6408, and a low power supply potential is applied to the power supply line 6407. In that case, the current flowing through the light emitting element 6404 is reversed. The configuration of the light emitting element 6404 may be changed as appropriate.

[0323] The capacitor 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 A capacitance may be formed between the channel region and the gate electrode.

[0324] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 In the test, the light emitting element driving transistor 6402 is either fully turned on or fully turned off. In other words, the light emitting element driving transistor 6402 is inputted with a video signal that is in the state of The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage equal to or higher than the Vth of 6402.

[0325] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 14 can be used.

[0326] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply the forward voltage of 6404 + a voltage equal to or higher than the Vth of the light emitting element driving transistor 6402 The forward voltage of the light emitting element 6404 refers to a voltage for achieving a desired luminance. At least the forward threshold voltage is included. By inputting a video signal that operates in the region, a current is passed to the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in the saturation region, the power supply line 6 The potential of the gate of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal flows through the light emitting element 6404. Analog gray scale driving is possible.

[0327] Note that the pixel configuration shown in FIG. 14 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0328] Next, the configuration of the light emitting element will be described with reference to FIG. FT is n-type, and the upper electrode of the light-emitting element is an anode, and the lower electrode is an n-type. The cross-sectional structure of a pixel will be described below by taking the case where the electrode is a cathode as an example. (B) and (C) are TFTs for driving light-emitting elements used in the semiconductor device, TFT7001 and 7 The thin film transistors 011 and 7021 are formed in the same manner as the thin film transistors arranged in the pixel shown in the first embodiment. The thin film transistor according to the embodiment includes an oxide semiconductor layer. The thin film transistors arranged in the pixels indicated by 2 to 4 are TFTs 7001, 7011, and 702. It can also be applied as 1.

[0329] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0330] A light emitting element having a top emission structure will be described with reference to FIG.

[0331] In FIG. 15A, a TFT 7001 for driving a light-emitting element is an n-type TFT, and a light-emitting element 700 FIG. 15(A) shows a cross-sectional view of a pixel when light emitted from the cathode 7002 exits to the anode 7005 side. ) is a cathode 7003 of a light-emitting element 7002 and a TFT 7001 which is a TFT for driving the light-emitting element. are electrically connected, and a light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. The cathode 7003 may be made of any conductive film having a small work function and capable of reflecting light. Various materials can be used. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or may be composed of multiple layers stacked together. When it is made up of multiple layers, the cathode 7003 is provided with a layer The electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. It is not necessary to provide all of these layers. The anode 7005 is made of a conductive material having a light transmitting property. For example, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide Alternatively, a light-transmitting conductive film such as indium tin oxide to which silicon oxide is added may be used. .

[0332] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering the ends of each. The partition wall 7009 is made of polyimide, acrylic, polyamide, epoxy, etc. The partition wall 7009 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition wall 7009 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0333] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 15(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0334] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. The TFT 7011 is an n-type, and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013. FIG. 15B shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a A cathode 7013 of the light-emitting element 7012 is formed on the conductive film 7017 having a light-transmitting property and is electrically connected to the light-emitting element 7012. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 has a light-transmitting property, a light-reflecting Alternatively, a shielding film 7016 for shielding may be formed. The cathode 7013 is As in the case of (A), various conductive materials with small work functions can be used. However, the film thickness must be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 is composed of a single layer, as in FIG. The anode 7015 may be a single layer or a laminate of multiple layers. Although it is not necessary for the material to transmit light, the material is formed using a conductive material having light transmitting properties, as in FIG. 15(A). The shielding film 7016 can be made of, for example, a light-reflecting metal. However, the material is not limited to a metal film. For example, a resin containing a black pigment may be used. do.

[0335] In addition, between the conductive film 7017 and the conductive film 7018 of the adjacent pixel, A partition wall 7019 is provided. The partition wall 7019 is made of polyimide, acrylic, polyamide, or epoxy. The partition wall 7019 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7019 is formed with a continuous curvature. It is preferable to form the partition wall 7019 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0336] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 15B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0337] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive film 702 electrically connected to a light-emitting element driving TFT 7021 is A cathode 7023 of a light-emitting element 7022 is formed on the substrate 701, and a light-emitting layer 7023 is formed on the cathode 7023. 15(A) and an anode 7025 are laminated in this order. Similarly, various conductive materials with small work functions can be used. The thickness of the cathode 702 is set to a level that allows light to pass through. For example, an Al film having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed of a single It may be configured as a layer or as a laminate of a plurality of layers. The anode 7025 is made of a light-transmitting conductive material, similar to that in FIG. It can be formed by:

[0338] In addition, between the conductive film 7027 and the conductive film 7028 of the adjacent pixel, A partition 7029 is provided. The partition 7029 is made of polyimide, acrylic, polyamide, or epoxy. The partition wall 7029 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7029 is formed with a continuous curvature. It is preferable to form the partition wall 7029 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0339] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 15C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0340] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0341] In addition, a thin film transistor (a TFT for driving a light-emitting element) that controls the driving of the light-emitting element and a light-emitting element In the above example, the light-emitting element driving TFT and the light-emitting element are electrically connected. A control TFT may be connected.

[0342] The semiconductor device is not limited to the configuration shown in FIG. 15, and may be any of the configurations disclosed in this specification. Various modifications based on the technical concept are possible.

[0343] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 13. FIG. 13(A) shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 13(B) is a plan view of the above-mentioned embodiment, and FIG. 13(B) is a cross-sectional view taken along line HI of FIG. 13(A).

[0344] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0345] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 13B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0346] The thin film transistors 4509 and 4510 each include the oxide semiconductor layer described in Embodiment 1 or 2. A highly reliable thin film transistor including a thin film transistor arranged in a driving circuit can be applied. The transistor 4509 can be the thin film transistor 141 described in Embodiment 1 or 2. 143, as the thin film transistor 4510 arranged in the pixel, the thin film transistor 142 In this embodiment, thin film transistors 4509 and 144 can be used. 510 is an n-channel thin film transistor.

[0347] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A back gate electrode 4540 is provided at a position overlapping with the channel forming region. By providing the electrode 4540 in a position overlapping with a channel formation region of the oxide semiconductor layer, In order to reduce the change in the threshold voltage of the thin film transistor 4509 before and after the BT test, In addition, the back gate electrode 4540 can be connected to the gate of the thin film transistor 4509. The second gate electrode layer may be the same as or different from the first gate electrode layer. In addition, the potential of the back gate electrode 4540 can be set to GND, 0 V, or The signal may be in a pinging state.

[0348] In the thin film transistor 4509, an insulating layer 4541 is formed as a channel protection layer. The transistor 4510 has an insulating layer 4542 formed thereon as a channel protection layer. 541 and 4542 are made of the same material as the channel protection layers 116 and 216 shown in the first embodiment. In addition, in order to reduce the surface unevenness of the thin film transistor, a planarizing insulating film may be formed. The insulating layer 4541 is a layer that covers the insulating film 4544. As the film 4542, a silicon oxide film is formed by the sputtering method described in the first embodiment.

[0349] In addition, a protective insulating layer 4543 is formed over the thin film transistors 4509 and 4510. The protective insulating layer 4543 is formed using a material and a method similar to those of the protective insulating film 107 described in Embodiment 1. Here, the protective insulating layer 4543 is formed by a PCVD method using silicon nitride. A bare film is formed.

[0350] In addition, an insulating layer 4544 is formed as a planarization insulating film. The second protective insulating film 108 may be formed using a material and a method similar to those of the second protective insulating film 108 described in the first embodiment. The insulating layer 4544 is made of acrylic.

[0351] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0352] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0353] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0354] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0355] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0356] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of a source electrode layer and The drain electrode layer is formed from the same conductive film as the drain electrode layer.

[0357] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0358] The second substrate is not transparent to light, and is located in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0359] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0360] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0361] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0362] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0363] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0364] (Embodiment 10) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 22.

[0365] FIG. 22 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 The device is made up of two housings, housing 2701 and housing 2703. 03 is integrated with an axis portion 2711, and performs opening and closing operations around the axis portion 2711. This configuration makes it possible to operate like a paper book. .

[0366] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 22) and An image can be displayed on the display unit 2707 in FIG.

[0367] FIG. 22 shows an example in which the housing 2701 is provided with an operation unit and the like. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0368] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0369] (Embodiment 11) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0370] FIG. 23A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0371] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0372] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0373] FIG. 23B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0374] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have one as it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and the captured image data can be displayed on the display unit 9703. do.

[0375] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0376] FIG. 24(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 24(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 24(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 24(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0377] FIG. 24(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. Other auxiliary equipment may be provided as appropriate.

[0378] FIG. 25A is a perspective view showing an example of a portable computer.

[0379] The portable computer of FIG. 25(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0380] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0381] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0382] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0383] The portable computer shown in FIG. 25A is configured with a receiver and the like, and is also a television. It is possible to receive broadcasts and display images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. 7. Slide the screen to expose the entire screen, and adjust the screen angle to watch TV broadcasts. In this case, the hinge unit can be opened to display the display unit 9303. Furthermore, it only activates the circuits that display TV broadcasts, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0384] FIG. 25(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0385] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0386] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera switch and the camera start switch, there are also other buttons, such as a button that starts an Internet program. Each function can be associated with a specific function, such as being started.

[0387] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 25(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0388] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0389] The mobile phone shown in FIG. 25(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. As a configuration equipped with a storage device, television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 2 may have a function for collecting location information such as GPS.

[0390] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 25(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0391] Although FIG. 25B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0392] (Embodiment 12) In this embodiment mode, the thin film transistor shown in any one of Embodiments 1 to 5 is used as one mode of a semiconductor device. An example of a display device having a star will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element as an element will be described with reference to FIGS. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistor shown in FIG. 5 can be applied to the thin film transistor shown in FIG. The TFT628 is a thin-film transistor with excellent electrical characteristics and high reliability that can be fabricated easily. The TFT 629 has a channel protection layer 611, and the TFT 629 has an oxide semiconductor The layer is an inverted staggered thin-film transistor having a channel formation region.

[0393] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. A VA type LCD is a type of LCD that controls the alignment of liquid crystal molecules in the LCD panel. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are aligned relative to the panel surface. In this embodiment, the pixels are arranged in a vertical direction. It is designed to divide the area (subpixels) into separate areas and tilt the molecules in different directions. This is called multi-domain or multi-domain design. In the following explanation, A liquid crystal display device in which the display design is taken into consideration will be described.

[0394] 27 and 28 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 26 shows the same. FIG. 28 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0395] FIG. 26 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is laminated on the counter substrate 601. 4 shows the state in which liquid crystal has been injected.

[0396] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. On the pixel electrode layer 624, an alignment film 648 is formed. An alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between opposing substrates 601 .

[0397] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. The insulating film 620 covering the insulating film 30 and the insulating film 622 covering the insulating film 620 are penetrated by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 may be a thin-film transistor. The first capacitance wiring 604 formed at the same time as the gate wiring 602, the gate insulating film 606, and the wiring It is composed of a second capacitance wiring 617 formed at the same time as the lines 616 and 618 .

[0398] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0399] FIG. 27 shows a structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the embodiment mode 1. The pixel electrode layer 624 is provided with a slit 625. The slit 625 is formed by This is for controlling the orientation.

[0400] The TFT 629 and the pixel electrode layer 626 and the storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor portion 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

[0401] 28 shows a planar structure of the opposing substrate side. An opposing electrode layer 640 is formed on a light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 644 are formed to control the alignment of the liquid crystal. In FIG. 28, a pixel electrode layer 624 and a pixel electrode layer 626 formed on a substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how the system is being used.

[0402] The equivalent circuit of this pixel structure is shown in Figure 29. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0403] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0404] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 30 to 33. do.

[0405] 30 and 31 show the pixel structure of a VA type liquid crystal display panel. FIG. 30 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0406] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The control circuit has a configuration in which the

[0407] The pixel electrode layer 624 is formed in a contact hole 623 that penetrates the insulating film 622. The pixel electrode layer 626 is connected to a TFT 628 through a wiring 618. In the contact hole 627 that penetrates each of them, the wiring 619 is connected to the TFT 629. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 have different On the other hand, the gate signal is separated so that the gate signal can be given to the data line. The wiring 616 is shared by the TFT 628 and the TFT 629. The thin film transistors shown in any of the embodiments 1 to 5 can be appropriately used for the TFT 629. In addition, a gate insulating film 606 is formed on the gate wiring 602, the gate wiring 603 and the capacitance wiring 690. 06 is formed.

[0408] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes. A pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624. By applying different voltages to the electrode layer 626 to the TFTs 628 and 629, The alignment of the liquid crystal is controlled by the pixel structure shown in Figure 33. The TFT 629 is connected to the gate wiring 603. The TFT 628 and the TFT 629 are both connected to the wiring 616. By applying different gate signals to the gate wiring 603, the liquid crystal element 651 and the liquid crystal element 652 are operated. In other words, the operation of the TFT628 and TFT629 can be controlled separately. By controlling the liquid crystal orientation of the liquid crystal elements 651 and 652, the viewing angle can be precisely controlled. You can widen the corners.

[0409] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 32 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the substrate, and has a slit 641 formed therein. The element electrode layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle. In addition, in FIG. 32, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are indicated by dashed lines. , the counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. It shows how it is placed.

[0410] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel described in FIG. 30 to FIG. 33 has a first liquid crystal element and a second liquid crystal element in one pixel. The display has a multi-domain structure in which crystal elements are provided.

[0411] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0412] FIG. 34 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. A colored film 636, a flattening film 637, etc. are formed on the counter substrate 601. No counter electrode is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed on the substrate 610 with an alignment film 646 and an alignment film 648 interposed therebetween.

[0413] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitance wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. The TFT 628 can be formed using the thin film transistor shown in any one of the first to fifth embodiments. The electrode layer 607 may be the pixel electrode layer described in any of the embodiments 1 to 5. The electrode layer 607 may be formed of a similar material. A gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. can be.

[0414] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0415] An insulating film 620 is formed on the wiring 616 and the wiring 618. In the contact hole formed in the insulating film 620, the pixel electrode layer 6 The pixel electrode layer 624 is formed using the same material as the pixel electrode shown in the embodiment mode 1. and form it.

[0416] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0417] 35 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 34. The pixel electrode layer 624 is provided with a slit 625. The liquid crystal alignment layer 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is applied to the electrode layer 607 and The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. The thickness of the gate insulating film 606 is 50 to 200 nm. Since the thickness of the liquid crystal layer is about 10 μm, the thickness of the substrate 600 is substantially parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the alignment of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in a nearly parallel direction. Since the display is horizontal even in this state, the effect of contrast on the viewing angle is minimal, and the viewing angle is wide. In addition, since the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes, , the aperture ratio can be improved.

[0418] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0419] Figures 36 and 37 show the pixel structure of an IPS type liquid crystal display device. Figure 37 is a plan view. The cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0420] FIG. 36 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A color film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. Between the substrate 600 and the counter substrate 601, an alignment film 646 and an alignment film 64 A liquid crystal layer 650 is formed via the substrate 8 .

[0421] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. For this, the thin film transistors described in any of Embodiments 1 to 5 can be applied.

[0422] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0423] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is the same as the pixel electrode shown in the first to fifth embodiments. As shown in FIG. 37, the pixel electrode layer 624 is formed of a common potential The wire 609 is formed so that a lateral electric field is generated together with the comb-shaped electrode formed at the same time. The comb-tooth portion of the electrode layer 624 alternately interdigitates with the comb-shaped electrode formed at the same time as the common potential line 609. formed to fit.

[0424] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. Rotate the molecules horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast, etc., and results in a wider viewing angle.

[0425] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is provided with a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitance electrode 615 and the pixel electrode layer 624 are formed through a contact hole 63. It is connected via 3.

[0426] Next, a configuration of a TN type liquid crystal display device will be described.

[0427] Figures 38 and 39 show the pixel structure of a TN type liquid crystal display device. Figure 39 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0428] The pixel electrode layer 624 is formed through a contact hole 623 and a wiring 618 formed in the insulating film 620. The wiring 616 that functions as a data line is connected to the TFT 628 via the The TFT 628 is connected to any one of the TFTs shown in the first to fifth embodiments. It is possible.

[0429] The pixel electrode layer 624 is formed using any of the pixel electrodes described in Embodiments 1 to 5. The wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the line 602 and the capacitance wiring 604. A gate insulating film 606 is formed between the wiring 604 and the capacitance electrode 615 .

[0430] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is provided between the pixel electrode layer 624 and the counter electrode layer 640 with an alignment film 648 and an alignment layer 649. It is formed through a membrane 646 .

[0431] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0432] The colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistors are formed, and a counter substrate 601 A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

[0433] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio.

[0434] (Embodiment 13) In this embodiment, an example in which an oxide semiconductor layer is surrounded by a nitride insulating film as viewed from a cross section is shown in FIG. FIG. 40 differs from FIG. 1A in the shape of a top surface of the oxide insulating layer 416 and the position of an end portion thereof. Since the configuration is the same except for the difference in the configuration of the gate insulating layer, detailed description of the same parts will be omitted.

[0435] The thin film transistor 410 disposed in the driving circuit is a channel stop type thin film transistor. A gate electrode layer 411 and a nitride insulating film are formed on a substrate 400 having an insulating surface. The gate insulating layer 402, at least the oxide semiconductor layer 413, the first low-resistance N-type region 414a , and an oxide semiconductor layer having a second low-resistance N-type region 414b, a source electrode layer 415a, and the drain electrode layer 415b. An oxide insulating layer 416 functioning as a channel protective layer is provided in contact with the insulating layer 416 .

[0436] In addition, the thin film transistor 420 disposed in the pixel is a transistor similar to the thin film transistor 410. The thin film transistor is a channel stop type thin film transistor, and is made up of a gate electrode layer 421 and a nitride insulating film. The gate insulating layer 402, the oxide semiconductor layer 422, the source electrode layer 425a, and the drain electrode In addition, a channel protection layer 425b is provided in contact with a channel formation region of the oxide semiconductor layer 422. An oxide insulating layer 426 is provided to serve as a protective layer.

[0437] Note that the oxide insulating layer 416 and the oxide insulating layer 426 are formed by a photolithography process. In this case, the gate insulating layer 402 on the outside of the thin film transistor 410 and the thin film transistor 420 Process so that the is exposed.

[0438] Furthermore, the thin film transistor 410 and the thin film transistor 420 are covered with the upper and side surfaces thereof. A protective insulating layer 403 made of a nitride insulating film is formed.

[0439] In addition, the first low-resistance N-type region 414a is formed in a self-aligned manner in contact with the lower surface of the source electrode layer 415a. A second low-resistance N-type region is formed in contact with the lower surface of the drain electrode layer 405b. In addition, the channel formation region 414b of the oxide semiconductor layer 413 is formed in a self-aligned manner. The first low-resistance N-type region 4 is in contact with the oxide insulating layer 416 and has a thin film thickness. 14a, and the second low-resistance N-type region 414b (I-type region).

[0440] In addition, the channel formation region of the oxide semiconductor layer 413, the first low-resistance n-type region 414a, and A gate insulating layer 402 made of a nitride insulating film is formed in contact with the lower surface of the second low-resistance N-type region 414b. is formed.

[0441] The protective insulating layer 403 made of a nitride insulating film is a silicon nitride film obtained by a sputtering method, an oxynitride film, or the like. Moisture, hydrogen ions, and O H - The inorganic insulating film does not contain impurities such as fluorine and blocks them from entering from the outside. Use.

[0442] In this embodiment, the protective insulating layer 403 is made of a nitride insulating film. 10 and the upper and side surfaces of the thin film transistor 420 are surrounded by an RF sputtering method. A silicon nitride film having a thickness of 100 nm is provided. On the outside of the gate electrode 420, the protective insulating layer 403 is covered with the gate insulating layer 40 made of a nitride insulating film. It is configured to be in contact with 2.

[0443] By forming the structure shown in FIG. 40, the manufacturing process after forming the protective insulating layer 403 made of a nitride insulating film In the process, it is possible to prevent moisture from entering from the outside. For example, even after the device is completed as a liquid crystal display device, it will continue to prevent moisture from entering from the outside for a long period of time. This makes it possible to improve the long-term reliability of the device.

[0444] In addition, in this embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film has been shown. However, the present invention is not limited to this, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may be used. A plurality of thin film transistors in the region may be surrounded by a nitride insulating film. A protective insulating layer 403 and a gate insulating layer 404 are formed so as to surround the periphery of the pixel portion of the active matrix substrate. A region in contact with the layer 402 may be provided.

[0445] This embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0446] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 Substrates 102 Gate insulating film 102b Gate insulating film 107 Protective insulating film 107a Protective insulating film 108 Protective insulating film 111 Bottom gate electrode 113 Oxide semiconductor layer 113a Oxide semiconductor layer 113b Oxide semiconductor layer 113c Oxide semiconductor layer 113d Oxide semiconductor region 114a conductive layer 114b Conductive layer 115a conductive layer 115b Conductive layer 116 Channel Protection Layer 125 Contact Hole 128 pixel electrode 129 Backgate electrode 134 Resist Mask 135 Resist Mask 141 Thin-film transistor 142 Thin-film transistor 143 Thin-film transistor 144 Thin-film transistor 145 Thin-film transistor 146 Thin-film transistor 200 Substrates 202a Gate insulating layer 202b Gate insulating layer 203 Protective insulation layer 204 Protective insulation layer 210 Thin-film transistor 211 Bottom gate electrode 213 Oxide semiconductor layer 213a Oxide semiconductor layer 213b Oxide semiconductor layer 213c Oxide semiconductor layer 213d Oxide semiconductor region 214a Source electrode or drain electrode 214b Source electrode or drain electrode 215a conductive layer 215b Conductive layer 216 Channel Protection Layer 217 Conductive Layer 220 Thin-film transistor 224 Contact Hole 227 Pixel electrode layer 230 Capacitive wiring layer 231 Capacitive electrode 232 Gate wiring layer 234 Source wiring 235 Terminal electrode 236 Metal wiring layer 237 Metal wiring layer 238 Gate wiring layer 240 Thin-film transistor 241 Metal wiring layer 242 Metal wiring layer 250 capacitive wiring layer 251 Oxide semiconductor layer 400 Substrates 402 Gate insulating layer 403 Protective insulation layer 405b Drain electrode layer 410 Thin Film Transistor 411 Gate electrode layer 413 Oxide semiconductor layer 414a Low resistance N-type region 414b Low resistance N-type region 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulating layer 420 Thin Film Transistor 421 Gate electrode layer 422 Oxide semiconductor layer 425a Source electrode layer 425b Drain electrode layer 426 Oxide Insulation Layer 580 Substrate 581 Thin Film Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 Board 600 Substrates 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 607 Electrode layer 608 Channel Protection Layer 609 Common potential line 611 Channel Protection Layer 615 Capacitive electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 632 Light-shielding film 633 Contact Hole 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4035 Spacer 4040 Backgate electrode 4041 Insulation layer 4042 Insulation layer 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Backgate electrode 4541 Insulation layer 4542 Insulation layer 4543 Insulation layer 4544 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin Film Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7008 Cathode 7009 Bulkhead 7011 Driving TFT 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7018 Conductive film 7019 Bulkhead 7021 Driving TFT 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 7028 Conductive film 7029 Bulkhead 9201 Display section 9202 Display button 9203 Operation switch 9204 Band 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Input means (operation keys) 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. A display device having a first oxide semiconductor layer disposed in a pixel portion and a second oxide semiconductor layer disposed outside the pixel portion, a first conductive layer electrically connected to the first oxide semiconductor layer and functioning as a source electrode or a drain electrode of a transistor; a pixel electrode having a region in contact with the first conductive layer; a second conductive layer having a stacked structure and including a region in contact with an upper surface of the second oxide semiconductor layer; a third conductive layer located above the second oxide semiconductor layer and having a region overlapping with the second oxide semiconductor layer, the first conductive layer comprises a material that transmits visible light; the second conductive layer includes a first conductive film having the same material as the first conductive layer, and a second conductive film having a metal conductive material having a lower resistance than the first conductive layer; the third conductive layer is in a floating state; The third conductive layer overlaps with the second conductive layer.

2. A display device having a first oxide semiconductor layer disposed in a pixel portion and a second oxide semiconductor layer disposed outside the pixel portion, a first conductive layer electrically connected to the first oxide semiconductor layer and functioning as a source electrode or a drain electrode of a transistor; a pixel electrode having a region in contact with the first conductive layer; a second conductive layer having a stacked structure and including a region in contact with an upper surface of the second oxide semiconductor layer; a third conductive layer located above the second oxide semiconductor layer and having a region overlapping with the second oxide semiconductor layer, the first conductive layer comprises a material that transmits visible light; the second conductive layer includes a first conductive film having the same material as the first conductive layer, and a second conductive film having a metal conductive material having a lower resistance than the first conductive layer; the third conductive layer is in a floating state; the third conductive layer has an overlap with the second conductive layer; the second oxide semiconductor layer has a first region overlapping with the second conductive layer, and a second region not overlapping with the second conductive layer and overlapping with the third conductive layer; The second region has a higher resistance than the first region.

Images