Wiring board and method for manufacturing the same

Abstract

To provide a wiring board that enables the easy formation of an insulating layer having a plurality of roughened surfaces with different roughness on the same plane.SOLUTION: A wiring board 10 includes a wiring layer 50, an insulating layer 51 covering the wiring layer 50, and a wiring layer 52 electrically connected to the wiring layer 50 and formed on the upper surface of the insulating layer 51. The insulating layer 51 has a roughened surface 51A and a roughened surface 51B having roughness greater than that of the roughened surface 51A. The roughened surface 51B has a wrinkle pattern W1 formed by buckling. The volume ratio of the wiring layer 50 in a first region overlapping with the roughened surface 51A in a planar view is greater than the volume ratio of the wiring layer 50 in a second region overlapping with the roughened surface 51B in a planar view.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, as a wiring board on which electronic components such as semiconductor elements are mounted, a wiring board in which a plurality of wiring layers and insulating layers are laminated on both the upper and lower surfaces of a core substrate by a build-up method in order to increase the density of the wiring pattern has been known. As this type of wiring board, a wiring board has been proposed in which a high-density wiring layer including an insulating layer made of a photosensitive resin is formed on a low-density wiring layer including an insulating layer made of a thermosetting resin (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-225632 A Summary of the Invention [Problem to be solved by the invention]

[0004] Meanwhile, in the above-mentioned wiring board, it is desirable to easily form an insulating layer having a plurality of roughened surfaces with different roughness on the same plane. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device comprises a first wiring layer, a first insulating layer covering the first wiring layer, and a second wiring layer electrically connected to the first wiring layer and formed on an upper surface of the first insulating layer, wherein the upper surface of the first insulating layer has a first roughened surface and a second roughened surface having a roughness greater than that of the first roughened surface, the second roughened surface having a wrinkle pattern formed by buckling, and a volume fraction of the first wiring layer in a first region overlapping with the first roughened surface in a planar view is greater than a volume fraction of the first wiring layer in a second region overlapping with the second roughened surface in a planar view. Effect of the Invention

[0006] Advantageous Effects of Invention According to one aspect of the present invention, an insulating layer having a plurality of roughened surfaces with different roughnesses on the same plane can be easily formed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view showing a part of the wiring board of the embodiment, specifically, a part surrounded by a dashed line frame in FIG. [Diagram 3] FIG. 3 is a schematic plan view showing a wrinkle pattern according to one embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 14]FIG. 14 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a wiring board according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment will be described with reference to the accompanying drawings. In the attached drawings, for convenience, characteristic parts may be shown enlarged to make the features easier to understand, and the dimensional ratios of each component may differ from one drawing to another. In addition, in the cross-sectional views, in order to make the cross-sectional structure of each component easier to understand, the hatching of some components is shown as a matte finish, and the hatching of some components is omitted.

[0009] (Overall structure of wiring board 10) The wiring board 10 has a wiring structure 11, a wiring structure 12 formed on the upper surface of the wiring structure 11, and a solder resist layer 13 laminated on the lower surface of the wiring structure 11. The wiring structure 11 is, for example, a low-density wiring layer in which a wiring layer with a lower wiring density than the wiring structure 12 is formed. The wiring structure 12 is, for example, a high-density wiring layer in which a wiring layer with a higher wiring density than the wiring structure 11 is formed. The planar shape of the wiring board 10 can be any shape and size. The planar shape of the wiring board 10 can be, for example, a quadrangle of about 20 mm×20 mm to 40 mm×40 mm.

[0010] (Specific structure of wiring structure 11) The wiring structure 11 has a core substrate 20. The core substrate 20 is provided, for example, at the center of the wiring structure 11 in the thickness direction. The core substrate 20 may be a so-called glass epoxy substrate, which is made by impregnating a reinforcing material, glass cloth (woven glass fabric), with a thermosetting insulating resin mainly composed of an epoxy resin and curing the impregnated resin. The reinforcing material is not limited to glass cloth, and may be, for example, a glass nonwoven fabric, an aramid woven fabric, an aramid nonwoven fabric, a liquid crystal polymer (LCP: Liquid Crystal Polymer) woven fabric, or an LCP nonwoven fabric. The thermosetting insulating resin is not limited to epoxy resin, and may be, for example, a resin material such as a polyimide resin or a cyanate resin. The core substrate 20 may contain, for example, a filler such as silica (SiO2) or alumina (Al2O3). The thickness of the core substrate 20 may be, for example, about 800 μm to 2000 μm.

[0011] The core substrate 20 has through holes 20X at required locations (four locations in FIG. 1). The through holes 20X are formed so as to penetrate the core substrate 20 in the thickness direction. A through electrode 21 is formed in the through hole 20X so as to penetrate the core substrate 20 in the thickness direction. The through electrode 21 is formed, for example, so as to fill the through hole 20X. The material of the through electrode 21 can be, for example, copper (Cu) or a copper alloy.

[0012] A wiring layer 22 is formed on the upper surface of the core substrate 20, and a wiring layer 23 is formed on the lower surface of the core substrate 20. These wiring layers 22, 23 are electrically connected to each other via through electrodes 21. The wiring layers 22, 23 may be made of, for example, copper or a copper alloy. The thickness of the wiring layers 22, 23 may be, for example, about 15 μm to 35 μm. The line and space (L / S) of the wiring layers 22, 23 may be, for example, about 20 μm / 20 μm. Here, the line and space refers to the width of the wiring and the distance between adjacent wirings.

[0013] On the upper surface of the core substrate 20, an insulating layer 31, a wiring layer 32, an insulating layer 33, a wiring layer 34, an insulating layer 35, and a via wiring 36 are laminated in this order. The insulating layers 31, 33, and 35 may be made of a non-photosensitive insulating resin mainly composed of a thermosetting resin such as an epoxy resin or a polyimide resin. The insulating layers 31, 33, and 35 may contain a filler such as silica or alumina. The wiring layers 32, 34 and the via wiring 36 may be made of copper or a copper alloy. The insulating layers 31, 33, and 35 may have a thickness of, for example, about 20 μm to 45 μm. The wiring layers 32, 34 may have a thickness of, for example, about 15 μm to 35 μm. The line and space (L / S) of the wiring layers 32, 34 may be about 20 μm / 20 μm.

[0014] The insulating layer 31 is laminated on the upper surface of the core substrate 20 so as to cover the wiring layer 22. The wiring layer 32 is laminated on the upper surface of the insulating layer 31. The wiring layer 32 is formed integrally with, for example, via wiring penetrating the insulating layer 31 in the thickness direction, and is electrically connected to the wiring layer 22 through the via wiring. The insulating layer 33 is laminated on the upper surface of the insulating layer 31 so as to cover the wiring layer 32. The wiring layer 34 is laminated on the upper surface of the insulating layer 33. The wiring layer 34 is formed integrally with, for example, via wiring penetrating the insulating layer 33 in the thickness direction, and is electrically connected to the wiring layer 32 through the via wiring.

[0015] The insulating layer 35 is the uppermost insulating layer in the wiring structure 11. The insulating layer 35 is laminated on the upper surface of the insulating layer 33 so as to cover the wiring layer 34. The insulating layer 35 has a through hole 35X formed therein, which penetrates the insulating layer 35 in the thickness direction and exposes a part of the upper surface of the wiring layer 34.

[0016] The upper surface of the insulating layer 35 is a smooth surface (low roughness surface) with few irregularities. The upper surface of the insulating layer 35 is, for example, a polished surface. The roughness of the upper surface of the insulating layer 35 is set to, for example, an arithmetic mean roughness Ra value of about 15 nm to 40 nm. Here, the arithmetic mean roughness Ra value is a type of numerical value that represents surface roughness, and specifically, is the arithmetic mean of absolute values ​​of height changes within a measurement region measured from the surface, which is the average line.

[0017] The via wiring 36 is formed in the through hole 35X. The via wiring 36 electrically connects the wiring layer 34 and the wiring layer 50 formed on the upper surface of the insulating layer 35. The via wiring 36 is formed so as to fill the through hole 35X. The via wiring 36 is formed in the same shape as the through hole 35X. The via wiring 36 is formed in a tapered shape in which the diameter becomes smaller from the upper side (the wiring layer 50 side) to the lower side (the wiring layer 34 side) in FIG. 1. For example, the via wiring 36 is formed in an inverted truncated cone shape in which the upper end face has a larger diameter than the lower end face. The upper end face of the via wiring 36 is exposed from the insulating layer 35. The upper end face of the via wiring 36 is formed, for example, flush with the upper surface of the insulating layer 35. The upper end face of the via wiring 36 is, for example, a polished surface. The diameter of the upper end face of the via wiring 36 can be, for example, about 60 μm to 70 μm.

[0018] On the lower surface of the core substrate 20, an insulating layer 41, a wiring layer 42, an insulating layer 43, a wiring layer 44, an insulating layer 45, and a wiring layer 46 are laminated in this order. The insulating layers 41, 43, and 45 may be made of a non-photosensitive insulating resin mainly composed of a thermosetting resin such as an epoxy resin or a polyimide resin. The insulating layers 41, 43, and 45 may contain a filler such as silica or alumina. The wiring layers 42, 44, and 46 may be made of copper or a copper alloy. The insulating layers 41, 43, and 45 may have a thickness of, for example, about 20 μm to 45 μm. The wiring layers 42, 44, and 46 may have a thickness of, for example, about 15 μm to 35 μm. The line and space (L / S) of the wiring layers 42, 44, and 46 may be about 20 μm / 20 μm.

[0019] The insulating layer 41 is laminated on the lower surface of the core substrate 20 so as to cover the wiring layer 23. The wiring layer 42 is laminated on the lower surface of the insulating layer 41. The wiring layer 42 is formed integrally with, for example, via wiring penetrating the insulating layer 41 in the thickness direction, and is electrically connected to the wiring layer 23 through the via wiring. The insulating layer 43 is laminated on the lower surface of the insulating layer 41 so as to cover the wiring layer 42. The wiring layer 44 is laminated on the lower surface of the insulating layer 43. The wiring layer 44 is formed integrally with, for example, via wiring penetrating the insulating layer 43 in the thickness direction, and is electrically connected to the wiring layer 42 through the via wiring. The insulating layer 45 is laminated on the lower surface of the insulating layer 43 so as to cover the wiring layer 44. The insulating layer 45 is an insulating layer formed on the lowest layer of the wiring structure 11. The wiring layer 46 is laminated on the lower surface of the insulating layer 45. The wiring layer 46 is a wiring layer formed on the lowest layer of the wiring structure 11. The wiring layer 46 is formed integrally with, for example, via wiring that penetrates the insulating layer 45 in the thickness direction, and is electrically connected to the wiring layer 44 through the via wiring.

[0020] (Specific structure of solder resist layer 13) The solder resist layer 13 is the outermost insulating layer (here, the lowest layer) of the wiring board 10. The solder resist layer 13 is formed on the lower surface of the wiring structure 11, specifically, on the lower surface of the insulating layer 45 formed on the lowest layer of the wiring structure 11 so as to cover the lowest wiring layer 46. The material of the solder resist layer 13 may be, for example, an insulating resin containing a photosensitive resin such as a phenolic resin or a polyimide resin as a main component. The solder resist layer 13 may contain, for example, a filler such as silica or alumina.

[0021] Openings 13X are formed in the solder resist layer 13 to expose parts of the lowermost wiring layer 46 as external connection pads 46P. External connection terminals 76 (see FIG. 4) used when mounting the wiring board 10 on a mounting board such as a motherboard are connected to the external connection pads 46P.

[0022] A surface treatment layer is formed on the lower surface of the wiring layer 46 exposed at the bottom of the opening 13X, as necessary. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating a Ni layer and a Pd layer in this order), and a Pd layer / Au layer (a metal layer formed by laminating a Pd layer and an Au layer in this order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer) or a metal layer formed by electrolytic plating (electrolytic plated metal layer). The surface treatment layer may be an OSP film formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment on the lower surface of the wiring layer 46 exposed in the opening 13X. The OSP film may be an organic coating such as an azole compound or an imidazole compound. When a surface treatment layer is formed on the lower surface of the wiring layer 46, the surface treatment layer functions as the external connection pad 46P. The wiring layer 46 exposed from the opening 13X (or, when a surface treatment layer is formed on the wiring layer 46, the surface treatment layer) itself may be used as an external connection terminal.

[0023] The planar shape of the external connection pads 46P and the openings 13X may be any shape and any size. For example, the planar shape of the external connection pads 46P and the openings 13X may be a circle with a diameter of about 200 μm to 300 μm.

[0024] (Specific structure of wiring structure 12) The wiring structure 12 has a structure in which a wiring layer 50, which is stacked on the upper surface of an insulating layer 35, an insulating layer 51, a wiring layer 52, an insulating layer 53, a wiring layer 54, an insulating layer 55, and a wiring layer 56 are stacked in that order.

[0025] Here, for example, copper or a copper alloy can be used as the material of the wiring layers 50, 52, 54, and 56. For example, a photosensitive insulating resin containing a phenolic resin, a polyimide resin, or the like as a main component can be used as the material of the insulating layers 51, 53, and 55. For example, it is preferable that the material of the insulating layers 51, 53, and 55 does not contain a filler such as silica or alumina.

[0026] Each of the wiring layers 50, 52, 54, 56 is a wiring layer thinner than each of the wiring layers 22, 23, 32, 34, 42, 44, 46 of the wiring structure 11. The thickness of the wiring layers 50, 52, 54 can be, for example, about 1 μm to 5 μm. The thickness of the wiring layer 56 can be, for example, about 10 μm to 15 μm. The line and space (L / S) of the wiring layers 50, 52, 54, 56 can be, for example, about 2 μm / 2 μm. Each of the insulating layers 51, 53, 55 is an insulating layer thinner than each of the insulating layers 31, 33, 35, 41, 43, 45 of the wiring structure 11. The thickness of the insulating layers 51, 53, 55 can be, for example, about 5 μm to 15 μm.

[0027] The wiring layer 50 is laminated on the upper surface of the insulating layer 35 so as to be connected to the upper end surface of the via wiring 36. That is, a part of the lower surface of the wiring layer 50 contacts the upper end surface of the via wiring 36, and the wiring layer 50 and the via wiring 36 are electrically connected. In other words, the wiring layer 50 and the via wiring 36 are electrically connected but are not integrated. Specifically, the wiring layer 50 has, for example, a seed layer formed on the upper end surface of the via wiring 36 and a metal layer formed on the seed layer.

[0028] The wiring layer 50 has, for example, a wiring pattern 50A and a wiring pattern 50B on the same plane. For example, the wiring patterns 50A and 50B have different volumes. The wiring pattern 50A has a larger volume than the wiring pattern 50B.

[0029] The wiring pattern 50A is formed to have a larger surface area (e.g., upper surface area) than the wiring pattern 50B, for example. The wiring pattern 50A is, for example, a plane layer (e.g., a power plane or a GND plane) or a land. The wiring pattern 50A is formed, for example, in a solid shape. The wiring pattern 50B is a finer wiring than the wiring pattern 50A. The wiring pattern 50B is a wiring with a small line and space (L / S), for example, a fine wiring with L / S=5 μm / 5 μm or less. The wiring pattern 50B in this example is a fine wiring with L / S=2 μm / 2 μm or less.

[0030] The wiring pattern 50A and the wiring pattern 50B have different thicknesses, for example. The wiring pattern 50A is formed to be thicker than the wiring pattern 50B. The thickness of the wiring pattern 50A can be, for example, about 2 μm to 5 μm. The thickness of the wiring pattern 50B can be, for example, about 1 μm to 2 μm.

[0031] The wiring pattern 50A and the wiring pattern 50B differ from each other in, for example, the density (degree of density) of the wiring. The wiring pattern 50A is formed at a higher density (i.e., denser) than the wiring pattern 50B. The wiring pattern 50B is formed at a lower density (i.e., sparser) than the wiring pattern 50A.

[0032] The high-density region where the wiring pattern 50A is formed and the low-density region where the wiring pattern 50B is formed have different volume ratios between the volume of the metal (copper in this case) of the wiring layer 50 and the volume of the resin of the insulating layer 51. In the high-density region where the wiring pattern 50A is formed, the ratio of copper is higher and the ratio of resin is lower than in the low-density region where the wiring pattern 50B is formed. That is, in the high-density region where the wiring pattern 50A is formed, the volume ratio of the wiring layer 50 is higher than in the low-density region where the wiring pattern 50B is formed. Here, the volume ratio of the wiring layer 50 is the ratio of the volume of all the wiring layers 50 included in the specific region to the volume of the entire region (i.e., the volume of the entire wiring layers 50 and insulating layers 51 in the specific region).

[0033] The insulating layer 51 is formed on the upper surface of the insulating layer 35 so as to cover the wiring layer 50. The insulating layer 51 has a through hole 51X formed therein, which penetrates the insulating layer 51 in the thickness direction and exposes a part of the upper surface of the wiring layer 50.

[0034] As shown in FIG. 2, the upper surface of the insulating layer 51 has a roughened surface 51A and a roughened surface 51B. The surface roughness of the roughened surface 51A is smaller than that of the roughened surface 51B. Thus, the upper surface of the insulating layer 51 has a plurality of roughened surfaces 51A and 51B having different roughnesses on the same plane. The arithmetic mean height Sa of the roughened surface 51A can be, for example, 200 nm or less. The arithmetic mean height Sa of the roughened surface 51B can be, for example, 2 μm or less. Here, the arithmetic mean height Sa is a type of numerical value representing surface roughness, and is a parameter obtained by extending the arithmetic mean roughness Ra of a line to a surface. The arithmetic mean height Sa is a parameter representing the average of the absolute values ​​of the differences in height from the average surface of each measurement point in the reference region.

[0035] The roughened surface 51A is formed on the upper surface of the insulating layer 51 located above the wiring pattern 50A. The roughened surface 51A is formed at a position overlapping the wiring pattern 50A in a plan view. The roughened surface 51A is formed at a position overlapping the high density region in which the wiring pattern 50A is provided in a plan view. The roughened surface 51B is formed on the upper surface of the insulating layer 51 located above the wiring pattern 50B. The roughened surface 51B is formed at a position overlapping the wiring pattern 50B in a plan view. The roughened surface 51B is formed at a position overlapping the low density region in which the wiring pattern 50B is provided in a plan view.

[0036] In other words, the volume proportion of the wiring layer 50 (here, the wiring pattern 50A) in a first region that overlaps with the roughened surface 51A in a planar view is greater than the volume proportion of the wiring layer 50 (here, the wiring pattern 50B) in a second region that overlaps with the roughened surface 51B in a planar view.

[0037] Roughened surface 51A is a roughened surface formed by, for example, performing a roughening treatment such as a desmear treatment on the upper surface of insulating layer 51. Roughened surface 51A is formed, for example, with random projections and recesses. In FIG. 2, for the sake of simplicity, roughened surfaces 51A, 51B, 53A, and 53B are illustrated as having projections and recesses with a certain regularity.

[0038] The roughened surface 51B is a roughened surface formed by buckling. The roughened surface 51B is formed, for example, with random unevenness. The roughened surface 51B has a wrinkle pattern W1 formed by buckling. The cross-sectional structure of the wrinkle pattern W1 is formed, for example, with a wave-like structure.

[0039] As shown in Fig. 3, the planar shape of the wrinkle pattern W1 is formed, for example, in a meandering shape. The planar shape of the wrinkle pattern W1 is formed, for example, in a shape having curved portions. The planar shape of the wrinkle pattern W1 is formed, for example, in a shape having meandering portions. The planar shape of the wrinkle pattern W1 is formed, for example, in a shape extending in random directions without direction dependency. The planar shape of the wrinkle pattern W1 is formed, for example, in a maze shape.

[0040] 1, the wiring layer 52 is laminated on the upper surface of the insulating layer 51. The wiring layer 52 is electrically connected to the wiring layer 50 through, for example, a via wiring filled in the through hole 51X. The wiring layer 52 is formed integrally with, for example, the via wiring filled in the through hole 51X.

[0041] 2, the wiring layer 52 has, for example, a wiring pattern 52A and a wiring pattern 52B on the same plane. For example, the wiring patterns 52A and 52B have different volumes. The wiring pattern 52A has a larger volume than the wiring pattern 52B.

[0042] The wiring pattern 52A is formed to have a larger surface area (e.g., upper surface area) than the wiring pattern 52B, for example. The wiring pattern 52A is, for example, a plane layer or a land. The wiring pattern 52A is formed in a solid shape, for example. The wiring pattern 52B is a finer wiring than the wiring pattern 52A. The wiring pattern 52B is a wiring with a small line and space (L / S), for example, a fine wiring with L / S=5 μm / 5 μm or less. The wiring pattern 52B in this example is a fine wiring with L / S=2 μm / 2 μm or less.

[0043] The wiring patterns 52A and 52B have different thicknesses, for example. The wiring pattern 52A is formed to be thicker than the wiring pattern 52B. The thickness of the wiring pattern 52A may be, for example, about 2 μm to 5 μm. The thickness of the wiring pattern 52B may be, for example, about 1 μm to 2 μm.

[0044] The wiring pattern 52A and the wiring pattern 52B differ from each other in, for example, the density of the wiring. The wiring pattern 52A is formed at a higher density (i.e., denser) than the wiring pattern 52B. The wiring pattern 52B is formed at a lower density (i.e., sparser) than the wiring pattern 52A.

[0045] The high-density region where the wiring pattern 52A is formed and the low-density region where the wiring pattern 52B is formed have different volume ratios between the volume of the metal (copper in this case) of the wiring layer 52 and the volume of the resin of the insulating layer 53. In the high-density region where the wiring pattern 52A is formed, the ratio of copper is higher and the ratio of resin is lower than in the low-density region where the wiring pattern 52B is formed. That is, in the high-density region where the wiring pattern 52A is formed, the volume ratio of the wiring layer 52 is higher than in the low-density region where the wiring pattern 52B is formed. Here, the volume ratio of the wiring layer 52 is the ratio of the volume of all the wiring layers 52 included in the specific region to the volume of the entire region (i.e., the volume of the entire wiring layers 52 and insulating layers 53 in the specific region).

[0046] The wiring pattern 52A is formed on the roughened surface 51B. For example, the wiring pattern 52A is provided at a position overlapping with the wiring pattern 50B in a planar view. The wiring pattern 52B is formed on the roughened surface 51A. For example, the wiring pattern 52B is provided at a position overlapping with the wiring pattern 50A in a planar view.

[0047] The wiring layer 52, i.e., the wiring patterns 52A and 52B, has a seed layer 52C formed on the upper surface of the insulating layer 51 and a metal layer 52D formed on the upper surface of the seed layer 52C. The seed layer 52C (second seed layer) of the wiring pattern 52A is formed in a shape that conforms to the roughened surface 51B. The metal layer 52D (second metal layer) of the wiring pattern 52A is laminated on the seed layer 52C formed along the roughened surface 51B. The seed layer 52C (first seed layer) of the wiring pattern 52B is formed in a shape that conforms to the roughened surface 51A. The metal layer 52D (first metal layer) of the wiring pattern 52B is laminated on the seed layer 52C formed along the roughened surface 51A.

[0048] The seed layer 52C may be, for example, a metal film formed by a sputtering method, that is, a sputtered film. The seed layer 52C formed by a sputtering method may be, for example, a two-layered metal film in which a Ti layer made of titanium (Ti) and a Cu layer made of Cu are laminated in this order on the upper surface of the insulating layer 51. In this case, the thickness of the Ti layer may be, for example, about 20 nm to 50 nm, and the thickness of the Cu layer may be, for example, about 100 nm to 300 nm. The Ti layer functions as a metal barrier film that suppresses the diffusion of copper from the Cu layer or the metal layer 52D (for example, the Cu layer) to the insulating layer 51. As a material of the metal film that functions as a metal barrier film, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. may be used in addition to Ti. The seed layer 52C may be, for example, an electroless plated metal film formed by an electroless plating method. The seed layer 52C formed by electroless plating may be a metal film having a single-layer structure made of a Cu layer.

[0049] The metal layer 52D is formed so as to cover the entire upper surface of the seed layer 52C. For example, an electroplated metal layer can be used as the metal layer 52D. Note that, for example, copper or a copper alloy can be used as the material of the metal layer 52D.

[0050] Here, in the wiring patterns 52A and 52B, for example, the seed layers 52C are formed to have the same thickness, whereas the metal layers 52D are formed to have different thicknesses.

[0051] 1, the insulating layer 53 is formed on the upper surface of the insulating layer 51 so as to cover the wiring layer 52. The insulating layer 53 has a through hole 53X formed therein, which penetrates the insulating layer 53 in the thickness direction and exposes a part of the upper surface of the wiring layer 52.

[0052] 2, the upper surface of insulating layer 53 has roughened surface 53A and roughened surface 53B. The surface roughness of roughened surface 53A is smaller than the surface roughness of roughened surface 53B. In this manner, the upper surface of insulating layer 53 has a plurality of roughened surfaces 53A, 53B having different roughnesses on the same plane. The arithmetic mean height Sa of roughened surface 53A can be, for example, 200 nm or less. The arithmetic mean height Sa of roughened surface 53B can be, for example, 2 μm or less.

[0053] Roughened surface 53A is formed on the upper surface of insulating layer 53 located above wiring pattern 52A. Roughened surface 53A is formed at a position overlapping wiring pattern 52A in a plan view. Roughened surface 53A is formed at a position overlapping a high density region in which wiring pattern 52A is provided in a plan view. Roughened surface 53B is formed on the upper surface of insulating layer 53 located above wiring pattern 52B. Roughened surface 53B is formed at a position overlapping wiring pattern 52B in a plan view. Roughened surface 53B is formed at a position overlapping a low density region in which wiring pattern 52B is provided in a plan view.

[0054] Roughened surface 53A is a roughened surface formed by, for example, performing a roughening treatment such as a desmear treatment on the upper surface of insulating layer 53. Roughened surface 53A is formed, for example, with random projections and recesses. Roughened surface 53B is a roughened surface formed by buckling. Roughened surface 53B is formed with random projections and recesses. Roughened surface 53B has, for example, a wrinkle pattern W1 formed by buckling, similar to roughened surface 51B.

[0055] 1, the wiring layer 54 is laminated on the upper surface of the insulating layer 53. The wiring layer 54 is electrically connected to the wiring layer 52 through, for example, a via wiring filled in the through hole 53X. The wiring layer 54 is formed integrally with, for example, the via wiring filled in the through hole 53X.

[0056] As shown in FIG. 2, the wiring layer 54 has wiring patterns 54A and 54B on the same plane, for example. The wiring pattern 54A is formed to have a larger surface area (for example, the area of ​​the upper surface) than the wiring pattern 54B, for example. The wiring pattern 54A is, for example, a plane layer or a land. The wiring pattern 54A is formed in a solid shape, for example. The wiring pattern 54B is, for example, a finer wiring than the wiring pattern 54A. The wiring pattern 54B is a wiring with a small line and space (L / S), for example, a fine wiring pattern with L / S=5 μm / 5 μm or less. The wiring pattern 54B in this example is a fine wiring with L / S=2 μm / 2 μm or less. The wiring patterns 54A and 54B are formed to have the same thickness, for example. The thicknesses of the wiring patterns 54A and 54B can be, for example, about 1 μm to 5 μm.

[0057] The wiring pattern 54A is formed on the roughened surface 53B. For example, the wiring pattern 54A is provided at a position overlapping with the wiring pattern 52B in a planar view. The wiring pattern 54B is formed on the roughened surface 53A. For example, the wiring pattern 54B is provided at a position overlapping with the wiring pattern 52A in a planar view.

[0058] The wiring layer 54, i.e., the wiring patterns 54A and 54B, has a seed layer 54C formed on the upper surface of the insulating layer 53 and a metal layer 54D formed on the upper surface of the seed layer 54C. The seed layer 54C of the wiring pattern 54A is formed in a shape that conforms to the roughened surface 53B. The seed layer 54C of the wiring pattern 54B is formed in a shape that conforms to the roughened surface 53A. As the seed layer 54C, for example, a sputtered film or an electroless plated metal film can be used, similar to the seed layer 52C. The metal layer 54D is formed so as to cover the entire upper surface of the seed layer 54C. As the metal layer 54D, for example, an electrolytic plated metal layer can be used, similar to the metal layer 52D.

[0059] 1, insulating layer 55 is formed on the upper surface of insulating layer 53 so as to cover wiring layer 54. Insulating layer 55 has through-holes 55X formed therein, which penetrate insulating layer 55 in the thickness direction and expose a portion of the upper surface of wiring layer 54. The upper surface of insulating layer 55 is formed so as to have only a single surface roughness, for example. The arithmetic mean height Sa of the upper surface of insulating layer 55 can be, for example, 200 nm or less.

[0060] The wiring layer 56 is laminated on the upper surface of the insulating layer 55. The wiring layer 56 is electrically connected to the wiring layer 54 through the via wiring filled in the through hole 55X. The wiring layer 56 is formed integrally with the via wiring filled in the through hole 55X, for example, and has a pad P1 protruding from the upper surface of the insulating layer 55. The planar shape of the pad P1 can be any shape and any size. The planar shape of the pad P1 can be, for example, a circular shape with a diameter of about 20 μm to 30 μm. The pitch of the pads P1 can be, for example, about 40 μm to 60 μm. The thickness of the pads P1 can be, for example, about 10 μm to 15 μm. The pads P1 function as pads for mounting electronic components for electrically connecting to electronic components such as semiconductor chips.

[0061] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or only the top surface) of the pad P1. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, and a Pd layer / Au layer, and an OSP film.

[0062] (Structure of semiconductor device 60) Next, the structure of the semiconductor device 60 will be described with reference to FIG. The semiconductor device 60 includes a wiring substrate 10, one or more semiconductor chips 70, an underfill resin 75, and external connection terminals 76.

[0063] The semiconductor chip 70 is flip-chip mounted on the wiring substrate 10. For example, bumps 71 formed on a circuit formation surface (here, the lower surface) of the semiconductor chip 70 are bonded to pads P1 of the wiring substrate 10, so that the semiconductor chip 70 is electrically connected to the wiring layer 56 via the bumps 71.

[0064] The semiconductor chip 70 may be, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip. The semiconductor chip 70 may be, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or a flash memory chip. When multiple semiconductor chips 70 are mounted on the wiring board 10, a logic chip and a memory chip may be combined and mounted on the wiring board 10.

[0065] The size of the semiconductor chip 70 may be, for example, about 3 mm×3 mm to 12 mm to 12 mm in plan view, and the thickness of the semiconductor chip 70 may be, for example, about 50 μm to 100 μm.

[0066] For example, a gold bump or a solder bump can be used as the bump 71. For example, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and silver (Ag), an alloy of Sn, Ag and Cu, etc. can be used as the material of the solder bump.

[0067] The underfill resin 75 is provided so as to fill the gap between the wiring board 10 and the semiconductor chip 70. As the material for the underfill resin 75, for example, an insulating resin such as an epoxy resin can be used.

[0068] The external connection terminals 76 are formed on the external connection pads 46P of the wiring board 10. The external connection terminals 76 are connection terminals that are electrically connected to pads provided on a mounting board such as a motherboard (not shown). The external connection terminals 76 may be, for example, solder balls or lead pins. The external connection terminals 76 in this example are solder balls.

[0069] (Method of Manufacturing Wiring Board 10) Next, a description will be given of a method for manufacturing the wiring board 10. For ease of explanation, the parts that will ultimately become the components of the wiring board 10 will be described by using the reference numerals of the final components.

[0070] 5, a structure is prepared in which wiring layer 22, insulating layer 31, wiring layer 32, insulating layer 33, wiring layer 34, insulating layer 35, and via wiring 36 are laminated in this order on the upper surface of core substrate 20. Also, a structure is prepared in which wiring layer 23, insulating layer 41, wiring layer 42, insulating layer 43, wiring layer 44, insulating layer 45, and wiring layer 46 are laminated in this order on the lower surface of core substrate 20. Such a structure can be manufactured by a known manufacturing method, and therefore a detailed description will be omitted here.

[0071] Next, the upper surface of the insulating layer 35 and the upper end surface of the via wiring 36 are polished by a CMP (Chemical Mechanical Polishing) method or the like. By this process, the upper surface of the insulating layer 35 and the upper end surface of the via wiring 36 are formed to be flush with each other. Furthermore, by polishing the upper surface of the insulating layer 35, the upper surface of the insulating layer 35 is smoothed. For example, the roughness of the upper surface of the insulating layer 35 before polishing is about 300 nm to 400 nm in arithmetic mean roughness Ra value, whereas the roughness of the upper surface of the insulating layer 35 can be made to about 15 nm to 40 nm in arithmetic mean roughness Ra value by polishing. In other words, in this process, the upper surface of the insulating layer 35 is polished so as to be smoothed. By the polishing in this process, the upper surface of the insulating layer 35 and the upper end surface of the via wiring 36 become polished surfaces.

[0072] Through the above manufacturing steps, the wiring structure 11 is manufactured. 6, a wiring layer 50 is formed on the upper surface of the insulating layer 35. The wiring layer 50 can be formed by using various wiring forming methods such as a subtractive method or a semi-additive method. The wiring layer 50 is formed to have a wiring pattern 50A and a wiring pattern 50B.

[0073] 7, an insulating layer 51 is formed on the upper surface of the insulating layer 35 so as to cover the wiring layer 50. For example, when a resin film is used as the insulating layer 51, the resin film is laminated on the upper surface of the insulating layer 35 by thermocompression bonding to form the insulating layer 51. As the resin film, for example, a film of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. Also, when a liquid or paste insulating resin is used as the insulating layer 51, for example, the liquid or paste insulating resin is applied to the upper surface of the insulating layer 35 by a spin coat method or the like to form the insulating layer 51. As the liquid or paste insulating resin, for example, a photosensitive resin such as a phenolic resin or a polyimide resin can be used. Note that the insulating layer 51 in this process is in an uncured state.

[0074] 8, only the surface layer 51S of the insulating layer 51 is cured. For example, the uncured insulating layer 51 is cured (curing process) in an atmosphere at a temperature of about 150° C. to 200° C., thereby curing only the surface layer 51S of the insulating layer 51. In this process, curing is performed so that an inner layer portion of the insulating layer 51 that is located inside the surface layer 51S is not cured. That is, in this process, the curing process time and the like are set so that the inner layer portion of the insulating layer 51 is not cured. Therefore, the inner layer portion of the insulating layer 51 in this process is in an uncured state.

[0075] 9, a through hole 51X that exposes a part of the upper surface of the wiring layer 50 is formed in the insulating layer 51. The through hole 51X can be formed by laser processing using, for example, a CO2 laser, a UV-YAG laser, or the like.

[0076] Next, in the case where the through holes 51X are formed by laser processing, a desmear process is carried out to remove resin smears adhering to the exposed surface of the wiring layer 50 exposed at the bottom of the through holes 51X.

[0077] As shown in FIG. 10, the upper surface of the insulating layer 51 and the inner wall surface of the through hole 51X (see FIG. 9) are roughened by the desmear treatment. As a result, the entire upper surface of the insulating layer 51 is formed into a roughened surface 51A. At this time, the surface roughness of the roughened surface 51A can be set to, for example, 200 nm or less in terms of arithmetic mean height Sa. The surface roughness of the roughened surface 51A is set to a degree that does not interfere with the formation of fine wiring in a later process. Note that, although the upper surface of the insulating layer 51 is roughened by the desmear treatment in this example, the upper surface of the insulating layer 51 may be roughened by, for example, a plasma treatment such as O2 plasma ashing.

[0078] Next, in the process shown in FIG. 11, a seed layer 52C is formed so as to cover the entire upper surface of the insulating layer 51 and the entire inner surface of the through hole 51X (see FIG. 9). The seed layer 52C can be formed by, for example, a sputtering method or an electroless plating method. For example, when forming the seed layer 52C by a sputtering method, first, titanium (Ti) is deposited by sputtering on the upper surface of the insulating layer 51 to cover the upper surface of the insulating layer 51 to form a Ti layer. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This makes it possible to form the seed layer 52C of a two-layer structure (Ti layer / Cu layer). Also, when forming the seed layer 52C by an electroless plating method, for example, the seed layer 52C made of a Cu layer (one-layer structure) can be formed by an electroless copper plating method. The seed layer 52C in this process is formed along the roughened surface 51A of the insulating layer 51.

[0079] 12, the entire insulating layer 51 is cured. For example, the insulating layer 51 is cured in an atmosphere at a temperature of about 150°C to 200°C, thereby curing the entire insulating layer 51. That is, in this process, the inner layer portion of the insulating layer 51 is cured. After that, when the temperature returns to room temperature, each member of the structure shown in FIG. 12 shrinks. At this time, buckling occurs in the upper layer of the insulating layer 51 and the seed layer 52C depending on the difference between the elastic modulus of the insulating layer 51 and the elastic modulus of the seed layer 52C. To be more specific, in the structure shown in FIG. 12, the seed layer 52C having a higher elasticity than the insulating layer 51 is formed on the upper surface of the insulating layer 51 having a low elasticity. Here, the contraction force of the insulating layer 51 having a low elasticity when it returns to room temperature is larger than the contraction force of the seed layer 52C having a high elasticity when it returns to room temperature. Due to the difference in the contraction force between the insulating layer 51 and the seed layer 52C, a compressive stress is applied to the insulating layer 51 and the seed layer 52C in the surface direction, and the compressive stress causes buckling in the upper layer of the insulating layer 51 and the seed layer 52C. Such buckling is likely to occur in a region where the difference between the elastic modulus of the wiring layer 50 and the insulating layer 51, which are the base layer, and the elastic modulus of the seed layer 52C, which is the surface layer, is large. Here, when the volume ratio of the high elasticity wiring layer 50 in the base layer is small, the volume ratio of the low elasticity insulating layer 51 is large, so that the elastic modulus of the entire base layer is low. Therefore, in the region where the wiring pattern 50B, which has a smaller volume than the wiring pattern 50A, is formed, the elastic modulus of the entire base layer is lower than that of the wiring pattern 50A. Therefore, in the region where the wiring pattern 50B is formed, the difference between the elastic modulus of the base layer and the elastic modulus of the seed layer 52C, which is the surface layer, is large, so that buckling occurs in the upper layer of the insulating layer 51 and the seed layer 52C. As a result, a wrinkle pattern W1 is formed due to buckling on the upper surface of the insulating layer 51 in the region where the wiring pattern 50B is formed, and a roughened surface 51B including the wrinkle pattern W1 is formed.

[0080] Here, it is known that the wavelength λ of the wrinkle pattern W1, that is, the width of the wrinkle pattern W1, is determined by the following formula: In the following formula, E1 is the Young's modulus of the surface layer (here, the seed layer 52C), E2 is the Young's modulus of the underlayer (here, the wiring layer 50 and the insulating layer 51), and h is the thickness of the surface layer (here, the seed layer 52C).

[0081] λ ∝ h(E1 / E2) 1 / 3 As can be seen from the above formula, by adjusting the difference in Young's modulus between the surface layer and the base layer and the thickness of the surface layer, the wavelength λ of the wrinkle pattern W1 can be adjusted, and the roughness of the roughened surface 51B including the wrinkle pattern W1 can be adjusted. For example, as the difference between the Young's modulus E1 of the surface layer and the Young's modulus E2 of the base layer increases, the wavelength λ of the wrinkle pattern W1 increases.

[0082] In this embodiment, the Young's modulus E2 of the underlayer is adjusted by adjusting the volume ratio of the wiring layer 50. This adjusts the position where the wrinkle pattern W1 and the roughened surface 51B including the wrinkle pattern W1 are formed, and also adjusts the roughness of the roughened surface 51B. In more detail, in a region where the roughness of the upper surface of the insulating layer 51 is desired to be increased, the volume ratio of the wiring layer 50 is reduced to form the roughened surface 51B including the wrinkle pattern W1 on the upper surface of the insulating layer 51. For example, in a region where the roughness of the upper surface of the insulating layer 51 is desired to be increased, a wiring pattern 50B having a small volume is formed, or the wiring layer 50 is not formed. On the other hand, in a region where the roughness of the upper surface of the insulating layer 51 is desired to be kept small, the volume ratio of the wiring layer 50 is increased to maintain the upper surface of the insulating layer 51 as the roughened surface 51A. For example, in a region where the roughness of the upper surface of the insulating layer 51 is desired to be kept small, a wiring pattern 50A having a large volume is formed. An example of a region where it is desired to maintain the roughness of the upper surface of the insulating layer 51 small is a region where fine wiring is to be formed on the upper surface of the insulating layer 51.

[0083] By the adjustment described above, the roughened surface 51A is maintained in the region where the wiring pattern 50A is formed, and the roughened surface 51B including the wrinkle pattern W1 is formed in the region where the wiring pattern 50B is formed. By the process described above, the roughened surfaces 51A and 51B having a plurality of roughnesses are formed on the upper surface of the insulating layer 51. At this time, the seed layer 52C formed on the upper surface of the insulating layer 51 is formed in a shape that conforms to the roughened surfaces 51A and 51B. Therefore, the upper surface of the seed layer 52C has a roughened surface similar to the roughened surfaces 51A and 51B.

[0084] When the seed layer 52C is formed by a dry process such as a sputtering method, the seed layer 52C is formed in a temperature environment of about 150° C. to 200° C., so that the entire insulating layer 51 can be cured simultaneously with the formation of the seed layer 52C. Therefore, when the seed layer 52C is formed by a dry process, curing that is performed separately from the formation of the seed layer 52C can be omitted.

[0085] Next, in the process shown in FIG. 13, a resist layer 80 having opening patterns 80X, 80Y at predetermined positions is formed on the seed layer 52C. The opening pattern 80X is formed so as to expose the seed layer 52C in a portion corresponding to the formation region of the wiring pattern 52A (see FIG. 2). The opening pattern 80X is formed so as to expose the seed layer 52C formed on the roughened surface 51B. The opening pattern 80Y is formed so as to expose the seed layer 52C in a portion corresponding to the formation region of the wiring pattern 52B (see FIG. 2). The opening pattern 80Y is formed so as to expose the seed layer 52C formed on the roughened surface 51A. For example, a material having plating resistance against the electrolytic plating process in the next process can be used as the material of the resist layer 80. For example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin) can be used as the material of the resist layer 80. When a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the seed layer 52C by thermocompression bonding, and the dry film is patterned by photolithography to form the resist layer 80 having the opening patterns 80X, 80Y. Note that, when a liquid photoresist is used, the resist layer 80 can be formed through the same process.

[0086] 14, the seed layer 52C is subjected to electrolytic plating using the resist layer 80 as a plating mask, with the seed layer 52C being used as a plating power supply layer. That is, electrolytic plating, here electrolytic Cu plating, is performed on the upper surface of the seed layer 52C exposed from the opening patterns 80X, 80Y of the resist layer 80. This process forms the metal layer 52D provided inside the opening patterns 80X, 80Y. At this time, the metal layer 52D formed in the opening pattern 80X is formed thicker than the metal layer 52D formed in the opening pattern 80Y. Although not shown, the metal layer 52D is formed so as to fill the through-hole 51X (see FIG. 9) located inside the seed layer 52C.

[0087] Next, in a process shown in FIG. 15, the resist layer 80 shown in FIG. 14 is removed by an alkaline stripping solution (for example, an organic amine stripping solution, caustic soda, acetone, ethanol, or the like).

[0088] 16, unnecessary seed layer 52C is removed by etching using metal layer 52D as an etching mask. Through this process, wiring pattern 52A composed of seed layer 52C and metal layer 52D is formed on roughened surface 51B, and wiring pattern 52B composed of seed layer 52C and metal layer 52D is formed on roughened surface 51A. In this manner, wiring layer 52 having wiring patterns 52A and 52B is formed on the upper surface of insulating layer 51.

[0089] 17, an insulating layer 53 that covers the wiring layer 52 is formed on the upper surface of the insulating layer 51. The upper surface of the insulating layer 53 is formed to have a roughened surface 53A provided above the wiring pattern 52A and a roughened surface 53B provided above the wiring pattern 52B. The insulating layer 53 can be formed by the same processes as those shown in FIGS. 7 to 12.

[0090] Next, a wiring layer 54 is formed on the upper surface of the insulating layer 53. The wiring layer 54 is formed to have a wiring pattern 54A laminated on the roughened surface 53B and a wiring pattern 54B laminated on the roughened surface 53A. These wiring patterns 54A, 54B are formed to have a seed layer 54C formed on the roughened surfaces 53B, 53A and a metal layer 54D laminated on the seed layer 54C. The wiring layer 54 can be formed by the same steps as those shown in FIGS. 13 to 16.

[0091] Next, in the process shown in FIG. 18, an insulating layer 55 having a through hole 55X exposing a part of the upper surface of the wiring layer 54 is formed on the upper surface of the insulating layer 53. For example, when a resin film is used as the insulating layer 55, the resin film is laminated on the upper surface of the insulating layer 53 by thermocompression bonding, and the resin film is patterned by photolithography to form the insulating layer 55. Note that, as the resin film, for example, a film of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. Also, when a liquid or paste insulating resin is used as the insulating layer 55, for example, the liquid or paste insulating resin is applied to the upper surface of the insulating layer 53 by a spin coat method or the like, and the insulating resin is patterned by photolithography to form the insulating layer 55. Note that, as the liquid or paste insulating resin, for example, a photosensitive resin such as a phenolic resin or a polyimide resin can be used.

[0092] Next, for example, by a semi-additive method, via wiring is formed by filling the through hole 55X, and a wiring layer 56 is formed which is electrically connected to the wiring layer 54 through the via wiring and has a pad P1 laminated on the upper surface of the insulating layer 55. If necessary, a surface treatment layer may be formed on the surface of the pad P1.

[0093] By the above manufacturing process, the wiring structure 12 can be laminated on the upper surface of the insulating layer 35 formed on the uppermost layer of the wiring structure 11. 1 is laminated on the lower surface of the insulating layer 45. The solder resist layer 13 is formed so as to have openings 13X for exposing external connection pads 46P defined at required locations of the bottom wiring layer 46 of the wiring structure 11.

[0094] By the above manufacturing process, the wiring board 10 shown in FIG. 1 can be manufactured. Next, the effects of this embodiment will be described. (1) The wiring board 10 has a wiring layer 50, an insulating layer 51 covering the wiring layer 50, a wiring layer 52 electrically connected to the wiring layer 50 and formed on the upper surface of the insulating layer 51, and an insulating layer 53 formed on the upper surface of the insulating layer 51 so as to cover the wiring layer 52. The insulating layer 51 has a roughened surface 51A and a roughened surface 51B having a roughness greater than that of the roughened surface 51A. The roughened surface 51B has a wrinkle pattern W1 formed by buckling. The volume ratio of the wiring layer 50 in a first region overlapping with the roughened surface 51A in a planar view is greater than the volume ratio of the wiring layer 50 in a second region overlapping with the roughened surface 51B in a planar view.

[0095] According to this configuration, the upper surface of the insulating layer 51 is provided with a roughened surface 51A and a roughened surface 51B having a roughness greater than that of the roughened surface 51A. Therefore, the upper surface of the insulating layer 51 is provided with a plurality of roughened surfaces 51A and 51B having different roughnesses on the same plane. At this time, the roughened surface 51B has a wrinkle pattern W1 formed by buckling. Here, the buckling can be formed by adjusting the difference between the elastic modulus of the base layer and the elastic modulus of the surface layer. Therefore, it is possible to suppress an increase in the manufacturing process due to the formation of the roughened surface 51B. For example, compared to the case where a plurality of roughened surfaces having different roughnesses are formed by a plurality of roughening processes, it is not necessary to form a resist layer for masking a plurality of times, so that the plurality of roughened surfaces 51A and 51B can be easily formed.

[0096] (2) Furthermore, roughened surface 51A is formed in a first region where the volume ratio of wiring layer 50 is large, and roughened surface 51B having wrinkle pattern W1 is formed in a second region where the volume ratio of wiring layer 50 is small. That is, by adjusting the volume ratio of wiring layer 50, the position where wrinkle pattern W1 is formed, and therefore the position where roughened surface 51B is formed, can be adjusted. Therefore, by adjusting the design of wiring layer 50, roughened surface 51B with high roughness can be easily formed at a desired position.

[0097] (3) Furthermore, a wiring layer 52 is formed on the upper surface of the insulating layer 51 having the roughened surfaces 51A and 51B, and an insulating layer 53 is formed on the upper surface of the insulating layer 51 so as to cover the wiring layer 52. Therefore, when the wiring layer 52 is formed on the roughened surface 51B having a large roughness, the contact area between the wiring layer 52 and the roughened surface 51B can be increased, so that the adhesion between the wiring layer 52 and the insulating layer 51 can be improved. Similarly, when the insulating layer 53 is formed on the roughened surface 51B having a large roughness, the contact area between the insulating layer 53 and the roughened surface 51B can be increased, so that the adhesion between the insulating layer 53 and the insulating layer 51 can be improved. On the other hand, fine wiring can be suitably formed as the wiring layer 52 on the roughened surface 51A having a small roughness.

[0098] (4) The volume of wiring pattern 50A provided in the first region overlapping with roughened surface 51A in a plan view is larger than the volume of wiring pattern 50B provided in the second region overlapping with roughened surface 51B in a plan view. With this configuration, the volume ratio of wiring layer 50 in the first region can be easily adjusted to be larger than the volume ratio of wiring layer 50 in the second region.

[0099] (5) The wiring pattern 50A is formed to be thicker than the wiring pattern 50B. The upper surface of the wiring pattern 50A is formed to have a larger area than the upper surface of the wiring pattern 50B. With these configurations, the volume of the wiring pattern 50A can be easily adjusted to be larger than the volume of the wiring pattern 50B. Furthermore, the volume ratio of the wiring layer 50 in the first region can be easily adjusted to be larger than the volume ratio of the wiring layer 50 in the second region.

[0100] (6) The wrinkle pattern W1 has a maze-like planar shape. Such a wrinkle pattern W1 is formed so as to extend in a random direction. When the wiring layer 52 is formed on the roughened surface 51B including the wrinkle pattern W1, the wrinkle pattern W1 can increase the contact area between the insulating layer 51 and the wiring layer 52. Therefore, the contact area between the insulating layer 51 and the wiring layer 52 can be increased in the random direction in which the wrinkle pattern W1 extends, and the adhesion between the insulating layer 51 and the wiring layer 52 can be improved. Therefore, even if stress acts in various directions on the interface between the roughened surface 51B and the wiring layer 52, the occurrence of cracks at the interface between the roughened surface 51B and the wiring layer 52 due to the stress can be suitably suppressed.

[0101] (7) Wiring layer 52 has wiring pattern 52B formed on roughened surface 51A and wiring pattern 52A formed on roughened surface 51B. Wiring pattern 52B is finer than wiring pattern 52A. With this configuration, wiring pattern 52A, which is fine wiring, is formed on roughened surface 51A, which has a small degree of roughness. Therefore, even if roughened surface 51B, which has a large degree of roughness, is formed on the upper surface of insulating layer 51, wiring pattern 52A, which is fine wiring, can be suitably formed on the upper surface of insulating layer 51.

[0102] (8) Moreover, wiring pattern 52B having a larger surface area than wiring pattern 52A is formed on roughened surface 51B having a large roughness. With this configuration, it is possible to suitably improve the adhesion between wiring pattern 52B having a large surface area, such as a plane layer or a land, and insulating layer 51.

[0103] (Other embodiments) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0104] The planar shape of the wrinkle pattern W1 in the above embodiment can be changed as appropriate. For example, the planar shape of the wrinkle pattern W1 may be formed in a stripe shape. In this case, the direction in which each wrinkle pattern W1 extends can be any direction. The planar shape of the wrinkle pattern W1 can be controlled by adjusting, for example, the contraction direction of the insulating layers 51 and 53, the degree of density of the wiring layers 50 and 52, the difference in Young's modulus between the base layer and the surface layer, etc.

[0105] In the above embodiment, the wiring pattern 50A is formed to be thicker than the wiring pattern 50B, but this is not limited to the above. For example, the thickness of the wiring pattern 50A may be the same as that of the wiring pattern 50B, so long as the volume of the wiring pattern 50A is larger than the volume of the wiring pattern 50B. Similarly, the thickness of the wiring patterns 52A and 52B may be changed.

[0106] In the above embodiment, the area of ​​the upper surface of the wiring pattern 50A is formed to be larger than the area of ​​the upper surface of the wiring pattern 50B, but this is not limited to this. For example, the area of ​​the upper surface of the wiring pattern 50A may be formed to be the same size as the area of ​​the upper surface of the wiring pattern 50B, so long as the volume of the wiring pattern 50A is within a range larger than the volume of the wiring pattern 50B. Similarly, the area of ​​the upper surface of the wiring pattern 50A and the area of ​​the upper surface of the wiring pattern 50B can be changed.

[0107] In the above embodiment, the wiring pattern 50B is formed to be finer than the wiring pattern 50A, but the present invention is not limited to this. For example, as shown in Fig. 19, the wiring pattern 50B may be formed in a solid shape similar to the wiring pattern 50A. In this case, it is preferable to form the wiring pattern 50B thinner than the wiring pattern 50A so that the volume of the wiring pattern 50B is smaller than the volume of the wiring pattern 50A. Similarly, the wiring patterns 52A and 52B can also be changed.

[0108] In the above embodiment, the wiring pattern 50B is provided below the roughened surface 51B including the wrinkle pattern W1. However, for example, the wiring layer 50 may not be provided below the roughened surface 51B.

[0109] The upper surface of the insulating layer 55 in the above embodiment may be provided with a plurality of roughened surfaces with different roughnesses. In the above embodiment, the insulating layers 51, 53 of the wiring structure 12 are provided with the roughened surfaces 51A, 51B, 53A, 53B having different roughnesses, but the present invention is not limited to this. For example, the insulating layers 31, 33, 41, 43, 45 of the wiring structure 11 may be provided with the roughened surfaces having different roughnesses.

[0110] The number of wiring layers and insulating layers in the wiring structure 11 of the above embodiment, the layout of the wiring, and the like can be modified and changed in various ways. In the above embodiment, the upper and lower wiring layers 22, 23 of the core substrate 20 are electrically connected to each other via the through electrodes 21 filling the through holes 20X of the core substrate 20. However, the present invention is not limited to this, and the upper and lower wiring layers 22, 23 of the core substrate 20 may be electrically connected to each other via a through-hole plating layer provided on the inner wall of the through hole 20X. In this case, the hole of the through hole 20X formed on the inside of the through-hole plating layer may be filled with resin.

[0111] The wiring structure 11 may be omitted. The number of wiring layers and insulating layers in the wiring structure 12 of the above embodiment, the layout of the wiring, and the like can be modified and changed in various ways.

[0112] In the above embodiment, the solder resist layer 13 is given as an example of the protective insulating layer that is the outermost layer of the wiring board 10. However, the protective insulating layer can be formed from various insulating resins having photosensitivity.

[0113] The solder resist layer 13 in the above embodiment may be omitted. In the above embodiment, the semiconductor chip 70 is mounted on the wiring board 10. However, the present invention is not limited to this, and instead of the semiconductor chip 70, for example, chip components such as chip capacitors, chip resistors, and chip inductors, or electronic components other than semiconductor chips, such as crystal resonators, may be mounted on the wiring board 10.

[0114] Furthermore, the mounting form of electronic components such as the semiconductor chip 70, chip components, and crystal resonators (for example, flip chip mounting, wire bonding mounting, solder mounting, or a combination thereof) can be modified or changed in various ways. [Explanation of symbols]

[0115] 10 Wiring board 50 Wiring layer (1st wiring layer) 50A Wiring Pattern (First Wiring Pattern) 50B Wiring pattern (second wiring pattern) 51 Insulating layer (first insulating layer) 51A Roughened surface (1st roughened surface) 51B Roughened surface (second roughened surface) 51S surface layer 51X through hole 52 Wiring layer (2nd wiring layer) 52A Wiring Pattern (4th Wiring Pattern) 52B Wiring pattern (third wiring pattern) 52C Seed layer (first seed layer, second seed layer) 52D Metal layer (1st metal layer, 2nd metal layer) 53 Insulating layer 53A Roughened surface 53B Roughened surface 60 Semiconductor Devices W1 Wrinkle Pattern

Claims

1. A first wiring layer; a first insulating layer covering the first wiring layer; a second wiring layer electrically connected to the first wiring layer and formed on an upper surface of the first insulating layer; an upper surface of the first insulating layer has a first roughened surface and a second roughened surface having a roughness greater than that of the first roughened surface; the second rough surface has a wrinkle pattern formed by buckling; A wiring board, wherein a volume ratio of the first wiring layer in a first region overlapping with the first roughened surface in a planar view is greater than a volume ratio of the first wiring layer in a second region overlapping with the second roughened surface in a planar view.

2. the first wiring layer has a first wiring pattern provided in the first region and a second wiring pattern provided in the second region; The wiring board according to claim 1 , wherein a volume of the first wiring pattern is larger than a volume of the second wiring pattern.

3. The wiring board according to claim 2 , wherein the first wiring pattern is formed to be thicker than the second wiring pattern.

4. The wiring board according to claim 2 , wherein an upper surface of the first wiring pattern is formed to have a larger area than an upper surface of the second wiring pattern.

5. 3. The wiring board according to claim 2, wherein the second wiring pattern is a fine wiring having a line and space smaller than that of the first wiring pattern.

6. 2. The wiring board according to claim 1, wherein the wrinkle pattern has a planar shape in the form of a maze.

7. the second wiring layer has a third wiring pattern formed on the first roughened surface and a fourth wiring pattern formed on the second roughened surface, 2. The wiring board according to claim 1, wherein the third wiring pattern is a fine wiring having a line and space smaller than that of the fourth wiring pattern.

8. the third wiring pattern has a first seed layer formed on the first roughened surface and a first metal layer laminated on the first seed layer, The wiring board according to claim 7 , wherein the fourth wiring pattern has a second seed layer formed on the second roughened surface, and a second metal layer laminated on the second seed layer.

9. forming a first wiring layer; forming a first insulating layer covering the first wiring layer; forming a first roughened surface on the upper surface of the first insulating layer by performing a roughening treatment on the upper surface of the first insulating layer; forming a seed layer on an upper surface of the first insulating layer; forming a second roughened surface on a part of the upper surface of the first insulating layer, the second roughened surface including a wrinkle pattern formed by buckling caused according to a difference between an elastic modulus of the seed layer and an elastic modulus of the undercoat layer including the first wiring layer and the first insulating layer; In the step of forming the second roughened surface, the second roughened surface and the first roughened surface formed in a region other than the portion where the second roughened surface is formed are provided on the upper surface of the first insulating layer, A method for manufacturing a wiring substrate, wherein a volume ratio of the first wiring layer in a first region overlapping with the first roughened surface in a planar view is greater than a volume ratio of the first wiring layer in a second region overlapping with the second roughened surface in a planar view.

10. The step of forming the first insulating layer and the first roughened surface includes: forming the first insulating layer to cover the entire first wiring layer; hardening only a surface layer of the first insulating layer; forming a through hole penetrating the first insulating layer in a thickness direction and exposing a portion of an upper surface of the first wiring layer by a laser processing method; a step of removing resin smears attached to an upper surface of the first wiring layer exposed from the through hole by a desmear treatment and roughening the upper surface of the first insulating layer to form the first roughened surface; The method for manufacturing a wiring board according to claim 9 , further comprising the steps of:

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