Semiconductor device

Abstract

To provide a semiconductor device with a new structure that can retain memory contents even when power is not supplied and has no limit on the number of times data can be written.SOLUTION: A semiconductor device includes: a first transistor 160 having a channel formation region 116, a first gate insulating layer 108, a first gate electrode 110, and a first source electrode and a first drain electrode 130a, 130b; a second transistor having an oxide semiconductor layer 140, a second source electrode and a second drain electrode 142a, 142b, a second gate insulating layer 146, and a second gate electrode 148a; and a capacitor 164 having one of the second source electrode or the second drain electrode, the second gate insulating layer, and an electrode 148b provided to overlap with one of the second source electrode or the second drain electrode over the second gate insulating layer. The first gate electrode and one of the second source electrode or the second drain electrode are electrically connected to each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into volatile types, which retain their memory contents even if the power supply is cut off, and non-volatile types, which retain their memory contents even if the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] From the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage currents, and when the transistors are not selected, Because electric charges flow in and out at the same time, the data retention period is short. A re-write operation (refresh operation) is required, and power consumption must be sufficiently reduced. In addition, if the power supply is cut off, the memory contents are lost, so long-term memory To hold the information, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem that the memory element may become non-functional after a certain number of writes. In order to alleviate the effect of this problem, for example, the number of write operations to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] In order to hold or remove a charge on the floating gate, High voltage is required, and a circuit for it is also necessary. Furthermore, it is difficult to hold the charge and It takes a relatively long time to erase, and it is not easy to speed up writing and erasing. There are also problems. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure capable of retaining data and having no limit on the number of times it can be written. One of the objectives of the organization is to [Means for solving the problem]

[0011] In the disclosed invention, a semiconductor device is formed using a highly purified oxide semiconductor. Since a transistor using a tantalum oxide semiconductor has an extremely low leakage current, , it is possible to retain information for a long period of time.

[0012] One embodiment of the disclosed invention is a channel formation region and a pair of semiconductor layers provided to sandwich the channel formation region. a first gate insulating layer provided on the impurity region and a channel forming region; a first gate electrode provided on the insulating layer; and a first source electrically connected to the impurity region. a first transistor having a first drain electrode and a first drain electrode; an oxide semiconductor layer; a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; A second gate electrode is provided to cover the conductor layer, the second source electrode, and the second drain electrode. a second gate insulating layer provided over the second gate insulating layer so as to overlap with the oxide semiconductor layer; a second transistor having a gate electrode and a second source electrode or a second drain electrode; a second gate insulating layer; and a second source electrode or a capacitor having an electrode provided so as to overlap with one of the first and second drain electrodes; and the first gate electrode is electrically connected to one of the second source electrode and the second drain electrode. It is a semiconductor device that is electrically connected to the

[0013] In addition, one embodiment of the disclosed invention is a method for manufacturing a semiconductor device comprising: a first gate insulating layer provided on the impurity region and the channel forming region; A first gate electrode provided on the gate insulating layer and a first a first transistor having a source electrode and a first drain electrode; and an oxide semiconductor layer a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; The insulating layer contacts the second source electrode and the second drain electrode, the oxide semiconductor layer, the second source electrode, and the second drain electrode. a second gate insulating layer provided to cover the source electrode, the second drain electrode, and the insulating layer; a second gate insulating layer provided on the second gate insulating layer so as to overlap with the oxide semiconductor layer; a second transistor having a second source electrode or a second drain electrode; On the other hand, a second gate insulating layer and a second source electrode or a second drain electrode are formed on the second gate insulating layer. a capacitance element having an electrode provided so as to overlap one of the drain electrodes, The first gate electrode is electrically connected to either the second source electrode or the second drain electrode. It is a semiconductor device.

[0014] In the above, the oxide semiconductor layer is provided on the side surfaces of the second source electrode and the second drain electrode or In the above, the second transistor and the The capacitive element is preferably provided above the first transistor.

[0015] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating layer" is not limited to "directly under". ", it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in certain cases, this also includes those with the top and bottom reversed.

[0016] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0017] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It is possible.

[0018] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects.

[0019] For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as Effect of the Invention

[0020] In one embodiment of the present invention, a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor are A semiconductor device using the above-mentioned transistor stack structure is provided.

[0021] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0022] In addition, high voltage is not required to write information, and there is no problem with element degradation. Unlike non-volatile memory, there is no need to inject or extract electrons from the floating gate. In other words, the semiconductor device according to this embodiment does not suffer from problems such as deterioration of the gate insulating layer. There is no limit to the number of times that it can be rewritten, which is an issue with conventional non-volatile memory, and it is highly reliable. Furthermore, the on and off states of the transistors allow the writing of information. Since the data is erased, high-speed operation can be easily realized. It also has the advantage of being unnecessary.

[0023] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0024] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief description of the drawings]

[0025] [Figure 1] Cross-sectional view and plan view of a semiconductor device [Diagram 2] Cross-sectional view of a semiconductor device [Diagram 3] Circuit diagram of semiconductor device [Figure 4] Cross-sectional views relating to a manufacturing process of a semiconductor device [Diagram 5] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 6] Cross-sectional view and plan view of a semiconductor device [Figure 7] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 8] Circuit diagram of semiconductor device [Figure 9] Cross-sectional view and plan view of a semiconductor device [Figure 10] Cross-sectional view of a semiconductor device [Figure 11] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 12] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 13] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 14] FIG. 1 is a perspective view illustrating an electronic device; [Figure 15] Figure showing the results of the memory window width survey DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above, and may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. It should not be construed as being limited to the contents described.

[0027] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0029] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. 1 to 5. Note that in the circuit diagrams, To indicate that it is a transistor, the symbol OS may also be added.

[0030] <Plane and cross-sectional configurations of semiconductor device> FIG. 1 shows an example of the configuration of a semiconductor device. FIG. 1(A) shows a cross section of the semiconductor device. FIG. 1(A) shows a plan view of the semiconductor device. FIG. 1(B) shows a plan view of the semiconductor device. The cross sections shown in Fig. 1(A) and Fig. 1(B) correspond to those taken along lines 1-A2 and B1-B2. The semiconductor device has a transistor 160 using a material other than an oxide semiconductor in a lower portion. The semiconductor device has a transistor 162 using an oxide semiconductor and a capacitor 164 in the upper portion. The transistor 160 and the transistor 162 are both n-channel transistors. However, a p-channel transistor may be used. Needless to say, the technical essence of the disclosed invention is that it uses an acid to hold information. The point is that a nitride semiconductor is used for the transistor 162. There is no need to be limited to what is shown here.

[0031] The transistor 160 is disposed on a substrate 100 that includes a semiconductor material (such as silicon). A channel forming region 116 is formed by arranging impurity layers 116 so as to sandwich the channel forming region 116. Region 114 and high concentration impurity region 120 (collectively referred to as "impurity region") a gate insulating layer 108 provided on the channel forming region 116; A gate electrode 110 is provided on the semiconductor substrate 10 and a source electrode or drain electrode is provided on the semiconductor substrate 100. The source electrode or drain electrode is electrically connected to the impurity region. The transistor has a drain electrode 130a and a source or drain electrode 130b.

[0032] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, A high concentration impurity region 120 is provided, and a metal compound region 124 is provided adjacent to the high concentration impurity region 120. In addition, an element isolation insulating layer 10 is formed on the substrate 100 so as to surround the transistor 160. 6 is provided, and an interlayer insulating layer 126 and an interlayer insulating film 128 are provided to cover the transistor 160. A source or drain electrode 130a and a source electrode 130b are provided. A source or drain electrode 130b is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. Through the opening, the source electrode is electrically connected to the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are formed of metallized Electrically connected to the high concentration impurity region 120 and the impurity region 114 through the compound region 124 The electrode 130c is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. The gate electrode 110 is electrically connected to the transistor 1 through the opening. In some cases, the sidewall insulating layer 118 is not formed due to the integration of 60 or the like.

[0033] The transistor 162 has a source or drain electrode 14 disposed on the insulating layer 138. 2a, and a source or drain electrode 142b, and a source or drain electrode 142a, and an oxide electrically connected to the source electrode or drain electrode 142b. A semiconductor layer 140, a source electrode or a drain electrode 142a, and a source electrode or The drain electrode 142b, the insulating layer 144 in contact with the oxide semiconductor layer 140, and the source electrode The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 14 0, a gate insulating layer 146 covering the insulating layer 144, and an oxide semiconductor layer on the gate insulating layer 146 and a gate electrode 148a provided so as to overlap with the insulating layer 140. 44 is provided to reduce the capacitance caused by the gate electrode 148a, etc. In order to simplify the process, the insulating layer 144 may not be provided.

[0034] As described above, the transistor 162 shown in FIG. 1 is a top-gate type, and The connection between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a or the like is Since the process is performed in a region including the lower surface of the conductor layer 140, the top gate and bottom contact This can be called the contact type.

[0035] Here, the oxide semiconductor layer 140 is a layer in which impurities such as hydrogen have been sufficiently removed or in which there is sufficient oxidation. It is preferable that the raw material is highly purified by supplying the raw material. For example, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 Below, wish Preferably 5 x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 140 is determined based on the secondary ion mass. Secondary Ion Mass Spectroscop (SIMS) In this way, the hydrogen concentration is sufficiently reduced and the material is highly purified. The supply of sufficient oxygen reduces the defect levels in the energy gap caused by oxygen deficiency. In the oxide semiconductor layer 140, the carrier concentration is 1×10 12 / cm 3 Less than 1, preferably ×10 11 / cm 3 Less than 1.45×10 10 / cm 3 It is less than. For example, when the channel length is 10 μm and the thickness of the oxide semiconductor layer is 30 nm, When the drain voltage is in the range of about 1V to 10V, the off-current (gate-source voltage The drain current when the voltage is set to 0 V or less is 1×10 -13 A or less. Or, at room temperature The off-state current density (off-state current divided by the channel width of the transistor) is 1×10 -20 A / μm (10zA (zeptoamperes) / μm) to 1×10 -19 A / μm(100zA / μm), and the off-resistance is about 1×10 9 Ω·m or more, preferably 1×10 1 0 In this way, the i-type (intrinsic) or substantially i-type oxide By using a semiconductor, the transistor 162 can have excellent off-state current characteristics. Cut.

[0036] In addition, the source or drain electrode 142a is electrically connected to the electrode 130c. That is, the source or drain electrode 142a is connected to the gate voltage of the transistor 160. Similarly, the source or drain electrode 130a is electrically connected to the The electrode 142c is in contact with the source electrode or drain electrode 130b, and the electrode 142d is in contact with the source electrode or drain electrode 130b. , respectively.

[0037] The capacitor 164 includes a source or drain electrode 142a, a gate insulating layer 146, an electrode That is, the source electrode or drain electrode 142a is composed of a capacitive element. The electrode 148b functions as one electrode of the capacitor 164, and the electrode 148c functions as the other electrode of the capacitor 164. This will function as follows.

[0038] In addition, a protective insulating layer 150 is provided on the transistor 162 and the capacitor element 164. An interlayer insulating layer 152 is provided on the protective insulating layer 150 .

[0039] <Modifications of the upper transistor and capacitor element> Next, a modification of the transistor and the capacitor in the upper portion shown in FIG. 1A is shown in FIG.

[0040] The transistor and the capacitor shown in FIG. 2A are upper transistors of the semiconductor device shown in FIG. 4 is a modified example of the capacitor and the transistor.

[0041] The difference between the configuration shown in FIG. 2A and the configuration shown in FIG. 1A is that the insulating layer 144 is A source or drain electrode 142a and a source or drain electrode 142b are formed on the The oxide semiconductor layer 140 is connected to the insulating layer 144 and the source or drain electrode 14 2a and the source or drain electrode 142b. In addition, the oxide semiconductor layer 140 is connected to the source electrode through an opening provided in the insulating layer 144. The gate electrode 142a is disposed in contact with the source or drain electrode 142a.

[0042] In the transistor and the capacitor shown in FIG. The ends of the source or drain electrode 142a, the source electrode or drain electrode 142b, and the insulating layer 144 are tapered. Here, the taper angle is preferably, for example, 30° to 60°. The taper angle is preferably set to 0.05 mm. The electrode or drain electrode 142a is aligned in a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side and bottom of the layer when observed from the opposite direction. The ends of the source electrode 142a and the source or drain electrode 142b are tapered. This can improve coverage of the oxide semiconductor layer 140 and prevent discontinuities.

[0043] In addition, in the structure illustrated in FIG. 2A, the oxide semiconductor layer 140 is not processed. Therefore, the etching performed in the first step can prevent contaminants from being mixed into the oxide semiconductor layer 140. In the capacitor element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By this, the insulation between the source electrode or drain electrode 142a and the electrode 148b is This allows sufficient compatibility to be ensured.

[0044] The transistor and the capacitor shown in FIG. 2B are the same as those shown in FIG. The configuration is slightly different from that of the above.

[0045] The difference between the structure illustrated in FIG. 2B and the structure illustrated in FIG. 2A is that the oxide semiconductor layer is formed into an island shape. That is, in the structure shown in FIG. 2A, the oxide semiconductor layer 140 is an insulating The edge layer 144, the source or drain electrode 142a, and the source or drain electrode In contrast to the structure shown in FIG. 2B, the oxide semiconductor By forming the layers in an island shape, the insulating layer 144, the source electrode or drain electrode 142a, and A part of the source electrode or drain electrode 142b is covered. The end of the conductor layer 140 is preferably tapered. The taper angle is, for example, 3 It is preferable to set the angle between 0° and 60°.

[0046] In addition, in the capacitor 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. As a result, the insulation between the source electrode or drain electrode 142a and the electrode 148b is improved. can be sufficiently secured.

[0047] The transistor and the capacitor shown in FIG. 2C are the same as those shown in FIG. The configuration is slightly different from that of the above.

[0048] The difference between the configuration shown in FIG. 2C and the configuration shown in FIG. 2A is that the transistor 162 and the capacitor The difference is that the insulating layer 144 is not provided on the capacitance element 164. In the case of FIG. 2A, since the insulating layer 144 is not provided, the transistor and the capacitor are different from those in FIG. As a result, the manufacturing process is simplified and the manufacturing cost is reduced.

[0049] In addition, in the structure shown in FIG. 2C, the oxide semiconductor layer 140 is not processed. Therefore, the etching performed in the first step can prevent contaminants from being mixed into the oxide semiconductor layer 140. In the capacitor element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By this, the insulation between the source electrode or drain electrode 142a and the electrode 148b is This allows sufficient compatibility to be ensured.

[0050] The transistor and the capacitor shown in FIG. 2D are the same as those shown in FIG. The configuration is partially different from that of the element.

[0051] The difference between the configuration shown in FIG. 2D and the configuration shown in FIG. 2B is that the transistor 162 and the capacitor The transistor 162 and the capacitor 164 are not provided with the insulating layer 144. By providing the insulating layer 144 in the capacitor 164, the following structure is obtained as compared with that in FIG. As a result, the manufacturing process is simplified and the manufacturing cost is reduced.

[0052] In addition, in the capacitor 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. As a result, the insulation between the source electrode or drain electrode 142a and the electrode 148b is improved. can be sufficiently secured.

[0053] <Circuit Configuration and Operation of Semiconductor Device> Next, an example of the circuit configuration of the above-mentioned semiconductor device and its operation will be described. ) is an example of a circuit configuration corresponding to the semiconductor device shown in FIG.

[0054] In the semiconductor device shown in FIG. 3A, a first wiring (also called a source line) The second wiring (2nd The drain electrode of the transistor 160 is electrically connected to the bit line. In addition, the third wiring (also called the first signal line) and the transistor The other of the source electrode or the drain electrode of the capacitor 162 is electrically connected to a fourth wiring ( The 4th Line (also called the second signal line) and the gate electrode of the transistor 162 are connected to each other. The gate electrode of the transistor 160 and the gate electrode of the transistor 16 One of the source electrode and the drain electrode of the second transistor is electrically connected to one of the electrodes of the capacitor 164. A fifth wiring (also called a word line) and an electrode of the capacitance element 164 are connected to the fifth wiring (also called a word line). The other is electrically connected.

[0055] The transistor 160 using a material other than an oxide semiconductor can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed. The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 It is possible to hold the potential of the gate electrode for an extremely long period of time. By having the transistor 164, the charge applied to the gate electrode of the transistor 160 can be retained. This also makes it easier to read out the stored contents.

[0056] In the semiconductor device described in this embodiment, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0057] First, the writing and holding of information will be explained. The transistor 162 is turned on by applying a potential that turns the transistor 162 on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the That is, the gate electrode of the transistor 160 is provided with a predetermined A charge of 10 ... The charge level is called the low level charge or the high level charge. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the voltage applied to the gate electrode of the transistor 160 is The load is held (retained).

[0058] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0059] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the transistor electrode, the second wiring has a different potential. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode of the transistor 160. Apparent threshold V for a given charge th_H The gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is turned on. Therefore, the potential of the fifth wiring is defined as the potential of the fifth wiring required to make the fifth wiring V rank th_H and V th_L By setting the potential V0 to the intermediate potential V0, the The charge applied to the gate electrode can be determined. For example, in writing, If a charge is applied, the potential of the fifth wire is V0 (> V th_H ) Then, The transistor 160 is in the "on state." If a low level charge is applied, The potential of the fifth wire is V0( <V th_L ), the transistor 160 remains in the "off state" Therefore, by checking the potential of the second wiring, the stored information can be read. It can be put out.

[0060] When information is not read, the state of the gate electrode of the transistor 160 is not changed. First, the potential at which transistor 160 is in the "off state," i.e., V th_H Less than Alternatively, the potential may be changed depending on the state of the gate electrode of the transistor 160. The potential at which transistor 160 remains "on," i.e., V th_L twist A large potential may be applied to the fifth wiring.

[0061] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. Then, the potential of the fourth wiring is applied to one electrode of the transistor 162 so that the transistor 162 is in an off state. By setting the potential at the potential Vcc to a value such that the transistor 162 is turned off, the transistor 16 The gate electrode of 0 is given a charge related to new information.

[0062] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and makes it possible to suppress a decrease in operation speed caused by the erase operation. That is, high speed operation of the semiconductor device is achieved.

[0063] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. The flow cell is electrically connected to a gate electrode, and is used as a non-volatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 162 and the gate of the transistor 160 The portion to which the gate electrode is electrically connected is sometimes called the floating gate portion FG. When the transistor 162 is off, the floating gate portion FG is embedded in an insulator. The floating gate FG holds charge. In the transistor 162 using a conductor, the off-state current is generated by a transistor formed by a silicon semiconductor or the like. Since the resistance of transistor 162 is less than 1 / 100,000 of that of transistor 160, It is possible to ignore the loss of charge stored in the floating gate portion FG. In addition, a nonvolatile memory device can be realized by using the transistor 162 including an oxide semiconductor. It is possible.

[0064] For example, the off-state current density of transistor 162 at room temperature is 10 zA / μm (1 zA ( Ampere) is 1 x 10 -21 A) and the capacitance of the capacitance element 164 is about 1 pF. If so, at least 10 6 It is possible to hold data for more than 1000 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0065] In this case, the gate problem pointed out in the conventional floating gate type transistor is This avoids the problem of deterioration of the gate insulating film (tunnel insulating film). This solves the problem of gate insulating film deterioration when implanting electrons into the floating gate. As a result, in the semiconductor device shown in this embodiment, the fundamental writing There is no limit to the number of times the transistor can be turned on. There is no need for the high voltages that were previously required for writing and erasing.

[0066] The semiconductor device shown in FIG. 3(A-1) includes elements such as transistors that constitute the semiconductor device. can be replaced with a circuit like that shown in Figure 3(A-2) by assuming that includes resistance and capacitance. That is, in FIG. 3(A-2), the transistor 160 and the capacitor 164 are Each is considered to be composed of resistance and capacitance. R1 and C1 are the resistance and capacitance values ​​of the capacitive element 164, respectively, and the resistance value R1 is the capacitance value of the capacitive element 164. R2 and C2 correspond to the resistance of the insulating layer that constitutes 64. The resistance R2 is the resistance and capacitance of the transistor 160. The capacitance C2 corresponds to the resistance due to the gate insulation layer in the gate insulator state. This corresponds to the capacitance formed between the gate electrode and the source electrode or the drain electrode. , the resistance value R2 is the resistance value between the gate electrode and the channel forming region of the transistor 160. For illustrative purposes only, some of the connections are shown as dotted lines to make this point clear.

[0067] The resistance between the source and drain electrodes of the transistor 162 when it is in the off state (actual Let ROS be the effective resistance (also called ROS). R1 ​​and R2 satisfy the following conditions: R1 ≥ ROS, R2 ≥ ROS. When this condition is satisfied, the charge retention period (which can also be called the information retention period) is mainly due to the It is determined by the off-current of the transistor 162.

[0068] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. However, it is difficult to ensure a sufficient retention period. This is because the leakage current is large. It is desirable that the above relationship be satisfied.

[0069] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≧ C2. When controlling the potential of the floating gate portion FG by the fifth wiring (for example, when reading This is because the potential of the fifth wiring can be kept low when the fifth wiring is opened (when the fifth wiring is opened).

[0070] By satisfying the above relationship, a more suitable semiconductor device can be realized. In this embodiment, R1 and R2 are formed by the gate insulating layer 108, the gate insulating layer 146, etc. The same applies to C1 and C2. Therefore, the material of the gate insulating layer and It is desirable to appropriately set the thickness etc. so as to satisfy the above-mentioned relationship.

[0071] FIG. 3B shows a semiconductor device having a structure partially different from that of the above-mentioned semiconductor device. In the semiconductor device shown in FIG. 1, a gate electrode of a transistor 160 and a gate electrode of a transistor 166 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to The first wiring and the source electrode of the transistor 160 are electrically connected. The second wiring and the drain electrode of the transistor 160 are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor 166 are , and the fourth wiring and the first gate electrode of the transistor 166 are electrically connected to each other. The fifth wiring and the other electrode of the capacitor 164 are electrically connected to each other. The sixth wiring and the second gate electrode of the transistor 166 are electrically connected to each other. The sixth wiring may be given a potential equal to that of the fourth wiring, or a potential different from that of the fourth wiring. Alternatively, a potential different from that of the fourth wiring may be applied to the second wiring and controlled independently of the fourth wiring.

[0072] That is, the semiconductor device shown in FIG. 3B is a transistor of the semiconductor device shown in FIG. The transistor 162 is replaced with a transistor 166 having a second gate electrode. As a result, in the semiconductor device shown in FIG. 3B, In addition to the effect obtained, the electrical characteristics (e.g., threshold voltage) of the transistor 166 can be adjusted. For example, applying a negative potential to the sixth wiring It is possible to easily make the transistor 166 normally off.

[0073] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of positive hole-causing transistors instead of n-type transistors. It goes without saying that a p-type transistor can be used as the carrier.

[0074] <Method for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device shown in FIGS. 1 and 3(A-1) will be described. First, a method for manufacturing the lower transistor 160 will be described below with reference to FIG. Then, a method for manufacturing the upper transistor 162 and the capacitor 164 will be described with reference to FIG. This will be explained in light of the above.

[0075] <Method of manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 4(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has a silicon semiconductor on an insulating surface. A substrate having a conductor layer formed thereon is referred to as a substrate having a silicon layer formed on an insulating surface. The concept also includes a substrate having a semiconductor layer made of a material other than the above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The plate is configured such that a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. The following shall be included:

[0076] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 4(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0077] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor device is not attached (the exposed area) is removed. The conductive region 104 is formed (see FIG. 4(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0078] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like. Methods for removing the insulating layer include polishing such as CMP and etching. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulation After the layer 106 is formed, the protective layer 102 is removed.

[0079] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0080] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. It is performed using a mixture of rare gases such as e, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. m or less.

[0081] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a semiconductor material such as polycrystalline silicon can be used to form the conductive layer. A layer containing the material may be formed. The method of forming the layer is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, or the like. Various film formation methods such as a deposition method, a deposition method, a spin coating method, etc. can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let us assume that.

[0082] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, a gate electrode 110 is formed (see FIG. 4(C)).

[0083] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 4(C)). Phosphorus (P) or arsenic (As) is added to the conductor region 104 to form an impurity region with a shallow junction depth. 114 is formed (see FIG. 4(C)). Note that, in this case, in order to form an n-type transistor, In the case of forming a p-type transistor, boron (B) or arsenic is added. An impurity element such as aluminum (Al) may be added. As a result, a channel formation region 116 is formed below the gate insulating layer 108 in the semiconductor region 104. (See FIG. 4(C)). Here, the concentration of the added impurity can be appropriately set. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this embodiment, the step of forming the impurity region 114 after forming the insulating layer 112 is adopted. However, the insulating layer 112 may be formed after the impurity regions 114 are formed.

[0084] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, the film can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is a good idea to expose the top surface of 14.

[0085] Next, a semiconductor device is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed on the impurity region 114. Then, phosphorus (P) or arsenic ( As) or the like is added to form a high concentration impurity region 120 (see FIG. 4(E)). The insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, and the high concentration impurity A metal layer 122 is formed so as to cover the region 120 and the like (see FIG. 4(E)). 2 is formed using various film formation methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can react with the semiconductor material that constitutes the semiconductor region 104 to form a It is preferable to form the insulating layer using a metal material that forms a low-resistance metal compound. Examples of materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum. be.

[0086] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0087] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0088] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using silicon oxide. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The structure has a two-layer structure of an interlayer insulating layer 126 and an interlayer insulating layer 128. After the interlayer insulating layer 128 is formed, the surface of the interlayer insulating layer 128 may be subjected to a process such as CMP or etching. It is desirable to flatten the surface by using a method such as flattening.

[0089] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. A source electrode or drain electrode 130a and a source electrode or drain electrode 130b are provided on the The source electrode or drain electrode 130a and the source electrode or The drain electrode 130b is formed by, for example, depositing a layer on a region including an opening using a PVD method, a CVD method, or the like. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by removing

[0090] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as a natural oxide film) on the formation surface is reduced, and the lower electrode (here, the metal compound region 124 ) and the titanium nitride film formed thereafter has the function of reducing the contact resistance with the It has a barrier function that suppresses the diffusion of conductive materials. In addition, titanium and titanium nitride are used After the barrier film is formed, a copper film may be formed by plating.

[0091] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface of the electrode is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. Removes unnecessary tungsten, titanium, titanium nitride, etc. and improves the flatness of the surface. In this manner, the source electrode or drain electrode 130a, the source electrode Alternatively, the surface including the drain electrode 130b may be planarized to improve the quality of the resulting product in a later process. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0092] In this case, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the source electrode 130a or the drain electrode 130b is shown, in this process, An electrode 130c in contact with the source electrode 110 may also be formed. The electrode or drain electrode 130a and the source or drain electrode 130b are There is no particular limitation on the material that can be used, and various conductive materials can be used. For example, Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, Conductive materials such as scandium can be used. Also, taking into consideration the heat treatment that will be performed later, The source or drain electrode 130a and the source or drain electrode 130b are It is preferable that the insulating layer is made of a material having a sufficient heat resistance to withstand the heat treatment to be performed later. I wish.

[0093] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material (see FIG. After the above process, electrodes, wiring, insulating layers, etc. may be formed. The wiring structure is a multi-layer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers. This makes it possible to provide a highly integrated semiconductor device.

[0094] <How to make the upper transistor> Next, a process for forming the transistor 162 on the interlayer insulating layer 128 will be described with reference to FIG. 5 shows various electrodes on the interlayer insulating layer 128, a transistor 162, etc. Since this shows the manufacturing process, the transistor 16 below the transistor 162 is Details such as 0 are omitted.

[0095] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 138 is formed on the drain electrode 130b and the electrode 130c. The insulating layer 138 is formed by PVD. The film can be formed by using a method such as a CVD method. Inorganic insulating materials such as silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The insulating layer 138 can be formed using a material containing The insulating layer 138 functions as a base.

[0096] Next, the source or drain electrode 130a, the source or Openings are formed that reach the drain electrode 130b and the electrode 130c (see FIG. 5(A)). The opening can be formed by a method such as etching using a mask. The etching can be performed by exposure to light using a photomask. Either wet etching or dry etching may be used. In this case, it is preferable to use dry etching. , this step can be omitted.

[0097] Next, the source or drain electrode 142a, the source or drain electrode 142b 5B, the source electrode or the drain electrode 142c and the electrode 142d are formed. A source electrode 142a, a source or drain electrode 142b, an electrode 142c, and an electrode 142d In the first embodiment, a conductive layer is formed so as to cover the insulating layer 138, and then the conductive layer is selectively etched. It can be formed by

[0098] The conductive layer is formed by PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed by a method such as a method for forming a conductive layer using aluminum, chromium, or the like. , copper, tantalum, titanium, molybdenum, tungsten, or the above-mentioned Alloys containing the elements manganese, magnesium, zirconium, etc. can be used. Alternatively, a material selected from one or more of the following may be used: In addition, aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium Alternatively, a material containing a single element selected from the group consisting of zinc, zinc oxide, and scandium may be used. The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing conductors, and a two-layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and a titanium film are laminated.

[0099] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium zinc oxide alloy (In2O3-ZnO), or a combination of these metal oxide materials It is possible to use one containing silicon or silicon oxide.

[0100] The channel length (L) of the transistor is defined as the distance between the bottom end of the source or drain electrode 142a and the The distance between the bottom end of the source electrode or drain electrode 142b and the channel When the length (L) is less than 25 nm, the wavelength of the extreme ultraviolet rays (Ex It is recommended to use fluorine (treme ultraviolet) to form an etching mask. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is possible to form a turn, and the channel length (L) of the transistor can be increased to 10 nm or more. It is possible to make the channel length smaller than 0.000 nm. This is preferable because the circuit has a high operating speed and consumes less power.

[0101] In addition, the source electrode or drain electrode 142a and the source electrode or drain electrode 1 It is preferable that the end of the source electrode 42b is tapered. The ends of the drain electrode 142a and the source or drain electrode 142b are By forming the insulating film in a perforated shape, the coverage of the oxide semiconductor layer to be formed later can be improved, and the insulating film can be formed without any step. Here, the taper angle is, for example, 30° to 60°. The taper angle is preferably equal to or less than 100°. The source electrode or drain electrode 142a) is perpendicular to the cross section (a plane perpendicular to the surface of the substrate). This indicates the inclination angle between the side and bottom surfaces of the layer when observed from a perpendicular direction.

[0102] Next, the source or drain electrode 142a, the source or drain electrode 142b After forming an oxide semiconductor layer to cover the insulating film, etc., Therefore, the oxide semiconductor layer is processed to form an island-shaped oxide semiconductor layer 140 (FIG. 5(C) )reference).

[0103] The oxide semiconductor layer is preferably formed by a sputtering method. The four-component metal oxide In-Sn-Ga-Zn-O system and the three-component metal oxide In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O and binary metal oxides In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Metals such as Sn-Mg-O, In-Mg-O, In-O, Sn-O, and Zn-O. The metal oxide can be used to form the layer. Note that silicon can be added to the metal oxide. For example, a target containing 2% to 10% by weight of SiO2 is used to form an oxide semiconductor. A conductor layer may be formed.

[0104] In particular, by using In-Ga-Zn-O metal oxides, the resistance in the absence of an electric field is sufficiently low. To form a semiconductor device having sufficiently high field effect mobility (sufficiently small off-state current). In this respect, In-Ga-Zn-O-based metal oxides are suitable for use in semiconductor devices. It is suitable as a material.

[0105] A representative example of In-Ga-Zn-O metal oxide is InGaO3(ZnO). m (m >0). Also, M is used instead of Ga, resulting in InMO3(ZnO). m There are metal oxides that are written as (m>0), where M is gallium (Ga), Aluminum (Al), Iron (Fe), Nickel (Ni), Manganese (Mn), Cobalt (C) o) represents one or more metal elements selected from the following. For example, M is Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied. Note that the above composition is derived from the crystal structure. However, it should be noted that this is merely one example.

[0106] In this embodiment, the oxide semiconductor layer is formed using an In-Ga-Zn-O based metal oxide target. The insulating film is formed by a sputtering method using a gas such as fluorine.

[0107] The oxide semiconductor layer is formed by holding a substrate in a treatment chamber that is kept in a reduced pressure state and controlling the substrate temperature to The temperature is preferably 100°C or higher and 600°C or lower, and more preferably 200°C or higher and 400°C or lower. Here, the oxide semiconductor layer is formed while the substrate is heated, so that the oxide semiconductor The concentration of impurities in the oxide semiconductor layer can be reduced by sputtering. Damage can be reduced.

[0108] The atmosphere in which the oxide semiconductor layer is formed is one in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are sufficiently reduced. A rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically It is preferable to use a mixed atmosphere of hydrogen, water, etc. Impurities such as hydroxyl groups and hydrides are at a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a high purity gas atmosphere in which the purity is removed to as low as 100%.

[0109] In order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump is used. In addition, a cold trap is added to the turbo molecular pump as an exhaust means. The deposition chamber evacuated using a cryopump may be filled with, for example, hydrogen atoms, Compounds containing hydrogen atoms such as water (H2O) (and more preferably compounds containing carbon atoms) Since the gas is exhausted, the concentration of impurities in the oxide semiconductor layer formed in the deposition chamber can be reduced. Cut.

[0110] The thickness of the oxide semiconductor layer is 2 nm to 200 nm, preferably 5 nm to 30 nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. The thickness may be appropriately selected depending on the material used.

[0111] In addition, by using a pulsed direct current (DC) power supply when forming the oxide semiconductor layer, (Powdery or flake-like substances formed during film formation) can be reduced, and the film thickness distribution is uniform. It can be said that:

[0112] The sputtering conditions for the oxide semiconductor layer are, for example, The distance between the chamber and the workpiece was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was The conditions that can be applied are an oxygen (oxygen flow rate ratio 100%) atmosphere.

[0113] Note that before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. Then, reverse sputtering is performed to generate plasma, and the metal adhering to the surface of the insulating layer 138 is removed. Here, the reverse sputtering is a method for removing the In this method, ions are bombarded onto the sputtering target, but instead, ions are directed at the treatment surface. This is a method of modifying a surface by bombarding it with ions. The method for this is to apply a high frequency voltage to the surface to be treated in an argon atmosphere. In addition, nitrogen, helium, or Oxygen or the like may also be used.

[0114] The etching of the oxide semiconductor layer can be performed by either dry etching or wet etching. Of course, both can be used in combination. In order to match the etching conditions (etching gas, etching solution, etc.) to the material, The etching time, temperature, etc. may be appropriately set.

[0115] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride In addition, gases containing fluorine (fluorine-based gases, for example, tetrafluoroethylene (CCl4)) Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (H e) or a gas containing an added rare gas such as argon (Ar), etc. may also be used.

[0116] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0117] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) In addition, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0118] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. By performing the heat treatment, impurities such as hydrogen in the oxide semiconductor layer can be removed. If the etching is performed after the etching, even if wet etching is used, The first heat treatment temperature is 30 The temperature is set to 0°C or higher and 750°C or lower, preferably 400°C or higher and 700°C or lower. For example, resistance heating The substrate is placed in an electric furnace using a furnace or the like, and the oxide semiconductor layer 140 is heated to 450 ... Heat treatment is performed at 0° C. for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. In addition, the first heat treatment temperature is set to 100° C., and hydrogen (including water, etc.) is not re-mixed. It is desirable to determine the temperature in consideration of the heat resistance of the electrodes and wiring of the transistor 160 in the lower layer. It is.

[0119] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as a heated gas, or The apparatus may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0120] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650° C. to 700° C. After heating for a few minutes, the substrate is taken out of the inert gas (GRTA process). GRTA treatment allows high-temperature heat treatment in a short time. Since this is a heat treatment, when using a substrate with low heat resistance such as a glass substrate, distortion of the substrate may occur. This makes it possible to apply the method even under temperature conditions exceeding the melting point.

[0121] The first heat treatment is performed in a vacuum chamber mainly containing nitrogen or a rare gas (helium, neon, argon, etc.). It is preferable to carry out the process in an atmosphere that does not contain hydrogen, water, etc. The purity of nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. , the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0122] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In addition, the semiconductor layer may contain a crystalline component. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. be.

[0123] In addition, by providing a crystal layer on an amorphous surface, the electrical characteristics of the oxide semiconductor layer are changed. For example, it is possible to form a crystal layer in which crystal grains having electrical anisotropy are oriented. In this way, the electrical characteristics of the oxide semiconductor layer can be changed.

[0124] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0125] The heat treatment may have a dehydrogenation (dehydration) effect on the oxide semiconductor layer 140. This type of treatment can be called dehydrogenation treatment (dehydration treatment) or the like. After forming the conductor layer, an insulating layer (such as a gate insulating layer) is laminated on the oxide semiconductor layer 140. , after the formation of the gate electrode, or at any other timing. Moreover, this process may be carried out multiple times instead of just once.

[0126] In addition, by controlling the atmosphere in which the oxide semiconductor layer is formed, it is possible to prevent hydrogen from being sufficiently introduced. In a case where a reduced oxide semiconductor layer can be obtained, the first heat treatment may be omitted. It is also possible.

[0127] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. The plasma treatment may be performed to remove the oxide semiconductor layer from the exposed surface of the oxide semiconductor layer. In addition, it is possible to remove water and other substances that contain oxygen, such as a mixture of oxygen and argon gas. In this manner, oxygen can be supplied to the oxide semiconductor layer. It is possible to reduce defect levels in the energy gap caused by oxygen deficiency by supplying oxygen to the .

[0128] Next, the source or drain electrode 142a, the source or drain electrode 142b An insulating layer 144 is formed above the oxide semiconductor layer 140 and the like, and a gate electrode is formed in the region. An opening is formed in a part of the region where an electrode of the capacitor element is to be formed. After forming a gate insulating layer 146 so as to cover the region including the opening, a gate electrode 148a The opening in the insulating layer 144 is formed by using a mask. The gate electrode 148a and the electrode The electrode 148b is formed by forming a conductive layer to cover the gate insulating layer 146 and then selectively insulating the conductive layer. The insulating layer can be formed by selectively etching the insulating layer.

[0129] The insulating layer 144 and the gate insulating layer 146 are formed by using a CVD method, a sputtering method, or the like. The insulating layer 144 and the gate insulating layer 146 can be made of silicon oxide, nitride, or the like. silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. The insulating layer 144 and the gate insulating layer 146 are preferably formed to include a single layer. The thickness of the film may be, but is not limited to, for example, For example, the thickness of the insulating layer 144 may be set to 10 nm or more and 500 nm or less. For example, the insulating layer 144 is formed to reduce capacitance caused by overlapping. By forming the source electrode or drain electrode 142a, etc., and the gate electrode 148a The capacitance due to the above is reduced.

[0130] The insulating layer 144 and the gate insulating layer 146 are formed by a method that is less likely to be contaminated by impurities such as hydrogen and water. It is preferable that the insulating layer 144 and the gate insulating layer 146 contain hydrogen. Hydrogen enters the oxide semiconductor layer, and oxygen in the oxide semiconductor layer is extracted by hydrogen. This is because there is a risk of the following occurring:

[0131] For example, when the insulating layer 144 and the gate insulating layer 146 are formed by a sputtering method, The sputtering gas contains impurities such as hydrogen, water, hydroxyl groups, and hydrides at a concentration of 1ppm. A high-purity gas with a concentration of about 10 ppb is used. It is desirable to remove any residual moisture in the processing chamber.

[0132] As shown in this embodiment, the oxide semiconductor that has been made intrinsic by removing the impurities is Conductors (highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, when such an oxide semiconductor is used for the oxide semiconductor layer, the boundary with the gate insulating layer is Therefore, the surface of the gate insulating layer 146 in contact with the highly purified oxide semiconductor layer is important. will require high quality.

[0133] For example, the high-density plasma CVD method using microwaves (frequency 2.45 GHz) produces dense, insulating This is advantageous in that a high-quality gate insulating layer 146 with high withstand voltage can be formed. The close contact between the oxide semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can improve the properties.

[0134] Of course, if a high-quality insulating layer can be formed as a gate insulating layer, a highly purified oxide is acceptable. Even when a nitride semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, the insulating layer has a good film quality and is an oxide semiconductor layer. The gate insulating layer 146 capable of reducing the interface state density with the semiconductor substrate 141 may be formed.

[0135] In this embodiment, the insulating layer 144 and the gate insulating layer 146 are made of a material containing silicon oxide. The insulating layer is formed by a sputtering method.

[0136] After forming the insulating layer 144 or after forming the gate insulating layer 146, an inert gas atmosphere is A second heat treatment is performed in an atmosphere or an oxygen gas atmosphere (preferably at 200° C. to 400° C.). For example, it is preferable to perform the heating at a temperature of 250°C or higher and 350°C or lower. The second heat treatment is performed at 0° C. for 1 hour. When the second heat treatment is performed, the electrical characteristics of the transistor In addition, the second heat treatment can reduce the variation in the temperature of the insulating layer containing oxygen. The oxygen is supplied to the oxide semiconductor layer from the oxide semiconductor layer, and the defect level in the energy gap caused by oxygen deficiency is eliminated. It is also possible to reduce the amount of heat treatment. The atmosphere for the heat treatment is not limited to the above, and may be air or the like. In that case, however, hydrogen may be mixed into the oxide semiconductor layer. It is preferable to use an atmosphere that is free of metals and water. The second heat treatment is an essential step. Since there is no such

[0137] The conductive layer to be the gate electrode 148a and the electrode 148b can be formed by a method such as sputtering. The film can be formed by using a PVD method such as a plasma CVD method. The same applies to the source electrode or drain electrode 142a, etc., and the description thereof should be taken into consideration. can.

[0138] Etching for forming an opening in the insulating layer 144 and etching for forming the gate electrode 148a and the like are performed. For this etching, either dry etching or wet etching may be used. Of course, both can be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are adjusted according to the material. The degree, etc.) can be set appropriately.

[0139] Next, a protective insulating layer 150 and an interlayer insulating layer 152 are formed (see FIG. 5(E)).

[0140] The protective insulating layer 150 and the interlayer insulating layer 152 are formed by using a PVD method, a CVD method, or the like. In addition, silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, and oxide The insulating layer 11 can be formed using a material including an inorganic insulating material such as aluminum oxide or tantalum oxide. do.

[0141] The protective insulating layer 150 is located relatively close to the oxide semiconductor layer 140. Therefore, it is formed using a method such as sputtering that is less likely to introduce impurities such as hydrogen and water. It is more desirable to do so.

[0142] Moreover, it is desirable to form the interlayer insulating layer 152 so that its surface is flat. By forming the interlayer insulating layer 152 so that the surface is flat, electrodes and This is because wiring and the like can be formed suitably.

[0143] The protective insulating layer 150 and the interlayer insulating layer 152 are not essential components and may be omitted as necessary. It may be omitted.

[0144] Through the above steps, the transistor 162 including an oxide semiconductor and the capacitor 164 are completed. (See FIG. 5(E)).

[0145] The transistor 162 including an oxide semiconductor manufactured by the above method has an off-state current of For example, in a fully intrinsic (i-type) oxide semiconductor, In a body, the carrier density is, for example, 1×10 12 / cm 3 Less than 1.45× 10 10 / cm 3 For example, the off-state current of the transistor is When the gate voltage Vg is in the range of -5V to -20V, even if it is +1V or +10V, , 1×10 -13 A or less. Therefore, the data retention period of the semiconductor device is sufficiently secured. Furthermore, when a fully intrinsic oxide semiconductor is used, Leakage current 1×10 -20 A (10zA (zeptoamperes)) to 1×10 -19 A (100zA). In other words, the leakage current is essentially zero. By using such an oxide semiconductor, the data retention period can be extended. Therefore, a semiconductor device with a sufficiently high reliability can be provided.

[0146] In addition, the capacitor 164 is formed at the same time, so that the gate electrode of the transistor 160 This makes it easier to hold the applied charge and to read out the stored contents. In the method shown in the embodiment, it is not necessary to add a process for forming the capacitor element 164. This is preferable from the viewpoint of reducing costs.

[0147] Note that in this embodiment, a transistor using a material other than an oxide semiconductor and a The semiconductor device relating to the stacked structure (two layers) with the transistor using the semiconductor device has been described. The structure that can be used in the present invention is not limited to the laminated structure. Alternatively, a laminated structure of three or more layers may be used.

[0148] In addition, the arrangement and connection of electrodes (wiring), insulating layers, semiconductor layers, etc., wiring width, channel width, Various parameters such as channel length and other conditions are required for semiconductor integrated circuits. For example, the semiconductor device may be formed in a single layer structure. The configuration of electrodes, wiring, etc. in such a case is significantly different from that in the case of a laminated structure.

[0149] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0150] (Embodiment 2) In this embodiment, a semiconductor device having a different configuration from the semiconductor device shown in the previous embodiment is used. The device and manufacturing method thereof will be described with reference to FIGS. The structure and manufacturing process of the semiconductor device are common to those of the first embodiment. Therefore, in the following, the explanation of the overlapping parts will be omitted, and the differences will be explained in detail. do.

[0151] <Plane and cross-sectional configurations of semiconductor device> FIG. 6 shows an example of the configuration of a semiconductor device. FIG. 6(A) shows a cross section of the semiconductor device. FIG. 6(A) shows a plan view of the semiconductor device. FIG. 6(B) shows a plan view of the semiconductor device. 6(A) and 6(B) correspond to the cross sections at A3-A4 and B3-B4. The semiconductor device to be described has a structure in which a semiconductor other than an oxide semiconductor is provided in the lower portion as in the case of FIGS. The transistor 160 includes a transistor 16 using an oxide semiconductor. The semiconductor device shown in this embodiment has an insulating layer 2 and a capacitor element 164. Since the semiconductor device does not have the 144, the manufacturing process is simpler than that of the semiconductor device shown in FIG. In addition, the capacitance due to the gate electrode 148a, etc. is reduced. To reduce the amount of charge, an insulating layer 144 may be provided.

[0152] The transistor 162 illustrated in FIG. 6A includes an oxide semiconductor layer 1 40 and a source electrode or drain electrode electrically connected to the oxide semiconductor layer 140 142a, and a source electrode or drain electrode 142b, and a source electrode or drain electrode The electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 140 A gate insulating layer 146 is provided over the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 140. The transistor shown in FIG. 162 is a top gate type, and is connected to the oxide semiconductor layer 140 and a source electrode or drain electrode. The connection to the doped electrodes 142a and 142b is made in a region including the upper surface of the oxide semiconductor layer 140. Since the structure is similar to that of the conventional top-gate / top-contact type,

[0153] <Method for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for manufacturing the lower transistor 162 will be described with reference to FIG. The method for fabricating 0 is the same as that shown in FIG. 4 and will not be described.

[0154] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 138 is formed on the rain electrode 130b and the electrode 130c. Source or drain electrode 130a, source or drain electrode 130b, electrode An opening is formed that reaches 130c (see FIG. 7(A)). The method can be seen in FIG. 5(A), so the explanation is omitted. The insulating layer can be formed by a method such as etching using a mask.

[0155] Next, an oxide semiconductor layer is formed over the insulating layer 138, and then is subjected to etching or the like using a mask. The oxide semiconductor layer is processed by a method to form an island-shaped oxide semiconductor layer 140 ( The material and the formation method of the island-shaped oxide semiconductor layer 140 are the same as those shown in FIG. Since reference can be made thereto, the description will be omitted.

[0156] Next, the insulating layer 138, the openings provided in the insulating layer 138, and the island-shaped oxide semiconductor layer 1 A conductive layer is formed so as to cover 40, and the conductive layer is removed by a method such as etching using a mask. The electrode layer is processed to form a source electrode or drain electrode 142a in contact with the oxide semiconductor layer 140. , a source electrode or drain electrode 142b, an electrode 142c, and an electrode 142d are formed. Then, the source electrode or drain electrode 142a, the source electrode or drain electrode 14 2b, a gate insulating layer 146 is formed to cover the electrode 142c and the electrode 142d ( See FIG. 7(C). The material and the method for forming the electrodes 142b, 142c, and 142d are the same as those shown in FIG. The material and shape of the gate insulating layer 146 are not described here. The method of forming the same can be seen in FIG. 5(D), and therefore the explanation thereof will be omitted.

[0157] Next, a conductive layer is formed on the gate insulating layer 146, and then the conductive layer is etched using a mask or the like. The conductive layer is processed to form a gate electrode 148a and an electrode 148b (FIG. 7). The materials and the method of forming the gate electrode 148a and the electrode 148b are shown in FIG. Therefore, the description will be omitted.

[0158] Next, a protective insulating layer is formed to cover the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. An edge layer 150 and an interlayer insulating layer 152 are formed (see FIG. 7(E)). The material and the method of forming the interlayer insulating layer 152 can be seen from FIG. 5(E). The details are omitted.

[0159] In this manner, the semiconductor device shown in FIG. 6 can be manufactured.

[0160] (Embodiment 3) In this embodiment mode, a semiconductor device formed using a plurality of the semiconductor devices shown in Embodiment 1 will be described. An example of the circuit configuration and operation will be described with reference to FIG. 8 and FIG.

[0161] <Circuit Configuration and Operation of Semiconductor Device> 8(A) and 8(B) are diagrams illustrating the semiconductor device shown in FIG. 3(A-1) (hereinafter, memory cell 19 8A is a circuit diagram of a semiconductor device formed using a plurality of FIG. 8(B) is a circuit diagram of a NAND-type semiconductor device in which memory cells 190 are connected in series. 1 is a circuit diagram of a NOR type semiconductor device in which memory cells 190 are connected in parallel.

[0162] The semiconductor device shown in FIG. 8A includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, and a The memory cell 190 includes a signal line S2, a word line WL, and a plurality of memory cells 190. The gate electrode of transistor 160 and the source or drain electrode of transistor 162 are connected to each other. One of the electrodes of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. The signal line S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected The second signal line S2 and the gate electrode of the transistor 162 are electrically connected to each other. The word line WL and the other electrode of the capacitor element 164 are electrically connected to each other. There are.

[0163] The source electrode of the transistor 160 in the memory cell 190 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 in the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. 160 is electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 190 provided at one end of the The electrode is electrically connected to a bit line. The source electrode of the transistor 160 in the memory cell 190 at the other end is , and are electrically connected to the source line. In FIG. 8A, the source line SL and the bit line B However, the present invention is not limited to this, and the source line SL and the bipolar transistor 11 may have one each. A configuration having a plurality of bit lines BL may be used.

[0164] The semiconductor device shown in FIG. 8A performs writing and reading operations for each row. The write operation is performed as follows: Transistor 16 is connected to the second signal line S2 of the row to be written. 2 is turned on, and the transistor 162 of the row to be written is turned on. As a result, the voltage of the first signal line S1 is applied to the gate electrodes of the transistors 160 in the specified row. A specific charge is applied to the gate electrode of the specified row. Data can be written to the memory cells.

[0165] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are In addition, the transistor 160 is turned on regardless of the charge on the gate electrode of the transistor 160. A potential is applied so that the transistors 160 in the rows other than the one to be read out are turned on. Then, a constant potential is applied to the source line SL, and the bit line BL is connected to a read circuit (not shown). Here, a plurality of transistors 160 between the source line SL and the bit line BL are connected to Since all rows except for the one being read are on, the conductance between the source line SL and the bit line BL is The state of the transistor 160 in the row where the reading is performed is determined. The read circuit detects the charge on the gate electrode of the transistor 160 in the row that is to be read. The potential of the bit line BL to be read is different. In this way, the data is read from the memory cells of the specified row. The data can be read out.

[0166] Next, the semiconductor device shown in FIG. 8B includes a source line SL, a bit line BL, a first signal line S1, The memory cell 190 includes a plurality of second signal lines S2 and a plurality of word lines WL. The gate electrode of each transistor 160 and the source electrode or drain of each transistor 162 One of the drain electrodes and one of the electrodes of the capacitor 164 are electrically connected to each other. The source line SL and the source electrode of the transistor 160 are electrically connected to each other, and the bit line B L is electrically connected to the drain electrode of the transistor 160. The line S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected. The second signal line S2 and the gate electrode of the transistor 162 are electrically connected to each other. The word line WL and the other electrode of the capacitor 164 are electrically connected to each other.

[0167] The semiconductor device shown in FIG. 8B performs writing and reading operations for each row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The process is as follows: First, the word line WL of the row to be read is connected to the transistor 160. The on or off state of transistor 160 is selected depending on the charge carried by the gate electrode. Then, a constant potential is applied to the source line SL, and the bit line BL is read. The transistors 160 in the non-selected rows are connected to a read circuit (not shown). Here, the conductance between the source line SL and the bit line BL is This is determined by the state of the transistor 160 of the row. The potential of the gate electrode of the transistor 160 determines the potential of the bit line BL read by the read circuit. In this way, data can be read from the memory cells in a specified row. .

[0168] The semiconductor device shown in FIG. 8A and FIG. 8B is a transistor using a material other than an oxide semiconductor. Since the register 160 is capable of sufficiently high-speed operation, it is possible to read out the memory contents at high speed. In addition, the off-state current of the transistor 162 including an oxide semiconductor is extremely small. Therefore, by turning off the transistor 162, The potential of the gate electrode of transistor 160 can be maintained for a very long time. In addition, by including the capacitor 164, This makes it easier to hold a given charge and easier to read out the stored contents.

[0169] In the semiconductor device configured with a plurality of memory cells as described above, the storage capacity is In order to suppress the unit cost, it is necessary to reduce the area occupied by each memory cell. In order to solve this problem, for example, in a NAND type semiconductor device shown in FIG. In this case, the transistors 160 connected in series are configured as shown in the cross-sectional view of FIG. As a result, the area occupied by each memory cell can be reduced. These correspond to cross sections C1-C2 and D1-D2 in (B).

[0170] In the semiconductor device shown in FIG. 9A, a transistor 160 provided in a substrate 100 is The impurity region 120 (also simply referred to as the impurity region) and the metal compound region 124 are adjacent to each other. In other words, the transistor 160 is sandwiched between the The high concentration impurity region 120 and the metal compound region 124 form the source of one of the transistors 160. region and serves as the drain region of the other transistor 160 .

[0171] In addition, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover the transistor 160. In addition, at the end of the series-connected transistors 160, the interlayer insulating layer 12 6 and the interlayer insulating layer 128 through an opening formed therein, and electrically connected to the metal compound region 124. An electrode 192 is formed to connect the two.

[0172] Here, the transistor 160 is substantially the same as the transistor 160 shown in FIG. For details, please refer to the above. In this embodiment, in order to achieve high integration of the transistor 160, the sidewall insulating layer 1 shown in FIG. The configuration does not include 18.

[0173] The configuration shown in FIG. 9A can be used not only in the NAND type semiconductor device shown in FIG. It can also be used in the NOR type semiconductor device shown in FIG. In the memory cell array, adjacent columns of memory cells are arranged symmetrically. The transistor 160 of the transistor is connected to the high concentration impurity region 120 and the metal compound region 124. In this case, at least two transistors 160 are connected in the same manner. , are connected via the high concentration impurity region 120 and the metal compound region 124 .

[0174] By connecting a plurality of transistors 160 in the above configuration, the transistor 16 0 and the memory cell 190 can be highly integrated. The unit price per capacity can be reduced.

[0175] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0176] (Embodiment 4) Next, FIG. 10 shows a modified example of the configuration of the semiconductor device.

[0177] The semiconductor device shown in FIG. 10A is a modified example of the semiconductor device shown in FIG.

[0178] The difference between the configuration shown in FIG. 10(A) and the configuration shown in FIG. 1(A) is that the electrode 130c is disposed on the substrate 10 1(A) is electrically connected to the metal compound region provided at 0. In the configuration shown in FIG. 1, the source or drain electrode 142a and the gate electrode 110 are electrically connected 10(A) is connected to the source electrode or drain electrode. The electrode 142a and the metal compound region are electrically connected.

[0179] The structure shown in FIG. 10A is the same as the semiconductor device shown in the previous embodiment. Thus, semiconductor devices having different circuit configurations can be realized.

[0180] The semiconductor device shown in FIG. 10B is a modification of the semiconductor device shown in FIG.

[0181] The difference between the configuration shown in FIG. 10B and the configuration shown in FIG. 6A is that the electrode 130c is disposed on the substrate 10. 6A. The point is that the metal compound region is electrically connected to the metal compound region provided at the upper end of the insulating layer 10. In the configuration shown in FIG. 1, the source or drain electrode 142a and the gate electrode 110 are electrically connected 10B, the source electrode or drain electrode is connected to the The electrode 142a and the metal compound region are electrically connected.

[0182] By adopting the structure shown in FIG. 10B, the semiconductor device shown in the above embodiment can be Thus, semiconductor devices having different circuit configurations can be realized.

[0183] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0184] (Embodiment 5) Next, the transistor 162 in the previous embodiment (Embodiment 1, etc.) FIG. 1 shows another example of a method for manufacturing a transistor including an oxide semiconductor. In this embodiment, a highly purified oxide semiconductor (particularly, an amorphous In the following, we will explain in detail the case where a top-gate transistor is used. We will use a transistor as an example to explain this, but the transistor structure does not have to be limited to the top gate type. stomach.

[0185] First, an insulating layer 202 is formed on a lower substrate 200. Then, an oxide layer is formed on the insulating layer 202. A semiconductor layer 206 is formed (see FIG. 11(A)).

[0186] For example, the lower layer substrate 200 may be the same as that in the semiconductor device of the previous embodiment (FIG. 1 or FIG. 6, etc.). The structure below the interlayer insulating layer 128 can be used as the structure. The surface of the lower substrate 200 is as flat as possible. For example, it is desirable to reduce the surface height by using a chemical mechanical polishing method (CMP method) or the like. , 5 nm or less, preferably 1 nm or less. Alternatively, the root mean square of the surface roughness (RMS) may be set to 2 nm or less, preferably 0.4 nm or less.

[0187] The insulating layer 202 functions as a base, and is different from the insulating layer 138 in the previous embodiment. It can be formed in the same manner as the insulating layer 144. For details, refer to the previous embodiment. Note that the insulating layer 202 is formed so as not to contain hydrogen or water as much as possible. It is desirable to do so.

[0188] The oxide semiconductor layer 206 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O or a ternary The In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system The insulating film 10 can be formed using an oxide semiconductor such as a Zn—O-based semiconductor.

[0189] Among them, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. Since it is possible to sufficiently reduce the field current and the field effect mobility is high, It is suitable as a semiconductor material for use in devices.

[0190] A representative example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M is Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn The above composition is derived from the crystal structure. It should be noted that the above is merely an example.

[0191] The oxide semiconductor layer 206 was formed by a sputtering method using a target of In: The composition formula is Ga:Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In:Ga:Zn=1:1:1 [atom ratio] (x=1, y= 1), (i.e., In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) Alternatively, a target having a composition ratio of In:Ga:Zn=1:1:0.5 may be used. [atom ratio] (x=1, y=0.5) and In:Ga:Z A target with a composition ratio of n=1:1:2 (x=1, y=2) and In A target having a composition ratio of Ga:Zn=1:0:1 [atom ratio] (x=0, y=1) A marker can also be used.

[0192] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more. More preferably, the relative density is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form the oxide semiconductor layer 206 with a dense structure.

[0193] In this embodiment, the oxide semiconductor layer 206 having an amorphous structure is formed using an In-Ga-Zn-O based metal oxide. The layer is formed by sputtering using a metal oxide target.

[0194] The oxide semiconductor layer 206 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration is reduced to 10 ppb or less. It is.

[0195] When the oxide semiconductor layer 206 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The temperature of the substrate is maintained at 100° C. or higher and lower than 550° C., preferably 200° C. or higher and 400° C. or lower. The substrate is heated so that the moisture in the processing chamber is removed, and hydrogen, water, etc. are removed. The oxide semiconductor layer 206 is formed by using the above target. The oxide semiconductor layer 206 is formed while the substrate is heated. It is possible to reduce impurities contained in the material. It also reduces damage caused by sputtering. To remove moisture from inside the processing chamber, an adsorption type vacuum pump can be used. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. A turbo molecular pump with a cold trap can also be used. Hydrogen, water, etc. can be removed from the processing chamber by evacuating it using a cryopump. Therefore, the impurity concentration in the oxide semiconductor layer 206 can be reduced.

[0196] The oxide semiconductor layer 206 is formed under the following conditions: the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon In addition, a pulsed direct current (DC) power supply is used. This reduces dust (powdery material formed during film formation) and makes the film thickness distribution uniform. The thickness of the oxide semiconductor layer 206 is preferably 2 nm to 200 nm, more preferably 5 However, the thickness is determined depending on the oxide semiconductor material and the application of the semiconductor device. The appropriate thickness varies depending on the material and application, so the thickness should be selected according to the material and application. That's good.

[0197] Note that before the oxide semiconductor layer 206 is formed by a sputtering method, argon gas is In this manner, the deposits on the surface of the insulating layer 202 are removed by reverse sputtering, in which plasma is generated by introducing a gas. Here, the reverse sputtering is a method of removing the In this case, instead of bombarding the sputtering target with ions, the ions are bombarded on the treatment surface. This is a method of modifying the surface by bombarding the surface with ions. The method is to apply a high-frequency voltage to the processing surface in an argon atmosphere and place a plasma near the substrate. In addition, nitrogen, helium, or oxygen can be used instead of argon. The atmosphere may be changed as described above.

[0198] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 206a is formed.

[0199] The oxide semiconductor layer 206 can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching temperature) are adjusted according to the material so that the layer can be etched into the desired shape. The etching gas, the etching solution, the etching time, the temperature, and the like are set appropriately. The etching may be performed in a similar manner to the etching of the oxide semiconductor layer in the above embodiment. For details of the etching conditions, etc., the above embodiment may be referred to.

[0200] After that, the oxide semiconductor layer 206a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or a hydroxyl group) from the oxide semiconductor layer 206a. The structure of the oxide semiconductor layer is adjusted, and the energy The defect level in the gap can be reduced. The temperature of the first heat treatment is, for example, 300 The temperature is from 400°C to 500°C. If the etching is performed after the etching, even if wet etching is used, the etching This has the advantage of saving time.

[0201] The heat treatment is carried out, for example, by placing the lower substrate 200 in an electric furnace using a resistance heating element or the like and heating the lower substrate 200 in a nitrogen atmosphere. The heat treatment can be performed under the conditions of air at 450° C. for one hour. During this time, the oxide semiconductor layer 206a Do not expose to air and prevent contamination with water or hydrogen.

[0202] The heat treatment device is not limited to an electric furnace, and may be any type of heat treatment device, such as heat conduction from a medium such as a heated gas, or A device that heats the workpiece by thermal radiation may be used. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0203] For example, in the first heat treatment, the substrate is placed in a heated inert gas atmosphere and heated for several minutes. After that, a GRTA process may be performed in which the substrate is removed from the inert gas atmosphere. Treatment A allows high-temperature heat treatment in a short time. This makes it possible to apply the process even under temperature conditions that exceed the heat resistance of the substrate. The reactive gas may be switched to a gas containing oxygen. By performing this, it is possible to reduce the defect level in the energy gap caused by oxygen vacancies. This is because

[0204] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing 1,2-dichloroethane (CO), which is the main component, and does not contain water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into heat treatment equipment Purity should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0205] In any case, the first heat treatment reduces impurities and makes the semiconductor i-type or substantially i-type. By forming the oxide semiconductor layer 206a, a transistor with excellent characteristics can be realized. It is possible.

[0206] Note that the first heat treatment is performed on the oxide semiconductor layer 2 before it is processed into the island-shaped oxide semiconductor layer 206a. In that case, the lower substrate 20 is removed from the heating device after the first heat treatment. 0 and undergoes a photolithography process.

[0207] The first heat treatment has the effect of removing hydrogen and water, so the first heat treatment is also called dehydration treatment or dehydration treatment. The dehydration or dehydrogenation treatment may be called hydrogenation treatment or the like. After forming the oxide semiconductor layer 206a or stacking a source electrode or a drain electrode over the oxide semiconductor layer 206a, In addition, such dehydration treatment and dehydrogenation can be performed at the following timing. The chemical treatment may be carried out not only once but also multiple times.

[0208] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. By selectively etching the source or drain electrode 208a, the source or drain The source electrode 208b is formed (see FIG. 11(B)). The process is similar to that for the electrode 142a, drain electrode 142b, etc. The embodiments can be referred to.

[0209] Next, the gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (FIG. 11). For details, please refer to the description of the insulating layer 138 in the previous embodiment. It is possible.

[0210] After the gate insulating layer 212 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0 and 350°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. In addition, when the gate insulating layer 212 contains oxygen, the oxide semiconductor layer 206 By supplying oxygen to the oxide semiconductor layer 206a, oxygen vacancies in the oxide semiconductor layer 206a are compensated for, and the oxide semiconductor layer 206a becomes an i-type (intrinsic semiconductor). ) or an oxide semiconductor layer that is as close to i-type as possible.

[0211] In this embodiment, the second heat treatment is performed after the gate insulating layer 212 is formed. The timing of the second heat treatment is not particularly limited to this.

[0212] Next, a gate electrode was formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a. The gate electrode 214 is formed on the gate insulating layer 212 (see FIG. 11(D)). After forming a conductive layer on the substrate, the conductive layer is selectively patterned to form the insulating film. For details, see the description of the gate electrode 148a in the previous embodiment. I can pour drinks.

[0213] Next, an interlayer insulating layer 216 and an interlayer insulating film 217 are formed on the gate insulating layer 212 and the gate electrode 214. The edge layer 218 is formed (see FIG. 11(E)). The interlayer insulating layer 216 and the interlayer insulating layer 218 are The can be formed by using a PVD method, a CVD method, etc. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. The insulating layer 11 can be formed by using a material containing an organic insulating material. The insulating layer 216 and the interlayer insulating layer 218 are laminated together. There is no limitation to the number of layers. It may be a single layer or a laminated structure of three or more layers.

[0214] It is preferable that the interlayer insulating layer 218 is formed so that its surface is flat. By forming the interlayer insulating layer 218 so as to have a flat surface, a conductive layer is formed on the interlayer insulating layer 218. This is because electrodes, wiring, etc. can be formed suitably.

[0215] Through the above steps, the transistor 250 including the highly purified oxide semiconductor layer 206a is completed. (See FIG. 11(E)).

[0216] The transistor 250 shown in FIG. 11(E) is disposed on the lower substrate 200 via the insulating layer 202. The oxide semiconductor layer 206a is electrically connected to the source A source or drain electrode 208a, a source or drain electrode 208b, and an oxide semiconductor A conductor layer 206a, a source electrode or a drain electrode 208a, a source electrode or a drain electrode a gate insulating layer 212 covering the electrode 208b; and a gate electrode 214 on the gate insulating layer 212. An interlayer insulating layer 216 on the gate insulating layer 212 and the gate electrode 214; and an interlayer insulating layer 218.

[0217] In the transistor 250 described in this embodiment, the oxide semiconductor layer 206a is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below 5, preferably ×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Below The carrier density of the oxide semiconductor layer 206a is lower than that of a general silicon wafer. Carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., , 1×10 12 / cm 3 less than 1.45×10 10 / cm 3 (less than) This makes the off-current sufficiently small. For example, when the channel length is 10 μm, When the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is 1 V to 10 V. When the gate-source voltage is in the range of about 0 V, the off-state current (the drain current when the gate-source voltage is 0 V or less) The input current is 1×10 -13 A or less. Or, the off-current density at room temperature (off-current divided by the transistor channel width) is 1×10 -20 A / μm (10zA / μm) From 1×10 -19 A / μm (100zA / μm).

[0218] In addition to the off-state current and off-state current density, the characteristics of the above-mentioned transistors include the off-state resistance (transistor The resistance value when the transistor is off and the off resistivity (resistivity when the transistor is off) Here, the off-resistance R can be expressed using the off-current and drain voltage as The off-resistivity ρ is the value calculated from Ohm's law. This value can be calculated by using the area A and the channel length L, and is expressed as ρ=RA / L. In the above case, the off-resistance is 1×10 9Ω·m or more (or 1×10 10 Ω·m or more) The cross-sectional area A is expressed as A=dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. will be done.

[0219] By using the oxide semiconductor layer 206a which has been highly purified and made intrinsic, Therefore, the off-state current of the transistor can be sufficiently reduced.

[0220] In this embodiment, a transistor Although the present invention has been described with reference to the embodiment using the stencil 250, it is not necessary to interpret the present invention as being limited to this embodiment. For example, by sufficiently improving the electrical properties of oxide semiconductors, It is also possible to use an oxide semiconductor for all the transistors including the transistor. In such a case, it is not necessary to have a laminated structure as shown in the previous embodiment. To achieve good circuit operation, the field effect mobility μ of the oxide semiconductor must be μ>100 cm 2 In this case, a glass substrate or other substrate is used to form a semiconductor It is possible to form a body device.

[0221] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0222] (Embodiment 6) Next, the transistor 162 in the previous embodiment (Embodiment 1, etc.) FIG. 1 shows another example of a method for manufacturing a transistor including an oxide semiconductor, which can In this embodiment, the oxide semiconductor layer has a crystalline region. A first oxide semiconductor layer and a second oxide semiconductor layer formed by crystal growth from a crystalline region of the first oxide semiconductor layer. In the following, a top-gate type semiconductor layer is used. However, the structure of the transistor is not necessarily limited to the top gate type. There is no need.

[0223] First, an insulating layer 302 is formed on a lower substrate 300. Then, a first An oxide semiconductor layer is formed, and at least a surface of the first oxide semiconductor layer is subjected to a first heat treatment. The region containing the oxide semiconductor layer is crystallized to form a first oxide semiconductor layer 304 (see FIG. 12A). ).

[0224] For example, the lower layer substrate 300 may be the same as that in the semiconductor device of the previous embodiment (FIG. 1 or FIG. 6, etc.). The structure below the interlayer insulating layer 128 can be used as the structure. The surface of the lower substrate 300 is as flat as possible. For example, it is desirable to reduce the surface height by using a chemical mechanical polishing method (CMP method) or the like. , 5 nm or less, preferably 1 nm or less. Alternatively, the root mean square of the surface roughness (RMS) may be set to 2 nm or less, preferably 0.4 nm or less.

[0225] The insulating layer 302 functions as a base, and is the same as the insulating layer 138 in the previous embodiment. It can be formed in the same manner as the insulating layer 144. For details, refer to the previous embodiment. Note that the insulating layer 302 is formed so as not to contain hydrogen or water as much as possible. It is desirable to do so.

[0226] The first oxide semiconductor layer is formed in a manner similar to that of the oxide semiconductor layer 206 in the above embodiment. The details of the first oxide semiconductor layer and the method for forming the first oxide semiconductor layer can be found in the above embodiment. However, in this embodiment, the first oxide is formed by the first heat treatment. In order to intentionally crystallize the semiconductor layer, the first It is preferable to form an oxide semiconductor layer. Examples of such an oxide semiconductor include In addition, oxide semiconductors such as In-Ga-Zn-O are also available. For example, a high concentration of Zn is easily crystallized, and the metal elements of Zn (In, Ga, Zn) A ratio of 60% or more is preferable for this purpose. The thickness of the semiconductor layer is preferably 3 nm or more and 15 nm or less. However, the thickness may vary depending on the oxide semiconductor material and the application of the semiconductor device. The appropriate thickness varies depending on the material, so the thickness should be selected according to the material and application. good.

[0227] The temperature of the first heat treatment is 550° C. or higher and 850° C. or lower, preferably 600° C. or higher and 750° C. or lower. The heat treatment time should be between 1 minute and 24 hours. The temperature and time of the heat treatment vary depending on the type of oxide semiconductor. The atmosphere for the heat treatment is preferably an atmosphere that does not contain hydrogen or water. The atmosphere is nitrogen, oxygen, or rare gas (helium, neon, argon, etc.) from which oxygen has been sufficiently removed. It is possible.

[0228] Heat treatment equipment includes electric furnaces, as well as equipment that uses heat conduction from a medium such as heated gas or heat radiation. For example, a GRTA (Gas Ra pid Thermal Anneal) equipment, LRTA (Lamp Rapid Th RTA (Rapid Thermal Anneal) equipment l) Equipment can be used. LRTA equipment includes halogen lamps, metal halide lamps, etc. xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp It is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as benzene or nitrogen. is used.

[0229] By the above-mentioned first heat treatment, at least a region including a surface of the first oxide semiconductor layer is crystallized. The crystalline region extends from the surface of the first oxide semiconductor layer to the inside of the first oxide semiconductor layer. The crystal growth proceeds toward the crystal region. The crystal region may contain plate-like crystals with an average thickness of 2 nm to 10 nm. The oxide semiconductor layer has an ab-plane that is approximately parallel to the surface of the oxide semiconductor layer, and a c-axis that is approximately perpendicular to the surface. In this case, the term "approximately parallel" refers to a state in which the orientation is within ±10° from the parallel direction. "Approximately vertical" refers to a state within ±10° from the vertical direction.

[0230] In addition, the first heat treatment forms a crystalline region and removes hydrogen from the first oxide semiconductor layer. It is desirable to remove hydrogen and other substances (including water and hydroxyl groups). Nitrogen and oxygen with a purity of 6N (99.9999%) or more (i.e. impurity concentration of 1ppm or less) The first heat treatment is preferably performed in a nitrogen or rare gas (helium, neon, argon, etc.) atmosphere. More preferably, the purity is 7N (99.99999%) or more (i.e., the concentration of impurities is 0.1 ppm or less). In addition, it is preferable to use ultra-dry air with H2O of 20 ppm or less. Alternatively, the first heat treatment may be performed in ultra-dry air with an H2O concentration of 1 ppm or less.

[0231] In addition, the first heat treatment is performed to form a crystalline region and to supply oxygen to the first oxide semiconductor layer. For example, by changing the heat treatment atmosphere to an oxygen atmosphere, Oxygen can be supplied to the oxide semiconductor layer 1.

[0232] In this embodiment, the first heat treatment is performed in a nitrogen atmosphere at 700° C. for 1 hour. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere is switched to an oxygen atmosphere. The first heat treatment is performed mainly to supply oxygen to the inside of the first oxide semiconductor layer. Since this is a process for forming a region, the removal of hydrogen and other substances and the treatment for the purpose of supplying oxygen must be carried out separately. For example, after heat treatment to remove hydrogen and other substances, or treatment to supply oxygen, In this case, it is possible to carry out a heat treatment for crystallization.

[0233] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. Thus, a first oxide semiconductor layer to which oxygen is supplied is obtained.

[0234] Next, a first oxide semiconductor layer 304 having a crystalline region at least in a region including a surface thereof is formed with A second oxide semiconductor layer 305 is formed (see FIG. 12B).

[0235] The second oxide semiconductor layer 305 is formed in the same manner as the oxide semiconductor layer 206 in the above embodiment. The details of the second oxide semiconductor layer 305 and a method for forming the second oxide semiconductor layer 305 will be described below. The above embodiment may be referred to. Note that the second oxide semiconductor layer 305 is It is preferable that the first oxide semiconductor layer 304 is formed thicker than the first oxide semiconductor layer 304. The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are formed so that the sum of their thicknesses is 3 nm to 50 nm. It is preferable to form the oxide semiconductor layer 305 of the second oxide semiconductor material. The appropriate thickness varies depending on the material and application of the semiconductor device. The method may be selected depending on the purpose.

[0236] The second oxide semiconductor layer 305 is made of a material having the same main component as the first oxide semiconductor layer 304. Therefore, it is desirable to use materials with close lattice constants after crystallization (mismatch of 1% or less). When such a material is used, the second oxide semiconductor layer 305 is crystallized. This is because crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed is likely to proceed. Furthermore, when the main components are the same, the interface properties and electrical characteristics are also improved.

[0237] In addition, if the desired film quality can be obtained by crystallization, a second film may be formed using a material with a different main component. Alternatively, the oxide semiconductor layer 305 may be formed in the same manner as above.

[0238] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 is The crystalline region is used as a seed for crystal growth to form a second oxide semiconductor layer 306 (FIG. 12). (C))).

[0239] The temperature of the second heat treatment is 550° C. or higher and 850° C. or lower, preferably 600° C. or higher and 750° C. or lower. The heating time of the second heat treatment is from 1 minute to 100 hours, preferably from 5 hours to 100 hours. The heat treatment time is set to 20 hours or less, typically 10 hours. It is preferable that the atmosphere during the process does not contain hydrogen, water, etc.

[0240] The details of the atmosphere and the effects of the heat treatment are the same as those of the first heat treatment. The heat treatment apparatus that can perform this is the same as that for the first heat treatment. By sometimes placing the inside of the furnace in a nitrogen atmosphere and sometimes placing the inside of the furnace in an oxygen atmosphere during cooling, Hydrogen and the like can be removed in the atmosphere, and oxygen can be supplied in the oxygen atmosphere.

[0241] By performing the above-described second heat treatment, the oxide semiconductor layer 304 is formed. The crystal growth is caused to proceed from the crystalline region to the entire second oxide semiconductor layer 305, so that the second oxide semiconductor A conductor layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like are removed. In addition, the second oxide semiconductor layer 306 to which oxygen is supplied can be formed. The heat treatment can improve the orientation of the crystalline region of the first oxide semiconductor layer 304. be.

[0242] For example, an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 306. In this case, the second oxide semiconductor layer 306 is InGaO3(ZnO). m (m: integer) The crystals represented by the formula In2Ga2ZnO7 (In:Ga:Zn:O = 2:2:1:7) Such crystals may include crystals in which the c-axis is aligned in the second heat treatment. The oxide semiconductor layer 306a is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer 306a.

[0243] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be considered as a laminated structure of layers parallel to the a-axis and b-axis. In general, the above crystals are made up of layers containing In and layers not containing In (Ga or The layer has a structure in which layers containing Zn or a layer containing Zn are stacked in the c-axis direction.

[0244] In the case of In-Ga-Zn-O oxide semiconductor crystals, the in-plane direction of the layer containing In, In other words, the electrical conductivity in the directions parallel to the a-axis and b-axis is good. In a-Zn-O oxide semiconductor crystals, electrical conduction is mainly controlled by In. , and the 5s orbital of one In overlaps with the 5s orbital of an adjacent In. , and career paths are formed.

[0245] In addition, the first oxide semiconductor layer 304 may have an amorphous region at the interface with the insulating layer 302. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region toward the bottom of the first oxide semiconductor layer, and the In some cases, the amorphous region may be crystallized. Depending on the conditions, the amorphous region may remain.

[0246] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are made of oxide semiconductors having the same main component. In the case where a dielectric material is used, as shown in FIG. 12C, a first oxide semiconductor layer 304 and a second oxide semiconductor layer 305 are formed. In some cases, the oxide semiconductor layer 306 may have the same crystal structure as the oxide semiconductor layer 306 in FIG. In FIG. 3C, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are shown by dotted lines. The boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable. In some cases they may be considered to be the same layer.

[0247] Next, the first oxide semiconductor layer 304 and the The second oxide semiconductor layer 306 is processed into an island-shaped first oxide semiconductor layer 304a and a second oxide semiconductor layer 304b. An oxide semiconductor layer 306a is formed (see FIG. 12D). After the etching, the oxide semiconductor is processed into an island-shaped oxide semiconductor layer. After that, a second heat treatment may be performed. In this case, wet etching may be used. However, there is an advantage in that the time required for etching can be shortened.

[0248] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are etched using a dry etching method. Either etching or wet etching may be used. Of course, a combination of both may also be used. In order to etch the oxide semiconductor layer into a desired shape, a material Etching conditions (etching gas, etching solution, etching time, temperature, etc.) The etching temperature of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is set appropriately. The etching can be performed in a manner similar to the etching of the oxide semiconductor layer in the above embodiment. For details, please refer to the above embodiment.

[0249] Note that a region to be a channel formation region in the oxide semiconductor layer has a flat surface. For example, it is preferable that the height difference of the surface of the second oxide semiconductor layer 306 is such that the gate electrode overlaps the second oxide semiconductor layer 306. In the region where the electrodes overlap (channel formation region), the overlapping distance is 1 nm or less (preferably 0.2 nm or less). It is preferable to have one.

[0250] Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. The conductive layer is selectively etched to form the source or drain electrode 308a, The source or drain electrode 308b is formed (see FIG. 12(D)). The electrode 308a and the source or drain electrode 308b are the same as those in the previous embodiment. The source or drain electrode 142a has a shape similar to that of the source or drain electrode 142b. For details, the above embodiment may be referred to.

[0251] In the step shown in FIG. 12D, the first oxide semiconductor layer 304a and the second oxide semiconductor layer On the side of the conductor layer 306a, a source electrode or drain electrode 308a, Alternatively, the crystal layer in contact with the drain electrode 308b may become amorphous. The entire region of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a is crystalline. It is not necessarily a structure.

[0252] Next, a gate insulating layer 312 is formed in contact with a part of the second oxide semiconductor layer 306a. The gate insulating layer 312 can be formed by using a CVD method, a sputtering method, or the like. After that, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b on the gate insulating layer 312 are A gate electrode 314 is formed in a region overlapping with the layer 306a. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed on the gate electrode 314 (FIG. 12(E)). A gate insulating layer 312, a gate electrode 314, an interlayer insulating layer 316 and a layer The interlayer insulating layer 318 is the same as the insulating layer 138, the gate electrode 148a, and the interlayer insulating layer 318 in the previous embodiment. The insulating layer 216 and the interlayer insulating layer 218 can be formed in the same manner. Please refer to the embodiment of the present invention.

[0253] After the gate insulating layer 312 is formed, a third heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is preferably 200° C. or more and 450° C. or less. For example, in an oxygen-containing atmosphere at 250°C for 1 hour, By performing the third heat treatment, the electrical characteristics of the transistor are improved. In addition, when the gate insulating layer 312 is an insulating layer containing oxygen, In this case, oxygen is supplied to the second oxide semiconductor layer 306a, and the oxygen of the second oxide semiconductor layer 306a is Compensating for elemental deficiencies to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible It is also possible.

[0254] In this embodiment, the third heat treatment is performed after the gate insulating layer 312 is formed. The timing of the third heat treatment is not limited to this. In addition, the timing of the third heat treatment may be different from that of the second heat treatment. Therefore, when oxygen is supplied to the second oxide semiconductor layer, the third heat treatment can be omitted. good.

[0255] As a result of the above, the first oxide semiconductor layer 304a and A transistor 350 including a second oxide semiconductor layer 306a grown from a crystalline region is completed (see FIG. 12(E)).

[0256] The transistor 350 shown in FIG. 12(E) is disposed on the lower substrate 300 via the insulating layer 302. The first oxide semiconductor layer 304a is provided on the first oxide semiconductor layer 304a. The second oxide semiconductor layer 306a is electrically connected to the second oxide semiconductor layer 306a. A source or drain electrode 308a, a source or drain electrode 308b, and a The second oxide semiconductor layer 306a, the source or drain electrode 308a, The gate insulating layer 312 covers the drain electrode 308b, and the gate electrode 308a on the gate insulating layer 312 is 314, an interlayer insulating layer 316 on the gate insulating layer 312 and the gate electrode 314, and an interlayer insulating layer and an interlayer insulating layer 318 on the border layer 316 .

[0257] In the transistor 350 described in this embodiment, the first oxide semiconductor layer 304a and Since the second oxide semiconductor layer 306a and the second oxide semiconductor layer 306b are highly purified, the hydrogen concentration is 5×10 19 / cm 3 Less than 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The carrier density of the oxide semiconductor layer 206a is as follows: Carrier density in the silicon wafer (1×10 14 / cm 3 is sufficiently small compared to the Value (e.g. 1×10 12 / cm 3 less than 1.45×10 10 / cm 3 This makes the off-current sufficiently small. For example, When the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is When the voltage is in the range of V to 10V, the off-state current (when the gate-source voltage is 0V or less) The drain current when -13 A or less. Or, the off-current density at room temperature (Off-state current divided by the channel width of the transistor) is 1×10 -20 A / μm(10z A / μm) to 1×10 -19 A / μm (100zA / μm).

[0258] In addition to the off-state current and off-state current density, the characteristics of the above-mentioned transistors include the off-state resistance (transistor The resistance when the transistor is off and the off resistivity (resistance when the transistor is off) Here, the off-resistance R can be expressed using the off-current and drain voltage as The off-resistance ρ is the value calculated from Ohm's law. This value can be calculated by using the area A and the channel length L, and is expressed as ρ=RA / L. In the above case, the off-resistance is 1×10 9 Ω·m or more (or 1×10 10 Ω·m or more) The cross-sectional area A is expressed as A=dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. will be done.

[0259] The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are thus highly purified and intrinsic. By using the compound semiconductor layer 306a, the off-state current of the transistor can be sufficiently reduced. Cut.

[0260] Further, in this embodiment, a first oxide semiconductor having a crystalline region is used as the oxide semiconductor layer. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are crystal-grown from the crystalline region of the first oxide semiconductor layer 304a. The use of the oxide semiconductor layer 306a improves the field effect mobility and provides good electrical characteristics. It is possible to realize a transistor having the above structure.

[0261] In this embodiment, a transistor Although the present invention has been described with reference to the embodiment using the stencil 350, it is not necessary to interpret the present invention as being limited to this embodiment. For example, the transistor 350 described in this embodiment has a first oxide film having a crystalline region. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are grown from the crystalline region of the first oxide semiconductor layer 304a. Since the second oxide semiconductor layer 306a has a good field-effect mobility, it is possible to integrate the It is possible to use oxide semiconductors for all transistors, including those that constitute circuits. In such a case, the laminated structure shown in the above embodiment is However, in order to realize good circuit operation, the field effect mobility of the oxide semiconductor is required. μ is μ>100cm 2 / V·s. In this case, the glass substrate A semiconductor device can be formed using a substrate such as a silicon substrate.

[0262] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0263] (Embodiment 7) In this embodiment mode, a manufacturing method of a semiconductor device different from the manufacturing method shown in Embodiment Mode 1 will be described. In this embodiment, the gate voltage of the lower transistor is formed by a so-called damascene method. The electrode is formed, and the source and drain electrodes of the upper transistor are formed using the electrode material. It is characterized by forming a rain electrode, etc.

[0264] First, the state shown in FIG. 4(G) is obtained by the method shown in the first embodiment. Then, the interlayer insulating layer 126 and the interlayer insulating layer 128 are polished by a CMP method or the like, and the gate The upper surface of the gate electrode 110 is exposed. Then, the gate electrode is removed by selective etching. The pole 110 is etched to form a cavity 127 (see FIG. 13(B)).

[0265] Next, a conductive film made of a metal or metal nitride is formed by a deposition method so as to completely fill the voids 127. The conductive layer may be a single layer or a multilayer. Then, the conductive layer is etched to form an electrode layer. (Source or drain electrode 142a and source or drain electrode 142b ) is obtained (see FIG. 13(C)). At this stage, the same as FIG. 5(B) shown in the first embodiment is obtained. The composition is as follows.

[0266] Thereafter, in the same manner as in the first embodiment, the island-shaped oxide semiconductor layer 140, the gate insulating layer 146, A gate electrode 148a and an electrode 148b are formed (see FIG. 13(D)). What should be done is that the electrode layer (source electrode or drain electrode 142a) is It is the gate electrode of the upper transistor and also the source or drain electrode of the upper transistor. In this embodiment, the lower transistor required in the first embodiment is eliminated. This makes it possible to omit the step of forming a contact hole to the gate electrode 110 of the semiconductor device. In the embodiment, the island-shaped oxide semiconductor layer 140 is in contact with the interlayer insulating layer 128. Before forming the oxide semiconductor layer 140, the surface of the interlayer insulating layer 128 is sufficiently dehydrogenated. It is hoped that this will happen.

[0267] (Embodiment 8) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 14. In this embodiment, Telephones, mobile phone devices, portable information terminals (including portable game consoles, audio playback devices, etc.) (including), digital cameras, digital video cameras, electronic paper, television equipment (television The above-described semiconductor device is applied to electronic devices such as a television receiver. This section explains what happens when

[0268] FIG. 14A shows a notebook personal computer, which includes a housing 401, a housing 402, The display unit 403 and the keyboard 404 are included. The semiconductor device described in the above embodiment is provided inside the semiconductor device. A novel device that can store and read data at high speed, can store data for a long period of time, and consumes sufficiently low power. This makes it possible to realize a portable personal computer.

[0269] FIG. 14B shows a portable information terminal (PDA), and a main body 411 includes a display unit 413 and an external The terminal 415 includes an external interface, an operation button 414, and the like. The main body 411 includes a stylus 412 for operating the terminal. Therefore, writing and reading of data can be performed at high speed and for a long time. Thus, a portable information terminal capable of storing data for a long period of time and having sufficiently reduced power consumption is realized.

[0270] FIG. 14C shows an electronic book 420 equipped with electronic paper. The electronic book 420 is made up of a housing 421 and a housing 422. The display unit 42 is disposed in the housing 421 and the housing 423. 5 and a display unit 427 are provided. The housing 421 and the housing 423 are connected by a shaft portion 437. The housing 421 is connected to the shaft 437, and can be opened and closed around the shaft 437. The portable terminal 421 includes a power source 431, an operation key 433, a speaker 435, and the like. At least one of the bodies 423 is provided with the semiconductor device shown in the previous embodiment. This allows for high speed writing and reading of information, long-term storage, and low power consumption. This realizes an electronic book with sufficiently reduced image quality.

[0271] FIG. 14D shows a mobile phone that is configured with two housings, a housing 440 and a housing 441. Furthermore, the housing 440 and the housing 441 slide and unfold as shown in FIG. 14(D). It can be folded up and folded up, making it possible to make it compact and suitable for carrying. The housing 441 also includes a display panel 442, a speaker 443, a microphone 444, and a pointing device. The camera includes a display device 446, a camera lens 447, and an external connection terminal 448. The housing 440 also includes a solar cell 449 for charging the mobile phone, an external memory slot, and The antenna is built into the housing 441. At least one of the housing 40 and the housing 441 is provided with the semiconductor device shown in the above embodiment. Therefore, information can be written and read at high speed, and memory can be retained for a long period of time. A mobile phone with sufficiently reduced power consumption is realized.

[0272] FIG. 14E shows a digital camera, which includes a main body 461, a display unit 467, an eyepiece unit 463, and an operation unit. It is composed of an operation switch 464, a display unit 465, a battery 466, etc. The semiconductor device described in the above embodiment is provided in the inside of 461. It has high speed writing and reading, long-term memory retention, and low power consumption. This leads to the realization of a digital camera.

[0273] FIG. 14F shows a television device 470, which includes a housing 471, a display unit 473, and a stand. The television device 470 is operated by a switch provided in the housing 471. This can be done by a switch or a remote control 480. The semiconductor device described in the above embodiment is mounted on the device 480. It has high speed writing and reading, long-term memory retention, and low power consumption. A television device having such a configuration is realized.

[0274] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This makes it possible to realize electronic devices with reduced power consumption. EXAMPLES

[0275] The number of times that the semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0276] The semiconductor device used in the investigation has a circuit configuration shown in FIG. In addition, an oxide semiconductor is used for the transistor corresponding to the transistor 162. The capacitance element corresponding to the capacitor 164 had a capacitance of 0.33 pF.

[0277] The investigation involves setting the initial memory window width and holding data and writing data a given number of times. This is done by comparing the memory window width after the repetition. To write data, 0 V or 5V to the wire corresponding to the fourth wire, and 0V or 5V to the wire corresponding to the fourth wire. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor Since the transistor corresponding to the transistor 162 is in the off state, the floating gate portion FG The applied potential is maintained. If the potential of the wiring corresponding to the fourth wiring is 5V, Since the transistor corresponding to the transistor 162 is in the on state, the wiring corresponding to the third wiring The line potential is applied to the floating gate portion FG.

[0278] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The shift of the curve (Vcg-Id curve) showing the relationship between the drain current Id of the transistor The different memory states are 0V to the floating gate FG and (hereinafter referred to as the Low state) and 5V is applied to the floating gate FG. The memory window width is a given state (hereinafter referred to as the High state). This can be confirmed by sweeping the potential Vcg in the low and high states.

[0279] Figure 15 shows the memory window width in the initial state and the 1×10 9 After writing The results of the investigation of the memory window width are shown in Fig. 15. In Fig. 15, the horizontal axis is Vcg (V). The vertical axis indicates Id(A). From FIG. 9 Before and after writing, It can be seen that the memory window width has not changed. 9 Before and after writing The fact that the memory window width does not change during this period means that the semiconductor device This indicates that there is no deterioration.

[0280] As described above, the semiconductor device according to one embodiment of the disclosed invention can store and write data many times. The characteristics do not change even after repeated use. In other words, one embodiment of the disclosed invention provides extremely reliable It can be said that a highly efficient semiconductor device can be realized. [Explanation of symbols]

[0281] 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130 electrodes 130a source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 138 Insulating Layer 140 Oxide semiconductor layer 140a Oxide semiconductor layer 140b Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source or drain electrode 142c electrode 142d electrode 144 Insulating Layer 146 Gate Insulation Layer 148a Gate electrode 148b Electrode 150 Protective insulation layer 152 Interlayer insulation layer 160 Transistors 162 Transistor 164 Capacitive element 166 Transistor 190 memory cells 200 Lower layer board 202 Insulating layer 206 Oxide semiconductor layer 206a Oxide semiconductor layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate insulating layer 214 Gate electrode 216 Interlayer Insulation Layer 218 Interlayer Insulation Layer 250 Transistors 300 Lower layer board 302 Insulating layer 304 Oxide semiconductor layer 304a Oxide semiconductor layer 305 Oxide semiconductor layer 306 Oxide semiconductor layer 306a Oxide semiconductor layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate insulation layer 314 Gate electrode 316 Interlayer Insulation Layer 318 Interlayer Insulation Layer 350 Transistors 401 Case 402 Case 403 Display section 404 Keyboard 411 Main unit 412 Stylus 413 Display section 414 Operation button 415 External Interface 420 e-books 421 Case 423 Case 425 Display section 427 Display section 431 Power supply 433 Operation Key 435 Speaker 437 Shaft 440 Case 441 Case 442 Display Panel 443 Speaker 444 Microphone 446 Pointing Device 447 Camera Lenses 448 External connection terminal 449 Solar Cells 450 external memory slot 461 Main unit 463 Eyepiece 464 Operation Switch 465 Display section 466 Battery 467 Display section 470 Television Equipment 471 Case 473 Display section 475 Stand 480 Remote Controlled Device

Claims

1. A first transistor, a second transistor, and a capacitor element, one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive layer having a function as a gate electrode of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a semiconductor layer having a region disposed above the first insulating layer and having a channel formation region of the second transistor; a second conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as one of a source and a drain of the second transistor; a third conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as the other of the source and drain of the second transistor; a fourth conductive layer having a region disposed above the first insulating layer and functioning as one of a source and a drain of the first transistor; a fifth conductive layer having a region disposed above the semiconductor layer and functioning as a gate electrode of the second transistor; a sixth conductive layer having a function as the other electrode of the capacitor element; the semiconductor layer includes an oxide semiconductor, the third conductive layer is electrically connected to the first conductive layer; the third conductive layer functions as one electrode of the capacitor element; Semiconductor device.

2. A first transistor, a second transistor, and a capacitor element, one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive layer having a function as a gate electrode of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a semiconductor layer having a region disposed above the first insulating layer and having a channel formation region of the second transistor; a second conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as one of a source and a drain of the second transistor; a third conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as the other of the source and drain of the second transistor; a fourth conductive layer having a region disposed above the first insulating layer and functioning as one of a source and a drain of the first transistor; a fifth conductive layer having a region disposed above the semiconductor layer and functioning as a gate electrode of the second transistor; a sixth conductive layer having a function as the other electrode of the capacitor; a second insulating layer having a region in contact with an upper surface of the fifth conductive layer and a region in contact with an upper surface of the sixth conductive layer; the semiconductor layer includes an oxide semiconductor, the third conductive layer is electrically connected to the first conductive layer; the third conductive layer functions as one electrode of the capacitor element; Semiconductor device.

3. A first transistor, a second transistor, and a capacitor element, one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; A signal is input to the other electrode of the capacitance element, A semiconductor device in which a constant potential is applied to one of a source and a drain of the first transistor, a first conductive layer having a function as a gate electrode of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a semiconductor layer having a region disposed above the first insulating layer and having a channel formation region of the second transistor; a second conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as one of a source and a drain of the second transistor; a third conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as the other of the source and drain of the second transistor; a fourth conductive layer having a region disposed above the first insulating layer and functioning as one of a source and a drain of the first transistor; a fifth conductive layer having a region disposed above the semiconductor layer and functioning as a gate electrode of the second transistor; a sixth conductive layer having a function as the other electrode of the capacitor element; the semiconductor layer includes an oxide semiconductor, the third conductive layer is electrically connected to the first conductive layer; the third conductive layer functions as one electrode of the capacitor element; Semiconductor device.

4. A first transistor, a second transistor, and a capacitor element, one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; A signal is input to the other electrode of the capacitance element, A semiconductor device in which a constant potential is applied to one of a source and a drain of the first transistor, a first conductive layer having a function as a gate electrode of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a semiconductor layer having a region disposed above the first insulating layer and having a channel formation region of the second transistor; a second conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as one of a source and a drain of the second transistor; a third conductive layer having a region disposed above the first insulating layer, electrically connected to the semiconductor layer, and functioning as the other of the source and drain of the second transistor; a fourth conductive layer having a region disposed above the first insulating layer and functioning as one of a source and a drain of the first transistor; a fifth conductive layer having a region disposed above the semiconductor layer and functioning as a gate electrode of the second transistor; a sixth conductive layer having a function as the other electrode of the capacitor; a second insulating layer having a region in contact with an upper surface of the fifth conductive layer and a region in contact with an upper surface of the sixth conductive layer; the semiconductor layer includes an oxide semiconductor, the third conductive layer is electrically connected to the first conductive layer; the third conductive layer functions as one electrode of the capacitor element; Semiconductor device.

5. In any one of claims 1 to 4, each of the second conductive layer and the third conductive layer includes at least one of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; Semiconductor device.

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