Semiconductor device

Abstract

To provide a transistor comprising an oxide semiconductor which suppresses fluctuation of electric characteristics and improves reliability.SOLUTION: A transistor 100A comprises a first gate electrode 106, a first insulator film 104 on the first gate electrode, an oxide semiconductor film 108 on the first insulator film, a second insulator film 110 on the oxide semiconductor film, a second gate electrode 112 on the second insulator film, and a third insulator film 116 on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region 108i which is overlapped with the second gate electrode, a source region 108s in contact with the third insulator film, and a drain region 108d in contact with the third insulator film. The first gate electrode and the second gate electrode are electrically connected and when electron field-effect mobility in a saturation range of the transistor is measured, a difference between a minimum value of the electron field-effect mobility and a maximum value of the electron field-effect mobility is within 15 cm2 / Vs.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] For example, a technique for fabricating thin-film oxide transistors with a self-aligned top-gate structure. has been disclosed (see Patent Document 1).

[0006] In addition, a plurality of oxide semiconductor layers are stacked, and a channel and a gate electrode are formed in the plurality of oxide semiconductor layers. The oxide semiconductor layer contains indium and gallium, and the ratio of indium to gallium is By increasing the ratio of A semiconductor device in which the resistance to vibration is improved has been disclosed (see Patent Document 2). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2009-278115 A [Patent Document 2] JP 2014-7399 A Summary of the Invention [Problem to be solved by the invention]

[0008] The structure of a transistor including an oxide semiconductor film can be, for example, a bottom gate structure or A top-gate structure or the like can be given. When applied, bottom-gate transistors are preferred over top-gate transistors. is more commonly used because the manufacturing process is relatively simple and the manufacturing costs are kept low. stomach.

[0009] However, as the screen size of a display device increases or the image quality of a display device increases (for example, 4k x 2k (horizontal pixels = 3840 pixels, vertical pixels = 2160 pixels) or 8 k×4k (horizontal pixel count = 7680 pixels, vertical pixel count = 4320 pixels) As the development of high-definition display devices progresses, the gate electrode and the There is a parasitic capacitance between the source electrode and the drain electrode, which causes signal delays, etc. In order to solve this problem, the oxide semiconductor film The top-gate transistor has stable semiconductor characteristics and high reliability. It is desirable to develop a structure having the above structure.

[0010] In view of the above problems, one embodiment of the present invention is to provide a transistor including an oxide semiconductor. One of the objectives is to suppress fluctuations in thermal characteristics and improve reliability. One embodiment of the present invention is to provide a top-gate transistor including an oxide semiconductor. Another object of one embodiment of the present invention is to provide a semiconductor device having an oxide semiconductor and having a large on-state current. Another object of the present invention is to provide a transistor having a large capacitance. One object of the present invention is to provide a transistor including a semiconductor material and having a low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. do.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a gate electrode, a first insulating film on the first gate electrode, and an oxide semiconductor on the first insulating film. a second insulating film on the oxide semiconductor film; a second gate electrode on the second insulating film; a third insulating film on the second gate electrode, the oxide semiconductor film being A channel region overlapping with the gate electrode of the second insulating film, a source region contacting the third insulating film, and a second insulating film and a drain region in contact with the insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. When the field-effect mobility of the transistor in the saturation region was measured, The difference between the minimum and maximum field effect mobility is 15 cm 2 / Vs.

[0013] In the above embodiment, the field effect mobility is measured by applying a voltage to the first gate electrode and the second gate electrode. The voltage applied to the drain region is set to a range of 3 V to 10 V. It is preferable to measure the voltage in the range of 5 V or more and 20 V or less.

[0014] In the above embodiment, the oxide semiconductor film contains In and M (M is Al, Ga, Y, or It is preferable that the alloy contains Sn) and Zn.

[0015] In the above embodiment, the atomic ratio of In, M, and Zn is In:M:Zn=4:2. : Near 3, when In is 4, M is 1.5 or more and 2.5 or less, and Zn is 2 or more It is preferable that the number is 4 or less.

[0016] Another embodiment of the present invention is a semiconductor device and a display device according to any one of the above embodiments. Another embodiment of the present invention is a display device including the display device and a touch sensor. Another aspect of the present invention is a display module having any one of the above aspects. The semiconductor device according to any one of claims 1 to 5, the display device, or the display module, and an operation key or and a battery. Effect of the Invention

[0017] According to one embodiment of the present invention, a transistor including an oxide semiconductor can be prevented from fluctuating in electrical characteristics. Furthermore, according to one embodiment of the present invention, It is possible to provide a top-gate transistor having an oxide semiconductor. According to one embodiment of the present invention, a transistor including an oxide semiconductor and having high on-state current is provided. According to one embodiment of the present invention, the off-state current of a semiconductor device having an oxide semiconductor can be reduced. According to one embodiment of the present invention, a transistor with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. A conductor device can be provided.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0019] [Figure 1] FIG. 13 is a graph showing Id-Vg characteristics of a transistor. [Diagram 2] 13A and 13B are graphs showing Id-Vg and Id-Vd characteristics of transistors. [Diagram 3] FIG. 1 is a diagram illustrating the Id-Vg characteristics and mobility curves (linear and saturation) calculated based on GCA. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 5] 1 is a schematic diagram illustrating the concept of an effective channel length of a transistor. [Figure 6] FIG. 2 is a schematic diagram illustrating donor density. [Figure 7] FIG. 4 is a diagram illustrating Id-Vg characteristics. [Figure 8] FIG. 4 is a diagram illustrating Id-Vg characteristics. [Figure 9] 13A and 13B are diagrams for explaining calculation results of interface state density. [Figure 10] FIG. 4 is a diagram illustrating Id-Vg characteristics. [Figure 11] FIG. 4 is a diagram for explaining the shape of a mobility curve. [Figure 12] FIG. 13 is a diagram for explaining calculation results of a mobility curve. [Figure 13] Diagram illustrating the sDOS results. [Figure 14] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 15] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 16] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 17] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 18] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 19] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 20] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 21] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 22] FIG. 2 is a diagram for explaining a band structure. [Diagram 23] 1A and 1B are diagrams illustrating the range of atomic ratios of oxide semiconductors. [Figure 24] A diagram explaining the InMZnO4 crystal. [Diagram 25] 1A and 1B are diagrams illustrating energy bands of a transistor in which an oxide semiconductor is used for a channel region. [Figure 26] 1A and 1B illustrate a cross-sectional TEM image and a cross-sectional HR-TEM image of an oxide semiconductor film. [Figure 27] 1A and 1B illustrate a cross-sectional TEM image and a cross-sectional HR-TEM image of an oxide semiconductor film. [Figure 28] 1A and 1B illustrate a cross-sectional TEM image and a cross-sectional HR-TEM image of an oxide semiconductor film. [Figure 29] 13A to 13C show XRD measurement results and electron beam diffraction patterns of an oxide semiconductor film. [Diagram 30] 13A to 13C show XRD measurement results and electron beam diffraction patterns of an oxide semiconductor film. [Diagram 31] 13A to 13C show XRD measurement results and electron beam diffraction patterns of an oxide semiconductor film. [Diagram 32] FIG. 2 is a diagram for explaining an electron beam diffraction pattern. [Diagram 33] FIG. 2 is a diagram for explaining a line profile of an electron beam diffraction pattern. [Diagram 34] 1 is a conceptual diagram illustrating a line profile of an electron beam diffraction pattern, a relative brightness R of the line profile, and a half-width of the line profile. [Diagram 35] 3A to 3C are diagrams illustrating electron beam diffraction patterns and line profiles. [Diagram 36] 13A and 13B are graphs showing relative luminance estimated from electron diffraction patterns of oxide semiconductor films. [Figure 37] 1A to 1C show cross-sectional TEM images of an oxide semiconductor film and cross-sectional TEM images after image analysis. [Figure 38] 13A to 13C show SIMS measurement results of an oxide semiconductor film. [Figure 39] FIG. 1 is a top view illustrating one embodiment of a display device. [Diagram 40] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 41] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 42] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 43] 1A to 1C are cross-sectional views illustrating a method for forming an EL layer. [Diagram 44] FIG. 2 is a conceptual diagram illustrating a droplet ejection device. [Diagram 45] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 46] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 47] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 48] 1A and 1B are cross-sectional views of a semiconductor device. [Figure 49] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 50] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 51] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 52] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 53] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 54] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 55] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 56] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 57] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 58] FIG. 2 is a diagram illustrating a display module. [Figure 59] 1A to 1C are diagrams illustrating electronic devices. [Figure 60] 1A to 1C are diagrams illustrating electronic devices. [Figure 61] FIG. 1 is a perspective view illustrating a display device. [Figure 62] FIG. 13 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 63]FIG. 13 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 64] FIG. 13 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 65] FIG. 13 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 66] FIG. 13 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 67] FIG. 13 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 68] 1A to 1C are diagrams illustrating threshold voltages of transistors in an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0021] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0022] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0023] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0024] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A channel region is provided between the source and drain, and a current flows between the source and drain through the channel region. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to the area in which the fluid flows.

[0025] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0026] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0027] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0028] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0029] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to a state in which the voltage Vgs between the n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt This may refer to the drain current when it is lower than h.

[0030] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there exists a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off-state at a given Vgs. , an off-state at Vgs within a given range or a sufficiently reduced off-current is obtained. In some cases, it may refer to the off-state current at Vgs.

[0031] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs -0.5 V is 1×10 -19 A and Vg The drain current at s = -0.8 V is 1 × 10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is said to be A or lower. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0032] In this specification, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per watt. Also, for a given channel width (for example, 1 μm), In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0033] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the operating temperature is room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of a semiconductor device including the transistor may be guaranteed. The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, the off-state current at any one of temperatures from 5° C. to 35° C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or The temperature at which the semiconductor device containing the transistor is used (for example, any one of 5°C to 35°C) (temperature), there exists a value of Vgs at which the off-state current of the transistor is equal to or less than I. There are cases where it is pointed out.

[0034] The off-state current of a transistor may depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, and In some cases, it indicates the off-state current at 20 V. In other cases, it indicates the off-state current at 20 V. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices including the transistor The term may also refer to the off-state current at Vds used in the transistor off-state. The current is equal to or less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is used, or Vds used in semiconductor devices, etc., where the off-state current of the transistor is I or less This may refer to the existence of a gs value.

[0035] In the above description of the off-state current, the drain may be read as the source. The current may also refer to the current through the source when the transistor is in the off state.

[0036] In this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0037] In this specification, the threshold voltage of a transistor is the threshold voltage of a transistor. This refers to the gate voltage (Vg) when a gate is formed. Specifically, it refers to the threshold voltage of a transistor. Voltage is plotted on the horizontal axis as gate voltage (Vg) and on the vertical axis as the square root of drain current (Id). The line obtained by extrapolating the tangent line with the maximum slope in the simulated curve (Vg-√Id characteristics) is , the gate voltage (Vg Alternatively, the threshold voltage of a transistor can be expressed as the channel length L and the The channel width is W, and the value of Id[A]×L[μm] / W[μm] is 1×10 -9 [A] Sometimes it refers to the gate voltage (Vg) applied to the device.

[0038] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is low enough, the material may have the properties of an insulator. The boundary between "insulators" and "insulators" is unclear, and it may not be possible to strictly distinguish them. In some cases, the term "semiconductor" in the above can be replaced with "insulator." In some cases, the term "insulator" in the specification can be replaced with "semiconductor." In some cases, the term "insulator" in this specification can be rephrased as "semi-insulator." .

[0039] In addition, even when the term "semiconductor" is used in this specification, for example, If the electrical conductivity is high enough, it may have the properties of a "conductor". The boundary between the term "conductor" and the term "electrical conductor" is unclear, and it may not be possible to strictly distinguish between them. In some cases, the term "semiconductor" in the above can be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0040] In this specification, the term "impurities in a semiconductor" refers to anything other than the main component that constitutes the semiconductor film. For example, an element with a concentration of less than 0.1 atomic percent is an impurity. This causes the formation of DOS (Density of States) in the semiconductor and the In some cases, the rear mobility and crystallinity of the semiconductor may decrease. In the case of an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 There are elements, group 2 elements, group 14 elements, group 15 elements, transition metals other than the main components, etc. Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, In the case of oxide semiconductors, oxygen vacancies can occur due to the inclusion of impurities such as hydrogen. In addition, when the semiconductor contains silicon, the properties of the semiconductor may be changed. Examples of impurities include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0041] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal An oxide may be called an oxide semiconductor. In other words, the transistor can be a transistor including a metal oxide or an oxide semiconductor.

[0042] In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0043] In the present specification, CAAC (c-axis aligned crystal l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Shows an example.

[0044] An example of the crystal structure of an oxide semiconductor or a metal oxide will be described below. In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) An oxide semiconductor film formed by a sputtering method will be described as an example. The substrate temperature was set to 100°C or higher and 130°C or lower, and the sputtering method was used. The oxide semiconductor formed by this method is called sIGZO, and the substrate temperature is kept at room temperature using the above target. The oxide semiconductor formed by sputtering at RT is called tIGZO. For example, sIGZO is either nc (nano crystal) or CAAC. In addition, tIGZO has an nc crystal structure. In addition, room temperature (RT) here includes the temperature when the substrate is not intentionally heated. .

[0045] In the present specification and the like, CAC-OS or CAC-metal oxide means Some materials have the function of a conductor and some materials have the function of a dielectric (or insulator). The material as a whole functions as a semiconductor. When etal oxide is used in the active layer of a transistor, the conductor acts as a carrier. The dielectric has the function of not allowing the electrons (or holes) that become carriers to flow. The function as a conductor and the function as a dielectric are complementarily acted. By doing so, the switching function (On / Off function) can be set by CAC-OS or It can be added to CAC-metal oxide. By separating the functions of each metal oxide, can be increased to the maximum.

[0046] In the present specification and the like, CAC-OS or CAC-metal oxide is The conductive region has the above-mentioned function of the conductor and the dielectric region. The conductive region has the above-mentioned function of the dielectric. The regions may be separated at the nanoparticle level. The conductive regions may be unevenly distributed in the material. They may be observed connected in a dot-like pattern.

[0047] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0048] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The dielectric regions are each 0.5 nm to 10 nm thick, preferably 0.5 nm to 3 nm thick. They may be dispersed in the material at sizes of less than one millimeter.

[0049] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. Explanations will be given.

[0050] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a gate electrode, a first insulating film on the first gate electrode, and an oxide semiconductor on the first insulating film. a second insulating film on the oxide semiconductor film; a second gate electrode on the second insulating film; a third insulating film on the second gate electrode, the oxide semiconductor film being A channel region overlapping with the gate electrode of the second insulating film, a source region contacting the third insulating film, and a second insulating film and a drain region in contact with the insulating film. The first gate electrode and the second gate electrode are electrically connected to each other. are connected to the network.

[0051] In addition, the minimum value of the field effect mobility and the field effect mobility in the saturation region of the transistor are The difference from the maximum movement is 15 cm2 / Vs.

[0052] In other words, the semiconductor device according to one embodiment of the present invention has an oxide semiconductor layer in a channel region. A transistor having a dielectric film, the field effect transition in the saturation region of the transistor being Such a semiconductor device is used for the display of an organic electroluminescence (EL) display, for example. By using it in elemental transistors, high reliability can be imparted.

[0053] <1-1. Transistor characteristics> First, general characteristics of a transistor will be described with reference to FIGS.

[0054] [Transistor Id-Vg characteristics] First, let us explain the drain current-gate voltage characteristics (Id-Vg characteristics) of a transistor. FIG. 2A is a graph illustrating an example of the Id-Vg characteristics of a transistor. In 2(A), for ease of understanding, the active layer of the transistor is made of polycrystalline silicon. In FIG. 2(A), the vertical axis represents Id and the horizontal axis represents Vg. Each represents

[0055] As shown in FIG. 2(A), the Id-Vg characteristics can be roughly divided into three regions. The first region is the OFF region, and the second region is the subthreshold region. The third region is the ON region. The subthreshold region and the on region are called the on-state region and the on-state region, respectively. The boundary gate voltage is called the threshold voltage (Vth).

[0056] The characteristics of a transistor are the drain current in the off region (also called the off current or Ioff). It is desirable to have a low drain current (also called the on-state current or Ion) and a high drain current (also called the on-state current or Ion) in the on-state. It is preferable that the on-state current of a transistor is measured using the field effect mobility. The details of field effect mobility will be described later.

[0057] In order to operate the transistor at a low voltage, the I It is desirable for the slope of the d-Vg characteristic to be steep. As an index showing the magnitude of change in gender, SS (subthreshold swing) It is also called the S value. The S value is expressed by the following formula (1).

[0058]

number

[0059] The S value is the gate capacitance required to change the drain current by one order of magnitude in the subthreshold region. The smaller the S value, the smaller the on-off switching operation. can be performed sharply.

[0060] [Transistor Id-Vd characteristics] Next, we will explain the drain current-drain voltage characteristics (Id-Vd characteristics) of a transistor. FIG. 2B is a graph showing an example of the Id-Vd characteristics of a transistor. In FIG. 2B, the vertical axis represents Id and the horizontal axis represents Vd.

[0061] As shown in FIG. 2B, the ON region is further divided into two regions. The first region The first region is the linear region, and the second region is the saturation region. are respectively referred to as the linear region and the saturation region. In the linear region, the drain current increases parabolically as the drain voltage rises. On the other hand, in the saturation region, the drain current does not change significantly even when the drain voltage changes . Note that, analogous to a vacuum tube, the linear region may sometimes be referred to as the triode region, and the saturation region may sometimes be referred to as the pentode region.

[0062] Also, the linear region may sometimes refer to the state where Vg is larger than Vd (Vd < Vg) . Also, the saturation region may sometimes refer to the state where Vd is larger than Vg (Vg < Vd) . However, in reality, it is necessary to consider the threshold voltage of the transistor. Therefore, the state where the value obtained by subtracting the threshold voltage of the transistor from Vg is larger than Vd (Vd < Vg - Vth) may be regarded as the linear region. Similarly, the state where the value obtained by subtracting the threshold voltage of the transistor from Vg is smaller than Vd (Vg - Vth < Vd) may be regarded as the saturation region . .

[0063] In the Id-Vd characteristics of a transistor, the characteristic where the current in the saturation region is constant may be expressed as "good saturation". The goodness of the saturation of a transistor is particularly important in applications to organic EL displays. For example, by using a transistor with good saturation in the transistor of a pixel of an organic EL display, it is possible to suppress the change in the brightness of the pixel even when the drain voltage changes .

[0064] [Analytical Model of Drain Current] Next, the analytical model of the drain current will be described. As an analytical model of the drain current , an analytical expression of the drain current based on the Gradual channel approximation (GCA) is known According to the GCA, the drain current of a transistor is expressed by the following equation (2): do.

[0065]

number

[0066] In equation (2), the upper part is the drain current equation in the linear region, and the lower part is the drain current equation in the saturation region. This is the equation for the drain current in

[0067] [Field effect mobility] Next, the field effect mobility will be described. As mentioned above, the on-region of a transistor is divided into a linear region and a saturation region. Based on the characteristics of each region, the drain current is calculated based on the analytical formula based on GCA. Based on this, the field effect mobility of the transistor can be calculated. are the linear mobility and the saturation mobility, respectively. The linear mobility is expressed by the following equation (3): The saturation mobility is expressed by the following equation (4).

[0068]

number

[0069]

number

[0070] In this specification, the curve calculated from the formula (3) and the formula (4) is called a mobility curve. FIG. 3 shows the mobility curve calculated from the analytical expression for the drain current based on the GCA. In addition, FIG. 3 shows the transition of the linear mobility and the saturation mobility with respect to the Id-Vg characteristics of the transistor. The kinetic curves are shown superimposed on each other.

[0071] In Fig. 3, the Id-Vg characteristics are calculated from the analytical formula for the drain current based on GCA. The shape of the mobility curve provides clues to understanding the internal structure of a transistor. .

[0072] For example, let us look at the shape of the saturation mobility curve shown in Figure 3. As the gate voltage increases, the electrons (electrons or holes) are accelerated by the electric field and gain energy. Therefore, the carriers gain a certain amount of energy due to the electric field, and the saturation mobility increases. However, the carriers are not infinitely accelerated by the electric field, but are thermally vibrating interstitial atoms. Since it loses energy by colliding with electrons, electron ions, or ionized impurity atoms, The saturation mobility gradually decreases.

[0073] <1-2. Fabrication of transistors for characteristic evaluation> Next, a structure of a transistor of one embodiment of the present invention will be described. A transistor was fabricated, and the electrical characteristics of the transistor were evaluated. The results are described below.

[0074] [Transistor configuration example 1] FIG. 4A is a top view of a transistor 100A, and FIG. 4B is a cross-sectional view of a portion of FIG. 4A. 4(C) is a cross-sectional view taken along dashed line X1-X2, and FIG. 4(C) is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 4(A). In addition, in FIG. 4(A), components such as an insulating film 110 are omitted for clarity. Note that the top view of the transistor is shown in FIG. As in (A), some of the components may be omitted. The X2 direction is called the channel length (L) direction, and the dashed line Y1-Y2 direction is called the channel width (W) direction. It may be referred to as.

[0075] The transistor 100A shown in FIGS. 4A, 4B, and 4C includes a conductive film 106 on a substrate 102. the insulating film 104 on the conductive film 106; the oxide semiconductor film 108 on the insulating film 104; An insulating film 110 on the semiconductor film 108, a conductive film 112 on the insulating film 110, and an insulating film 104 , the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112. The semiconductor film 108 has a channel region 108i overlapping with the conductive film 112 and a contact region 116. The source region 108s contacts the insulating film 116, and the drain region 108d contacts the insulating film 116.

[0076] The insulating film 116 contains nitrogen or hydrogen. s and the drain region 108d, the nitrogen or hydrogen in the insulating film 116 is converted into The source region 108s and the drain region 108d are doped with Zn. The carrier density of the rain region 108d is increased by adding nitrogen or hydrogen.

[0077] The transistor 100A also includes an insulating film 118 on the insulating film 116, and an insulating film 116, A conductor electrically connected to the source region 108s is provided through an opening 141a in the semiconductor substrate 18. The drain electrode 120a is connected to the drain electrode 141 via the opening 141b provided in the insulating films 116 and 118. and a conductive film 120b electrically connected to the region 108d. An insulating film 122 may be provided over the film 118, the conductive film 120a, and the conductive film 120b. Although the insulating film 122 is provided in the configuration illustrated in FIGS. 4B and 4C, the present invention is not limited to this. However, the insulating film 122 may not be provided.

[0078] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. The insulating film 116 is a third insulating film, the insulating film 118 is a fourth insulating film, and the insulating film 122 is a fourth insulating film. The insulating film 104 is also called the first gate insulating film. The insulating film 110 functions as a second gate insulating film. The insulating films 116 and 118 function as protective insulating films, and the insulating film 122 serves as a planarizing film. It functions as an insulating film.

[0079] The insulating film 110 has an excess oxygen region. As a result, excess oxygen is supplied to the channel region 108i of the oxide semiconductor film 108. Therefore, oxygen vacancies that may be formed in the channel region 108i can be compensated for by the excess oxygen. Since the semiconductor device can be filled with the conductive material, a highly reliable semiconductor device can be provided.

[0080] In order to supply excess oxygen to the oxide semiconductor film 108, Excess oxygen may be supplied to the insulating film 104 formed below the insulating film 108. The excess oxygen contained in the oxide semiconductor film 108 is The source region 108s and the drain region 108d may also be supplied with When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance It may be higher.

[0081] On the other hand, in the structure in which the insulating film 110 formed above the oxide semiconductor film 108 contains excess oxygen, By forming the semiconductor layer 108 in this manner, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, the channel region 108i, the source region 108s, and the drain region 10 After supplying excess oxygen to the source region 108s and the drain region 108d, By selectively increasing the rear density, the resistance of the source region 108s and the drain region 108d is reduced. Therefore, it is possible to suppress the resistance from increasing.

[0082] The source region 108s and the drain region 108d of the oxide semiconductor film 108 are Each of them preferably has an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative elements that form the oxygen vacancies or that bond with the oxygen vacancies include Hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gases, etc. Representative examples of rare gas elements include helium, neon, argon, krypton, and The insulating film 116 contains one or more of the above elements that form oxygen vacancies. When the insulating film 116 is filled with fluorine, the fluorine diffuses from the insulating film 116 to the source region 108s and the drain region 108d. And / or, the element that forms the oxygen vacancy is added to the source region by an impurity addition process. 108s, and the drain region 108d.

[0083] When an impurity element is added to an oxide semiconductor film, a bond between a metal element and oxygen in the oxide semiconductor film is formed. The bond is broken, and oxygen vacancies are formed. Alternatively, an impurity element is added to the oxide semiconductor film. Then, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The carrier density increases and the conductivity becomes higher.

[0084] The conductive film 106 functions as a first gate electrode, and the conductive film 112 functions as a second gate electrode. The conductive film 120a functions as a gate electrode of the The conductive film 120b functions as a drain electrode.

[0085] As shown in FIG. 4C, the insulating films 104 and 110 are provided with an opening 143. In addition, the conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the conductive film 106 and the conductive film 112 are applied with the same potential. Alternatively, the conductive film 106 and the conductive film 112 may be applied with different potentials without providing the third potential. Alternatively, the conductive film 106 may be used as a light-shielding film without providing the opening 143. By forming 106 from a light-shielding material, the channel region 108i is prevented from being irradiated from below. This can suppress the light.

[0086] As shown in FIGS. 4B and 4C, the oxide semiconductor film 108 serves as a first gate electrode. The conductive film 106 functions as a second gate electrode, and the conductive film 112 functions as a second gate electrode. and is sandwiched between two conductive films that function as gate electrodes.

[0087] The length of the conductive film 112 in the channel width direction is longer than that of the oxide semiconductor film 108. The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 110 in the channel width direction. The conductive film 112 and the conductive film 106 are sandwiched between the insulating film 112 and are covered with the conductive film 112. 104 and the insulating film 110 through an opening 143. One of the side surfaces of the conductive film 108 in the channel width direction is connected to a conductive film 112 with an insulating film 110 sandwiched therebetween. and is opposed to.

[0088] In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive The film 112 is connected to the insulating film 104 and the insulating film 110 at an opening 143 provided therein. At the same time, the oxide semiconductor film 108 is surrounded with the insulating film 104 and the insulating film 110 interposed therebetween. This is a configuration that includes:

[0089] With such a structure, the oxide semiconductor film 10 included in the transistor 100A 8 is a conductive film 106 functioning as a first gate electrode and a conductive film 108 functioning as a second gate electrode. The transistor 100A can be electrically surrounded by the electric field of the conductive film 112. Thus, a channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the oxide semiconductor film 108 is called Surro. This can be called an unded channel (S-channel) structure.

[0090] Since the transistor 100A has an S-channel structure, the conductive film 106 or The conductive film 112 effectively applies an electric field for inducing a channel to the oxide semiconductor film 108. This improves the current drive capability of the transistor 100A and provides a high on-state current. It is also possible to obtain high on-current characteristics. The transistor 100A can be miniaturized. The semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112. This increases the mechanical strength of the transistor 100A.

[0091] Note that an opening in the oxide semiconductor film 108 in the channel width direction of the transistor 100A An opening different from opening 143 may be formed on the side where portion 143 is not formed.

[0092] [Making a transistor] Next, a transistor corresponding to the transistor 100A described above is fabricated. In this embodiment, the following samples A1 to A3 were used to evaluate the electrical characteristics of the transistors. was prepared.

[0093] Each of the samples A1 to A3 has a channel length L of 2 μm and a channel width W of 3 μm. The samples A1 and A2 are samples with 100-μm transistors. Sample A3 is a sample in which a transistor of one embodiment of the present invention is formed. Note that the oxide semiconductor films of Samples A1 to A3 were formed under the same conditions. The other steps were the same as in the previous embodiment.

[0094] [Method of preparing samples A1 to A3] First, a titanium film having a thickness of 10 nm and a copper film having a thickness of 100 nm were sputtered on a glass substrate. The conductive film was then processed by photolithography. Ta.

[0095] Next, four insulating layers were formed on the substrate and the conductive film. The insulating film was formed in a vacuum using a phase-effect chemical vapor deposition (PECVD) system. Silicon nitride film with a thickness of 50 nm, silicon nitride film with a thickness of 300 nm, silicon nitride film with a thickness of 50 nm A 50 nm thick silicon oxynitride film and a 50 nm thick silicon oxide nitride film were used.

[0096] Next, an oxide semiconductor film is formed over the insulating film and processed into an island shape. The oxide semiconductor film 108 was formed by a 40-nm-thick oxide semiconductor Note that in Samples A1 to A3, the oxide semiconductor films were formed under the following deposition conditions. different.

[0097] The oxide semiconductor film of the sample A1 was grown by annealing the substrate at a temperature of 170° C. with an argon gas flow rate of 140 sccm. Gon gas and oxygen gas with a flow rate of 60 sccm were introduced into the chamber of the sputtering device. The pressure was set to 0.6 Pa, and a metal oxide ternary containing indium, gallium, and zinc was used. The get (In:Ga:Zn=4:2:4.1 [atomic ratio]) was supplied with 2.5 kW of AC power. The ratio of oxygen in the entire deposition gas is called the "oxygen flow rate ratio." The oxygen flow rate during deposition of the oxide semiconductor film of Sample A1 is 30%. It is.

[0098] The oxide semiconductor film of the sample A2 was grown using an argon gas with a flow rate of 180 sccm at a substrate temperature of 130° C. Gon gas and oxygen gas at a flow rate of 20 sccm were introduced into the chamber of the sputtering device. The pressure was set to 0.6 Pa, and a metal oxide ternary containing indium, gallium, and zinc was used. The get (In:Ga:Zn=4:2:4.1 [atomic ratio]) was supplied with 2.5 kW of AC power. The oxide semiconductor film of Sample A2 was formed by applying an oxygen flow rate of 1000 V to the oxide semiconductor film. is 10%.

[0099] The oxide semiconductor film of sample A3 was grown at a substrate temperature of room temperature (RT) and a flow rate of 180 scc. Argon gas at a flow rate of 20 sccm and oxygen gas at a flow rate of 20 sccm were placed in the chamber of the sputtering device. The pressure was set to 0.6 Pa, and a metal oxide having indium, gallium, and zinc was introduced into the The ion beam was applied to a 2.5kW ion source for a Zn-In oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxide semiconductor film of Sample A3 was formed by applying an electric current. The elemental flow ratio is 10%.

[0100] Next, an insulating film was formed over the insulating film and the oxide semiconductor layer. A 0 nm silicon oxynitride film was formed using a PECVD apparatus.

[0101] Next, a heat treatment was performed. The heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen for 3 h. The heat treatment was carried out at 50°C for 1 hour.

[0102] Next, openings were formed in desired areas of the insulating film. The etching method was used.

[0103] Next, a 100-nm-thick oxide semiconductor film is formed on the insulating film so as to cover the opening. The oxide semiconductor film was processed into an island shape to form a conductive film. Then, the insulating film in contact with the lower side of the conductive film was processed to form an insulating film.

[0104] The conductive film is a 10-nm-thick oxide semiconductor film, a 50-nm-thick titanium nitride film, and A copper film having a thickness of 100 nm was then formed. The plate temperature was set at 170°C, and oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering equipment. A gold alloy containing indium, gallium and zinc was introduced into the bar at a pressure of 0.6 Pa. Metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) at 2.5kW The titanium nitride film and the copper film were formed by applying an AC power of 1000 V. The film was formed using a film forming apparatus.

[0105] Next, plasma treatment was performed from above the oxide semiconductor film, the insulating film, and the conductive film. For the PECVD process, a substrate temperature was set at 220°C, and argon gas and nitrogen gas were used. The reaction was carried out in a mixed gas atmosphere.

[0106] Next, an insulating film was formed over the oxide semiconductor film, the insulating film, and the conductive film. A 100 nm thick silicon nitride film and a 300 nm thick silicon oxynitride film were deposited by PECV. The film was laminated using the D device.

[0107] Next, a mask is formed on the formed insulating film, and an opening is formed in the insulating film using the mask. did.

[0108] Next, a conductive film is formed to fill the opening, and the conductive film is processed into an island shape. A conductive film having a thickness of 10 nm was formed as a source electrode and a drain electrode. A titanium film with a thickness of 1.0 nm and a copper film with a thickness of 100 nm were formed using a sputtering device. Successful.

[0109] Next, an insulating film was formed on the insulating film and the conductive film. An acrylic photosensitive resin was used.

[0110] In this manner, Samples A1 to A3 were prepared.

[0111] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistors of Samples A1 to A3 fabricated as described above were measured. The Id-Vg characteristics of the transistor were measured under the following conditions: The voltage applied to the conductive film that functions as a gate voltage (Vg) and the second gate The voltage applied to the conductive film that functions as an electrode (hereinafter referred to as the back gate voltage (Vbg)) ) was applied from -10 V to +10 V in steps of 0.25 V. The voltage applied to the conductive film that functions as a source voltage (Vs) is set to 0 V (co mm), and the voltage applied to the conductive film functioning as the drain electrode (hereinafter referred to as the drain voltage ( Vd) was set to 0.1 V and 20 V.

[0112] Figure 1 (A), (B), and (C) show the Id-Vg characteristics of samples A1, A2, and A3. In FIG. 1(A), (B), and (C), the first vertical axis represents Id(A), the second vertical axis represents Id(B), and the third vertical axis represents Id(C). 2 The vertical axis is the field effect mobility (μFE(cm 2 / Vs)) and the horizontal axis is Vg (V), The field effect mobility is a value measured at Vd of 20 V.

[0113] As shown in Figure 1(A), (B), and (C), the oxide semiconductor film can be grown by changing the deposition conditions. Different trends are observed in the Id-Vg characteristics of the transistors. In particular, the field effect of the transistor A difference is observed in the shape of the mobility curve.

[0114] From the shapes of the mobility curves of Samples A1 to A3 shown in FIG. The minimum, maximum, and maximum minus minimum values ​​of the field-effect mobility in the saturation region of the transistor are The results were calculated by dividing the total voltage by the voltage Vg. This range is often used for displays and other applications. This is the gate voltage that can be applied.

[0115] For sample A1, the minimum field effect mobility in the saturation region of the transistor is 9. 8cm 2 / Vs, with a maximum value of 28.3 cm 2 / Vs. That is, the sample A1 The minimum and maximum field-effect mobility in the saturation region of a transistor The difference is 18.5cm. 2 / Vs. In addition, the saturation voltage of the transistor in sample A2 was The minimum field effect mobility in this region is 23.3 cm 2 / Vs, with a maximum value of 51. 1cm 2 / Vs. That is, the electric field in the saturation region of the transistor of sample A2 The difference between the minimum and maximum field effect mobility is 27.8 cm 2 / Vs. In addition, in the sample A3, the minimum value of the field effect mobility in the saturation region of the transistor is 55.8cm 2 / Vs, with a maximum value of 67.0 cm 2 / Vs. The minimum value of the field effect mobility and the field effect mobility in the saturation region of the transistor of material A3 The difference between the maximum value is 11.2 cm. 2 / Vs.

[0116] In other words, the minimum value of the field effect mobility in the saturation region of the transistor in the sample A1 is The field effect mobility of the sample A2 is about 65.3% lower than the maximum value of the field effect mobility. The minimum value of the field effect mobility in the saturation region of the Sample A3 also exhibits a field effect mobility in the saturation region of the transistor of 54.4% lower than that of the other samples. The minimum value is about 16.7% lower than the maximum value of the field effect mobility. The sample A3 in which the transistor of one embodiment was formed had a field effect in the saturation region of the transistor. The minimum value of the field effect mobility is preferably 30% or less, more preferably 30% or less, of the maximum value of the field effect mobility. Preferably, the characteristic is 20% or less.

[0117] In this manner, Sample A3 in which the transistor of one embodiment of the present invention was formed had a The difference between the minimum and maximum field-effect mobility in the saturated region is 15 cm 2 / Vs, which is an extremely low characteristic. The transistor has high field-effect mobility in the region of 5 V above V. By using transistors as pixel transistors in organic electroluminescence displays, for example, This provides current driving capability and high reliability.

[0118] <1-3. Evaluation of the shape of the mobility curve by device simulation> Next, let us consider the shape of the field-effect mobility curve of the transistor shown in Figure 1(A)(B)(C). Since differences in the shape of the mobility curve were confirmed, the shape of the mobility curve was evaluated by device simulation. Ta.

[0119] In the device simulation, the factors that determine the shape of the mobility curve are: 1. 1. Temperature dependence of mobility, 2. Donor density distribution in the channel region, 3. Shallow Three factors of defect state density are assumed.

[0120] [1. Temperature dependence of mobility] In a transistor using an oxide semiconductor film, the field-effect mobility increases rapidly due to self-heating. The electron mobility (μ n The temperature dependence of ) is expressed by the following formula (5): will be done.

[0121]

number

[0122] In formula (5), μ n 300 is the electron mobility of the oxide semiconductor film at room temperature, and T L is a lattice As shown in formula (5), the transistor using the oxide semiconductor film The field-effect mobility of a GaN-based semiconductor increases approximately in proportion to the temperature T to the power of 1.5.

[0123] [2. Donor density distribution in the channel region] The transistors of Samples A1 to A3 fabricated above have different oxide semiconductor film formation conditions. Therefore, the donor density distribution in the channel region is different. The transistors have different effective channel lengths.

[0124] Here, the effective channel lengths of the transistors of Samples A1 to A3 are shown in FIG. He explains.

[0125] FIG. 5 is a schematic diagram illustrating the concept of the effective channel length of a transistor.

[0126] In FIG. 5, GE represents the gate electrode, GI represents the gate insulating film, and OS represents the oxide semiconductor film. In addition, an n-type region is formed in the oxide semiconductor film. The effective channel length of the transistor (L eff ) is expressed by the following equation (6).

[0127]

number

[0128] In formula (6), L g represents the gate length, and ΔL represents the reduction in channel length. .

[0129] The effective channel length of a transistor is, for example, This can be obtained from a sion Line Model analysis.

[0130] In the following description, the effective channel length is calculated based on the above-mentioned effective channel length. We assume a model in which the donor density gradually decreases over the region. The donor density in samples A1 to A3 decreases according to a Gaussian distribution. 6(A), (B), and (C) are schematic diagrams for explaining the above. Note that FIG. 6(A) shows the donor of sample A1. 6(B) shows the donor density of sample A2, and FIG. 6(C) shows the donor density of sample A3. , and are explanatory diagrams respectively.

[0131] In Fig. 6(A)(B)(C), GE denotes the gate electrode, GI denotes the gate insulating film, and OS The oxide semiconductor film shown in FIG. In the membrane, the donor density is 5×10 18 cm -3 The above regions are shown in gray, and the donor density is 1×10 16 cm -3 The following areas are shown in black:

[0132] From the results shown in Fig. 6(A), (B), and (C), the effective channel length of sample A1 is estimated to be 2.0 μm. The effective channel length of sample A2 was estimated to be 1.2 μm, and the effective channel length of sample A3 was estimated to be 1.2 μm. The length of the loop was estimated to be 0.8 μm. In other words, ΔL of sample A1 was estimated to be 0 μm. The ΔL of sample A2 was estimated to be 0.4 μm, and the ΔL of sample A3 was estimated to be 0.6 μm. .

[0133] [3. Density of shallow defect states in oxide semiconductor films] Next, the shallow defect state density (sDOS) in an oxide semiconductor film will be described. The sDOS of an oxide semiconductor film can be determined from the electrical characteristics of a transistor using the oxide semiconductor film. In the following, we evaluate the density of the interface states of a transistor and calculate the In addition to the density, the number of electrons trapped in the interface states N trap Considering the above, A method for predicting the threshold leakage current will now be described.

[0134] Number of electrons trapped in the interface state N trap is, for example, the drain current of a transistor -Measurement of gate voltage (Id-Vg) and drain current-gate voltage (Id-Vg) characteristics It can be evaluated by comparing it with a calculated value.

[0135] Figure 7 shows the results of calculations for a source voltage of Vs = 0V and a drain voltage of Vd = 0.1V. The ideal Id-Vg characteristics obtained and the actually measured Id-Vg characteristics of the transistor are compared. Among the measurement results of the transistor, the 1×10 -13 Only values ​​above A are plotted.

[0136] Compared to the ideal Id-Vg characteristics calculated by calculation, the actual Id-Vg characteristics are The change in drain current Id with respect to g becomes gradual. This is because the energy at the bottom of the conduction band ( This is thought to be due to the electrons being trapped in the shallow interface states located near the interface. Here, the Fermi distribution function is used to estimate the trapping in shallow interface states (per unit area , number of electrons per unit energy) N trap By taking into account the above, the interface state Density N it can be estimated.

[0137] First, the electrons trapped in the interface trap states were measured using the schematic Id-Vg characteristics shown in FIG. Number of electrons N trap The evaluation method of is explained below. The dashed line shows the trap level obtained by calculation. The dashed line shows the ideal Id-Vg characteristic with no offset. The change in gate voltage Vg when it changes from Id2 to Id3 is ΔV id The solid line indicates the actual measurement. The solid line shows the Id-Vg characteristics of the transistor. When the drain current changes from Id1 to Id2, The change in gate voltage Vg at ex When the drain current is Id1 and Id2, The potentials at the target interfaces are φ it1 , φ it2 Let the change amount be Δφ it Tosu do.

[0138] In Figure 8, the actual measurement has a smaller slope than the calculation, so ΔV ex is always ΔV id Greater than At this time, ΔV ex and ΔV id The difference in the electron density causes the electron to be trapped in the shallow interface state. Therefore, the change in charge due to the trapped electrons is expressed as ΔQ trap can be expressed by the following equation (7).

[0139]

number

[0140] C tg is the combined capacitance of the insulator and semiconductor per area. Also, ΔQ trap Is, tiger Number of electrons (per unit area, per unit energy) trap Using equation (8), It can also be expressed as follows, where q is the elementary charge.

[0141]

number

[0142] Equation (9) can be obtained by solving equations (7) and (8) simultaneously.

[0143]

number

[0144] Next, Δφ in Eq. (9) it By taking the limit of zero for, we obtain equation (10). can.

[0145]

number

[0146] That is, using the ideal Id-Vg characteristics, the actually measured Id-Vg characteristics, and equation (10), Number of electrons trapped on the surface, N trap It is possible to estimate the drain current. The relationship between the potential at the interface with the current was calculated using the device simulator mentioned above. Therefore, it can be obtained.

[0147] Also, the number of electrons per unit area and unit energy, N trap and the density of interface states N it teeth The relationship is as shown in equation (11).

[0148]

number

[0149] where f(E) is the Fermi distribution function. N obtained from Eq. (10) trap The formula By fitting with (11), N it is determined. This N it The device that you set By calculation using a seat simulator, we were able to obtain transfer characteristics including Id<0.1pA. Cut.

[0150] Next, equation (10) is applied to the measured Id-Vg characteristics shown in Figure 7, and N trap Extracted The results are shown in Fig. 9 by white circles. Here, the vertical axis of Fig. 9 is the frequency of the ferroelectric The energy Ef is the maximum value just below Ec. 11) N it Assuming the tail distribution of equation (12), the distribution is very similar to the dotted line in Figure 9. Good N trap can be fitted, and the peak value N t a =1.67×10 13 cm -2 eV -1 , characteristic width W ta =0.105 eV was obtained.

[0151]

number

[0152] Next, the fitting curve of the obtained interface state was calculated using a device simulator. The Id-Vg characteristics were calculated by feeding the results back to the Id-Vg characteristics shown in Figure 10. 0(A), calculated for drain voltages Vd of 0.1V and 1.8V. Id-Vg characteristics and transistors when drain voltage Vd is 0.1V and 1.8V FIG. 10(B) shows the Id-Vg characteristics of the drain of FIG. 10(A). 1 is a graph showing the logarithm of the in-current Id.

[0153] The curve obtained by calculation and the plot of the actual measured values ​​are almost the same, and the calculated values ​​and the measured values ​​are Therefore, it is considered that the method for calculating the density of shallow defect states is highly reproducible. It can be seen that the above method is quite valid.

[0154] [Mobility curve calculation results] The sDOS in the oxide semiconductor film described above affects the field-effect mobility curve. In particular, near the threshold voltage, electrons are trapped in the sDOS, and the shape of the mobility curve changes. The sDOS in the oxide semiconductor film is expressed by the formula (12) ta and W ta and an oxide semiconductor film Thickness (t OS Based on the above formula (12), the mobility curve is expressed as The parameters used in the calculation are shown in Table 1.

[0155] [Table 1]

[0156] In this embodiment, W ta The mobility curves for different values ​​of W ta The shape of the mobility curve when the value of is changed is shown in FIG. , N ta =2.5×10 19 cm -3 eV-1 And ΔL=0. Also, W ta to 0 .015eV, 0.02eV, 0.025eV, 0.03eV, 0.035eV, 0.0 The seven conditions were: 0.4 eV, 0.045 eV, and 0.5 eV.

[0157] As shown in Fig. 11, the smaller the value of Wta, that is, the narrower the energy width of the sDOS, the It can be seen that the rise of the mobility curve becomes steeper. The narrower the Vg, the more the peak value of the mobility curve shifts from the high Vg side to the low Vg side, and the It is clear that it is declining.

[0158] Next, the donor density distributions of the samples A1 to A3 shown in FIGS. 6(A), 6(B), and 6(C) and the donor density distributions of the samples A1 to A3 shown in FIG. Based on the shape of the mobility curve shown in FIG. 1, the mobility curves of the models corresponding to the samples A1 to A3 are The shape of the mobility curve was calculated. The calculated mobility curve is shown in Figure 12.

[0159] FIG. 12 shows the calculation results of the mobility curves of the models corresponding to samples A1 to A3. In sample A1, N ta =3.0×10 19 cm -3 eV -1 Let ΔL = 0, and W ta was set to 0.045 eV. In addition, in the sample A2, N ta =3.0×10 19 cm -3 eV -1 Let ΔL = 0.4 μm, and W ta was set to 0.035 eV. For sample A3, N ta =2.5×10 19 cm -3 eV -1 Let ΔL = 0.6 μm, and W ta to 0. The energy was set to 025 eV.

[0160] The results shown in FIG. 12 are the mobility curves of Samples A1 to A3 shown in FIGS. This is thought to be a result that roughly reflects the shape of the line.

[0161] Thus, the shape of the field effect mobility curve of the transistor is similar to that of sDOS. It was suggested that the influence of the oxide semiconductor was large. The value of sDOS in the body membrane may be different.

[0162] In order to evaluate the sDOS in the oxide semiconductor films of Samples A1 to A3, Sample B1 Samples B1 to B3 were fabricated. Samples B1 to B3 differ only in the size of the transistors. The respective samples were fabricated in the same manner as samples A1 to A3.

[0163] The results of sDOS for samples B1 to B3 are shown in FIG. The size of the transistor was L / W=6 / 50 μm.

[0164] As shown in FIG. 13, the sDO in the oxide semiconductor film is increased in the order of Sample B1, Sample B2, and Sample B3. In other words, the oxide semiconductor film S was larger in the order of Sample A1, Sample A2, and Sample A3. The results show that there is a large amount of sDOS in the middle, and the results of the device simulation shown above are appropriate. It can be seen that.

[0165] In addition, in all of the samples B1 to B3, the peak value of sDOS was 5× 10 12 cm -2 eV -1 This indicates that the sample has an extremely low sDOS. Note that the peak value of sDOS in the oxide semiconductor film is preferably 2.5×10 12 c m -2 eV -1 less than 1.5×10 12 cm -2 eV -1 Less than or equal to Preferably 1.0 x 10 12 cm -2 eV -1 is less than.

[0166] In this way, by reducing the sDOS in the oxide semiconductor film, the mobility curve becomes steeper. In addition, by reducing the sDOS in the oxide semiconductor film, The peak value of the mobility curve on the g side can be shifted to the low Vg side, making the peak value smaller. That is, by reducing the sDOS in the oxide semiconductor film, The rise of the field effect mobility curve of the transistor can be made steeper, and the mobility curve The saturation of the compound can be increased.

[0167] <1-4. Components of a transistor> Next, the components of the transistors shown in FIGS. 4(A), 4(B), and 4(C) will be described in detail. .

[0168] [substrate] The substrate 102 is made of a material having a heat resistance sufficient to withstand the heat treatment during the manufacturing process. It is possible.

[0169] Specifically, non-alkali glass, soda-lime glass, potash glass, crystal glass, Quartz, sapphire, or the like can be used. In addition, an inorganic insulating film may be used. Examples of inorganic insulating films include silicon oxide films, silicon nitride films, silicon oxynitride films, An example of the film is an aluminum oxide film.

[0170] The alkali-free glass may have a thickness of, for example, 0.2 mm or more and 0.7 mm or less. Alternatively, the non-alkali glass may be polished to the above thickness.

[0171] In addition, we also offer 6th generation (1500mm x 1850mm) and 7th generation non-alkali glass. (1870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 10th generation (2950mm x 3400mm) etc. This allows the use of a large glass substrate, making it possible to manufacture a large display device. can be done.

[0172] The substrate 102 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline A semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. may be used. .

[0173] Alternatively, the substrate 102 may be made of an inorganic material such as a metal. Examples of the material include stainless steel and aluminum.

[0174] The substrate 102 is made of an organic material such as resin, a resin film, or plastic. The resin film may be polyester, polyolefin, polyamide (naphthalene, etc. Iron, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, Epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (P EN), polyethersulfone (PES), or silicone with siloxane bonds Examples of the resin include a resin having the above structure.

[0175] Alternatively, the substrate 102 may be made of a composite material that combines an inorganic material and an organic material. The composite material is a material in which a metal plate or a thin glass plate is bonded to a resin film. Materials made of composites, fibrous metals, particulate metals, fibrous glass, or particulate glass. Materials dispersed in an oil film, or fibrous or particulate resin dispersed in an inorganic material Materials, etc.

[0176] The substrate 102 is at least capable of supporting a film or layer formed thereon or therebelow. Any suitable material may be used, and the material may be one or more of an insulating film, a semiconductor film, and a conductive film. stomach.

[0177] [First insulating film] The insulating film 104 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating film 104 can be formed by appropriately using a photolaser laser deposition (PLD) method, a printing method, a coating method, or the like. For example, a single layer or a stacked layer of an oxide insulating film or a nitride insulating film can be formed. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, In this case, at least a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. It is preferable to use an oxide insulating film that releases oxygen by heating as the insulating film 104. Then, oxygen contained in the insulating film 104 is transferred to the oxide semiconductor film 108 by heat treatment. It is possible.

[0178] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. This can increase the amount of oxygen released from the insulating film 104 and also can prevent the insulating film 104 and the oxide semiconductor from The interface state at the interface with the conductive film 108 and the channel region 1 of the oxide semiconductor film 108 It is possible to reduce the oxygen vacancies contained in 08i.

[0179] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film may be a single layer or a stacked layer. The layer structure of the silicon nitride film and the silicon oxynitride film is used as the layer 104. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and an oxynitride film on the upper layer. By using a silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. Cut.

[0180] [Oxide semiconductor film] The oxide semiconductor film 108 will be described in detail in Embodiment 2.

[0181] [Second insulating film] The insulating film 110 supplies oxygen to the oxide semiconductor film 108, particularly to the channel region 108i. For example, the insulating film 110 may be a single layer of an oxide insulating film or a nitride insulating film. Alternatively, the oxide semiconductor film 108 may be formed by stacking the oxide semiconductor film 108. In order to achieve this, the insulating film 110 must be formed such that at least a region thereof in contact with the oxide semiconductor film 108 is The insulating film 110 is preferably formed using an oxide insulating film. Silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.

[0182] The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 nm or less. m or less, or from 10 nm to 250 nm.

[0183] In addition, it is preferable that the insulating film 110 has few defects. (ESR: Electron Spin Resonance) observed signal For example, the above signal is observed at a g value of 2.001. The E' center is caused by the dangling bond of silicon. The insulating film 110 has a spin density due to the E' center of 3×10 17 spi ns / cm 3 Less than or equal to 5×10 16 spins / cm 3 Silicon oxide is less than A silicon oxynitride film or a silicon oxide nitride film may be used.

[0184] In addition to the above-mentioned signals, the insulating film 110 also contains signals due to nitrogen dioxide (NO2). A null may be observed. The signal is divided into three signals due to the nuclear spin of N. The g value of each is between 2.037 and 2.039 (this is the first signal). , g value is 2.001 to 2.003 (second signal), and g value is 1.96 It is observed between 4 and 1.966 (referred to as the third signal).

[0185] For example, the insulating film 110 may have a spin density of 1×10 1 7 spins / cm 3 More than 1×10 18 spins / cm 3 When an insulating film having a thickness of less than This is preferable.

[0186] In addition, nitrogen oxides (NO x ) creates a level in the insulating film 110 The level is located within the energy gap of the oxide semiconductor film 108. Therefore, nitrogen oxides (NOx) diffuse to the interface between the insulating film 110 and the oxide semiconductor film 108. When this level occurs, the level may trap electrons on the insulating film 110 side. The trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108. This causes the threshold voltage of the transistor to shift in the positive direction. 0, if a film with a low content of nitrogen oxide is used, the threshold voltage of the transistor The shift can be reduced.

[0187] Nitrogen oxides (NO x An example of an insulating film with a low emission amount of ) is a silicon oxynitride film. The silicon oxynitride film can be analyzed by thermal desorption spectroscopy (TDS). Nitrogen oxides were detected by thermal desorption spectroscopy. (NO x ) is a membrane that releases more ammonia than water. Output is 1×10 18 cm -3 5×10 or more 19 cm -3 The above is the ammo. The amount of Ni released was 50°C or more and 650°C or less for the TDS heat treatment. This is the total amount in the range of ℃ to 550℃.

[0188] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating film that releases a large amount of monia, nitrogen oxides (NO x ) is reduced.

[0189] When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6×10 20 ato ms / cm 3 It is preferable that the following is true:

[0190] The insulating film 110 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ) and high-k materials such as hafnium oxide may also be used. The use of this high-k material can reduce gate leakage of transistors.

[0191] [Third insulating film] The insulating film 116 contains nitrogen or hydrogen. The insulating film 116 also contains fluorine. The insulating film 116 may be, for example, a nitride insulating film. Examples of the silicon nitride include silicon nitride oxide, silicon oxynitride, and silicon nitride fluoride. The insulating film 116 can be formed using silicon fluoride nitride or the like. is 1 x 10 22 atoms / cm 3 The insulating film 116 is preferably made of an acid. The source region 108s and the drain region 108d of the nitride semiconductor film 108 are in contact with each other. As a result, impurities in the source region 108s and the drain region 108d in contact with the insulating film 116 The (nitrogen or hydrogen) concentration becomes high, and the source region 108s and the drain region 108d The carrier density can be increased.

[0192] [Fourth insulating film] The insulating film 118 can be an oxide insulating film. For the insulating film 118, a stacked film of an oxide insulating film and a nitride insulating film can be used. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, Hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used.

[0193] The insulating film 118 functions as a barrier film against hydrogen, water, and the like from the outside. It is preferable that

[0194] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. m or less.

[0195] [Fifth insulating film] The insulating film 122 may be formed using an inorganic or organic material as long as it has insulating properties. The inorganic material may be a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. , silicon nitride film, aluminum oxide film, aluminum nitride film, etc. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin. can be done.

[0196] [Conductive film] The conductive films 106, 112, 120a, and 120b are formed by sputtering or vacuum deposition. The film can be formed by using a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. The conductive films 106, 112, 120a, and 120b are made of conductive metal films. If a conductive film having a function of reflecting visible light or a conductive film having a function of transmitting visible light is used, good.

[0197] Conductive metal films include aluminum, gold, platinum, silver, copper, chromium, tantalum, Titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium or manganese Alternatively, a material containing the above-mentioned metal element can be used. An alloy containing such a metal may also be used.

[0198] Specifically, the metal film having the above-mentioned conductivity is a two-layer structure in which a copper film is laminated on a titanium film. Two-layer structure with copper film laminated on titanium nitride film, two-layer structure with copper film laminated on tantalum nitride film A three-layer structure is used, in which a copper film is laminated on a titanium film, and a titanium film is formed on top of that. In particular, the use of a conductive film containing copper can reduce the resistance. As the conductive film containing copper, an alloy film containing copper and manganese is preferable. The alloy film is suitable because it can be processed using a wet etching method. .

[0199] The conductive films 106, 112, 120a, and 120b are made of tantalum nitride films. The tantalum nitride film is preferably conductive and has a high resistance to copper or hydrogen. In addition, the tantalum nitride film has a low hydrogen release rate, Therefore, a metal film in contact with the oxide semiconductor film 108 or a metal film near the oxide semiconductor film 108 It can be most preferably used as such.

[0200] In addition, a conductive polymer or a conductive high molecule is used as the conductive film having the above-mentioned conductivity. This is also fine.

[0201] The conductive film having the above-mentioned function of reflecting visible light may be made of gold, silver, copper, or parallax. In particular, a conductive material containing a metal element selected from the group consisting of silver and tin can be used. The use of a film is preferable because it can increase the reflectance in visible light.

[0202] The conductive film having the above-mentioned function of transmitting visible light may be made of indium, tin, zinc, A material containing an element selected from gallium or silicon can be used. are In oxide, Zn oxide, In-Sn oxide (also called ITO), In-Sn-Si Examples include In-Zn oxide (also called ITSO), In-Ga-Zn oxide, and In-Zn oxide. do.

[0203] The conductive film having a function of transmitting visible light may be made of graphene or graphene. A film containing graphene may be used. As the film containing graphene, a film containing graphene oxide may be used. and reducing the film containing graphene oxide to form a film containing graphene. The reduction method can be, for example, the application of heat or the use of a reducing agent. can be done.

[0204] Moreover, the conductive films 112, 120a, and 120b can be formed by electroless plating. Materials that can be formed by the electroless plating method include, for example, Cu, Ni, Al, One or more selected from Au, Sn, Co, Ag, and Pd may be used. In particular, the resistance of the conductive film can be reduced by using Cu or Ag. Therefore, it is preferable.

[0205] In addition, when a conductive film is formed by electroless plating, the constituent elements of the conductive film tend to diffuse outward. In order to prevent the conductive film from diffusing, a diffusion prevention film may be formed under the conductive film. A seed layer may be formed between the film and the conductive film on which the conductive film can be grown. The diffusion prevention film can be formed by using, for example, a sputtering method. The diffusion prevention film may be, for example, a tantalum nitride film or a titanium nitride film. The seed layer can be formed by electroless plating. The seed layer is made of a conductive film material that can be formed by electroless plating. Materials similar to those used for the stencil printing can be used.

[0206] The conductive film 112 is formed using an oxide semiconductor such as In-Ga-Zn oxide. When nitrogen or hydrogen is supplied from the insulating film 116, the oxide semiconductor can be In other words, the oxide semiconductor is an oxide conductor (OC). Therefore, the oxide semiconductor functions as a gate electrode. It can be used.

[0207] For example, the conductive film 112 may have a single-layer structure of an oxide conductor (OC) or a single-layer structure of a metal film. or a laminated structure of an oxide conductor (OC) and a metal film.

[0208] Note that the conductive film 112 may have a single-layer structure of a metal film having a light-shielding property or an oxide conductor ( When a laminated structure of an OC and a metal film having a light-shielding property is used, This is preferable because the conductive film 11 can shield the channel region 108i from light. 2. A laminate of an oxide semiconductor or oxide conductor (OC) and a metal film having a light-shielding property. When using this structure, a metal film (e.g., a tin film) is formed on an oxide semiconductor or an oxide conductor (OC). By forming a metal film, the constituent elements in the metal film can be converted to an oxide semiconductor. or diffusion into the oxide conductor (OC) side, resulting in low resistance; damage during deposition of the metal film (e.g. , sputtering damage, etc.) or oxide semiconductors in the metal film Or, oxygen in the oxide conductor (OC) diffuses, forming oxygen vacancies and lowering the resistance. do.

[0209] The thickness of the conductive films 106, 112, 120a, and 120b is 30 nm or more and 500 nm or less. or less, or from 100 nm to 400 nm.

[0210] <1-5. Transistor configuration example 2> Next, regarding the transistors having structures different from those shown in FIGS. This will be explained using FIG.

[0211] 14(A) and (B) are cross-sectional views of a transistor 100B, and FIGS. 16A and 16B are cross-sectional views of a transistor 100D. 1 is a cross-sectional view of a transistor 100B, a transistor 100C, and a transistor The top view of the transistor 100D is the same as that of the transistor 100A shown in FIG. , the explanation will be omitted here.

[0212] The transistor 100B shown in FIGS. 14A and 14B has a stacked structure of a conductive film 112, a conductive film The shape of the insulating film 112 and the shape of the insulating film 110 are different from those of the transistor 100A.

[0213] The conductive film 112 of the transistor 100B is a conductive film 112_1 on the insulating film 110 and a conductive For example, the conductive film 112_1 is made of an acid. By using a nitride conductive film, excess oxygen can be added to the insulating film 110. The oxide conductive film is formed by sputtering in an atmosphere containing oxygen gas. The oxide conductive film may be, for example, an oxide film containing indium and tin. tungsten, indium and zinc oxides; oxide having titanium and indium; oxide having titanium, indium and tin oxides containing indium and zinc; oxides containing silicon, indium, and tin; Examples of suitable oxides include indium, gallium, and zinc oxides.

[0214] 14B, in the opening 143, the conductive film 112_2 and the conductive When the opening 143 is formed, the conductive film 112_1 is connected to the conductive film 106. After the formation of the hole, the opening 143 is formed, so that the shape shown in FIG. 14(B) can be obtained. When an oxide conductive film is used as the conductive film 112_1, the conductive film 112_2 and the conductive film 1 By using a structure in which the conductive film 112 and the conductive film 106 are connected, the contact resistance between the conductive film 112 and the conductive film 106 can be reduced. It is possible.

[0215] The conductive film 112 and the insulating film 110 of the transistor 100B have a tapered shape. More specifically, the lower end of the conductive film 112 is formed outside the upper end of the conductive film 112. In addition, the lower end of the insulating film 110 is formed outside of the upper end of the insulating film 110. Moreover, the lower end of the conductive film 112 is formed at approximately the same position as the upper end of the insulating film 110 .

[0216] The conductive film 112 and the insulating film 110 of the transistor 100B are tapered. In comparison with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular, the insulating film 1 This is preferable because it can improve the coverage of 16.

[0217] The other configurations of the transistor 100B are the same as those of the transistor 100A described above. and has the same effect.

[0218] The transistor 100C shown in FIGS. 15A and 15B has a stacked structure of a conductive film 112, a conductive film The shape of the insulating film 112 and the shape of the insulating film 110 are different from those of the transistor 100A.

[0219] The conductive film 112 of the transistor 100C includes a conductive film 112_1 on the insulating film 110 and a conductive The conductive film 112_2 is disposed on the conductive film 112_1. For example, the conductive film 112_1 and the conductive film 112_2 are formed on the outer side of the upper end of the conductive film 112_1. The film 112_2 and the insulating film 110 are processed using the same mask, and the conductive film 112_2 is wet The conductive film 112_1 and the insulating film 110 are dry-etched by etching. By processing, the above structure can be obtained.

[0220] In addition, by using the structure of the transistor 100C, the region 1 Region 108f may be formed by forming channel region 108i and source region 108i. 08s and between the channel region 108i and the drain region 108d.

[0221] The region 108f functions as either a high resistance region or a low resistance region. The resistance region is a conductive region that has a resistance equivalent to that of the channel region 108i and functions as a gate electrode. This is a region where the film 112 does not overlap. When the region 108f is a high resistance region, the region 108f is This region functions as a so-called offset region. When the region 108f functions as an offset region, In order to suppress the decrease in the on-current of the transistor 100C, the channel length (L ) direction, the region 108f may be set to 1 μm or less.

[0222] The low resistance region is a region having a lower resistance than the channel region 108i and a The region 108f is a low resistance region. In this case, the region 108f is a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as an LDD region, the drain This allows the electric field in the drain region to be relaxed, which reduces the threshold voltage of the transistor caused by the electric field in the drain region. This can reduce fluctuations in the value voltage.

[0223] In addition, when the region 108f is used as an LDD region, for example, One or more of nitrogen, hydrogen, and fluorine are supplied to the insulating film 110 and the conductive film 11 By using the conductive film 112_1 as a mask, an impurity element is added from above the conductive film 112_1, The impurities pass through the conductive film 112_1 and the insulating film 110 and are added to the oxide semiconductor film 108. It can be formed by

[0224] As shown in FIG. 15B, in the opening 143, the conductive film 112_2 and the conductive The membrane 106 is connected.

[0225] The other configurations of the transistor 100C are the same as those of the transistor 100A described above. and has the same effect.

[0226] The transistor 100D shown in FIGS. 16A and 16B has a stacked structure of a conductive film 112, a conductive film The shape of the insulating film 112 and the shape of the insulating film 110 are different from those of the transistor 100A.

[0227] The conductive film 112 of the transistor 100D is a conductive film 112_1 on the insulating film 110 and a conductive The conductive film 112_2 is disposed on the conductive film 112_1. The insulating film 110 is formed on the outer side of the lower end of the conductive film 112_2. For example, the conductive film 112_1 and the conductive film The conductive film 112_2 and the insulating film 110 are processed using the same mask. 12_1 is etched by a wet etching method, and the insulating film 110 is etched by a dry etching method. By performing the above-mentioned processing, the above-mentioned structure can be obtained.

[0228] In addition, like the transistor 100C, the transistor 100D has an oxide semiconductor film 1 In some cases, a region 108f is formed in the semiconductor substrate 108. The region 108f is a channel region 108i. between the source region 108s and the channel region 108i and the drain region 108d is formed.

[0229] 16B, in the opening 143, the conductive film 112_2 and the conductive The membrane 106 is connected.

[0230] The other configurations of the transistor 100D are the same as those of the transistor 100A described above. and has the same effect.

[0231] <1-6. Transistor configuration example 3> Next, regarding a configuration different from that of the transistor 100A shown in FIGS. This will be explained with reference to Figures 17 to 21.

[0232] 17(A) and (B) are cross-sectional views of a transistor 100E, and FIGS. 19(A) and (B) are cross-sectional views of a transistor 100G. 20(A) and (B) are cross-sectional views of a transistor 100H, and FIG. 21 is a cross-sectional view of a transistor 100H. 1A and 1B are cross-sectional views of a transistor 100J. Transistor 100F, transistor 100G, transistor 100H, and transistor The top view of the transistor 100J is the same as that of the transistor 100A shown in FIG. , the explanation will be omitted here.

[0233] Transistor 100E, transistor 100F, transistor 100G, transistor The transistor 100H and the transistor 100J are the same as the transistor 100A shown above, and each of them is a transistor having an oxide semiconductor. The structure of the film 108 is different. Other configurations are the same as the transistor 100A shown above. They have the same configuration and provide the same effects.

[0234] The oxide semiconductor film 108 included in the transistor 100E illustrated in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d are The oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film It has a three-layer laminated structure of 108_3.

[0235] The oxide semiconductor film 108 included in the transistor 100F illustrated in FIGS. The oxide semiconductor film 108_2 on the insulating film 104 and the oxide semiconductor film 108_2 on the oxide semiconductor film The semiconductor device further includes a channel region 108i, a source region 108s, and a semiconductor film 108_3. The drain region 108d is formed by the oxide semiconductor film 108_2 and the oxide semiconductor film 1 It has a two-layer laminated structure of 08_3.

[0236] The oxide semiconductor film 108 included in the transistor 100G illustrated in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film The semiconductor device further includes a channel region 108i, a source region 108s, and a semiconductor film 108_2. The drain region 108d is formed of the oxide semiconductor film 108_1 and the oxide semiconductor film 1 It has a two-layer laminated structure of 08_2.

[0237] The oxide semiconductor film 108 included in the transistor 100H illustrated in FIGS. The oxide semiconductor film 108_1 on the insulating film 104 and the oxide semiconductor film 108_1 on the oxide semiconductor film and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i is formed by the oxide semiconductor film 108_1 and the oxide semiconductor film 108 The source region 108s and the oxide semiconductor film 108_3 are stacked in a three-layer structure. The drain region 108d is formed of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2. The transistor 100H has a two-layer stack structure of 108_2. In the cross section in the axial direction, the oxide semiconductor film 108_3 is It covers the side surface of the semiconductor film 108_2.

[0238] The oxide semiconductor film 108 included in the transistor 100J illustrated in FIGS. The oxide semiconductor film 108_2 on the insulating film 104 and the oxide semiconductor film 108_2 on the oxide semiconductor film The channel region 108i includes an oxide semiconductor film 108_3. 2 and an oxide semiconductor film 108_3. The drain region 108d has a single-layer structure of the oxide semiconductor film 108_2. In the cross section of the transistor 100J in the channel width (W) direction, the oxide semiconductor film 108 _3 covers the side surfaces of the oxide semiconductor film 108_2.

[0239] The side surface or the vicinity of the channel region 108i in the channel width (W) direction is processed. Damage in the junctions can easily lead to the formation of defects (e.g. oxygen vacancies) or the presence of impurities. Therefore, even if the channel region 108i is substantially intrinsic, When a stress such as an electric field is applied, the channel width ( The side surface or its vicinity in the W direction is activated and tends to become a low-resistance (n-type) region. When the side surface or the vicinity of the side surface of the channel region 108i in the channel width (W) direction is an n-type region, Since the n-type region serves as a path for carriers, a parasitic channel may be formed.

[0240] Therefore, in the transistor 100H and the transistor 100J, the channel region The channel region 108i has a laminated structure, and the side surface of the channel region 108i in the channel width (W) direction is By using this structure, the side surface of the channel region 108i is covered with one layer of the structure. or suppressing defects on or near the side of the channel region 108i. This makes it possible to reduce the adhesion of impurities to the substrate.

[0241] [Band structure] Here, the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film The band structure of the insulating film 110, the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and The band structure of the insulating film 110, the insulating film 104, and the oxide semiconductor films 108_1 and 108_ The band structure of 2 will be explained with reference to Figs. 22(A), (B), and (C). A), (B), and (C) are band structures in the channel region 108i.

[0242] FIG. 22A shows the insulating film 104 and the oxide semiconductor films 108_1, 108_2, and 108_3. 2 is an example of a band structure in the thickness direction of a laminated structure having the insulating film 110. 2(B) shows the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. FIG. 22(C) shows an example of a band structure in the thickness direction of a laminated structure having an insulating film. 104, a stacked structure including oxide semiconductor films 108_1 and 108_2, and an insulating film 110. This is an example of a band structure in the film thickness direction. Note that the band structure is shown as an insulating film for ease of understanding. 104, oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110 The energy level (Ec) at the lower band edge is shown.

[0243] FIG. 22A shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_1 is a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using an oxide semiconductor target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 was used. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by The oxide formed using a metal oxide target with a numerical ratio of In:Ga:Zn=1:3:2 FIG. 1 is a band diagram of a configuration using a semiconductor film.

[0244] FIG. 22B shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_2 is a metal film having an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108_3 is formed by using an oxide semiconductor film formed by using an oxide target. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 was used. FIG. 13 is a band diagram of a structure using an oxide semiconductor film formed in accordance with the present invention.

[0245] FIG. 22C shows a case where a silicon oxide film is used as the insulating films 104 and 110, and an oxide semiconductor film is used as the insulating films 104 and 110. The conductor film 108_1 is a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=1:3:2. An oxide semiconductor film formed using an oxide semiconductor target was used as the oxide semiconductor film 108_2. A metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 was used. A band gap formed by using an oxide semiconductor film FIG.

[0246] As shown in FIG. 22A, in the oxide semiconductor films 108_1, 108_2, and 108_3, In addition, as shown in FIG. 22(B), the energy level at the bottom of the conduction band changes gradually. As shown in FIG. 1, the energy levels of the conduction band minimums of the oxide semiconductor films 108_2 and 108_3 are As shown in FIG. 22C, the oxide semiconductor films 108_1 and 1 In 08_2, the energy level at the bottom of the conduction band changes smoothly. It can be said that the band structure changes continuously or changes continuously. For this purpose, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the oxide At the interface between the semiconductor film 108_2 and the oxide semiconductor film 108_3, a trap center or a recombination Assume that there are no impurities that would form defect levels such as coalescence centers.

[0247] In order to form a continuous junction in the oxide semiconductor films 108_1, 108_2, and 108_3, A multi-chamber deposition system (sputtering system) equipped with a load lock chamber was used. It is necessary to laminate each film in succession without exposing them to the atmosphere.

[0248] By using the structure shown in FIG. 22(A), (B), and (C), the oxide semiconductor film 108_2 is a well. In a transistor using the above stacked structure, the channel region is an oxide semiconductor. It can be seen that it is formed on the conductive film 108_2.

[0249] Note that by providing the oxide semiconductor films 108_1 and 108_3, defect states are It can be located away from the semiconductor film 108_2.

[0250] In addition, the defect level is the minimum of the conduction band of the oxide semiconductor film 108_2 which functions as a channel region. The energy level (Ec) of the electron can be farther from the vacuum level, and electrons accumulate in the defect level. When electrons accumulate in the defect level, they become a negative fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. is closer to the vacuum level than the energy level (Ec) of the conduction band minimum of the oxide semiconductor film 108_2. By doing so, electrons are less likely to accumulate in the defect level. This increases the on-state current of the transistor and also increases the field effect mobility. can be increased.

[0251] In addition, the oxide semiconductor films 108_1 and 108_3 are more conductive than the oxide semiconductor film 108_2. The energy level of the conduction band minimum is close to the vacuum level. The energy levels of the conduction band minimum and the conduction band minimum of the oxide semiconductor films 108_1 and 108_3 are The difference between the energy levels is 0.15 eV or more, or 0.5 eV or more and 2 eV or less. That is, the electron affinity of the oxide semiconductor films 108_1 and 108_3 is The difference between the electron affinity of the oxide semiconductor film 108_2 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, or 0. The electron transport energy is 5 eV or more and 2 eV or less, or 1 eV or less.

[0252] With such a structure, the oxide semiconductor film 108_2 serves as a main current path. That is, the oxide semiconductor film 108_2 functions as a channel region. The films 108_1 and 108_3 function as oxide insulating films. The films 108_1 and 108_3 constitute the oxide semiconductor film 108_2 in which a channel region is to be formed. It is preferable to use an oxide semiconductor film formed of one or more metal elements that form the oxide semiconductor layer. By adopting such a structure, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, Alternatively, the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 may be diffused at the interface between them. Therefore, the movement of carriers is not hindered at the interface, and therefore, The field effect mobility of the transistor is increased.

[0253] The oxide semiconductor films 108_1 and 108_3 function as part of a channel region. To prevent this, materials with sufficiently low electrical conductivity are used. The conductive films 108_1 and 108_3 are each made of oxide insulating material based on their physical properties and / or functions. Alternatively, the oxide semiconductor films 108_1 and 108_3 may be formed of a material having a high electron affinity (vacuum the energy level of the oxide semiconductor film 108_2 is smaller than that of the oxide semiconductor film 108_2, The energy level of the conduction band minimum is the same as that of the oxide semiconductor film 108_2. A material with a band offset is used. In order to suppress the occurrence of a difference in threshold voltage depending on the thickness of the oxide semiconductor film 108, The energy levels of the conduction band minimums of the oxide semiconductor films 108_1 and 108_3 are lower than the conduction band minimum of the oxide semiconductor film 108_2. It is preferable to use a material that is closer to the vacuum level than the lower energy level. For example, an oxide The energy level of the conduction band minimum of the semiconductor film 108_2 and the oxide semiconductor films 108_1 and 10 The difference between the energy level of the conduction band minimum of 8_3 is 0.2 eV or more, preferably 0.5 eV. It is preferable that the amount is equal to or more than that.

[0254] In addition, the oxide semiconductor films 108_1 and 108_3 each have a spinel crystal structure. It is preferable that the oxide semiconductor films 108_1 and 108_3 do not include a spinel type crystal. When the spinel type crystal structure is included, the conductive film 120 is In some cases, the constituent elements of the oxide semiconductor film 108_2 may diffuse into the oxide semiconductor film 108_2. When the oxide semiconductor films 108_1 and 108_3 are CAAC-OS films, which will be described later, This is preferable because it enhances the blocking properties of the constituent elements of 120a and 120b, for example, copper element.

[0255] In this embodiment, the oxide semiconductor films 108_1 and 108_3 are made of a metal The atomic ratio of elements was In:Ga:Zn=1:3:2. However, the present invention is not limited to this structure. The compound semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 [atomic ratio] ], In:Ga:Zn=1:1:1.2[atomic ratio], In:Ga:Zn=1:3:4[ [Atomic ratio], In:Ga:Zn=1:3:6 [Atomic ratio], In:Ga:Zn=1:4: 5 [atomic ratio], In:Ga:Zn=1:5:6 [atomic ratio], or In:Ga:Zn =1:10:1 [atomic ratio] metal oxide target is used to form oxide semiconductor film Alternatively, the oxide semiconductor films 108_1 and 108_3 may be formed using a metal element. The oxide semiconductor formed using a metal oxide target with an atomic ratio of Ga:Zn=10:1 In this case, the oxide semiconductor film 108_2 may be formed by using a metal element having an atomic ratio of 100 to 1000. Oxide semiconductor formed using a metal oxide target with In:Ga:Zn=1:1:1 The atomic ratio of metal elements in the oxide semiconductor films 108_1 and 108_3 is Ga:Z When an oxide semiconductor film is formed using a metal oxide target of n=10:1, The energy level of the conduction band minimum of the oxide semiconductor film 108_1, The difference in energy level between the conduction band minimum of 108_3 and the This is preferable.

[0256] Note that the oxide semiconductor films 108_1 and 108_3 are made of In:Ga:Zn=1:1:1 When a metal oxide target having an atomic ratio of 108 is used, the oxide semiconductor films 108_1 and 108 _3 is the case where In:Ga:Zn=1:β1(0<β1≦2):β2(0<β2≦2) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga:Zn=1. When a metal oxide target having an atomic ratio of 3:4 is used, the oxide semiconductor film 108_1 , 108_3 is In:Ga:Zn=1:β3(1≦β3≦5):β4(2≦β4≦6) In addition, the oxide semiconductor films 108_1 and 108_3 may be formed of In:Ga: When a metal oxide target with an atomic ratio of Zn=1:3:6 is used, the oxide semiconductor film 1 08_1 and 108_3 are In:Ga:Zn=1:β5(1≦β5≦5):β6(4≦β 6≦8).

[0257] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0258] (Embodiment 2) In this embodiment, a composition of an oxide semiconductor film that can be used in one embodiment of the present invention will be described. The structure of the oxide semiconductor film and the like will be described with reference to FIGS.

[0259] <2-1. Composition of oxide semiconductor film> First, the composition of the oxide semiconductor film will be described.

[0260] The oxide semiconductor film preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, silicon, or yttrium. , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from titanium, neodymium, hafnium, tantalum, tungsten, or magnesium. The composition may contain one or more of the above-mentioned compounds.

[0261] Here, the case where the oxide semiconductor film contains indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, etc. Other elements that can be used include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum However, the element M may be a combination of multiple of the above elements. It's okay to combine them.

[0262] First, referring to FIG. 23(A), FIG. 23(B), and FIG. 23(C), Regarding a preferable range of the atomic ratio of indium, the element M, and zinc in the oxide semiconductor film, The atomic ratio of oxygen is not shown in FIG. 23. The atomic ratios of indium, element M, and zinc in the conductor film are [In], [ [M] and [Zn].

[0263] In Figures 23(A), 23(B), and 23(C), the dashed lines indicate [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2, [I n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4, and the line where [I This represents the line where the atomic ratio is [n]:[M]:[Zn]=(1+α):(1-α):5.

[0264] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is The line where the atomic ratio is 1:3:β, [In]:[M]:[Zn ]=1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atomic ratio line The line with the atomic ratio of [In]:[M]:[Zn]=5:1:β Represents in.

[0265] The dotted line indicates the atomic arrangement of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The line where the ratio of [In]:[M]:[ The oxide semiconductor film with an atomic ratio of Zn=0:2:1 or close to it has a spinel type crystal structure. Easy to structure.

[0266] 23A and 23B show an indium-ion semiconductor film having an oxide semiconductor film according to one embodiment of the present invention. 1 shows an example of a preferable range of the atomic ratio of tungsten, the element M, and zinc.

[0267] As an example, FIG. 24 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 24 shows the crystal structure of InMZ when observed from a direction parallel to the b-axis. The crystal structure of nO4 is shown in FIG. 24. The layer having M, Zn, and oxygen (hereinafter, (M, The metal element in the layer (Zn) represents element M or zinc. In this case, element M and zinc The proportion of lead is equal. The elements M and zinc are interchangeable and the arrangement is random. do.

[0268] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 24. The layer containing elements M, zinc, and oxygen (hereinafter referred to as the In layer) is 1. The (M,Zn) layer containing oxygen is layer 2.

[0269] Indium and element M can be substituted for each other. Therefore, the elements of the (M, Zn) layer The element M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, In It has a layered structure with one layer and two (In,M,Zn) layers.

[0270] In the oxide with the atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is 1: The (M,Zn) layer is three. That is, for [In] and [M], [ When the oxide crystallizes, the ratio of the (M,Zn) layer to the In layer increases. increases.

[0271] However, in the oxide, the number of (M, Zn) layers per In layer is non-integer. In this case, the number of (M, Zn) layers is an integer for each In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, In A layered structure with one layer and two (M,Zn) layers, and a layered structure with three (M,Zn) layers. In some cases, the structure may be a layered structure that is a mixture of granular and non-granular structures.

[0272] For example, when forming an oxide film using a sputtering device, the ratio of the number of atoms in the target is different. In particular, depending on the substrate temperature during film formation, the [Z In some cases, the [Zn] of the film may be smaller than the [n].

[0273] In addition, multiple phases may coexist in an oxide (two-phase coexistence, three-phase coexistence, etc.). For example, In the atomic ratios near the atomic ratio of [In]:[M]:[Zn]=0:2:1, Two phases, a pinel type crystal structure and a layered crystal structure, tend to coexist. At atomic ratios close to the atomic ratio of Zn=1:0:0, bixbyite type In the case where multiple phases coexist in an oxide, In this case, grain boundaries are formed between the different crystal structures. There are cases.

[0274] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide can be increased.

[0275] On the other hand, when the content of indium and zinc in the oxide is low, the carrier mobility is low. Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and its vicinity In the case of an atomic ratio that is near the value (eg, region C shown in FIG. 23(C)), the insulating property is high.

[0276] Therefore, the oxide according to one embodiment of the present invention has a layered structure with high carrier mobility and few grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 23(A), which is likely to form the structure.

[0277] In addition, in the region B shown in FIG. 23B, [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M The oxides having the atomic ratio shown in region B are particularly In addition, it is an excellent oxide with high crystallinity and high carrier mobility.

[0278] In addition, in the case where the oxide semiconductor film is an In-M-Zn oxide film, the In-M-Zn oxide film is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose is In≧M, Zn≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target and In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn =2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, I n:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1 The atomic ratio of the oxide semiconductor film to be formed is preferably 1:7 or the like. The atomic ratio of metal elements contained in the target varies by about ±40%. For example, a sputtering target with an atomic ratio of In:Ga:Z When n=4:2:4.1 is used, the atomic ratio of the oxide semiconductor film to be formed is In:Ga :Zn=4:2:3 or so.

[0279] In this specification, the term "vicinity" refers to a region that is within a range of the atomic ratio of a certain metal atom M. It is better to keep it within the range of minus 1, and more preferably within plus or minus 0.5. For example, when the composition of the oxide semiconductor film is in the vicinity of In:Ga:Zn=4:2:3, Ga is Ga is 1 or more and 3 or less (1≦Ga≦3) and Zn is 2 or more and 4 or less (2≦Zn≦4), preferably Or Ga is 1.5 or more and 2.5 or less (1.5≦Ga≦2.5) and Zn is 2 or more It is sufficient that the Zn content is 4 or less (2≦Zn≦4).

[0280] The condition for the oxide semiconductor film to form a layered structure is uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. Even if the ratio is the same, a layered structure may or may not be formed depending on the formation conditions. Therefore, the illustrated region is a region showing an atomic ratio in which the oxide semiconductor film has a layered structure. The boundaries between areas A and C are not strict.

[0281] <2-2. Carrier density of oxide semiconductor film> Next, the carrier density of the oxide semiconductor film will be described below.

[0282] The factors that affect the carrier density of an oxide semiconductor film include oxygen in the oxide semiconductor film, Examples of the causes include vacancies (Vo) and impurities in the oxide semiconductor film.

[0283] When the number of oxygen vacancies in the oxide semiconductor film increases, hydrogen bonds to the oxygen vacancies (this state is called Vo When the oxide semiconductor film is heated to 1000 V, the density of defect states increases. When the amount of the impurities increases, the density of defect states due to the impurities increases. By controlling the density of defect states in the oxide semiconductor film, the carrier density in the oxide semiconductor film can be controlled. do.

[0284] Here, a transistor in which an oxide semiconductor film is used for a channel region will be considered.

[0285] Suppression of negative shift of the threshold voltage of a transistor or suppression of off-current of a transistor In order to reduce the carrier density of the oxide semiconductor film, it is preferable to reduce the carrier density of the oxide semiconductor film. In the case where the carrier density of the oxide semiconductor film is reduced, impurities in the oxide semiconductor film It is sufficient to lower the impurity concentration and the defect level density. A material with a low density of defect states is called high purity intrinsic or substantially high purity intrinsic. The carrier density of the oxide semiconductor film is 8×10 15 cm -3 Less than 1 ×10 11 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 That should be enough.

[0286] On the other hand, the improvement of the on-state current of a transistor or the field effect mobility of a transistor In that case, it is preferable to increase the carrier density of the oxide semiconductor film. In order to increase the carrier density of the oxide semiconductor film, the impurity concentration of the oxide semiconductor film is Alternatively, the density of defect states in the oxide semiconductor film may be increased slightly. Alternatively, the band gap of the oxide semiconductor film may be made smaller. In the range where the on / off ratio of the Id-Vg characteristics is obtained, the impurity concentration is slightly high, or An oxide semiconductor film having a high density of defect states or a slightly high density of defect states can be regarded as substantially intrinsic. The electron affinity is large, and the band gap is small, resulting in thermal excitation. The oxide semiconductor film in which the density of trapped electrons (carriers) is increased can be regarded as being substantially intrinsic. In addition, when an oxide semiconductor film having a higher electron affinity is used, the threshold voltage of the transistor is The voltage becomes lower.

[0287] The carrier density of a substantially intrinsic oxide semiconductor film is 1×10 5 cm -3 More than 1×101 8 cm -3 Less than 1×10 is preferable. 7 cm -3 More than 1×10 17 cm -3 The following is preferred: 1×10 9 cm -3 5×10 or more 16 cm -3 More preferably, 1×10 10 cm -3 More than 1×10 16 cm -3 More preferably, 1×10 11 cm -3 Below top 1×10 15 cm -3 The following is even more preferred:

[0288] In addition, by using the above-described substantially intrinsic oxide semiconductor film, the reliability of the transistor can be improved. Here, referring to FIG. 25, when an oxide semiconductor film is used for a channel region, The reason why the reliability of a transistor is improved will be described. 1 is a diagram illustrating an energy band in a transistor used in a channel region.

[0289] In FIG. 25, GE denotes a gate electrode, GI denotes a gate insulating film, and OS denotes an oxide semiconductor film. 25 represents the gate electrode and SD represents the source electrode or drain electrode, respectively. a gate electrode, a gate insulating film, an oxide semiconductor film, and a source electrode or is an example of an energy band of the drain electrode.

[0290] In FIG. 25, a silicon oxide film is used as the gate insulating film, and an oxide semiconductor The structure uses In-Ga-Zn oxide as the film. The defect transition level (εf) is located about 3.1 eV away from the conduction band edge of the gate insulating film. The oxide semiconductor film and the silicon oxide film are formed when the gate voltage (Vg) is 30 V. The Fermi level (Ef) of the silicon oxide film at the interface with the gate insulating film is below the conduction band of the The ferroelectric film is formed at a distance of about 3.6 eV from the edge of the silicon oxide film. The electron level varies depending on the gate voltage. For example, by increasing the gate voltage, the oxide Fermi level (Ef) of the silicon oxide film at the interface between the semiconductor film and the silicon oxide film The white circles in Fig. 25 represent electrons (carriers), and X in Fig. 25 represents silicon oxide. This represents the defect level in the silicon film.

[0291] As shown in FIG. 25, when a gate voltage is applied, for example, carriers are thermally excited. When this happens, carriers are trapped in the defect level (X in the figure), and the charge changes from positive ("+") to neutral. The charge state of the defect level changes to “0”. That is, the Fermi level of the silicon oxide film The sum of (Ef) and the thermal excitation energy mentioned above is higher than the defect transition level (εf). When the charge level of the defect in the silicon oxide film is increased, the charge state of the defect level in the silicon oxide film changes from a positive state to a neutral state, and a transistor This causes the threshold voltage of the transistor to shift in the positive direction.

[0292] In addition, when oxide semiconductor films having different electron affinities are used, The depth at which the Fermi level is formed at the interface with the oxide with a large electron affinity may differ. When an oxide semiconductor film is used, the gate insulating film is In this case, the defect level that may be formed in the gate insulating film is The Fermi level of the gate insulating film and the oxide semiconductor The energy difference between the Fermi level of the film and the Therefore, the amount of electric charge trapped in the gate insulating film is reduced. The change in the charge state of the defect level that can be formed in the gate bias heat (Gate Bias Temperature (GBT) stress on transistors This can reduce the variation in the threshold voltage of the transistor.

[0293] In addition, in a transistor using an oxide semiconductor film for a channel region, carriers at grain boundaries This reduces scattering and other problems, making it possible to realize transistors with high field effect mobility. In addition, a highly reliable transistor can be realized.

[0294] In addition, it takes a long time for charges trapped in defect states in the oxide semiconductor film to disappear. Therefore, oxides with high defect level density are Transistors in which the channel region is formed in a semiconductor film may have unstable electrical characteristics. be.

[0295] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor film is In order to reduce the impurity concentration in the oxide semiconductor film, It is preferable that the impurity concentration in the adjacent film is also reduced. , alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0296] Here, the influence of each impurity in the oxide semiconductor film will be described.

[0297] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor film, Therefore, the defect level is generated in the silicon oxide semiconductor film. The concentration of silicon and carbon near the interface with the oxide semiconductor film (secondary ion mass) Secondary Ion Mass Spectrometer (SIMS) The concentration obtained by y) is 2 × 10 18 atoms / cm 3 Below, preferably 2 x 1 0 17 atoms / cm 3 The following applies.

[0298] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor film, a defect level Therefore, alkali metal or alkaline earth metals may form A transistor using an oxide semiconductor film containing metals tends to be normally on. For this reason, it is necessary to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor film. Specifically, it is preferable to obtain an alkali metal oxide film in the oxide semiconductor film by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Hereinafter, preferably 2×10 16 atoms / cm 3 To the following:

[0299] In addition, hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. Therefore, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, the carrier Electrons may be produced. Also, some of the hydrogen may combine with oxygen, which combines with the metal atom, Therefore, the oxide semiconductor film containing hydrogen may generate electrons, which are carriers. A transistor using such a semiconductor film tends to be normally on. It is preferable that the amount of hydrogen in the oxide semiconductor film is as small as possible. The hydrogen concentration obtained by SIMS was 1×10 20 atoms / cm 3 Less than, preferred 1×10 19 atoms / cm 3 less than 5×10 18 atoms / c m 3 less than 1×10 18 atoms / cm 3 Less than.

[0300] An oxide semiconductor film in which impurities are sufficiently reduced is used for a channel formation region of a transistor. This makes it possible to impart stable electrical characteristics.

[0301] In addition, the oxide semiconductor film has an energy gap of 2 eV or more, or 2.5 eV or more. It is preferable to have one.

[0302] The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0303] <2-3. Structure of oxide semiconductor> Next, the structure of the oxide semiconductor will be described.

[0304] Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- amorphous oxide semiconductors, etc. be.

[0305] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0306] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0307] That is, a stable oxide semiconductor is transformed into a completely amorphous In addition, the semiconductor is not isotropic (for example, A periodic oxide semiconductor cannot be called a completely amorphous oxide semiconductor. -like OS is not isotropic, but has an unstable structure with voids. In terms of instability, the a-like OS is physically an amorphous oxide semiconductor. Close to.

[0308] [CAAC-OS] First, let me explain about CAAC-OS.

[0309] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0310] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. CAAC-OS is designed to prevent impurities and defects from causing degradation. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0311] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0312] [nc-OS] Next, we will explain nc-OS.

[0313] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0314] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS may have a higher density of defect states than the CAAC-OS.

[0315] [a-like OS] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0316] A-like OS has porosity or low density areas. Therefore, it is an unstable structure.

[0317] In addition, a-like OS has porosity, so compared with nc-OS and CAAC-OS, Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS and CAAC- The density of the OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78%.

[0318] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0319] If single crystals of the same composition are not available, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0320] As described above, oxide semiconductors have various structures and each structure has various characteristics. Note that the oxide semiconductor film of one embodiment of the present invention can be formed using an amorphous oxide semiconductor, an a-like OS, or Two or more of nc-OS and CAAC-OS may be mixed. As shown below.

[0321] The oxide semiconductor film of one embodiment of the present invention includes two types of crystal parts. In other words, it is an oxide semiconductor film in which two types of crystal parts are mixed. (also called the first crystal part) is in the thickness direction of the film (film surface direction, the surface on which the film is formed, or the surface of the film). The crystal part has an orientation in the c-axis direction (also called the direction perpendicular to the c-axis), that is, has a c-axis orientation. The other part of the crystal (also called the second crystal) does not have the c-axis orientation and is oriented in various directions. This is the crystalline part.

[0322] In the following, for ease of explanation, the crystal portion having the c-axis orientation is referred to as the first crystal portion. The crystal part that does not have the c-axis orientation is explained separately from the second crystal part, but these are crystallinity and In some cases, there is no difference in the size of the crystals and they cannot be distinguished. The compound semiconductor film may be expressed without distinguishing between these.

[0323] For example, the oxide semiconductor film of one embodiment of the present invention has a plurality of crystal parts. At least one of the crystal parts has a c-axis orientation. Among the crystal parts, the crystal parts not having the c-axis orientation are more abundant than the crystal parts having the c-axis orientation. For example, the oxide semiconductor film of one embodiment of the present invention may have a thickness In the cross-section in the direction of the crystal, a plurality of crystals are observed in the observation image by a transmission electron microscope. Among the plurality of crystal portions, a second crystal portion not having a c-axis orientation is a first crystal portion having a c-axis orientation. In other words, in the oxide semiconductor of one embodiment of the present invention, the crystal parts are sometimes observed more than the crystal parts of the oxide semiconductor of one embodiment of the present invention. The film contains a large proportion of second crystal portions that do not have c-axis orientation.

[0324] By increasing the proportion of the second crystal portions that do not have c-axis orientation in the oxide semiconductor film, The following excellent effects are achieved.

[0325] When there is a sufficient oxygen source near the oxide semiconductor film, the oxide semiconductor film does not have a c-axis orientation. The second crystal portion can be a diffusion path for oxygen. In the case where a source of element is present, a first crystal part having a c-axis orientation is formed through a second crystal part not having a c-axis orientation. Therefore, oxygen can be supplied to the first crystal portion of the oxide semiconductor film. When such an oxide semiconductor film is applied to a semiconductor film of a transistor, the amount of loss can be reduced. By using such a material, it is possible to obtain high reliability and high field effect mobility.

[0326] In addition, the first crystal portion has a specific crystal plane oriented in the thickness direction of the film. Therefore, for the oxide semiconductor film including the first crystal portion, the X When X-ray diffraction (XRD) is performed, the diffraction angle ( 2θ), a diffraction peak originating from the first crystal portion is observed. Even if the first crystal portion is included, the X-rays may be scattered by the supporting substrate or may be scattered above the background. In some cases, the diffraction peaks may not be clearly visible due to the increase in the diffraction intensity. ) increases in accordance with the proportion of the first crystal portion contained in the oxide semiconductor film, and It can also be used as an index to estimate the crystallinity of a semiconductor film.

[0327] In addition, one method for evaluating the crystallinity of an oxide semiconductor film is electron beam diffraction. For example, a cross-section of the oxide semiconductor film of one embodiment of the present invention is subjected to electron diffraction measurement. When the fold pattern is observed, a first region having a diffraction spot due to the first crystal portion is identified. A second region having a diffraction spot caused by the second crystal portion is observed.

[0328] The first region having the diffraction spots due to the first crystal portion is a crystal having a c-axis orientation. On the other hand, the second region having a diffraction spot due to the second crystal part is due to the orientation It is derived from crystals that have no orientation or crystals that are randomly oriented in all directions. Therefore, the beam diameter of the electron beam used in electron diffraction, i.e., the area of ​​the region to be observed, determines the size of the region. In this specification, the beam diameter of the electron beam is set to 1 Electron diffraction measured at wavelengths between nmΦ and 100 nmΦ is called nanobeam electron diffraction (NBED). This is called Nano Beam Electron Diffraction.

[0329] However, the crystallinity of the oxide semiconductor film of one embodiment of the present invention was evaluated by a method different from NBED. Examples of the method for evaluating the crystallinity of the oxide semiconductor film include electron diffraction, X-ray diffraction, and Among electron diffraction methods, in addition to the NBED mentioned above, there is also a transmission electron microscope. Transmission Electron Microscopy (TEM) , Scanning Electron Microscope (SEM) py), Convergent Beam Electron Diffraction (CBED) Selected Area Electron Diffraction (SAED) a Electron Diffraction) can be suitably used.

[0330] In addition, in NBED, the electron beam diameter is increased (for example, 25 nmΦ or less). Nanobeam electron diffraction (up to 100 nmΦ, or 50 nmΦ to 100 nmΦ) A ring-shaped pattern is observed. The ring-shaped pattern is also radially On the other hand, in NBED, the beam diameter of the electron beam is sufficiently small. In the electron beam diffraction pattern under the condition of minutely reduced size (for example, 1 nmΦ or more and 10 nmΦ or less), At the position of the ring-shaped pattern, a plurality of spots are distributed in the circumferential direction (also called the θ direction). In other words, the ripples observed under conditions where the electron beam diameter is increased may be observed. The ring-like pattern is formed by a collection of the above-mentioned multiple spots.

[0331] <2-4. Evaluation of crystallinity of oxide semiconductor film> Three samples in which oxide semiconductor films were formed under different conditions (samples X1 to X 3) were prepared and their crystallinity was evaluated. First, the preparation methods of samples X1 to X3 are as follows: explain.

[0332] [Sample X1] Sample X1 is a sample in which an oxide semiconductor film with a thickness of about 100 nm is formed on a glass substrate. The oxide semiconductor film contains indium, gallium, and zinc. The conditions for forming the nitride semiconductor film were as follows: the substrate was heated to 170° C. and an argon gas flow rate of 140 sccm was used. Gon gas and oxygen gas at a flow rate of 60 sccm were introduced into the chamber of the sputtering device. The pressure was 0.6 Pa, and a metal oxide target having indium, gallium, and zinc was A 2.5kW AC power was applied to the ZnO-based quartz crystal (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio in the preparation condition of sample X1 was 30%.

[0333] [Sample X2] Sample X2 is a sample in which an oxide semiconductor film with a thickness of about 100 nm is formed on a glass substrate. The oxide semiconductor film of sample X2 was formed under the following conditions: the substrate was heated to 130° C. and the flow rate was 18 Argon gas with a flow rate of 0 sccm and oxygen gas with a flow rate of 20 sccm were placed in the chamber of the sputtering device. The oxygen flow rate in the preparation condition of sample X2 was 10%. The conditions other than the substrate temperature and oxygen flow rate were the same as those for sample X1. It was decided.

[0334] [Sample X3] Sample X3 is a sample in which an oxide semiconductor film with a thickness of about 100 nm is formed on a glass substrate. The oxide semiconductor film of sample X3 was formed under the following conditions: the substrate was kept at room temperature (RT) and the flow rate was Argon gas at 180 sccm and oxygen gas at 20 sccm were used in the sputtering system. The oxygen flow rate in the preparation condition of sample X3 was 10%. The conditions other than the substrate temperature and oxygen flow rate are the same as those of the sample X1 described above. The conditions were:

[0335] Table 2 shows the formation conditions of samples X1 to X3.

[0336] [Table 2]

[0337] Next, the crystallinity of the samples X1 to X3 prepared as above was evaluated. The crystallinity of the samples was evaluated by cross-sectional TEM observation, XRD measurement, and electron diffraction.

[0338] [Cross-sectional TEM observation] 26 to 28 show the cross-sectional TEM observation results of samples X1 to X3. 6(A) and (B) are cross-sectional TEM images of sample X1, and Fig. 27(A) and (B) are cross-sectional images of sample X2. 28(A) and (B) are cross-sectional TEM images of sample X3.

[0339] FIG. 26(C) shows a high-resolution transmission electron microscope (HR-TEM) image of the cross section of sample X1. 27(C) is a cross-sectional HRTEM image of sample X2. FIG. 28(C) is a cross-sectional HR-TEM image of sample X3. For R-TEM image observation, spherical aberration correction (SCA) is required. A high-resolution TEM image using the spherical aberration correction function can be used. A Cs-corrected high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. Observation is performed using an atomic resolution analytical electron microscope such as JEM-ARM200F manufactured by Denshi Co., Ltd. It is possible.

[0340] As shown in FIGS. 26 and 27, in samples X1 and X2, atoms are layered in the film thickness direction. Crystals arranged in layers are observed. In particular, the HR-TEM image shows As shown in Figure 28, the atoms in sample X3 are layered in the film thickness direction. It is difficult to see how they are arranged in a straight line.

[0341] [XRD measurement] Next, the XRD measurement results of each sample will be described.

[0342] Figure 29(A) shows the XRD measurement results for sample X1, and Figure 30(A) shows the XRD measurement results for sample X2. FIG. 31(A) shows the XRD measurement results of sample X1 and sample X2.

[0343] In XRD measurement, the powder method (also called the θ-2θ method), which is a type of out-of-plane method, is used. The θ-2θ method involves changing the incidence angle of the X-rays and This is a method for measuring X-ray diffraction intensity by setting the angle of the detector to the same as the angle of incidence. The X-rays were incident at an angle of about 0.40° from the film surface, and the X-ray diffraction was measured by changing the detector angle. Grazing-Induced Reflection-Resonance (GIXRD) is an out-of-plane method for measuring the strength of Incidence XRD) method (also called thin film method or Seemann-Bohlin method) The vertical axis in FIG. 29(A), FIG. 30(A), and FIG. 31(A) is The diffraction intensity is shown in arbitrary units, and the horizontal axis indicates the angle 2θ.

[0344] As shown in FIG. 29(A) and FIG. 30(A), in the samples X1 and X2, 2θ A peak in the diffraction intensity is observed around =31°. In sample X3, the diffraction intensity peak near 2θ=31° is difficult to confirm, or The peak of the diffraction intensity around 31° is extremely small, or the diffraction intensity around 2θ=31° is There is no peak.

[0345] The diffraction angle at which the diffraction intensity peak was observed (around 2θ = 31°) was the same as that of single-crystal InGaZ This coincides with the diffraction angle of the (009) plane in the structure model of nO4. The above peaks were observed in sample X1 and sample X2, which indicates that the c-axis is oriented in the film thickness direction. The crystal portion having the c-axis orientation is also called the first crystal portion. It can be confirmed that sample X3 has a c-axis orientation from the XRD measurement. It is difficult to determine whether crystals are present.

[0346] [Electron diffraction] Next, the results of electron diffraction measurements performed on samples X1 to X3 will be described. In electron diffraction measurements, the electron beam is incident perpendicularly to the cross section of each sample. The pattern was acquired. The electron beam diameter was set to two values: 1 nmΦ and 100 nmΦ. .

[0347] In electron beam diffraction, not only the diameter of the incident electron beam but also the thickness of the sample is important. The more the electron beam diffraction pattern contains information about the depth direction, the more likely it is that the information will be accurate. In addition to reducing the electron beam diameter, the thickness of the sample in the depth direction can be reduced to obtain a better image. On the other hand, the thickness of the sample in the depth direction is too thin. In this case (for example, when the thickness of the sample in the depth direction is 5 nm or less), only information on extremely fine areas can be obtained. Therefore, if crystals exist in a very small area, the electron beam diffraction pattern obtained The pattern may be similar to that of a single crystal. If this is not the purpose, the thickness of the sample in the depth direction is set to, for example, 10 nm or more and 100 nm or less. Typically, it is preferably 10 nm or more and 50 nm or less.

[0348] 29(B)(C) show the electron diffraction patterns of sample X1, and FIG. 30(B)(C) shows the electron diffraction patterns of sample X2. The electron diffraction patterns of sample 2 are shown in Fig. 31(B) and (C) are shown in Fig. 31(C) and the electron diffraction patterns of sample X3 are shown in Fig. 31(D). Each is shown below.

[0349] In addition, the electrons shown in Figs. 29(B)(C), 30(B)(C), and 31(B)(C) The electron diffraction pattern was imaged with the contrast adjusted to make the electron diffraction pattern clear. 29(B)(C), 30(B)(C), and 31(B)( In C), the brightest spot in the center is due to the incident electron beam. This is the center of the line diffraction pattern (also called the direct spot or transmitted wave).

[0350] In addition, as shown in FIG. 29(B), when the diameter of the incident electron beam is set to 1 nmΦ, Since a plurality of spots distributed in a circumferential shape are observed, the oxide semiconductor film is extremely fine. It can be seen that multiple crystal parts with plane orientations in various directions are mixed. As shown in FIG. 29(C), when the diameter of the incident electron beam is 100 nmΦ, The diffraction spots from these multiple crystals are connected together, and the brightness is averaged to form a ring-shaped diffraction pattern. In addition, in Fig. 29(C), two ring-shaped The diffraction pattern can be confirmed. Here, from the smallest diameter, the first ring, the second ring, It can be seen that the first ring is brighter than the second ring. In addition, two spots of high brightness (first regions) are confirmed at the positions overlapping with the first ring. It is recognized.

[0351] The radial distance from the center of the first ring is This is almost equal to the radial distance from the center of the diffraction spot of the (009) plane in the The first region is a diffraction spot due to the c-axis orientation.

[0352] In addition, as shown in Figure 29(C), a ring-shaped diffraction pattern is observed, In the oxide semiconductor film, there are crystal parts oriented in various directions (hereinafter, referred to as crystal parts having no c-axis orientation). In other words, there exists a new crystal part (also called a new crystal part or a second crystal part).

[0353] The two first regions are arranged symmetrically with respect to the center point of the electron beam diffraction pattern. Since the degrees of symmetry are similar, it is inferred that the two-fold symmetry is present. The two first regions are diffraction spots due to the c-axis orientation. The direction of the line connecting the region and the center coincides with the direction of the c-axis of the crystal part. In the oxide semiconductor film, the c-axis is aligned in the film thickness direction. It can be seen that there are crystalline parts aligned in the same direction.

[0354] Thus, the oxide semiconductor film of sample X1 has a crystal part having a c-axis orientation and a It can be seen that the film is a mixture of crystalline parts having no crystals and crystalline parts having no crystals.

[0355] In the electron beam diffraction patterns shown in Figs. 30(B)(C) and 31(B)(C), The results are almost the same as those of the electron beam diffraction patterns shown in Fig. 29(B)(C). The brightness of the two spots (first region) due to the above is in the order of sample X1, sample X2, and sample X3. It is suggested that the abundance ratio of crystal parts having c-axis orientation is high in this order.

[0356] [Method for quantifying the crystallinity of oxide semiconductor films] Next, an example of a method for quantifying the crystallinity of an oxide semiconductor film will be described with reference to FIGS. He explains.

[0357] First, an electron beam diffraction pattern is prepared (see FIG. 32(A)).

[0358] Note that in FIG. 32A, the beam diameter is 100 nm for a 100-nm-thick oxide semiconductor film. FIG. 32(B) shows the electron diffraction pattern measured at mΦ. This is an electron beam diffraction pattern after contrast adjustment of the diffraction pattern.

[0359] In FIG. 32(B), two clear spots (first area) are visible above and below the direct spot. These two spots (first region) are the structural model of InGaZnO4. The diffraction spots corresponding to (00l) in the model, i.e., the crystal parts with c-axis orientation, On the other hand, apart from the first region, there is a region of low luminance approximately concentric with the first region. A red ring-shaped pattern (second region) appears overlapping the electron beam. By setting the diameter to mΦ, the structure of the crystal part (second crystal part) that does not have the c-axis orientation was The intensity of the spots is averaged to form a ring.

[0360] Here, the electron beam diffraction pattern shows diffraction spots due to crystal parts having c-axis orientation. The first region having a diffraction spot due to the second crystal portion and the second region having a diffraction spot due to the second crystal portion are overlapped. Therefore, a line profile including the first region and a line profile including the second region are observed. By acquiring and comparing line profiles, the crystallinity of the oxide semiconductor film can be quantified. It becomes.

[0361] First, a line profile including a first region and a line profile including a second region This will be explained with reference to FIG.

[0362] Figure 33 shows the structure model of InGaZnO4 irradiated with an electron beam from the (100) plane. The simulated electron diffraction pattern obtained when the sample was irradiated with the electron beam was divided into two parts: area A-A' and area B- 13B' and area C-C' are indicated with auxiliary lines.

[0363] The region A-A' shown in FIG. 33 shows two diffraction patterns caused by the first crystal part having the c-axis orientation. The area B-B' shown in FIG. In the region C-C', a diffraction spot due to the first crystal part having c-axis orientation was observed. The area includes the straight line passing through the direct spot and the area not covered by the direct spot. The angle at which it intersects with B' or area C-C' is around 34°, specifically, between 30° and 38° Preferably, the angle is 32° or more and 36° or less, and more preferably, 33° or more and 35° or less. Good.

[0364] Note that the line profile has a gradient as shown in FIG. 34 depending on the structure of the oxide semiconductor film. Figure 34 shows the image of the line profile for each structure, the relative brightness R, and the half-width (FWHM) of the spectrum due to the c-axis orientation obtained from the electron diffraction pattern. 1 is a diagram explaining the width at half maximum.

[0365] The relative luminance R shown in FIG. 34 is the integral intensity of the luminance in the area A-A' relative to the area B -B' divided by the integral intensity of the luminance in the region C-C' The integrated intensity of the luminance in the areas A-A', B-B', and C-C' is The background brightness caused by the direct spot appearing at the center position is excluded. It has been removed.

[0366] By calculating the relative brightness R, the strength of the c-axis orientation can be quantitatively determined. For example, as shown in FIG. 34, in a single crystal oxide semiconductor film, the c-axis alignment in the region A-A′ is The peak intensity of the diffraction spot due to the first crystal part having the orientation is high, and the regions B-B' and In the region C-C', no diffraction spots due to the first crystal part with c-axis orientation were observed. Therefore, the relative brightness R exceeds 1 and becomes extremely large. Only AAC (details on CAAC will be described later), CAAC+Nanocrystal In particular, the order of the crystal orientation is For amorphous and nanocrystals, the relative luminance R is 1. .

[0367] In addition, the higher the periodicity of the crystal structure, the greater the spatial distribution of the first crystal part with c-axis orientation. The spectrum intensity becomes higher and the half-width of the spectrum becomes smaller. The price range is the smallest, CAAC only, CAAC+Nanocrystal, Nanocrystal The half-width increases in the order of stal, and the half-width is very large in amorphous. The profile will be called Hello.

[0368] [Line profile analysis] As described above, the integral intensity of the luminance in the first region and the integral intensity of the luminance in the second region The intensity ratio is important information in terms of estimating the proportion of oriented crystal parts.

[0369] Therefore, from the electron beam diffraction patterns of the samples X1 to X3 shown above, the line profile Analysis was performed using the FT-IR ...

[0370] The line profile analysis results of sample X1 are shown in Fig. 35 (A1) and (A2), and sample X2 The line profile analysis results are shown in Figure 35 (B1) and (B2), and the line profile of sample X3 is shown. The profile analysis results are shown in Figures 35(C1) and (C2), respectively.

[0371] FIG. 35(A1) shows the electron beam diffraction pattern of the region A-A' and the region FIG. 35(B1) is an electron diffraction pattern showing the region B-B' and the region C-C'. In the electron beam diffraction pattern shown in FIG. 30(C), there are a region A-A', a region B-B', and a region C- FIG. 35(C1) is the electron diffraction pattern shown in FIG. 31(C). Electron diffraction pattern showing areas A-A', B-B', and C-C' It's a pattern.

[0372] In addition, the regions A-A', B-B', and C-C' are electron beam diffraction patterns. This can be calculated by normalizing the brightness of the direct spot that appears at the center of the This also allows relative comparisons to be made between samples.

[0373] In addition, when calculating the brightness profile, the brightness caused by inelastic scattering from the sample, etc. Subtracting the components as background allows for more accurate comparisons. Here, the brightness component due to inelastic scattering has a very broad profile in the radial direction. To obtain the image, the brightness of the background may be calculated by linear approximation. Draw straight lines along both sides of the peak, and then select the area on the lower brightness side of the lines. can be subtracted as background.

[0374] Here, the area A-A' is calculated from the data after background subtraction using the method described above. The integrated intensity of the luminance in the regions A, B-B', and C-C' was calculated. The integral intensity of the luminance in the region B-B' or the region C The relative luminance R was calculated by dividing the luminance at -C' by the integrated intensity.

[0375] FIG. 36 shows the relative luminance R of samples X1 to X3. The direct intensities in the luminance profiles shown in Figs. 35(A2), 35(B2), and 35(C2) are The integrated intensity of the brightness in the region A-A' in the spectrum located to the left and right of the spot is divided by the integrated intensity of the brightness in the region B-B', and the product of the brightness in the region A-A' The individual intensities were calculated by dividing the individual intensities by the integrated intensity of brightness in the region C-C'.

[0376] As shown in FIG. 36, the relative luminance of samples X1 to X3 is as follows: Relative luminance of sample X1 R=25.00 Relative luminance of sample X2 R=3.04 Relative luminance of sample X3 R=1.05 The above-mentioned relative luminance R was the average value at the four positions. Thus, the relative luminance R is The order of increasing is sample X1, sample X2, and sample X3.

[0377] The oxide semiconductor film of one embodiment of the present invention is used as a semiconductor film in which a channel of a transistor is formed. In the case where the light source is a reflective film, the relative luminance R is more than 1 and not more than 40, preferably more than 1 and not more than 10, and In this case, it is preferable to use an oxide semiconductor film having an intensity ratio of more than 1 and not more than 3. By using such an oxide semiconductor film as a semiconductor film, the electrical characteristics are highly stable and the gate voltage is It is possible to achieve both high field effect mobility in a low pressure region.

[0378] <2-5. Crystalline fraction> The proportion of crystals in an oxide semiconductor film can be estimated by analyzing cross-sectional TEM images. can be done.

[0379] First, the method of image analysis will be described. A two-dimensional fast Fourier transform (FFT) was performed on the TEM image. The FFT image is then processed to obtain a periodic image. Then, masking is performed to remove the rest of the range. The masked FFT image is Then, perform a two-dimensional inverse Fourier transform (IFFT: Inverse Fast Fourier Transform transform) to obtain an FFT filtered image.

[0380] This allows a real space image to be obtained in which only the crystal part is extracted. The proportion of the crystalline part can be estimated from the area ratio of the area used in the calculation. By subtracting the remaining area from the area of ​​the original image (also called the area of ​​the original image), the area other than the crystal part is The proportion of these parts can be estimated.

[0381] FIG. 37(A1) shows a cross-sectional TEM image of sample X1, and FIG. 37(A2) shows a cross-sectional TEM image of sample X1. The images obtained after image analysis of the images are shown in Fig. 37(B1). The cross-sectional TEM image of sample X2 was obtained after image analysis in FIG. 37(B2). The cross-sectional TEM image of sample X3 is shown in FIG. 37(C1), and the cross-sectional TEM image of sample X2 is shown in FIG. ) show the images obtained after image analysis of the cross-sectional TEM image of sample X3.

[0382] In the image obtained after image analysis, the white areas in the oxide semiconductor film are The areas shown in black correspond to areas containing crystalline parts with orientation, and do not have orientation. It corresponds to a region containing crystalline parts or crystalline parts oriented in various directions.

[0383] From the results shown in FIG. 37(A2), the region including the crystalline part having orientation in the sample X1 is The proportion of the removed area was about 43.1%. In addition, from the results shown in FIG. 37(B2), sample X The proportion of the area excluding the region containing the oriented crystal parts in No. 2 was approximately 61.7%. In addition, from the results shown in FIG. 37(C2), the region including the crystalline part having orientation in sample X3 The proportion of the area excluding the abovementioned areas was approximately 89.5%.

[0384] The proportion of the portion excluding the crystalline portion having the orientation in the oxide semiconductor film estimated in this manner When the ratio is 5% or more and less than 40%, the oxide semiconductor film has extremely high crystallinity. In this case, oxygen vacancies are unlikely to occur, and the electrical properties are very stable, which is preferable. The proportion of the portion other than the crystalline portion having orientation in the solid film is 40% or more and less than 100%, preferably When the ratio of the oriented crystal portion to the oriented crystal portion is 60% or more and 90% or less, the oxide semiconductor film has an oriented crystal portion and an oriented crystal portion. The appropriate proportion of non-crystalline portions ensures both stable electrical properties and high mobility. It is possible.

[0385] Here, it can be clearly confirmed by a cross-sectional TEM image or by image analysis of the cross-sectional TEM image. The region excluding the crystal part is called the Lateral Growth Buffer Region. It can also be called on(LGBR).

[0386] <2-6. Oxygen diffusion into oxide semiconductor films> Next, the results of evaluation of the ease of diffusion of oxygen into the oxide semiconductor film will be described.

[0387] Here, the following three samples (samples Y1 to Y3) were prepared.

[0388] [Sample Y1] First, a 50 nm thick oxide film was formed on a glass substrate using the same method as for sample X1. Next, a silicon oxynitride film with a thickness of about 30 nm was formed on the oxide semiconductor film. A silicon oxide nitride film with a thickness of about 100 nm, a silicon oxide nitride film with a thickness of about 20 nm, In the following description, the oxide semiconductor The silicon oxynitride film may be referred to as OS, and the silicon oxynitride film may be referred to as GI.

[0389] Next, a heat treatment was performed at 350° C. for 1 hour in a nitrogen atmosphere.

[0390] Then, a 5 nm thick In-Sn-Si oxide film was formed by sputtering.

[0391] Subsequently, oxygen was added to the silicon oxynitride film under the following conditions: Using an ashing device, the substrate temperature was set to 40°C and oxygen gas ( 16 O ) and oxygen gas with a flow rate of 100 sccm ( 18 O) was introduced into the chamber, and the pressure was increased to 15 The parallel parallel plate was installed in the ashing device so that a bias was applied to the substrate side. RF power of 4500 W was supplied between the electrodes of the plate for 600 seconds. 1 8 The reason for using oxygen (O) is that the silicon oxynitride film 16 O) at the principal component level This is to accurately measure the oxygen added by the oxygen addition process. do.

[0392] Subsequently, a silicon nitride film having a thickness of about 100 nm was formed by plasma CVD.

[0393] [Sample Y2] Sample Y2 is a sample in which the deposition conditions of the oxide semiconductor film of Sample Y1 are different. In the same manner as in the case of sample X2 described above, an oxide semiconductor film having a thickness of about 50 nm was formed. .

[0394] [Sample Y3] Sample Y3 is a sample obtained by changing the deposition conditions of the oxide semiconductor film of Sample Y1. In the same manner as in the case of sample X3 described above, an oxide semiconductor film having a thickness of about 50 nm was formed. .

[0395] Through the above steps, samples Y1 to Y3 were prepared.

[0396] [SIMS analysis] For Samples Y1 to Y3, SIMS (Secondary Ion Mass Spectroscopy) Spectrometry (Spectrometry) analysis 18 The concentration of O was measured. In this study, the samples Y1 to Y3 prepared above were evaluated without heat treatment, and The conditions for heat treatment of samples Y1 to Y3 at 350° C. for 1 hour under a nitrogen atmosphere and sample Y The three conditions are: 1) heat treatment of samples Y1 to Y3 at 450° C. for 1 hour under a nitrogen atmosphere; The matter was decided as follows.

[0397] SIMS measurement results are shown in Fig. 38(A), (B), and (C). Note that Fig. 38(A) is for sample Y FIG. 38(B) is the SIMS measurement result of sample Y1, FIG. 38(C) is the SIMS measurement result of sample Y2, and FIG. 8(C) shows the SIMS measurement result of sample Y3.

[0398] In addition, Fig. 38(A), (B), and (C) show the analysis results of the region including GI and OS. In addition, Figure 38 (A), (B), and (C) show SIMS analysis (SSDP (S Surface Side Depth Profile (SIMS) Here are the results.

[0399] In addition, in Figure 38(A), (B), and (C), the gray dashed lines indicate the samples that were not heat-treated. The black dashed line is the profile of the sample that was heat treated at 350°C. The black solid line is the profile of the sample that was heat treated at 450°C.

[0400] In each of samples Y1 to Y3, 18 O is diffused, and During the OS 18 It can be seen that O is diffused. In addition, samples Y1, Y2, and Y3 In order, to deeper positions 18 It can be seen that O is diffused. By performing heat treatment at 450℃, the area can be penetrated to a deeper position. 18 It was confirmed that O was spreading. Cut.

[0401] From the above results, it is considered that oriented and non-oriented crystal parts are mixed and that the orientation is not important. An oxide semiconductor film having a low ratio of crystal parts having a low oxygen permeability is a film through which oxygen easily permeates. It can be confirmed that the film is one in which oxygen easily diffuses. It can be confirmed that oxygen in the GI film diffuses into the OS by performing the treatment.

[0402] The above results indicate that the higher the proportion (density) of oriented crystals, the greater the amount of oxygen in the thickness direction. This indicates that oxygen is less likely to diffuse in the thickness direction, and that the lower the density, the easier it is for oxygen to diffuse in the thickness direction. The ease of diffusion of oxygen in an oxide semiconductor film can be considered as follows. Cut.

[0403] An oxide semiconductor that contains a mixture of oriented crystal parts and extremely fine crystal parts that do not have orientation. In the membrane, the non-crystalline regions (LGBR) that can be clearly observed in the cross-sectional observation image are oxygen-rich regions. The oxide semiconductor film is a region where oxygen can easily diffuse, i.e., it can become a diffusion path for oxygen. When there is a sufficient oxygen source nearby, the crystals are oriented through the LGBR. It is believed that oxygen vacancies in the film can be reduced because oxygen is easily supplied to the film. can be.

[0404] For example, an oxide film that is in contact with an oxide semiconductor film and that easily releases oxygen is provided, and heat treatment is performed. As a result, the oxygen released from the oxide film is transported in the thickness direction of the oxide semiconductor film by the LGBR. Then, oxygen is supplied laterally to the oriented crystal part via the LGBR. As a result, the crystal part having the orientation of the oxide semiconductor film and the other region can be formed. Therefore, oxygen is sufficiently distributed in the film, and oxygen vacancies in the film can be effectively reduced.

[0405] For example, if hydrogen atoms that are not bonded to metal atoms exist in the oxide semiconductor film, When oxygen atoms bond with the metal, OH is formed and the metal is fixed. Hydrogen atoms were trapped in oxygen vacancies (Vo) in the oxide semiconductor film by forming the film at low temperature. state (called VoH) by a certain amount (for example, 1×10 17 cm -3 By forming O H is suppressed from being generated. In addition, VoH generates carriers, so A certain amount of carriers are present in the film. This results in an oxide film with an increased carrier density. During the film formation, oxygen vacancies are also formed, but the oxygen The defects can be reduced by introducing oxygen through the LGBR as described above. By using this method, the carrier density is relatively high and oxygen vacancies are sufficiently reduced. An oxide semiconductor film can be formed.

[0406] In addition, the regions other than the crystalline portions having orientation are extremely fine crystals that do not have orientation during film formation. Since the oxide semiconductor film is made up of crystalline regions, no clear crystal grain boundaries can be observed. The fine crystal parts are located between a plurality of crystal parts having orientation. The heat from the crystallization causes the crystals to grow laterally, bonding with adjacent crystals that have the same orientation. The fine crystals also function as regions for generating carriers. When an oxide semiconductor film having such a structure is used in a transistor, the field-effect mobility thereof is significantly improved. It is believed that this will significantly improve the

[0407] In addition, an oxide semiconductor film is formed, and an oxide insulating film such as a silicon oxide film is formed thereon. It is preferable to carry out a plasma treatment in an oxygen atmosphere after the deposition. In addition to supplying oxygen to the gas, the hydrogen concentration can be reduced. For example, plasma treatment During the process, fluorine remaining in the chamber may be doped into the oxide semiconductor film. Fluorine exists as negatively charged fluorine atoms and as positively charged water molecules. The electrons bond with the atomic atoms through Coulomb forces to generate HF, which is then oxidized during the plasma treatment. As a result, the hydrogen concentration in the oxide semiconductor film is reduced. In addition, oxygen atoms and hydrogen atoms are bonded to form H2O during plasma processing. It may also be released outside the membrane.

[0408] In addition, a structure in which a silicon oxide film (or a silicon oxynitride film) is laminated on an oxide semiconductor film The fluorine in the silicon oxide film bonds with the hydrogen in the film, forming an electrically neutral H Since it can exist as F, it does not affect the electrical properties of the oxide semiconductor film. Although bonds may occur, these are also electrically neutral. Also, HF in the silicon oxide film is It is believed that there is no effect on oxygen diffusion.

[0409] Due to the above-described mechanism, oxygen vacancies in the oxide semiconductor film are reduced, and By reducing hydrogen that is not bonded to metal atoms, reliability can be improved. In addition, when the carrier density of the oxide semiconductor film is higher than a certain level, the electrical characteristics are improved. It is expected to rise.

[0410] <2-7. Method for forming oxide semiconductor film> A method for forming an oxide semiconductor film according to one embodiment of the present invention will be described below.

[0411] The oxide semiconductor film of one embodiment of the present invention can be formed by sputtering in an oxygen-containing atmosphere. The film can be formed by the above method.

[0412] The substrate temperature during film formation is from room temperature to 150° C., preferably from 50° C. to 150° C. More preferably, the temperature is 100° C. or higher and 150° C. or lower, typically 130° C. By setting the temperature of the substrate within the above range, it is possible to separate crystalline parts having orientation and crystalline parts not having orientation. The ratio of the crystal portion to the crystal portion can be controlled.

[0413] In addition, the flow rate ratio of oxygen (oxygen partial pressure) during film formation is set to 1% or more and less than 33%, preferably 5% or less. More preferably, the ratio is 5% to 20%, and even more preferably, the ratio is 5% to 15%. The oxygen flow rate is preferably set to 10% or less. This allows the film to contain more crystal parts that do not have the crystal structure.

[0414] Therefore, by setting the substrate temperature during film formation and the oxygen flow rate during film formation within the above ranges, the orientation It is possible to obtain an oxide semiconductor film in which crystal parts having orientation and crystal parts not having orientation are mixed. In addition, by setting the substrate temperature and oxygen flow rate within the above ranges, it is possible to obtain crystals having an orientation. It is possible to control the ratio of crystal parts and crystal parts not having orientation.

[0415] As an oxide target that can be used for forming an oxide semiconductor film, In-Ga- The oxides are not limited to Zn-based oxides, but may be, for example, In-M-Zn-based oxides (where M is Al, Ga, Y, or or Sn) can be applied.

[0416] In addition, a sputtering target including a polycrystalline oxide having a plurality of crystal grains is used, When an oxide semiconductor film including a crystal portion is formed, a polycrystalline oxide film is formed. Compared with the case where a thin sputtering target is used, a crystalline oxide semiconductor film can be obtained. It is easy to be.

[0417] The following is a consideration of the mechanism of oxide semiconductor film formation. The ring target has a plurality of crystal grains, and the crystal grains have a layered structure, If the crystal grains have an interface that is easily cleaved, the sputtering target is By colliding with the ion, the crystal grains are cleaved and form plate- or pellet-shaped sputtered particles. The resulting plate-like or pellet-like sputtered particles may be deposited on a substrate. It is believed that an oxide semiconductor film containing nanocrystals is formed by depositing the oxide semiconductor film on the substrate. By heating the plate, the nanocrystals bond or rearrange on the substrate surface. It is believed that by using the above-mentioned method, an oxide semiconductor film including oriented crystal parts is easily formed. can be done.

[0418] Although the method of forming the film by sputtering has been described here, The sputtering method is preferred because it is easy to control the crystallinity. In addition to the laser deposition method, other methods such as pulsed laser deposition (PLD) and plasma enhanced chemical vapor deposition (PEC) are also available. VD) method, thermal CVD (Chemical Vapor Deposition) method, AL D (Atomic Layer Deposition) method, vacuum deposition method, etc. An example of a thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). One example is the cal vapor deposition (Cal Vapor Deposition) method.

[0419] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0420] (Embodiment 3) In this embodiment, an example of a display device including a semiconductor device according to one embodiment of the present invention will be described. The following description will be given with reference to FIGS. 39 to 46.

[0421] 39 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 39, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0422] The display device 700 is surrounded by a sealant 712 on the first substrate 701. A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 705 are arranged in a region different from the region. and an FPC terminal portion 708 (FPC: Flexible Printed Circuit portion) electrically connected to each of the circuit portions 706. In addition, the FPC terminal portion 70 is provided with a flexible printed circuit. 8, an FPC 716 is connected to the pixel section 702, the source driver Various signals and the like are supplied to the circuit portion 704 and the gate driver circuit portion 706. 702, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal Signal lines 710 are connected to the respective units 708. Signals and the like are transmitted through a signal line 710 to the pixel section 702, the source driver circuit section 704, the gate It is provided to a driver circuit section 706 and an FPC terminal section 708 .

[0423] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0424] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit section 706 includes a plurality of transistors.

[0425] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (light-emitting elements that emit light according to electric current) transistors, electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Rowetting element, plasma display panel (PDP), MEMS (microelectromechanical systems) Electro-mechanical systems) displays (e.g., grating light bars) GLV, Digital Micromirror Device (DMD), Digital Microsha Dispersive Modulation (DMS) element, Interferometric Modulation (IMOD) element ), piezoelectric ceramic displays, etc.

[0426] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductio n Electron-emitter Display) and others. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink elements or electrophoretic elements include: Electronic paper. Semi-transmissive LCDs and reflective LCDs are also used. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0427] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB form one color element, and different two colors are generated depending on the color element. You can also select colors to configure the color. Or, you can select one or more colors such as yellow, cyan, and magenta for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used in monochrome display devices. The present invention can also be applied to display devices.

[0428] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0429] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts the light into red, green, and blue by filtering the light, A method that uses two colors of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method for converting to green (color conversion method, quantum dot method) may be applied.

[0430] In this embodiment, a liquid crystal element and an EL element are used as display elements. 40 to 42. Note that FIGS. 40 and 41 are diagrams showing the chain reaction of the one-dot chain shown in FIG. FIG. 1 is a cross-sectional view taken along line QR, showing a configuration in which a liquid crystal element is used as a display element. 42 is a cross-sectional view taken along the dashed line QR in FIG. 39, and shows a display device using an EL element as a display element. This is the configuration used.

[0431] First, the common parts shown in Figures 40 to 42 will be explained, and then the different parts will be explained. This will be explained below.

[0432] <3-1. Explanation of common parts of display devices> A display device 700 shown in FIGS. 40 to 42 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0433] Transistor 750 and transistor 752 are similar to transistor 100B shown above. The structures of the transistors 750 and 752 are the same as those described above. Other transistors shown in the embodiment of the present invention may be used.

[0434] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. It is possible to extend the retention time of electrical signals such as signals, and the write interval can be extended when the power is on. This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. It has the effect of suppressing power.

[0435] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0436] The capacitor 790 includes a conductive film that functions as a first gate electrode of the transistor 750. The lower electrode formed through a process of processing the same conductive film and the Through a process of processing the same conductive film as the conductive film that functions as the source electrode and the drain electrode, and an upper electrode formed on the lower electrode. A step of forming an insulating film identical to the insulating film functioning as the first gate insulating film of 750. The insulating film formed through the above process is the same as the insulating film that functions as a protective insulating film for the transistor 750. The insulating film is formed through a process of forming a first insulating film. 790 is a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. do.

[0437] 40 to 42, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0438] 40 to 42, a transistor 750 and a A transistor having the same structure as the transistor 752 included in the source driver circuit portion 704 is used. The configuration used is illustrated above, but is not limited to this. For example, A transistor different from that in the driver circuit section 704 may be used. A top-gate transistor is used for the source driver circuit section 702, and a bottom-gate transistor is used for the source driver circuit section 704. A structure using a bottom-gate transistor in the pixel portion 702. The source driver circuit section 704 is configured to use a top-gate type transistor. The source driver circuit section 704 may be referred to as a gate driver circuit section. It may be read differently.

[0439] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing this material are used, signal delays caused by wiring resistance are minimal, making it possible to display images on a large screen. It becomes Noh.

[0440] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0441] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0442] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0443] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0444] <3-2. Configuration examples of display devices using liquid crystal elements> The display device 700 shown in FIG. 40 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0445] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770. The pixel electrode functions as one electrode of the display element.

[0446] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum Alternatively, a material containing silver may be used.

[0447] In the case where a conductive film having a reflectivity to visible light is used as the conductive film 772, the display device 700 has the following characteristics: The liquid crystal display device is a reflective type. In this case, the display device 700 becomes a transmissive liquid crystal display device.

[0448] In addition, by changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. 41. The display device 700 shown in FIG. This is an example of a configuration using a horizontal electric field method (e.g., FFS mode) as a driving method. In the structure shown in FIG. 1, an insulating film 773 is provided over a conductive film 772, and a conductive film In this case, the conductive film 774 is used as a common electrode. The insulating film 773 functions as a conductive film between the conductive film 772 and the conductive film 774. The alignment state of the liquid crystal layer 776 can be controlled by the field.

[0449] Although not shown in FIGS. 40 and 41, the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the liquid crystal layer 776. Although not shown in FIG. 40 and FIG. 41, a polarizing member, a phase difference member, a reflecting member, etc. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may be used. Either may be used.

[0450] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0451] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational angle and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the occurrence of defects or damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0452] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electro-Oelectric Liquid Crystal mode can be used. .

[0453] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0454] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 42 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0455] Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, In addition, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Cadmium (Cd), selenium (Se), Zinc (Zn), Sulfur (S), Phosphorus (P), Indium (In), Tellurium (Te), Lead (P b) Quantum with elements such as gallium (Ga), arsenic (As), aluminum (Al), etc. Dot material may also be used.

[0456] The organic compounds and inorganic compounds described above can be prepared by deposition (including vacuum deposition), for example. The method includes the droplet ejection method (also called the inkjet method), the coating method, the gravure printing method, etc. The EL layer 786 can be formed using a low molecular weight material, a medium molecular weight material (O The polymer may comprise a polymeric material, such as a dendrimer or oligomer.

[0457] Here, a method for forming the EL layer 786 by using a droplet discharge method will be described with reference to FIG. 43(A) to 43(D) are cross-sectional views illustrating a method for manufacturing the EL layer 786. be.

[0458] First, a conductive film 772 is formed over a planarization insulating film 770. An insulating film 730 is formed as shown in FIG. 43(A).

[0459] Next, a droplet is discharged from a droplet discharge device 783 to an exposed portion of the conductive film 772, which is an opening in the insulating film 730. Droplets 784 are ejected to form a layer 785 containing the composition. The droplets 784 are a mixture of the composition containing a solvent. and is attached onto the conductive film 772 (see FIG. 43B).

[0460] The step of discharging the droplets 784 may be performed under reduced pressure.

[0461] Next, the solvent is removed from the layer 785 containing the composition, and the layer is solidified to form an EL layer 786. (See FIG. 43(C)).

[0462] The solvent may be removed by a drying step or a heating step.

[0463] Next, a conductive film 788 is formed on the EL layer 786 to form a light-emitting element 782 (FIG. 43( See D).

[0464] In this way, when the EL layer 786 is formed by the droplet discharge method, the composition can be selectively discharged. This reduces material loss. Since no additional steps are required, the process can be simplified and costs can be reduced.

[0465] The droplet discharge method described above is a method of discharging a composition using a nozzle having a discharge port, or using one or more is a general term for anything that has a means for ejecting droplets, such as a head having multiple nozzles.

[0466] Next, a droplet discharge device used in the droplet discharge method will be described with reference to FIG. 14 is a conceptual diagram illustrating a droplet ejection device 1400. FIG.

[0467] The droplet discharge device 1400 includes a droplet discharge means 1403. 3 has a head 1405 and a head 1412.

[0468] The head 1405 and the head 1412 are connected to a control means 1407, which controls a computer. By controlling the laser 1410, it is possible to draw a pre-programmed pattern. can.

[0469] The timing of drawing may be, for example, marker 1 formed on the substrate 1402. Alternatively, the reference point may be determined based on the outer edge of the substrate 1402. Here, the marker 1411 is detected by the imaging means 1404, and the image processing means 1 The signal converted to a digital signal by 409 is recognized by a computer 1410 and a control signal is generated. The generated signal is sent to the control means 1407.

[0470] The imaging means 1404 may be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor ( An image sensor using a CMOS (Complementary Metal Oxide Semiconductor) can be used. The information of the pattern to be formed on the substrate is stored in the storage medium 1408. Based on this, a control signal is sent to the control means 1407, and each head 1 of the droplet ejection means 1403 is controlled. The material to be discharged is supplied from the material supply source 1. 413, a material supply source 1414 is connected to the head 1405 and the head 1412 through piping. will be supplied.

[0471] The inside of the head 1405 is a space for filling the liquid material as shown by the dotted line 1406, and a space for discharging the material. The head 1412 has a nozzle as an outlet. The head 1405 and the head 1412 have the same internal structure. By providing a single head, different materials can be printed at different widths at the same time. It is possible to discharge multiple types of luminescent materials and perform drawing on a wide area. In order to improve throughput, the same material is ejected from multiple nozzles at the same time to create a pattern. When a large substrate is used, the head 1405 and the head 1412 move over the substrate as shown in FIG. 4. Freely scan in the directions of the X, Y, and Z arrows shown in the figure to freely set the area to be drawn. This allows the same pattern to be written multiple times on a single substrate.

[0472] The step of discharging the composition may be carried out under reduced pressure. After the composition is discharged, one or both of the steps of drying and baking are performed. Both processes are heat treatment processes, but the purpose, temperature and time are different. The drying and firing processes are carried out under normal or reduced pressure by irradiation with laser light, instantaneous thermal annealing, or heating. The timing of the heat treatment and the number of times the heat treatment is performed are not particularly limited. In order to perform the drying and baking processes well, the temperature at which they are performed should be adjusted according to the material and composition of the substrate. It depends on the nature of the composition.

[0473] As described above, the EL layer 786 can be manufactured using a droplet discharge apparatus.

[0474] The display device 700 shown in FIG. 42 will now be described.

[0475] In addition, in the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 772. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 772 and the conductive film 788; It can also be applied to al-emission structures.

[0476] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0477] <3-4. Example of a configuration in which an input / output device is provided on a display device> Moreover, the display device 700 shown in FIG. 41 and FIG. 42 may be provided with an input / output device. An example of the force device is a touch panel.

[0478] A configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 41 is shown in FIG. 45 and FIG. FIG. 46 shows a configuration in which a touch panel 791 is provided on a display device 700.

[0479] FIG. 45 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. FIG. 46 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0480] First, the touch panel 791 shown in FIGS. 45 and 46 will be described below.

[0481] The touch panel 791 shown in FIG. 45 and FIG. 46 is provided between a substrate 705 and a colored film 736. The touch panel 791 is a so-called in-cell type touch panel. 736 may be formed on the substrate 705 side before the colored film 736 is formed.

[0482] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as a stylus approaches, the mutual capacitance between electrode 793 and electrode 794 changes. It is possible to detect the change.

[0483] In addition, an electrode 793 and a transistor 750 shown in FIGS. The electrode 796 is formed by passing through an opening in the insulating film 795. The electrode 794 is electrically connected to the two electrodes 793 that sandwich the electrode 794 via the electrodes 793. 46 illustrates a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702. However, the present invention is not limited to this. For example, the light emitting diode 704 may be formed in the source driver circuit section 704.

[0484] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 46, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By this configuration, the electrode 793 does not block the light emitted by the light emitting element 782. Alternatively, the electrode 793 may be configured so as not to block light passing through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may be of a similar configuration.

[0485] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 may be made of a metal material having a low transmittance of visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, In addition, a metal material having a low transmittance of visible light can be used.

[0486] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the electrodes 793 and The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0487] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, and more preferably 5 nm or more and 25 nm or less. The wires are metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, electrodes 664, 665, 6666, or a wire or a carbon nanotube may be used. When Ag nanowires are used for either 65 or 667 or for all of them, the The light transmittance is to be 89% or more, and the sheet resistance is to be 40Ω / □ or more and 100Ω / □ or less. can.

[0488] 45 and 46 show an example of the configuration of an in-cell type touch panel. However, the present invention is not limited to this. For example, a so-called on-cell type transistor formed on the display device 700 may be used. A so-called out-cell type touch panel that is attached to the display device 700. It is also possible to use the following.

[0489] In this manner, the display device according to one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0490] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0491] (Embodiment 4) In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described. The transistor shown in the embodiment is suitable for miniaturization.

[0492] <4-1. Examples of transistor configurations suitable for miniaturization> FIG. 47 illustrates an example of a transistor 200. FIG. 47A illustrates the transistor 200. The top view is shown. Note that some of the films are omitted in FIG. 47(A) for clarity. FIG. 47(B) is a cross-sectional view corresponding to the dashed line X1-X2 shown in FIG. 47(A). FIG. 47C is a cross-sectional view corresponding to Y1-Y2.

[0493] The transistor 200 includes a conductor 205 (conductor 205a, and conductor 205b), and conductor 260 (conductor 260a and conductor 260b). , an insulator 220 serving as a gate insulating layer, an insulator 222, an insulator 224, and an insulator The oxide semiconductor 230 (oxide semiconductor 23) has a region in which a channel is formed. 0a, oxide semiconductor 230b, and oxide semiconductor 230c), and a source or drain A conductor 240a functions as one of the source and drain, and a conductor 240b functions as the other of the source and drain. and an insulator 280 having excess oxygen.

[0494] The oxide semiconductor 230 includes an oxide semiconductor 230a and an oxide layer on the oxide semiconductor 230a. The first and second oxide semiconductors 230a and 230b are electrically connected to each other via a first insulating film 230c. When the transistor 200 is turned on, a current flows mainly through the oxide semiconductor 230b. On the other hand, the oxide semiconductor 230a and the oxide semiconductor 230c are In the vicinity of the interface with the oxide semiconductor 230b (which may be a mixed region), a current does not flow. In some cases, the insulating region may act as an insulator, while other regions may act as an insulator.

[0495] In the structure shown in FIG. 47, the conductor 260 functioning as the gate electrode is a conductor 260a. The layer structure has a conductor 260b and a conductor 260c. 60 has an insulator 270 thereon.

[0496] The conductor 205 may be selected from the group consisting of molybdenum, titanium, tantalum, tungsten, aluminum, copper, A metal film containing an element selected from chromium, neodymium, and scandium, or Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) Indium tin oxide, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide with tin oxide, Indium oxide with titanium oxide, Titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide doped with silicon oxide Conductive materials such as oxides may also be applied.

[0497] For example, the conductor 205a may be a conductor having a barrier property against hydrogen, such as titanium nitride. For the conductor 205b, tungsten having high conductivity may be laminated. By using this combination, it is possible to obtain an oxide semiconductor 23 while maintaining the electrical conductivity of the wiring. 47, the conductor 205a and Although a two-layer structure of the conductor 205b is shown, the present invention is not limited to this configuration, and may be a single layer or a laminate of three or more layers. The structure may also be used.

[0498] The insulator 220 and the insulator 224 are made of a material such as a silicon oxide film or a silicon oxynitride film. It is preferable that the insulator contains oxygen. In particular, the insulator 224 contains excess oxygen (chemical It is preferable to use an insulator that contains oxygen in excess of the stoichiometric composition. By providing an insulator containing oxygen in contact with the oxide that constitutes the transistor 200, The insulator 220 and the insulator 224 can compensate for the oxygen vacancies in the oxide. They do not necessarily have to be made of the same material.

[0499] The insulator 222 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, zirconium titanate Lead (PZT), Strontium Titanate (SrTiO3) or (Ba,Sr)TiO3 It is preferable to use an insulator such as (BST) in a single layer or laminated form. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide Addition of titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide Alternatively, these insulators may be nitrided. Silicon oxynitride or silicon nitride may be used in a laminated form.

[0500] The insulator 222 may have a laminated structure of two or more layers. However, the present invention is not limited to a laminated structure made of the above-mentioned materials, and may be a laminated structure made of different materials.

[0501] Between the insulator 220 and the insulator 224, there is an insulator 222 including a high-k material. This allows the insulator 222 to capture electrons under certain conditions, increasing the threshold voltage. That is, the insulator 222 may become negatively charged.

[0502] For example, the insulators 220 and 224 are made of silicon oxide, and the insulator 222 is made of , materials with many electron capture levels such as hafnium oxide, aluminum oxide, and tantalum oxide. When used in a semiconductor device, the temperature is higher than the operating temperature or storage temperature (e.g., 125 The electric conductor 205 is heated at a temperature of 150° C. or higher and 450° C. or lower, typically 150° C. or higher and 300° C. or lower. The potential of the source electrode and drain electrode is kept higher than that of the drain electrode for 10 milliseconds or more, typically 1 minute. By maintaining the above, the oxide constituting the transistor 200 is At this time, some of the moving electrons are captured by the electron capture level of the insulator 222. will be done.

[0503] A transistor in which the necessary number of electrons are captured in the electron capture level of the insulator 222 reaches a threshold The voltage shifts to the positive side. Note that the voltage of the conductor 205 can be controlled to capture electrons. The amount of the charge can be controlled, and the threshold voltage can be controlled accordingly. By having this, the transistor 200 is in a non-conducting state (off) even when the gate voltage is 0V. The transistor is a normally-off type transistor in which the on-state is turned on.

[0504] The electron capture process may be performed during the manufacturing process of a transistor. After formation of a conductor that connects to the source or drain conductor of the transistor, or After the front-end process (wafer processing) or after the wafer dicing process, packaging This should be done at some stage before shipping from the factory, such as after the product is shipped.

[0505] In addition, by appropriately adjusting the film thicknesses of the insulators 220, 222, and 224, It is possible to control the voltage to a low level. In addition, it is possible to provide a transistor having stable electrical characteristics. Alternatively, a transistor with a large on-state current can be provided. It is possible to provide a transistor with a small threshold swing value. This makes it possible to provide a highly reliable transistor.

[0506] The oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are In It is formed of metal oxides such as -M-Zn oxide (M is Al, Ga, Y, or Sn). In addition, the oxide semiconductor 230 may be an In—Ga oxide or an In—Zn oxide.

[0507] The insulator 250 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, zirconium titanate Lead (PZT), Strontium Titanate (SrTiO3) or (Ba,Sr)TiO3 Insulators such as (BST) can be used in a single layer or laminate. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide Addition of titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide Alternatively, these insulators may be nitrided. Silicon nitride or a laminate of silicon nitrides may be used.

[0508] In addition, as the insulator 250, similar to the insulator 224, a material having a stoichiometric composition other than oxygen is used. It is preferable to use an oxide insulator containing as much oxygen as possible. By providing the insulator in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 are reduced. can be reduced.

[0509] The insulator 250 may be aluminum oxide, aluminum oxynitride, gallium oxide, or oxide. Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, oxynitride By using an insulating film with barrier properties against oxygen and hydrogen, such as hafnium or silicon nitride, When such a material is used, oxygen release from the oxide semiconductor 230 can be prevented. It functions as a layer that prevents the leakage of hydrogen and other impurities from the outside.

[0510] Note that the insulator 250 has the same multilayer structure as the insulators 220, 222, and 224. The insulator 250 may have a layer structure. By having an insulator, the threshold voltage of the transistor 200 is shifted to the positive side. With this configuration, the transistor 200 can be In this case, the transistor is a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the transistor is turned on.

[0511] In the semiconductor device illustrated in FIG. 47 , A barrier film may be provided in addition to the insulator 250. Alternatively, a barrier film may be provided on the oxide semiconductor 230c. It is also possible to use materials that have a high

[0512] For example, an insulating film containing excess oxygen is provided in contact with the oxide semiconductor 230, and a barrier film is provided. By wrapping the oxide, the oxide is in a state where the composition is almost stoichiometric, or The oxide semiconductor 230 can be in a supersaturated state with a higher oxygen content than the composition. This can prevent the intrusion of impurities such as oxygen.

[0513] One of the conductors 240a and 240b functions as a source electrode and the other It functions as a drain electrode.

[0514] The conductor 240a and the conductor 240b are made of aluminum, titanium, chromium, nickel, Copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, etc. The metal or alloy containing this metal as the main component can be used. However, a laminated structure of two or more layers may be used.

[0515] For example, a titanium film and an aluminum film may be laminated. A two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film. A two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, It may have a two-layer structure.

[0516] In addition, a titanium film or titanium nitride film and an alumina film are laminated on the titanium film or titanium nitride film. An aluminum film or a copper film is laminated, and then a titanium film or a titanium nitride film is formed on the aluminum film or a copper film. A three-layer structure consisting of a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum or copper film is layered on top of the molybdenum film, and then a molybdenum film or Indium oxide, tin oxide or molybdenum nitride are also used. Alternatively, a transparent conductive material containing zinc oxide may be used.

[0517] The conductor 260 having the function of a gate electrode is made of, for example, aluminum, chromium, A metal selected from copper, tantalum, titanium, molybdenum, and tungsten, or the above-mentioned gold The alloy may be made of an alloy containing the above metals or a combination of the above metals. In addition, the present invention uses a metal selected from one or more of manganese and zirconium. Also, a semiconductor such as polycrystalline silicon doped with an impurity element such as phosphorus may be used. Alternatively, a silicide such as nickel silicide may be used.

[0518] For example, a two-layer structure may be used in which a titanium film is laminated on an aluminum film. A two-layer structure in which a titanium film is laminated on a tungsten film, and a two-layer structure in which a tungsten film is laminated on a titanium nitride film A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. It may also be of this structure.

[0519] In addition, a titanium film is laminated on the titanium film, an aluminum film is laminated on the titanium film, and a titanium film is laminated on the aluminum film. There are also three-layer structures that form a film. A composite material made of one or more metals selected from the group consisting of tin, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film having a combination of these or a nitride film may be used.

[0520] The conductor 260 may be made of indium tin oxide, indium oxide containing tungsten oxide, or the like. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide Add indium tin oxide, indium zinc oxide, and silicon oxide containing titanium oxide. A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the light-transmitting conductive material and the above metal may also be used.

[0521] The conductor 260a is formed by using a thermal CVD method, an MOCVD method, or an ALD method. , using the atomic layer deposition (ALD) method. It is preferable to form the insulating layer 250 by using the ALD method or the like. It can reduce damage caused by Zuma. It can also improve coverage. In this case, it is preferable to form the conductor 260a by the ALD method or the like. A transistor 200 may be provided.

[0522] The conductor 260b is made of conductive material such as tantalum, tungsten, copper, or aluminum. It is formed using high quality materials.

[0523] Further, an insulator 270 is provided so as to cover the conductor 260. Oxygen is released from the insulator 280. When an oxide material is used, the conductor 260 is prevented from being oxidized by the desorbed oxygen. To achieve this, the insulator 270 is made of a material that has a barrier property against oxygen.

[0524] For example, the insulator 270 may be a metal oxide such as aluminum oxide. The insulator 270 may be provided to an extent that prevents the conductor 260 from being oxidized. For example, the thickness of the insulator 270 is 1 nm or more and 10 nm or less, preferably 3 nm or more and 7 nm or less. It is set as below.

[0525] Therefore, the oxidation of the conductor 260 is suppressed, and the oxygen desorbed from the insulator 280 is efficiently oxidized. The semiconductor layer 230 may be made of a fluorine-containing material.

[0526] Above the transistor 200, an insulator 280 is provided. The insulator 280 has a stoichiometric It is preferable to use an oxide containing more oxygen than satisfies the objective composition. The insulator 280 has a region where oxygen is present in excess of the stoichiometric composition (hereinafter, referred to as the excess oxygen region). In particular, the transistor 200 is preferably formed with an oxide semiconductor In this case, an insulator having an oxygen excess region is provided in an interlayer film near the transistor 200. By providing the insulating layer, the oxygen vacancies in the transistor 200 are reduced, thereby improving the reliability. This can be done.

[0527] As an insulator having an excess oxygen region, specifically, an oxide insulator in which a part of oxygen is released by heating is used. It is preferable to use a nitride material.

[0528] For example, such a material may include silicon oxide or silicon oxynitride. It is preferable to use a metal oxide. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0529] Also, the insulator 280 covering the transistor 200 is a flat surface that covers the uneven shape underneath. It may also function as a protective film.

[0530] <4-2. Application examples of transistors suitable for miniaturization> An example in which transistors having different compositions are stacked will be described below.

[0531] The semiconductor device shown in FIG. 48 includes a transistor 400, a transistor 200, and a capacitor. It has element 410.

[0532] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 200 is small, the transistor 200 can be used as a semiconductor device (memory By using this in a memory device, it is possible to retain memory contents for a long period of time. Semiconductor devices that do not require refresh operations or require refresh operations very infrequently Since it is possible to use the device as a semiconductor device (memory device), power consumption can be sufficiently reduced. Cut.

[0533] As shown in FIG. 48, the semiconductor device includes a transistor 400, a transistor 200, and a capacitance element. The transistor 200 is provided above the transistor 400, and the capacitance element The transistor 410 is disposed above the transistor 400 and the transistor 200 .

[0534] The transistor 400 is provided on a substrate 401, and includes a conductor 406, an insulator 404, and a substrate 402. A semiconductor region 402 consisting of a part of 401 and functioning as a source region or a drain region. The semiconductor device has a low resistance region 408a that is capable of resisting a current and a low resistance region 408b that is capable of resisting a current.

[0535] Transistor 400 can be either p-channel or n-channel.

[0536] A region in which a channel of the semiconductor region 402 is formed, a region in the vicinity thereof, a source region, or In the low resistance region 408a which becomes the drain region, and the low resistance region 408b, etc., It is preferable that the semiconductor material contains a silicon-based semiconductor, and it is preferable that the semiconductor material contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide) It may be made of materials such as gallium aluminum arsenide (GaAlAs) or Silicon with effective mass controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, GaAs and GaAlAs may be used to form a transistor. The Sta 400 is a HEMT (High Electron Mobility Transistor) stor) may also be used.

[0537] The low resistance region 408a and the low resistance region 408b are formed by applying a semiconductor In addition to the conductive material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The material contains an element that imparts electrical conductivity to the mold.

[0538] The conductor 406 that functions as a gate electrode is made of arsenic, phosphorus, or the like that imparts n-type conductivity. An element, or a semiconductor material such as silicon that contains an element that gives it p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. .

[0539] In addition, the threshold voltage can be adjusted by determining the work function depending on the conductor material. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, tungsten or aluminum is used as the conductor. It is preferable to use metal materials such as tungsten as the lamination layer. This is preferable from the viewpoint of thermal stability.

[0540] Note that the transistor 400 shown in FIG. 48 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0541] Covering the transistor 400 are an insulator 420, an insulator 422, an insulator 424, and an insulator 426. The edge members 426 are stacked in order.

[0542] The insulators 420, 422, 424, and 426 may be, for example, an acid. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0543] The insulator 422 serves to eliminate a step caused by the transistor 400 and the like provided below. The top surface of the insulator 422 is chemically treated to improve the planarization. Mechanical polishing (CMP) method The surface may be planarized by a planarization process using a polishing agent or the like.

[0544] The insulator 424 may include a transistor 400, a substrate 401, or a transistor 400. A film having a barrier property to prevent hydrogen and impurities from diffusing into the region where the resistor 200 is provided. It is preferable to use:

[0545] For example, silicon nitride formed by CVD is an example of a film that has a barrier property against hydrogen. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. When hydrogen diffuses into a semiconductor element, the characteristics of the semiconductor element may deteriorate. A film that suppresses hydrogen diffusion is used between the transistor 200 and the transistor 400. Specifically, the film that suppresses hydrogen diffusion is a film that desorbs a small amount of hydrogen. do.

[0546] It is preferable that the insulator 426 has a lower dielectric constant than the insulator 424. For example, The dielectric constant of the insulator 426 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 424 is preferably 0.7 times or less than the relative dielectric constant of the insulator 426, and more preferably 0.6 times or less. It is more preferable to use a material with a low dielectric constant as the interlayer film to reduce the parasitic capacitance between wirings. It can be reduced.

[0547] In addition, the insulators 420, 422, 424, and 426 are provided with a capacitance element. 410, or a conductor 428 electrically connected to the transistor 200, and a conductor 43 0 and the like are embedded. Note that the conductor 428 and the conductor 430 are plugs or wiring. It has a function as a line. As will be described later, a conductor that has a function as a plug or wiring In some cases, multiple structures may be collectively designated by the same symbol. Alternatively, the wiring and the plug electrically connected to the wiring may be integrated. In some cases, a part of the conductor functions as a wiring, and in other cases, a part of the conductor functions as a plug. do.

[0548] The materials of the plugs and wiring (the conductor 428, the conductor 430, etc.) are metal. Conductive materials such as metals, alloys, metal nitrides, or metal oxides are applied in a single layer or in a Materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use any high melting point material, and it is preferable to use tungsten. It is preferable to form the conductive member from a low resistance material such as aluminum or copper. By using this material, the wiring resistance can be reduced.

[0549] The conductor 428 and the conductor 430 are made of a conductor having a barrier property against hydrogen. In particular, the opening in the insulator 424 having a barrier property against hydrogen is preferably In the above structure, a conductor having a barrier property against hydrogen is formed. The transistor 400 and the transistor 200 can be separated by a barrier layer, and the transistor 4 Diffusion of hydrogen from the first insulating layer 00 to the transistor 200 can be suppressed.

[0550] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 400 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating material 424 has a structure in which the insulating material 424 is in contact with the insulating material 424 having a thickness of 100 .mu.m or less.

[0551] A wiring layer may be provided over the insulator 426 and the conductor 430. For example, as shown in FIG. 8, an insulator 450, an insulator 452, and an insulator 454 are stacked in this order. In addition, a conductor 456 is formed in the insulator 450, the insulator 452, and the insulator 454. The conductor 456 functions as a plug or a wiring. 6 can be provided using the same material as the conductor 428 and the conductor 430.

[0552] The conductor 456 is preferably made of a low resistance conductive material such as aluminum or copper. It is preferable to use a low-resistance conductive material to reduce the wiring resistance. When copper is used for the body 456, it is preferable to laminate it with a conductor that suppresses the diffusion of copper. Conductive materials that suppress copper diffusion include tantalum, tantalum nitride, and other tantalum-containing materials. It is preferable to use alloys, ruthenium, and alloys containing ruthenium.

[0553] Also, for example, the insulator 450 may be used to suppress the diffusion of copper or to provide resistance to oxygen and hydrogen. It is preferable to use an insulator having a barrier property that suppresses the diffusion of copper. As an example, silicon nitride can be used. Therefore, the same material as the insulator 424 can be used. It can be used.

[0554] In particular, the insulator 450 that suppresses copper diffusion is in contact with an opening that the insulator 450 has, and the insulator 450 suppresses copper diffusion. It is preferable to provide a conductor that suppresses the diffusion of copper, and to laminate copper on the conductor. This structure can suppress the diffusion of copper to the periphery of the wiring.

[0555] On the insulator 454, an insulator 458, an insulator 210, an insulator 212, and an insulator 21 are arranged. 4 are stacked in order. The insulating layer 214 or any of the insulating layers 212 may be formed to suppress copper diffusion or to resist oxygen and hydrogen. It is preferable to use a material having a barrier property.

[0556] The insulator 458 and the insulator 212 may include, for example, the substrate 401 or the transistor 4 00 to the region where the transistor 200 is to be provided. Alternatively, it is preferable to use a film having a barrier property that prevents diffusion of hydrogen or impurities. Therefore, materials similar to the insulator 424 can be used.

[0557] The insulator 210 may be made of the same material as the insulator 420. For example, The edge 210 may be a silicon oxide film, a silicon oxynitride film, or the like.

[0558] For example, the insulator 214 may be made of aluminum oxide, hafnium oxide, or tantalum oxide. It is preferable to use a metal oxide such as

[0559] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that does not allow impurities such as oxygen and moisture to pass through the membrane. Aluminum oxide is highly resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 200. This can suppress the release of oxygen from the oxide that constitutes the 00. It is suitable for use as a protective film for the capacitor 200.

[0560] On the insulator 214, an insulator 216 is provided. The insulator 216 has a structure similar to that of the insulator 420. For example, the insulator 216 may be a silicon oxide film or a silicon oxynitride film. A silicon film or the like can be used.

[0561] Also, the insulator 458, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 The conductive material 218 and the conductive material 205 constituting the transistor 200 are embedded in the insulating layer 214. Note that the conductor 218 is electrically connected to the capacitor 410 or the transistor 400. The conductor 218 functions as a plug or wiring for connecting the conductor 428 and the The conductive material 430 may be used for the conductive material 430 .

[0562] In particular, the insulator 458, the insulator 212, and the conductor 218 in the area in contact with the insulator 214. is a conductive material that suppresses copper diffusion or has barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 400 and the transistor 200 are preferably the same. is a layer that suppresses copper diffusion or has barrier properties against oxygen, hydrogen, and water. In other words, the diffusion of copper from the conductor 456 is suppressed, and the The diffusion of hydrogen from the transistor 400 to the transistor 200 can be suppressed.

[0563] Above the insulator 214, a transistor 200 and an insulator 280 are provided. In addition, the transistor 200 shown in FIG. 48 is only an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0564] On the insulator 280, an insulator 282, an insulator 284, and an insulator 470 are laminated in this order. In addition, the insulators 220, 222, 224, and 280 are provided. The conductor 244 and the like are embedded in the insulator 282, the insulator 284, and the insulator 470. In addition, the conductors 240a and 240b of the transistor 200 A conductor 245 and the like are provided on the conductor 244 to connect to the conductors in the upper layer. The capacitor 410, the transistor 200, or a transistor electrically connected to the transistor 400 The conductor 244 functions as a lug or wiring. It can be provided using the same material as 30.

[0565] In addition, either or both of the insulator 282 and the insulator 284 may have a resistance to oxygen and hydrogen. It is preferable to use a material having a barrier property for the insulator 282. The insulator 284 may be made of the same material as the insulator 212. The following materials can be used.

[0566] For example, the insulator 282 may be made of aluminum oxide, hafnium oxide, tantalum oxide, or the like. It is preferred to use metal oxides.

[0567] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that does not allow impurities such as oxygen and moisture to pass through the membrane. Aluminum oxide is highly resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 200. This can suppress the release of oxygen from the oxide that constitutes the 00. It is suitable for use as a protective film for the capacitor 200.

[0568] The insulator 284 is provided between a region where the capacitor 410 is provided and a region where the transistor 200 is provided. It is preferable to use a film having a barrier property to prevent diffusion of hydrogen and impurities in the region. Therefore, a material similar to that of the insulator 424 can be used.

[0569] For example, silicon nitride formed by CVD is an example of a film that has a barrier property against hydrogen. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. When hydrogen diffuses into a semiconductor element, the characteristics of the semiconductor element may deteriorate. A film that suppresses hydrogen diffusion is used between the transistor 200 and the transistor 400. Specifically, the film that suppresses hydrogen diffusion is a film that desorbs a small amount of hydrogen. do.

[0570] Therefore, the transistor 200 and the insulator 280 containing the excess oxygen region are treated as insulator 21. 0, a laminated structure of the insulator 212 and the insulator 214, and an insulator 282 and an insulator 284 The insulating material 210, the insulating material 212, and the insulating material 213 may be sandwiched between the insulating material 210, the insulating material 212, and the insulating material 213. The insulator 214, the insulator 282, and the insulator 284 are resistant to oxygen or hydrogen, water, and other gases. It has barrier properties that suppress the diffusion of impurities.

[0571] The oxygen released from the insulator 280 and the transistor 200 is transferred to the capacitor element 410 or Alternatively, it is possible to suppress diffusion into the layer in which the transistor 400 is formed. Alternatively, hydrogen and This can prevent impurities such as oxygen and water from diffusing into the transistor 200.

[0572] In other words, oxygen is efficiently drawn from the excess oxygen region of the insulator 280 to the transistor 200. This can supply oxygen to the oxide in which the channel is formed, thereby reducing oxygen vacancies. The oxide in which the channel of the transistor 200 is formed has oxygen vacancies due to impurities. Therefore, the channel of the transistor 200 is prevented from being formed. The oxide thus obtained can be an oxide semiconductor having a low density of defect states and stable characteristics. In other words, the fluctuation of the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved. It can be done.

[0573] A capacitor 410 and a conductor 474 are provided above the insulator 470. The capacitance element 410 is provided on an insulator 470, and includes a conductor 462, an insulator 480, and an insulator 470. 82, an insulator 484, and a conductor 466. Note that the conductor 474 is a capacitive element. a plug electrically connecting the transistor 410, the transistor 200, or the transistor 400; Or it has a function as wiring.

[0574] The conductor 462 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum that are both heat-resistant and conductive are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the insulating layer simultaneously with other structures, low-resistance metal materials such as copper and aluminum can be used. Good.

[0575] Note that the conductor 474 is formed using a material similar to that of the conductor 462 which functions as an electrode of the capacitor. It can be established as follows.

[0576] On the conductor 474 and the conductor 462, an insulator 480, an insulator 482, and an insulator The insulators 480, 482, and 484 are made of, for example, silicon oxide. Con, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxynitride Aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, oxynitride Hafnium, hafnium oxynitride, hafnium nitride, etc. may be used. Although a layered structure is described, a single layer, two layers, or a laminated structure of four or more layers may also be used.

[0577] For example, the insulator 480 and the insulator 484 may be made of a material having a high dielectric strength such as silicon oxynitride. The insulator 484 is made of a high-k material such as aluminum oxide. A laminated structure is formed by using a material with high dielectric strength such as silicon oxynitride. With this configuration, the capacitance element 410 is preferably made of a high-dielectric (high-k) insulator. By having a high dielectric strength, sufficient capacity can be secured, and by having an insulator with a high dielectric strength, The resistance is improved, and electrostatic damage to the capacitance element 410 can be suppressed.

[0578] A conductive material is provided on the conductive material 462 through an insulator 480, an insulator 482, and an insulator 484. The conductor 466 is made of a metal material, an alloy material, or a metal oxide material. Conductive materials such as tungsten and molybdenum, which are both heat-resistant and conductive, can be used. It is preferable to use a high melting point material such as buten, and particularly preferable to use tungsten. In addition, when forming the conductor and other structures at the same time, low-resistance metal materials such as copper and Aluminum or the like may be used.

[0579] For example, as shown in FIG. 48, insulator 480, insulator 482, and insulator 484 may be The conductor 466 is provided so as to cover the upper surface and the side surface of the conductor 462. 80, an insulator 482, and an insulator 484 are provided to cover the top and sides of the conductor 462. It shall be set up as follows.

[0580] In other words, the side surface of the conductor 462 also functions as a capacitance. It is possible to increase the capacitance per unit area. This allows the area of ​​semiconductor devices to be reduced, and the integration density to be increased. Miniaturization becomes possible.

[0581] An insulator 460 is provided on the conductor 466 and the insulator 484. The insulator 60 can be formed using a material similar to that of the insulator 420. The covering insulator 460 may function as a planarizing film that covers the underlying irregularities.

[0582] The above is a description of the application example.

[0583] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0584] (Embodiment 5) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0585] <5. Circuit configuration of display device> The display device shown in FIG. 49(A) has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0586] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0587] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0588] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0589] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0590] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0591] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0592] The protection circuit 506 shown in FIG. 49(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0593] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0594] As shown in FIG. 49A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be done like this.

[0595] In FIG. 49(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0596] In addition, the pixel circuits 501 shown in FIG. 49(A) may have a configuration shown in FIG. 49(B), for example. It can be said that:

[0597] The pixel circuit 501 shown in FIG. 49B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0598] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0599] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0600] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G L_m. The transistor 550 can be turned on or off. Thus, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0601] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0602] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0603] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0604] In addition, the pixel circuits 501 shown in FIG. 49(A) may be, for example, a configuration shown in FIG. It can be said that:

[0605] The pixel circuit 501 shown in FIG. 49C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0606] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0607] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0608] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0609] The capacitor 562 functions as a storage capacitor for storing written data.

[0610] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0611] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0612] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0613] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0614] In a display device having the pixel circuit 501 of FIG. 49(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0615] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0616] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0617] (Embodiment 6) In this embodiment, the circuit configuration to which the transistors described in the above embodiment can be applied is An example will be described with reference to FIGS.

[0618] <6. Example of inverter circuit configuration> FIG. 50(A) shows a circuit that can be applied to a shift register, a buffer, etc. in a driver circuit. 8 shows a circuit diagram of an inverter 800 that can convert the logic of a signal provided to an input terminal IN into a The inverter 800 outputs an inverted signal of the OS transistors to the output terminal OUT. Signal S BG is a signal that can switch the electrical properties of an OS transistor. The number is.

[0619] FIG. 50B is an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using only complementary metal-oxide semiconductor (CMOS) transistors, Y Metal Oxide Semiconductor inverter (CMOS inverter) It is possible to manufacture the device at a lower cost than manufacturing a conventional inverter.

[0620] The inverter 800 having OS transistors is made of Si transistors. The inverter 800 can be placed on the CMOS circuit. Therefore, an increase in the circuit area due to the addition of the inverter 800 can be suppressed.

[0621] The OS transistors 810 and 820 each have a first gate functioning as a front gate and a back gate. The second gate acts as a gate electrode and the first gate acts as either a source or a drain. It has one terminal and a second terminal that functions as the other of the source or drain.

[0622] The first gate of the OS transistor 810 is connected to the second terminal. The second gate of 10 is the signal S BG The OS transistor 810 is connected to a wiring that supplies The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The input terminal is connected to the output terminal OUT.

[0623] A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. The GND is connected to a wire that supplies

[0624] FIG. 50C is a timing chart for explaining the operation of the inverter 800. In the timing chart of Figure 50(C), the signal waveform of the input terminal IN and the output terminal OUT Signal waveform, signal S BG 8 and the change in the threshold voltage of the OS transistor 810. This shows the following:

[0625] signal S BG to the second gate of the OS transistor 810. The threshold voltage of 810 can be controlled.

[0626] signal S BGis the voltage V for shifting the threshold voltage negatively. BG_A ,threshold Voltage V for positively shifting the voltage BG_B The second gate has a voltage V BG_A By providing TH_A negative shift to Also, the second gate can be connected to the voltage V BG_B By providing The threshold voltage V TH_B can be shifted positively to

[0627] To visualize the above explanation, Figure 51(A) shows one of the electrical characteristics of a transistor. 1 shows an Id-Vg curve.

[0628] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A of By increasing the value so as to shift the curve to the curve represented by the dashed line 840 in FIG. The electrical characteristics of the OS transistor 810 can be expressed as follows: Voltage V BG_B By making it smaller, the curve represented by the solid line 841 in FIG. As shown in FIG. 51A, the OS transistor 810 can be signal S BG Voltage V BG_A Or voltage V BG_B By switching like this, The threshold voltage can be shifted positively or negatively.

[0629] Threshold voltage V TH_B By shifting the OS transistor The capacitor 810 can be made to have a state in which it is difficult for current to flow. Visualize and show.

[0630] As shown in FIG. 51B, a current I B Extremely small Therefore, when the signal applied to the input terminal IN is high level, the OS trans When the resistor 820 is in the ON state, it causes the voltage at the output terminal OUT to drop sharply. can be done.

[0631] As shown in FIG. 51B, the current flowing through the OS transistor 810 is difficult. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 831 can be changed sharply. Since the through current flowing between the wiring that supplies S can be reduced, it is possible to achieve low power consumption. The action can be performed.

[0632] Also, the threshold voltage is V TH_A By shifting it negatively, the OS The transistor 810 can be made to be in a state in which a current can easily flow. The state is visualized. As shown in FIG. 51(C), the current I A Less At least current I B Therefore, the signal applied to the input terminal IN can be When the OS transistor 820 is in an off state (OFF) at a low level, the voltage of the output terminal OUT As shown in FIG. 51(C), the OS transistor Since the current flowing through 810 can be made to flow easily, the type shown in FIG. This allows the signal waveform 832 at the output terminal in the timing chart to be changed sharply.

[0633] In addition, signal SBG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of register 820 changes, i.e., before time T1 or T2. For example, as shown in FIG. 50(C), when the signal applied to the input terminal IN is high level, Before the time T1 when the transistor switches to the TH_A From the threshold voltage V TH _B It is preferable to change the threshold voltage of the OS transistor 810 in FIG. As shown in FIG. 0(C), the signal applied to the input terminal IN is switched to a low level at time T Before 2, the threshold voltage V TH_B to threshold voltage V TH_A OS transistor It is preferable to switch the threshold voltage of 810.

[0634] In the timing chart of FIG. 50(C), the signal changes according to the signal applied to the input terminal IN. No. S BG However, other configurations may be used. For example, the threshold voltage is The control voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. As shown in (A).

[0635] In FIG. 52A, in addition to the circuit configuration shown in FIG. 50B, an OS transistor 850 The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (or Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No. S FThe second gate of the OS transistor 850 is connected to a wiring that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wire that provides the

[0636] The operation of FIG. 52(A) will be described with reference to the timing chart of FIG. 52(B).

[0637] A voltage for controlling the threshold voltage of the OS transistor 810 is applied to the input terminal IN. The second gate of OS transistor 810 is turned on before time T3 when the signal The signal S F is set to a high level to turn on the OS transistor 850. In this state, node N BG Voltage V for controlling the threshold voltage BG_B Gives.

[0638] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The threshold voltage V BG_B It is possible to hold Therefore, the second gate of the OS transistor 850 is supplied with a voltage V BG_B The number of actions to give is reduced. Therefore, the voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0639] In the circuit configurations in FIGS. 50B and 52A, the second We have shown a configuration in which the voltage applied to the gate is controlled from outside, but we will also consider other configurations. For example, a signal for controlling the threshold voltage may be applied to the input terminal IN. and provided to the second gate of the OS transistor 810. FIG. 53A shows an example of a circuit configuration that can realize the above configuration.

[0640] In FIG. 53(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810.

[0641] The operation of FIG. 53(A) will be described with reference to the timing chart of FIG. 53(B). In the timing chart of Figure 53(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the output waveform IN_C of the OS transistor 810. The change in threshold voltage is shown.

[0642] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is This can be a signal that controls the threshold voltage of the transistor 810. As described in FIG. 51A to FIG. 51C, the threshold voltage of the OS transistor 810 is controlled. For example, at time T4 in FIG. 53(B), the signal applied to the input terminal IN is When the signal is at a high level, the OS transistor 820 is turned on. B is at a low level. Therefore, the OS transistor 810 is in a state where it is difficult for a current to flow. This allows the voltage at the output terminal OUT to drop sharply.

[0643] At time T5 in FIG. 53(B), the signal applied to the input terminal IN becomes low. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be in a state where a current easily flows. This allows the voltage at the output terminal OUT to rise sharply.

[0644] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal applied to IN. The OUT voltage can be changed sharply. This allows the current to be reduced, thereby enabling low power consumption.

[0645] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0646] (Embodiment 7) In this embodiment, the transistor including the oxide semiconductor described in the above embodiment ( An example of a semiconductor device using an OS transistor in a plurality of circuits is shown in FIG. 7 will be used to explain.

[0647] <7. Circuit configuration example of semiconductor device> FIG. 54A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0648] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, It is acceptable to use multiple voltages instead of a single voltage. Voltage V ORG From the outside of the semiconductor device 900 The semiconductor device 900 can generate the voltage V1 based on the voltage V2 given from the outside. Based on a single power supply voltage, the voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0649] Circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is the voltage V ORG and voltage V SS (V ORG >V SS ) and applied based on The power supply voltage for the circuit 904 is, for example, a voltage V POG and voltage V SS (V POG >V ORG ) is applied based on the power supply voltage of the circuit 906. is the voltage V ORG and voltage V SS and voltage V NEG (V ORG >V SS >V NEG ) and based on is the voltage applied. Note that the voltage V SS If we consider it to be equal to the ground potential (GND), then Therefore, the number of types of voltages generated by the power supply circuit 901 can be reduced.

[0650] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG Therefore, The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage provided from the outside. It can be made.

[0651] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG Therefore, The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage provided from the outside. It can be made.

[0652] Figure 54(B) shows the voltage V POG FIG. 54(C) shows an example of a circuit 904 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0653] FIG. 54B shows a transistor 911. The signal to be applied is, for example, a voltage V POG and voltage V SS The signal is generated based on the When the transistor 911 is in the conductive state, the voltage V POG , voltage when in non-conducting state V SS Let the voltage V POG As shown in FIG. 54(C), the voltage V ORG Bigger Therefore, the transistor 911 has a more reliable connection between the source (S) and the drain (D). As a result, the circuit 904 can be a circuit with reduced malfunction. Cut.

[0654] Figure 54(D) shows the voltage V NEG FIG. 54(E) shows an example of a circuit 906 that operates in accordance with the 4 is an example of a waveform of a signal for operating the

[0655] FIG. 54D shows a transistor 912 having a back gate. The signal applied to the gate of the transistor 912 is, for example, a voltage V ORG and voltage V SS Generated based on The signal is a voltage V ORG , Non-guided When the voltage V SS Also, the back of the transistor 912 The signal applied to the gate is voltage V NEG It is generated based on the voltage V NEG Figure 54(E) As shown in the figure, the voltage V SS (GND). Therefore, the The threshold voltage can be controlled to be positively shifted. 12 can be made non-conductive more reliably, and the source (S) and drain (D) can be made As a result, the circuit 906 has reduced malfunctions and low power consumption. It is possible to provide a circuit with improved power.

[0656] In addition, the voltage V NEG can also be applied directly to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. Alternatively, a signal that corresponds to the back gate of the transistor 912 may be generated and provided to the back gate of the transistor 912. good.

[0657] Moreover, Figures 55(A) and (B) show modified examples of Figures 54(D) and (E).

[0658] In the circuit diagram shown in FIG. 55(A), a control circuit is provided between a voltage generating circuit 905 and a circuit 906. A transistor 922 whose conduction state can be controlled by a path 921 is shown. The control signal S output from the control circuit 921 is an n-channel OS transistor. BG is a signal for controlling the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors similar to transistor 922.

[0659] In the timing chart of FIG. 55(B), the control signal S BG The change in potential of the transformer The state of the potential of the back gates of the transistors 912A and 912B is BG The change in potential is shown by Control signal S BG When the voltage is high, the transistor 922 is turned on, and the node N BG is the voltage V NEG Then, the control signal S BG When is low, node N B G The transistor 922 is an OS transistor. Therefore, the off-current is small. BG Even if is electrically floating, Once the voltage V is applied NEG can be held.

[0660] FIG. 56A shows an example of a circuit configuration that can be applied to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. The charge pump has five stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SSand is applied based on If we consider this as a voltage, then by applying a clock signal CLK, the voltage V ORG Five times more positive The boosted voltage V POG In addition, the forward direction of the diodes D1 to D5 can be obtained. The voltage is set to 0 V. Also, by changing the number of stages of the charge pump, the desired voltage V P OG can be obtained.

[0661] FIG. 56B shows an example of a circuit configuration that can be applied to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. The charge pump has four stages including C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and is applied based on If we consider it as a voltage, then by applying a clock signal CLK, the SS to voltage V ORG The voltage V is stepped down to a negative voltage four times higher than the NEG You can get it. The forward voltage of the diodes D1 to D5 is set to 0 V. By changing the number, the desired voltage V NEG can be obtained.

[0662] The circuit configuration of the voltage generating circuit 903 described above corresponds to the circuit configuration shown in FIG. For example, modified examples of the voltage generating circuit 903 are shown in FIGS. The voltage generating circuit 903 may be modified as shown in FIG. In the circuits 903A to 903C, the voltage applied to each wiring may be changed, or the elements This can be achieved by changing the arrangement of the

[0663] The voltage generating circuit 903A shown in FIG. 57A includes transistors M1 to M10, a capacitor The clock signal CLK is supplied to the transistors C11 to C14 and the inverter INV1. The gates of the transistors M1 to M10 are supplied directly or through an inverter INV1. By applying a clock signal CLK, the voltage V ORG is boosted to four times the positive voltage Voltage V POG By changing the number of stages, the desired voltage V POG The voltage generating circuit 903A shown in FIG. By using OS transistors for M11 to M10, the off-state current can be reduced. This can suppress leakage of the charge stored in C14. Therefore, the voltage V ORG to voltage V POG It is possible to boost the voltage to

[0664] The voltage generating circuit 903B shown in FIG. 57B includes transistors M11 to M14, The clock signal CLK is , directly to the gates of transistors M11 to M14 or via inverter INV2 By applying a clock signal CLK, the voltage V ORG to twice the positive voltage The boosted voltage V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. Therefore, leakage of the electric charges stored in the capacitors C15 and C16 can be suppressed. Voltage V ORG to voltage V POG It is possible to boost the voltage to

[0665] The voltage generating circuit 903C shown in FIG. The transistor M15 has a diode D6 and a capacitor C17. The conduction state is controlled by the control signal EN. The control signal EN controls the voltage V ORG but The boosted voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor Ind1 is used to boost the voltage, the voltage is boosted with high conversion efficiency. It is possible to do so.

[0666] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is This allows the semiconductor device to reduce the number of power supply voltages that are applied from the outside. It can be reduced.

[0667] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0668] (Embodiment 8) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be explained with reference to Figures 58 to 61.

[0669] <8-1. Display module> The display module 7000 shown in FIG. 58 includes an upper cover 7001 and a lower cover 7002. Between them, touch panel 7004 connected to FPC 7003 and A display panel 7006, a backlight 7007, a frame 7009, and a printed circuit board 701 0, has battery 7011.

[0670] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0671] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 7006.

[0672] The touch panel 7004 is a resistive or capacitive touch panel. The display panel 7006 may be overlapped with the opposing substrate (sealing substrate). It is also possible to provide the display panel 7 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0673] The backlight 7007 has a light source 7008. In the above embodiment, the light source 7008 is disposed on the light source 7007. However, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a liquid crystal panel, the backlight 7007 may not be provided.

[0674] The frame 7009 protects the display panel 7006 and also supports the movement of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 7009 may also function as a heat sink.

[0675] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 7011 provided separately. , this can be omitted when using a commercial power source.

[0676] In addition, the display module 7000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0677] <8-2.Electronic equipment 1> Next, examples of electronic devices are shown in FIGS. 59(A) to 59(E).

[0678] FIG. 59(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0679] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0680] In this example, a camera 8000 is used, and a lens 8006 is detached from a housing 8001 and replaced. However, the lens 8006 and the housing may be integrated together.

[0681] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to capture an image by doing so.

[0682] The housing 8001 of the camera 8000 has a mount having electrodes, and a finder 810 In addition to 0, strobe devices etc. can also be connected.

[0683] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0684] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. The mount also includes an electrode The image received from the camera 8000 through the electrode is displayed on the display unit 8102. It is possible to do so.

[0685] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0686] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied.

[0687] In FIG. 59(A), the camera 8000 and the finder 8100 are treated as separate electronic devices. These are configured to be removable, but the camera 8000 has a housing 8001 equipped with a display device. The camera may have a built-in viewfinder that can be used to capture images.

[0688] FIG. 59(B) is a diagram showing the external appearance of the head mounted display 8200.

[0689] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0690] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as image data received is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movement of the user's eyeballs and eyelids. The system captures the user's gaze and calculates the coordinates of the user's gaze based on that information. It can be used as an input means.

[0691] Furthermore, the mounting unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's viewpoint. Also, the device may have a function of detecting the current flowing through the electrode. By doing so, the mounting unit 820 may have a function of monitoring the pulse of the user. The sensor 1 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The device may have a function of displaying the user's biological information on the display unit 8204. The image displayed on the display unit 8204 is changed according to the movemen...

Claims

[Claim 1] A semiconductor device having a transistor, The transistor is A first gate electrode; a first insulating film on the first gate electrode; an oxide semiconductor film on the first insulating film; a second insulating film on the oxide semiconductor film; a second gate electrode on the second insulating film; a third insulating film on the oxide semiconductor film and the second gate electrode; The oxide semiconductor film is a channel region overlapping the second gate electrode; a source region in contact with the third insulating film; a drain region in contact with the third insulating film, the first gate electrode and the second gate electrode are electrically connected to each other; When the field effect mobility of the transistor in the saturation region is measured, the difference between the minimum value of the field effect mobility and the maximum value of the field effect mobility is 15 cm ２ / Vs or less, Semiconductor device.

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