Addition method

Abstract

To provide an addition method of suppressing overflow, a semiconductor device, and an electronic apparatus.SOLUTION: An adder circuit includes a first memory M1, a second memory M2, a third memory M3, and a fourth memory M4. The first memory is given first data with code, the second memory is given first data with positive code stored in the first memory, and the third memory is given first data with negative code stored in the second memory. The first data with positive code stored in the second memory is added to the first data with negative code stored in the third memory to generate second data. The second data is stored in the fourth memory. When all of the second data stored in the fourth memory is second data with positive code or second data with negative code, all of the second data stored in the fourth memory is added.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an adding method, a semiconductor device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an object, a program, a method, or a manufacturing method. One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and a driving method thereof. The present invention relates to a method for producing the same, or a method for producing the same.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. An example of such a device is a semiconductor element such as a transistor or diode. In another example, the circuit having the semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. be. [Background technology]

[0004] IoT (Internet of Things), AI (Artificial I) With the development of information technology such as AI, the amount of data handled is increasing. In order for electronic devices to utilize information technology such as IoT and AI, they need to collect large amounts of data. In order to use electronic devices comfortably, In order to realize low power consumption, there is a demand for semiconductor devices that reduce the amount of calculations.

[0005] In Patent Document 1, a low-precision adder is used in parallel to obtain an adder with a specific precision. This publication discloses an addition method and an adder configuration that operate in this manner. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 9-222991 Summary of the Invention [Problem to be solved by the invention]

[0007] Electronic devices that combine IoT and AI have the challenge of reducing power consumption. Semiconductor devices used in such equipment are required to be miniaturized so that they can be stored in a small space. Therefore, a problem to be solved in semiconductor devices is how to reduce the circuit scale without reducing the processing power.

[0008] AI, especially deep learning, uses machine learning to It can extract features from various information (images, voice, big data, etc.). A neural network having a plurality of neurons Neurons are known to perform multiply-and-accumulate operations that mimic the function of synapses. The circuit having the function can calculate the sum of the results of multiplying multiple input signals by weighting coefficients. It is known that multiply-and-accumulate processing is a method of processing signed floating-point data by digital arithmetic. The problem is that the logic scale becomes large in order to process the data. Power consumption is proportional to the logic scale. There is a growing problem.

[0009] In view of the above problem, an object of one aspect of the present invention is to provide a method for adding signed integers. Another embodiment of the present invention is a semiconductor device having a signed integer type addition method. Another object of the present invention is to provide a method for performing neuron operations at low voltage. Another object of the present invention is to provide a semiconductor device that can improve the power consumption. Another object of the present invention is to provide a novel program. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a novel semiconductor device. One object of the present invention is to provide a method.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc.

[0011] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. However, this does not preclude the existence of other problems. The other problems are described below. Problems not mentioned in this section are problems that a person skilled in the art would be able to understand without reading the specification. or drawings, etc., and can be extracted appropriately from these descriptions. It should be noted that one embodiment of the present invention is to achieve at least one of the above-listed and / or other objects. It is something that solves at least one problem. [Means for solving the problem]

[0012] One aspect of the present invention is a method for detecting a data transfer error by using a first memory, a second memory, a third memory, and a fourth memory. The method includes the steps of: providing a first memory with first data having a code; The method includes the steps of: providing first data having a positive sign stored in a first memory; The memory is provided with first data having a negative sign stored in a first memory. and if the first data is zero, the first data is discarded. The first data having a positive sign stored in the third memory and the second data having a negative sign stored in the third memory. and generating second data by adding the first data to the fourth memory. A step of storing the second data in the fourth memory, the second data having a positive sign being stored in the fourth memory. or when the second data having a negative sign is not stored. In this case, the method further comprises adding up all the second data stored in the fourth memory. This is the method.

[0013] In each of the above configurations, the first data and the second data are signed integer data. The additive method is preferred.

[0014] In each of the above configurations, the addition method is preferably such that the second data is stored in the first memory.

[0015] a first memory, a second memory, a third memory, a selector circuit, a first adder circuit, a second adder circuit, and a counter circuit. The counter circuit includes a first counter, a second counter, The first memory is electrically connected to the first adder circuit and the selector circuit, and The selector circuit is electrically connected to the second memory and the third memory, and the second adder circuit is The counter circuit is electrically connected to the first memory and the third memory. The first memory is electrically connected to the circuit. The first data having a code is provided to the first memory. The first counter and the second counter have a function of being given an initial value. The second memory has the function of outputting the first underflow flag when there is no data stored in it. and the third memory outputs a second underflow flag when there is no data stored therein. The first data is provided to a first memory and a counter circuit. The counter circuit is activated when the first or second underflow flag is given. When the first counter or the second counter is detected, the first counter or the second counter is determined. When either the first counter or the second counter is at its initial value, the first adder circuit The semiconductor device has a function of adding the first data.

[0016] In each of the above configurations, the selector circuit has a positive sign stored in the first memory. A device for allocating first data to a second memory and first data having a negative sign to a third memory. The second adder circuit is connected to the first data having a positive sign stored in the second memory and the second adder circuit is connected to the second adder circuit. 3. A function for generating second data by adding first data having a negative sign stored in a memory to the first data. The second data is provided to a first memory and a counter circuit, and the counter circuit When the first underflow flag and the second underflow flag are given, The function of determining the value of the first counter or the second counter is provided. When any of the counters is at an initial value, the first adder circuit adds the second data stored in the first memory to the A semiconductor device having a function of adding is preferable.

[0017] In each of the above configurations, the second memory and the third memory are first-in-first-out. A semiconductor device having the above-mentioned function is preferred.

[0018] In each of the above configurations, the semiconductor device includes a first zero insertion circuit and a second zero insertion circuit. A first underflow flag is output, and a second underflow flag is output. When the flow flag is not output, the first data is output instead of the first data having a positive sign. The zero insertion circuit provides a zero value. When the flag is output and the first underflow flag is not output, the negative sign is Instead of the first data, a zero value is provided by the second zero insertion circuit. A semiconductor device having such a function is preferred.

[0019] A semiconductor device having a neural network, the neural network comprising: The sum-of-products circuit has multiple multiplier circuits and a multiplication circuit that suppresses overflow due to addition. and a first circuit for controlling the first memory, the second memory, the third memory, and a first adder circuit, and the output data of the multiplier circuit is provided to a first memory as first data. The second and third memories have a first-in, first-out function. The second memory is provided with the first data having a positive sign stored in the first memory. The third memory is provided with the first data having a negative sign stored in the first memory, and the third memory is provided with the first data having a negative sign stored in the first memory. The adder circuit receives the first data having a positive sign read from the second memory and the second data having a positive sign read from the third memory. By adding the first data having a negative sign read by the second counter, the overflow caused by the addition is prevented. This is a semiconductor device that suppresses low.

[0020] In each of the above configurations, a semiconductor device having an adding method and a housing in which the semiconductor device is stored , an electronic device having the same is preferred.

[0021] A semiconductor device having a neural network, the neural network comprising: The multiplication circuit includes a first transistor to a fourth transistor. The multiplication circuit outputs the multiplication result as an output current by applying a weight potential and a data potential. The first transistor has a function of applying a first potential to a gate of the first transistor. The first transistor has a function of passing a first current by being connected to the gate of the second transistor. The third transistor has a function of passing a second current when a second potential is applied to the third transistor. A third current flows when a third potential is applied to the gate of the transistor. The transistor passes a fourth current when a fourth potential is applied to the gate of the fourth transistor. The multiplication circuit subtracts the second current and the third current from the first current, and multiplies the first current by This is a semiconductor device that obtains an output current by adding a fourth current to the first current.

[0022] In each of the above configurations, the first potential is a sum of a reference potential, a weight potential, and a data potential. The first potential is generated by adding the reference potential and the data potential. The third potential is generated by adding the reference potential and the weight potential, and the fourth potential is generated when the reference potential is The given semiconductor device is preferred.

[0023] In each of the above configurations, the multiplication circuit includes a memory cell, a reference cell, a first programming a second programming cell, the memory cell having a first transistor; The reference cell has a second transistor, and the first programming cell has a third transistor. the first programming cell has a fourth transistor, and the memory cell has A first potential corresponding to a first current is held in the reference cell, and a second potential corresponding to a second current is held in the reference cell. The second potential is maintained and the first programming cell is maintained at a third potential corresponding to a third current. and a fourth potential corresponding to a fourth current is held in the second programming cell. Positioning is preferred. Effect of the Invention

[0024] One aspect of the present invention is to provide a signed integer type addition method. According to one embodiment of the present invention, a semiconductor device having a signed integer type addition method can be provided. Another embodiment of the present invention is to provide a semiconductor device that reduces power consumption for neuron operations. Alternatively, one aspect of the present invention can provide a novel program. Alternatively, one aspect of the present invention can provide a novel calculation method. According to one embodiment of the present invention, a novel semiconductor device can be provided. A method for driving a semiconductor device can be provided.

[0025] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. However, this does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to those skilled in the art. or drawings, etc., and can be extracted appropriately from these descriptions. It should be noted that one embodiment of the present invention has at least one of the above-listed effects and / or other effects. Therefore, one aspect of the present invention is, in some cases, There are cases where the above listed effects are not achieved. [Brief description of the drawings]

[0026] [Figure 1] FIG. [Diagram 2] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Diagram 3] 1A is a diagram illustrating a adding method, and FIG. [Figure 4] FIG. [Diagram 5] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 6] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 8] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 10] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 11] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 13] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 14] FIG. 1 is a circuit diagram showing a configuration example of a memory device. [Figure 15] FIG. 1 is a schematic diagram of a semiconductor device. [Figure 16] Schematic diagram of a storage device. [Figure 17] FIG. [Figure 18] 1A and 1B are diagrams illustrating examples of the configuration of a semiconductor device. [Figure 19] 1A to 1C illustrate examples of the structure of a transistor. [Figure 20] 1A to 1C illustrate examples of the structure of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, the embodiments will be described with reference to the drawings. It is understood that the present invention can be practiced in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and details may be made. However, the present invention should not be construed as being limited to the description of the following embodiment. The contents (or even a part of the contents) described in one embodiment of the present invention are the same as those described in the embodiment. Another content (or a part of the content) and / or one or more other embodiments The contents described in (or a part of) are applied, combined, or replaced. It should be noted that the drawings (or a part of them) described in one embodiment may be Another part of the figure, another figure (or a part) described in the embodiment, and / or The drawings may be combined with one or more figures (or a part thereof) described in another embodiment. By combining them, even more figures can be constructed.

[0028] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. and are not limited to the shapes or values ​​shown in the drawings.

[0029] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0030] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those given above, and can be rephrased appropriately depending on the situation.

[0031] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A channel region is provided, and a current flows between the source and the drain through the channel region. In this specification and the like, the channel region is a region through which a current can flow. This refers to the area where flow occurs primarily.

[0032] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0033] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0034] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0035] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to:

[0036] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to a state in which the voltage Vgs between the n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt This may refer to the drain current when it is lower than h.

[0037] The off-state current of a transistor may depend on Vgs. The off-state current of a transistor is I or less when the Vgs value is I or less. The off-state current of a transistor is the off-state current at a given Vgs. state, off state at Vgs within a given range, or a sufficiently reduced off current is obtained. The term "off-state current" may refer to the off-state current at Vgs applied to the device.

[0038] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs -0.5 V is 1×10 -19 A and Vg The drain current at s = -0.8 V is 1 × 10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is A or less. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 There are cases where it is A or lower.

[0039] In this specification, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per watt. Also, for a given channel width (for example, 1 μm), In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0040] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the operating temperature is room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of a semiconductor device including the transistor may be guaranteed. The temperature at which the transistor is certified, or the temperature at which a semiconductor device or the like that contains the transistor is used (e.g. For example, the off-state current at any one of temperatures from 5° C. to 35° C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which the transistor is The temperature at which the semiconductor device containing the transistor is used (for example, between 5°C and 35°C) There exists a value of Vgs at which the off-state current of the transistor at a certain temperature is equal to or less than I. It may refer to.

[0041] The off-state current of a transistor may depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, it indicates the off-state current at 20 V. In other cases, it indicates the off-state current at 20 V. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices including the transistor The term may also refer to the off-state current at Vds used in the transistor off-state. The current is equal to or less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device, etc., in which the transistor is included, or The off-state current of a transistor at Vds used in semiconductor devices is I or less. This may refer to the existence of a Vgs value.

[0042] In the above description of the off-state current, the drain may be read as the source. Current may also refer to the current through the source when the transistor is in the off state.

[0043] In this specification and the like, the term "leak current" may be used to mean the same thing as the "off current." In this specification, the off-state current refers to, for example, the current flowing when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0044] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0045] (Embodiment 1) In this embodiment, an addition method that suppresses overflow and a function of the addition method are provided. The semiconductor device will be described with reference to FIGS.

[0046] AI, for example, deep learning, uses machine learning to It is possible to learn features from information (images, voice, big data, etc.). However, the learning To do this, it is necessary to carry out calculations such as multiplication, addition, and subtraction of large amounts of data. Therefore, in AI, calculations are performed using semiconductor devices with neural networks. , learning speed, or power consumption. For example, a neural network It is known that the brain has neurons that mimic those in the human brain. The operation of neurons is as follows: In other words, to realize the function of a neuron, It is preferable to use an adder circuit. However, part of the calculation is done by software (program). ) may also be calculated.

[0047] The multiply-and-accumulate circuit adds positive or negative integers that are the results of multiplication by multiple multipliers. An example of a multiply-and-accumulate circuit is a signed floating-point arithmetic circuit. A circuit that performs arithmetic with signed integers is preferred. By using floating-point arithmetic, more accurate information features can be extracted. However, the scale of the multiply-and-accumulate circuit becomes larger, and the power consumption also increases. In this case, the size of the multiply-and-accumulate circuit can be reduced. As a result, the semiconductor device having the multiply-accumulate circuit can be made smaller, and power consumption can be reduced. .

[0048] In signed integer arithmetic, when adding positive or negative integers, the order of addition is In some cases, the addition circuit may overflow. Depending on the number, no overflow will occur and the answer can be obtained within the range of the adder's digits. In other words, in an addition circuit that handles a large amount of data, overflow suppression is important to obtain correct calculation results. In this embodiment, an addition method that suppresses overflow and The semiconductor device using the method and the program (software) for the semiconductor device will be described.

[0049] First, the addition method for suppressing overflow will be explained with reference to FIG. 1(A). In (A), as an example, a memory M1, a memory M2, a memory M3, and a memory M4 are included. Here, for the sake of explanation, the memory M4 is used, but instead of the memory M4, Alternatively, the memory M1 and the memory M4 may be replaced with registers. The memory M1, the memory M2, the memory M3, and the memory M4 may each be Each of the memory chips may be provided on a different memory chip, or at least two of the memory chips may be provided on the same memory chip. Alternatively, the memory M1, the memory M2, the memory M3, and the memory M4 are located on the same memory chip and are assigned to different memory areas. It may be possible.

[0050] As shown in FIG. 1(A), the process has steps ST1 to ST5. In step ST1 of (A), the memory M1 stores information about a sensor, an output circuit, a CPU, etc. In this example, data set 1 is provided as input data IN1 to IN9 from The data group 1 will now be described. It is preferable that the data group 1 can be classified into a plurality of ranges. For example, range A is the value 0 (zero), range B is the value of positive integers, and range C is the value of is a negative integer value.

[0051] The value of one piece of data in the data group 1 provided to the memory M1 is, for example, “A” being zero. "B1" represents a positive value, and "C1" represents a negative value. A positive integer is a number whose value is within range B, and the numbers "B1", "B2", "B3" The numbers after the "B" represent the value. Similarly, negative integers are in the range C are numbers with values ​​in the range, such as "C1", "C2", "C3", "C4", etc. The numbers after the "C" are used to distinguish the data. It represents the number.

[0052] Next, in step ST2, the positive sign stored in memory M1 is written to memory M2. The data in range B that has the same name is saved. For example, the data in range B, "B1" and "B2", , and "B3" are stored in memory M2. Memory M3 contains the same data as that stored in memory M1. The data in range C with the negative sign added is saved. For example, the data in range C, "C 1”, “C2”, “C3”, and “C4” are stored in memory M3. If the data in data group 1 stored in memory M1 is zero, you can discard that data. Alternatively, the data may be provided to either memory M2 or memory M3. After the data group 1 is stored in the memory M2 and the memory M3, the memory M1 is It is preferable to initialize the data in range A. Therefore, memory M1 has a reset function. For example, if the memory M1 has a register structure, the reset However, when new data is stored in memory M1, If the value can be overwritten, the memory M1 does not necessarily have to have a reset function. stomach.

[0053] Next, in step ST3, the memory M2 in which data having a positive sign is stored, Or, read data from each memory M3 in which data having a negative sign is stored. Add the extra number.

[0054] For example, read data “B1” from memory M2 and data “C1” from memory M3. Therefore, "B1" with a positive sign and "C1" with a negative sign are added together. Add them together. The result of the addition will be a number closer to zero than "B1" or "C1". In other words, the absolute value of the addition result is smaller than "B1". Or, the absolute value of the addition result is For example, the absolute value of the data in “B1” is smaller than the absolute value of “C1”. If the absolute value of the data in “B11” is greater than the absolute value of the data in “B20”, the sum result will be the positive sign data in “B11”. It becomes data.

[0055] Here, we will explain "B11". "B11" is a positive integer stored in memory M2. The result of adding the integer “B1” and the negative integer “C1” stored in memory M3 is the value in range B. Indicates a number with a value within a range, such as "B11", "B12", "B13", etc. As shown above, the two-digit number after the "B" represents a code to distinguish the data.

[0056] In addition, when "B2" with a positive sign is added to "C2" with a negative sign, the sum is The result is closer to zero than either “B2” or “C2”. The absolute value of the result is smaller than that of "B2". Or, the absolute value of the addition result is smaller than that of "C2". It will be smaller than the absolute value. For example, if the absolute values ​​of each data are the same, The sum is zero, which becomes the data for “A.” Also, “B3” has a positive sign, and “B4” has a negative sign. When you add “C3” with a sign, the result is less than “B3” or “C3”. , the number will be closer to zero. In other words, the absolute value of the addition result will be smaller than "B3". Or, the absolute value of the addition result is smaller than the absolute value of "C3". For example, "C3" If the absolute value of the data in "B1" is greater than the absolute value of the data in "B2", the addition result will be The data in “C11” has a negative sign. Also, the data in “C4” is stored in memory M3. Although there is data in memory M2, there is no data to be added. If there is no data, substitute the data of “A” as the alternative data and add “A” and “C4”. Therefore, the result of the addition is the data in “C4”. If there is no “C4” data, the data in “C4” is used as the addition result as is.

[0057] Here, we will explain “C11”. “C11” is a positive integer stored in memory M2. The result of adding the integer "B3" and the negative integer "C3" stored in memory M3 is within range C. Indicates a number with a value within a range, such as "C11", "C12", "C13", etc. As shown above, the two-digit number after the "C" represents a code to distinguish the data.

[0058] In this way, the addition result is stored in the memory M4 as data group 2. The data set 2 may be stored in the memory M1. By storing the data set in the memory M1, the scale of the circuit can be further reduced. The size of the memory M1 can be reduced, and the power consumption can also be reduced. In the case of step ST1, the number of data is smaller than that in step ST1. As mentioned above, before saving data in memory M1, initialize the data in memory M1. It is preferable to

[0059] Data group 2 includes data with positive signs, data with negative signs, and zero data. When storing data in memory M4, the number of data with a positive sign and It is preferable to count the number of data having a negative sign, and The counter CNP counts the number of data with a positive sign, and the counter CNM counts the number of data with a negative sign. For example, in ST3, the count value is counted by the counter CNP = 1, and counter CNM = 2. Note that counter CNP and counter CNM can be set to any time. It is preferable that the time and initial value can be initialized.

[0060] When data is saved from memory M2 or memory M3 to memory M4, counter C Determine the counter value of counter NP or counter CNM. If any of the CNMs have not been updated from their initial values, the data stored in memory M4 Group 2 can be added together. In that case, after adding them all together, the calculation process The process ends.

[0061] If counter CNP and counter CNM have been updated, proceed to step ST4. In the data group 2 stored in the memory M4, data having a positive sign is stored in the memory M4. M2, data with a negative sign can be stored in M3. For example, memory M2 has In this case, the data in range B, “B11” having a positive sign, is stored. In M3, there are data in range C, namely, “C11” and “C4” with negative signs. In the figure, it is stored in memory M2, but it can be stored in another memory, for example, Similarly, although shown in the figure as being stored in memory M3, it may be stored in another memory. For example, the data may be stored in the memory M6. In addition, when the data is stored in the memory M2, The number of data items is smaller than that in step ST2. It is preferable to initialize the data in memory M2 before saving the data. It is preferable to initialize the data in the M3.

[0062] Next, in step ST5, data of “B11” is read from memory M2, data of “B21” is read from memory M3, and data of “B12” is read from memory M4. The data in “C11” is read and added. That is, “B11” with a positive sign and “C21” with a negative sign are added. The result of the addition is "B11" or "C11" with a sign of "0". In other words, the absolute value of the sum is smaller than "B11". Or, the absolute value of the addition result will be smaller than the absolute value of "C11". For example, If the absolute value of the data in “C11” is greater than the absolute value of the data in “B11”, The result of the addition is the negative sign data "C111". Next, the following is stored in memory M3: When there is data in “C4” but there is no data to be added in memory M2 Substitute the data of “A” as the alternative data and add “A” and “C4”. Otherwise, “C4” is used as the addition result as is. Therefore, the addition result is the data in “C4”. become.

[0063] Here, we will explain about “C111”. “C111” is stored in memory M2. The result of adding the positive integer “B11” and the negative integer “C11” stored in memory M3 is , indicates that the value is within the range C, and "C111", "C112", "C The three-digit number after "C", such as "113", is a code to distinguish data. Although not shown in FIG. 1A, the positive sign stored in memory M2 is The result of adding the data having a negative sign stored in memory M3 to the data having a negative sign stored in memory M4 is For numbers with values ​​within range B, "B111", "B112", "B113", etc. The three-digit number after the "B" represents the code to distinguish the data. is doing.

[0064] The result of the addition is stored in memory M4 as data group 3. In addition, when storing in memory M1, the data in memory M1 It is preferable to initialize the circuit in advance. By storing the circuit in memory M1, the circuit size can be reduced. This allows the power consumption to be reduced. In step ST1, the number of data items is smaller than that in step ST3. Therefore, it is recommended that you initialize the data in memory M4 before saving it. is preferred.

[0065] For example, in ST5, the count values ​​are counter CNP=0 and counter CNM=2. Therefore, the counter CNP remains at its initial value and has not been updated, so the data stored in memory M4 Then, all the data in group 3 are added together, and the calculation process is completed.

[0066] By using the above addition method, the addition of multiple signed data is prevented. By suppressing overflow, the addition process In FIG. 1(A), the data degradation due to the step ST As in step ST2 and step ST4, data is temporarily stored in memory M2 and memory M3, but One aspect of the present invention is not limited to this. For example, Select data from input range B and input range C, add them together, and then memoize them. You can also save it on the M4.

[0067] In FIG. 1B, the addition method (steps ST1 to ST5) described in FIG. 1A is performed. ) is given actual numbers. First, in step ST11, 1 shows an example in which data set 1 is provided from IN1 to IN9. ,For example, “-1”, “-3”, “2”, “3”, “0”, “0”, “-3”, “- Although not explained in FIG. 1(A), the counters CNP and The count value may be managed using a counter CNM. For example, in step ST of FIG. 11 shows counter CNP=3 and counter CNM=4.

[0068] As an example, range B may be given the range of positive integers 1 to 3, and range C may be given the range of negative integers 1 to 3. The range is given from -1 to -3. In other words, if the range exceeds B or C (-3 For example, memory M If you add "-1" and "-3" to the data stored in 1, the result will be " However, as shown in Figures 1(A) and 1(B), As shown in the figure, in the method of adding an integer having a positive sign and an integer having a negative sign, Since the calculation result approaches zero, the occurrence of overflow can be suppressed.

[0069] Next, in step ST12, the memory M2 stores the positive sign stored in the memory M1. The memory M3 stores the data with a negative sign stored in the memory M1. That is, the data "2", "3", and "1" are stored in memory M2. Additionally, "-1", "-3", "-3", and "-1" are stored in memory M3.

[0070] Next, in step ST13, the memory M2 in which data having a positive sign is stored, Or, data from each memory M3 in which data having a negative sign is stored is read. In other words, the "2" stored in memory M2 and the "2" stored in memory M3 are read and added. The result of the addition, "1", is stored in memory M4. The "3" stored in memory M2 is added to the "-3" stored in memory M3. The result "0" is stored in memory M4. Next, the "1" stored in memory M2 and the The "-3" stored in memory M3 is added to the "-2" stored in memory M4. Then, since memory M2 has no data stored in it, zeros are assigned to it instead, and memory The "-1" stored in memory M3 is added to the "- The result of the addition, "-1", is stored in memory M4. If the result is "0", it does not need to be stored in memory M4.

[0071] At this time, the counter value of the integer having a positive sign is counter CNP=1, and the counter value of the integer having a negative sign is counter CNP=2. The integer counter value indicates counter CNM=2. Therefore, To achieve this, data is allocated and stored from memory M4 to memory M2 and memory M3.

[0072] Next, in step ST14, "1" is stored in memory M2, and "0" is stored in memory M3. will store "-2" and "-1".

[0073] Next, in step ST15, the "1" stored in the memory M2 and the "0" stored in the memory M3 are The result of the addition, "-1", is stored in memory M4. , memory M2 has no data stored in it, so it is given zeros instead, and memory M3 The "-1" stored in memory M3 is added to the "-1" stored in memory M4. The sum result "-1" is stored in memory M4.

[0074] In ST15, the count value becomes counter CNP=0 and counter CNM=2. Counter CNP has not been updated from its initial value, so all data stored in memory M4 is As a result, the addition result "-2" can be calculated. By adding integers with a positive sign and integers with a negative sign in sequence, This is an addition method that can suppress data degradation due to flow and calculate a correct solution.

[0075] FIG. 2A illustrates an adder circuit 10 having the function of the addition method shown in FIG. 1A. The adder circuit 10 includes a selector 20, a memory 21, a counter 22, a control circuit A circuit 23, a selector 24, a memory 24a, a memory 24b, a control circuit 25, and a zero insertion A gain circuit 26a, a zero insertion circuit 26b, an adder circuit 27, an adder circuit 28, and a gain The counter 22 includes a counter CNP22a and a counter CNP22b. The adder circuit 10 includes a signal line DI, a signal line DR, a signal line DA, Signal line DA1, signal line DA2, signal line DAP, signal line DAM, signal line FO1, signal line FO 2, Signal line FOUT1, Signal line FOUT2, Signal line DO, Signal line SEL1, Signal line SEL 2, Signal line WEP, Signal line WEM, Signal line UFP, Signal line UFM, Signal line REP, Signal line REM, signal line WER, signal line FC, signal line DUF, signal line MB1, signal line MB2, signal It has a line WE, a signal line IRQ, and a signal line ACK.

[0076] The selector 20 is electrically connected to the memory 21 via a signal line DA. The detector 20 is electrically connected to a counter 22 via a signal line DI, and is further connected to a signal line SE It is electrically connected to the gate circuit 29 via L1.

[0077] The memory 21 is electrically connected to a selector 24 via a signal line DA1. The data bus 24 is electrically connected to the memory 24a via a signal line DAP, and is further connected to a signal line DAM The memory 24b is electrically connected to the memory 24b via the

[0078] The control circuit 23 is electrically connected to the memory 21 via a signal line DA1. The control circuit 23 is electrically connected to the selector 24 via a signal line SEL2. The control circuit 23 is electrically connected to the memory 24a via a signal line WEP, and further to the signal It is electrically connected to the memory 24b via a line WEM.

[0079] The memory 24a is electrically connected to the zero insertion circuit 26a via a signal line FO1. The memory 24b is electrically connected to the zero insertion circuit 26b via a signal line FO2. are electrically connected.

[0080] The control circuit 25 is electrically connected to the memory 24a via a signal line UFP and a signal line REP. and is further electrically connected to the memory 24b via a signal line UFM and a signal line REM. The control circuit 25 is connected to the zero insertion circuit 26a via a signal line MB1. and is electrically connected to the zero insertion circuit 26b via a signal line MB2. , and the control circuit 25 is electrically connected to the counter 22 via a signal line DUF, Further, the signal line WER is electrically connected to the adder circuit 27 and the gate circuit 29. There are.

[0081] The adder circuit 27 is electrically connected to the zero insertion circuit 26a via a signal line FOUT1. and is further electrically connected to the zero insertion circuit 26b via a signal line FOUT2. The adder circuit 27 is electrically connected to the selector 20 and the counter 22 via a signal line DR. are connected to the network.

[0082] The signal line IRQ is electrically connected to the counter 22 and the control circuit 23. The arithmetic circuit 10 outputs a signal line ACK and a signal line DO.

[0083] Next, the function of each will be described. The selector 20 selects a signal given to a signal line SEL1. Depending on the signal, either the input data DI or the output DR of the adder circuit 27 is selected and a signal line The signal given to the signal line SEL1 is used for writing to the memory 21. or a signal line WER for writing the output DR of the adder circuit 27. The memory 21 corresponds to the memory M1 in FIG.

[0084] Memory 21 is a DRAM (Dynamic Random Access Memory y), or SRAM (Static Random Access Memory), etc. Alternatively, the memory 21 may be configured as a register. It is preferable that the reset function or the read reset function is provided. The reset function resets all data stored in the memory to the initial value at any time. A read reset is a reset that reads the data in the accessed memory address. This function initializes the data after reading it out.

[0085] The counter 22 receives data provided to the signal line DI or data provided to the signal line DR. For each of the above, a counter CNP22a that counts integers having a positive sign and a counter CNP22b that counts integers having a negative sign and a counter CNM22b for counting integers having a number. The counter 22 is It is preferable that the signal line DUF has a reset function and an enable function. The signal applied preferably resets the counter 22. Also, the signal line IR A signal applied to Q enables the counter 22. When this state is reached, counting up begins.

[0086] The control circuit 23 transfers the data stored in the memory 21 to the memory 24 via the selector 24. a and memory 24b. The control circuit 23 can move the The data stored in the memory 21 is transferred to the memory 24a or the memory 24b by a signal output from the memory 21. For example, the control circuit 23 can determine whether the data transferred from the memory 21 is correct. If the code is 0, it can be stored in the memory 24a via the signal line DAP. If the data transferred from the memory 21 has a negative sign, the control circuit 23 sets the signal line DA The control circuit 23 can store the signal in the memory 24b via the signal line DA1. It is preferable that the data has a function of discarding the zero data when the data is zero.

[0087] The memory 21, the memory 24a, and the memory 24b are first-in, first-out It is preferable that the memory 21, the memory 24a, and the memory 24b have the following functions: When there is no data, an underflow flag can be output. The first-out function adds a read reset function. The memory 24a and the memory 24b have a first-in, first-out function. In the following description, the memory 21, the memory 24a, and the memory 24b are The size of the memory 21 may be determined appropriately, but it is preferable that the memory 21 is larger than the memory 24a and the memory 24b. The larger the memory, the better. The memory 24a corresponds to the memory M2 in FIG. 1, and the memory 24b corresponds to the memory M2 in FIG. corresponds to the memory M3 in FIG.

[0088] The control circuit 25 controls the underflow flag and The state of the underflow flag output by the memory 24b to the signal line UFM can be monitored. Also, data is read from the memory 24a and the memory 24b and is provided to the adder circuit 27. However, the memory 24a outputs an underflow flag to the signal line UFP. When the zero insertion circuit 26a outputs zero as the substitute data, Similarly, when the memory 24b outputs an underflow flag to the signal line UFM, , the zero insertion circuit 26b provides zero as substitute data.

[0089] The result of the addition circuit is stored in the memory 21 via the signal line DR. If the sum has a positive sign, the counter CNP22a counts up. If the sum has a negative sign, the counter CNM22b is counted up. When both the buffer 24a and the memory 24b output an underflow flag, the control circuit 25 The counter 22 outputs a signal to the signal line DUF. Therefore, the counter CNP22a and the counter CNM22b are stopped and a determination is made. The result of the determination is notified to the control circuit 23 and the adder circuit 28 via a signal line FC. The result of the determination is the first result, which is determined by the counter CNP22a or the counter CNM2 Either 2b underflows or the second result does not underflow It is preferable that the count value of the counter is the count value of the counter.

[0090] The counter 22 starts when either the counter CNP22a or the counter CNM22b is first If the initial value remains, the data stored in memory 21 will have the same sign (including zero). It can be determined whether the counter CNP22a or the counter CNM22b When is the initial value, the adder circuit 28 reads out the data via the signal line DA2 and adds them. After the calculation is completed, the adder circuit 28 notifies the completion of the calculation by sending a signal to the signal line ACK. At this time, the addition result is output to the signal line DO. However, it is preferable to latch the data to hold it. The line ACK preferably has a read reset function.

[0091] If counter CNP22a and counter CNM22b are counting up Therefore, it can be determined that data having different codes is stored in the memory 21. If so, the control circuit 23 executes the addition operation again.

[0092] Therefore, a peripheral circuit such as a CPU stores multiple pieces of data to be added in the adder circuit 10. The signal is stored in the register 21, and a signal is sent to the signal line IRQ to start the calculation process of the adder circuit 10. When the calculation is completed, the adder circuit 10 outputs a signal to the signal line ACK to notify the CPU In other words, it sets data and executes the operation command. During the period when the adder circuit 10 is performing the calculation, the CPU Peripheral circuits such as the , ... By performing the calculation, overflow is suppressed, and data that results in zero is discarded. The semiconductor device has an adder circuit 10 having an addition method that can reduce the amount of calculations. .

[0093] FIG. 2B shows the zero insertion circuit 26 (zero insertion circuits 26a and 26b ) is a circuit diagram illustrating in detail the zero insertion circuit 26. The gate circuit 26c has two inputs, a switch SW0, and a switch SW1. The output terminal of the gate circuit 26c is connected to a signal line FOU. T[n:0]. The input terminal is electrically connected to one of the signal lines FO[n:0]. The terminal is electrically connected to one electrode of the switch SW0 and one electrode of the switch SW1. The other electrode of the switch SW0 is electrically connected to the wiring Vdd. It is preferable that the high power supply voltage of the adder circuit 10 is applied to the dd. The other electrode of the first electrode is electrically connected to the wiring Vss. The wiring Vss is connected to the low A power supply voltage, for example GND, is preferably applied.

[0094] The switches SW0 and SW1 are controlled by a signal applied to a signal line MB. In addition, it is preferable that the switches SW0 and SW1 operate exclusively. The gate circuit 26c turns on the switch SW0 in response to a signal applied to the signal line MB. The signal applied to the signal line FO can be turned off for the same period. The gate circuit 26c can output the same signal as the signal on the signal line M The signal applied to B turns switch SW0 off and turns switch SW1 on for the same period. Therefore, the signal line FOUT is given zero. The gate circuit 26c can convert any data given to the signal line FO to zero. can.

[0095] One aspect of the present invention is not limited to the above-described adding circuit. For example, In other words, one aspect of the present invention may be realized by software, not by hardware. The addition method may be implemented.

[0096] FIG. 3(A) shows an addition method that suppresses overflow and has a different configuration from that shown in FIG. 1(A). FIG.

[0097] FIG. 3(A) differs from FIG. 1(A) in that it has memories M5 and M6. Unlike Fig. 1(A), the input data or the data after the calculation is divided into several smaller ranges. For example, the range into which positive integers are classified is the range Range B and range BB. Range BB has values ​​greater than range B. The range into which negative integers fall can be divided into range C and range CC. Range CC has smaller values ​​than range C. So, when adding, you can make the sum result smaller. This can further suppress the occurrence of overflow when performing addition using the same arithmetic operation.

[0098] FIG. 3B is a circuit diagram illustrating a semiconductor device having a different structure from that in FIG. The adder circuit 10a includes a control circuit 30, a selector 31, memories 31a to 31d, and a control The circuit 32 includes a zero insertion circuit 33a and a zero insertion circuit 33b. The difference between the adder circuit 10 and the adder circuit 11 is that the display of the memory 31b and the memory 31c is The adder circuit 10a includes a signal line DAP1, a signal line DAP2, and a signal line DA M1, signal line DAM2, signal line FO1, signal line FO2, signal line FO3, signal line FO4, signal line Signal line WEP1, signal line WEP2, signal line WEM1, signal line WEM2, signal line UFP1, signal Line UFP2, Signal Line UFM1, Line UFM2, Signal Line REP1, Signal Line REP2, Signal It differs from the adding circuit 10 in that it has a line REM1 and a signal line REM2.

[0099] The control circuit 30 includes memories 31a to 31d (memories 31b and 31c are not shown). The selector 31 differs from the control circuit 23 in that it corresponds to the memory 31a to the memory 31b. The selector 24 differs from the selector 24 in that it corresponds to the memory 31d. The data within the range A is stored in the memory 31b, and the data within the range B is stored in the memory 31c. The memory 31c stores data within the range C, and the memory 31d stores data within the range CC. The control circuit 32 controls the points corresponding to the memories 31a to 31d. The zero insertion circuit 33a is different from the control circuit 25. The difference between the zero insertion circuit 26a and the zero insertion circuit 26b is that it corresponds to O2. The circuit 33b is connected to the zero insertion circuit 26 at points corresponding to the signal lines FO3 and FO4. is different from b.

[0100] As shown in Figure 3(B), in order to further suppress overflow during addition processing, It is preferable to add memory to manage the input range in detail. Overflow is suppressed. Therefore, a more accurate calculation can be performed.

[0101] FIG. 4(A) shows an addition method that suppresses overflow and has a different configuration from that shown in FIG. 1(A). FIG. 4A is a diagram for explaining steps ST31 to ST33. An example is shown in FIG. 1(A). In FIG. 1(A), integers are classified into integers with positive signs and integers with negative signs. On the other hand, in step ST32 in FIG. 4(A), Instead of just sorting numbers and negative integers, sort them by absolute value. The two values ​​with different signs are added in ascending order of absolute value. The sum of these values ​​is close to zero. As a result, overflow occurs, reducing the accuracy of the calculation. This allows faster addition processing without the need for additional calculations.

[0102] In FIG. 4A, the data is stored in memory M2 and memory M3 separately. One aspect of the present invention is not limited to this. For example, an integer having a positive sign and an integer having a negative sign may be used. For example, the integers may be stored in memory M2 in ascending order from the largest to the smallest. For example, as shown in FIG. 4(B), “3”, “2”, “1” ", "0", "0", "-1", "-1", "-3", "-3", in this order, memory M2 Then, add the largest value and the smallest value in order. For example, , add "3" and "-3", then add "2" and "-3", then add "1" and "-1" is added, then "0" and "-1" are added. As a result, the number of integers with positive signs and the number of integers with negative signs are large. Even if the difference is large, the process can be completed quickly. The data is stored in memory M2 and then added, however, one aspect of the present invention is not limited to this. For example, take the appropriate numbers from memory M1 and sequentially select the largest and smallest values. A value other than the above may be added.

[0103] In addition, in the case of Figure 4(B), even when adding unsigned integers, This reduces the loss of calculation accuracy due to barflow. Only numbers (including zero) or only integers with a negative sign (including zero) In the case where the number of values ​​is 1 or more, the number of values ​​is 1 or more, and the number of values ​​is 1 or more. Then, the largest value and the smallest value may be added in order. In this example, the data is stored in memory M2 and then added, but this is not a limitation of the present invention. For example, the appropriate values ​​are taken from memory M1 and set in order as the largest value. , and the smallest value may be added together.

[0104] In addition, step ST5 in FIG. 1(A), step ST15 in FIG. 1(B), and step ST15 in FIG. In step ST25 and other steps, unsigned integers can be added using a method similar to that shown in Figure 4(B). As a different example, we can add only integers with positive signs, or negative ones. When adding only signed integers, the same method as in Figure 4(B) can be used to add unsigned integers. Integers can be added.

[0105] This embodiment may be modified, added, revised, or deleted in part or in whole from other embodiments. , application, superordinate conception, or subordinate conception. Part or all of the above may be freely combined with part or all of the other embodiments, or It can be implemented in a replacement manner.

[0106] (Embodiment 2) In this embodiment, a semiconductor device having an adder circuit capable of suppressing overflow is provided. The placement will be described with reference to FIG. 5 to FIG.

[0107] FIG. 5A is a block diagram showing a semiconductor device 80 equipped with a neural network. The semiconductor device 80 includes, for example, a CPU 81, a memory 82, an imaging device 83, a network 84, a display controller 85a, a display device 85b, and an input / output The input bus 86 is connected to a CPU 81, a memory 82, an image pickup device 83, a neural network The network 84 and the display controller 85a are connected via an input / output bus 86. However, the image pickup device 83 does not communicate with the neural network 8 without using the input / output bus 86. 4, and the neural network 84 may be electrically connected to the The display controller 85a may be electrically connected to the display controller 85a without any need for the display controller 85a.

[0108] FIG. 5B shows an example in which an image capture device 83 is connected to a neural network 84. In this example, the neural network 84 outputs data to the CPU 81. The neural network 84 includes a multiplication cell block 84a and a driver 84d. The multiplication cell block 84a has a plurality of neurons 84b. The LTC 84b includes, for example, a plurality of multiplication cells 11, a plurality of reference cells 12, and a calculation The circuit 13 and the adder circuit 10 described in FIG. Alternatively, if the addition is performed by a program, the addition circuit 10 may not be provided.

[0109] FIG. 5C is a diagram illustrating the neuron 84b. The neuron 84b is an example of The multiplication circuit 40 and the conversion circuit 15 are included. The multiplication circuit 40 preferably includes a plurality of multiplication cells 11. The conversion circuit 15 is electrically connected to the adder circuit 10. That is, the neuron 8 4b has a multiply-and-accumulate circuit composed of a multiplier circuit 40 and an adder circuit 10.

[0110] FIG. 6A shows the transistors included in the multiplication cell 11. By giving a weighting factor ΔW and data ΔV to the gate of the transistor, The method for multiplying V is explained. The current Id flowing through the transistor is the current Id that flows when the transistor is saturated. When operating in the region, it can be expressed by Equation 1.

[0111] Ids = k × (Vgs - Vth) 2 (Formula 1)

[0112] The current Ids changes depending on Vgs. The gate of the transistor is connected to a reference voltage Vref. If the load factor ΔW and data ΔV are given, the current Ids is calculated by applying Equation 2 to Vg in Equation 1. It is necessary to substitute Vgs1 into s and calculate. The current Ids is defined as current I1.

[0113] Vgs1=Vref+ΔW+ΔV (Equation 2)

[0114] To obtain ΔW × ΔV as the multiplication result, we need to expand Equation 1 into which Equation 2 is substituted, 5 we can get the term ΔW×ΔV.

[0115] I1=k×(Vref+ΔW+ΔV-Vth) 2 (Formula 3)

[0116] When coefficient A=Vref+Vth

[0117] I1 = k × (ΔW + ΔV + A) 2 (Formula 4)

[0118] I1 = k × (A 2 +2×A×ΔW+ΔW 2 +2×A×ΔV+ΔV 2 +2×ΔW×ΔV) (Formula 5)

[0119] Similarly, if Vgs2=Vref+ΔV is substituted for Vgs in Equation 1, the current I2 can be obtained. This can be done.

[0120] In addition, if you substitute Vgs3=Vref+ΔW for Vgs in equation 1, you can obtain the current I3. can.

[0121] When Vgs4=Vref is substituted for Vgs in equation 1, the current I4 can be obtained.

[0122] A, obtained from Equation 5 2 +2×A×ΔW+ΔW 2 is obtained when Vgs3 is substituted This corresponds to current I3.

[0123] 2×A×ΔV+ΔV, obtained from Equation 5 2 is the current I obtained when Vgs2 is substituted This can be obtained by subtracting the current I4 obtained when Vgs4 is substituted from 2.

[0124] Therefore, in order to obtain the multiplication result of ΔW × ΔV from Equation 5, the following Equation 6 must be satisfied. In this case, I5 does not depend on the Vth of the transistor.

[0125] I5=2×k×ΔW×ΔV (Formula 6)

[0126] Equation 7 holds when ΔV>0 and ΔW>0, or ΔV<0 and ΔW<0.

[0127] I1+I4-I2-I3-I5=0 (Equation 7)

[0128] In addition, in the different cases, ΔV<0, ΔW>0, or ΔV<0, ΔW>0, Equation 8 is not satisfied. Stand up.

[0129] I1+I4-I2-I3+I5=0 (Equation 8)

[0130] In other words, in order to obtain the multiplication result of ΔW×ΔV using a transistor, the current I1 to It can be calculated by calculating the flow I4.

[0131] FIG. 6B shows currents I1 to I5 as an example. I5(7) is expressed by the formula 7. I5(8) indicates the direction of the current in equation 8.

[0132] FIG. 7A is a circuit diagram for explaining a multiplication circuit 40 of a product-sum calculation circuit as an example. The multiplication circuit 40 includes, for example, a multiplication cell 11, a reference cell 12, and an arithmetic circuit 13. and a conversion circuit 15. An example of the conversion circuit 15 is a Alternatively, an example of the conversion circuit 15 is a digital signal converter. Alternatively, the conversion circuit 15 may have a function of converting an output signal into a digital signal. The arithmetic circuit 13 has a function of removing noise components from the signal. S1, a first programming cell, and a second programming cell. Each of the multiplication circuit 40 includes a memory cell. For example, the wiring Vdd, the wiring Vss, the signal line SL, the signal line SLR, the signal line WL1, and It has a signal line WD.

[0133] Examples of memory cells included in the multiplication cell 11 include a transistor 41 and a transistor 4 2, and a capacitive element 43. The transistor 44, the transistor 45, and the capacitor element 46 are included as the transistors. An example of the calculation circuit 13 is a transistor 47 forming a current mirror, a transistor 48. Further, an example of the first programming cell is a transistor 49. , a capacitive element 50, and a switch S2. As an example, it includes a transistor 51, a capacitive element 52, and a switch S3.

[0134] The transistors 47 to 49 are p-channel transistors. The other transistors are n-channel transistors.

[0135] The multiply-and-accumulate circuit is a transistor that contains silicon (such as single crystal silicon) in the channel formation region. The channel forming region may be a silicon transistor. The transistors are made of oxide semiconductors (hereinafter referred to as OS transistors). In particular, since the off-state current of an OS transistor is extremely small, It is preferable to use both Si transistors and OS transistors. In FIG. 7A, as an example, a switch S2, a switch It is preferable that transistor S3, transistor 41, or transistor 44 is an OS transistor. I wish.

[0136] One of the source and drain of the transistor 41 is electrically connected to the signal line SL. The other of the source and drain of the transistor 41 is connected to the gate of the transistor 42, The source or drain of the transistor 42 is electrically connected to one of the electrodes of the capacitor 43. One of the drains of the transistor 42 is electrically connected to the wiring Vss. The other of the drains is connected to one of the electrodes of the switch S1, one of the electrodes of the switch S2, and the The electrode of the switch S2 is electrically connected to one of the source and drain of the transistor 49. The other end is electrically connected to the gate of the transistor 49 and one of the electrodes of the capacitor 50. The other of the source and drain of the transistor 49 is connected to the wiring Vdd and the capacitor 50. The other electrode of the switch S1 is electrically connected to the input of the conversion circuit 15. an input terminal, one of the source or drain of the transistor 51, one of the electrodes of the switch S3, and electrically connected to one of the source and drain of the transistor 48. The gate of the switch S3 is electrically connected to the other electrode of the switch S3 and one electrode of the capacitor element 52. The other of the source and drain of the transistor 51 is electrically connected to the wiring Vss, The other electrode of the capacitor 52 is electrically connected to one of the source and drain of the transistor 45. The other of the source and drain of the transistor 48 is connected to the wiring Vdd, and electrically connected to one of the source and drain of the transistor 47. The gate of 48 is the gate of the transistor 47, the source or drain of the transistor 47 and the other of the source or drain of the transistor 45. The gate of the transistor 45 is connected to one of the source and drain of the transistor 44, The other electrode of the capacitance element 46 is electrically connected to the wiring W The other of the source and the drain of the transistor 44 is electrically connected to the wiring SL It is electrically connected to R.

[0137] A node FN10 is connected to the other of the source or drain of the transistor 41, 2 and one of the electrodes of the capacitor 43. 20 is one of the source or drain of the transistor 44, the gate of the transistor 45, The node FN30 is connected to one of the electrodes of the capacitor 46. The other electrode of the switch S2, the gate of the transistor 49, and one electrode of the capacitance element 50 The node FN40 is formed by connecting the other electrode of the switch S3, the transistor The transistor 51 is connected to the gate of the capacitor 51 and one of the electrodes of the capacitor element 52 .

[0138] Here, the conversion circuit 15 will be described with reference to FIGS. 7(C), (D), and (E). An example of the circuit 15 includes an IV conversion circuit 15a and an amplifier circuit 15b. The conversion circuit 15a may include a resistor, a capacitor, a diode, and the like. The IV conversion circuit 15a can convert the current into a voltage. As a result, the output signal The output converted to a voltage by the amplifier circuit 15b can be easily extracted. The amplifier circuit 15b can output a signal appropriately. A common source circuit, a voltage follower circuit, or the like can be used. As shown in FIG. 7(D) or FIG. 7(E), an IV conversion circuit 15a may be used. It can also be configured using an amplifier and a passive element (e.g., a resistive element or a capacitive element). FIG. 7(D) shows an IV conversion circuit using an operational amplifier and a resistive element, and FIG. ) shows an integrating circuit using an operational amplifier and a capacitive element. As shown, by using an op-amp, the effect of virtual grounding can be utilized. This is preferable because it allows the potential of the input terminal to be controlled.

[0139] Next, an example of the operation of the multiplication circuit 40 will be described with reference to FIG. 7(A) and FIG. 7(B).

[0140] First, FIG. 7A will be described. The node FN10 is connected to a Vgs 3 (=Vref+ΔW) is written, and a current I3 flows through the transistor 42. A potential equivalent to the current I3 flowing through the transistor 49 is applied to the input terminal FN30 via the switch S2. At the same time, Vgs4 (=Vre f) is written, and a current I4 flows through the transistor 45. The transistor 47 forms a sigma-representing node FN, which is copied by the transistor 48. A potential equivalent to the current I4 flowing through the transistor 51 is applied to the output terminal 40 via the switch S3. can be obtained.

[0141] Next, referring to FIG. 7B, the switches S2 and S3 are turned off. The potential applied to the node FN30 or the node FN40 is stored.

[0142] Next, by changing the potential of the signal line WD by the data ΔV, the node FN10 Data ΔV is applied via the capacitance element 43. That is, the potential of the node FN10 is Vgs 3 to Vgs1 (=Vref+ΔW+ΔV). At the same time, the node FN20 Data ΔV is applied via the capacitance element 46. That is, the potential of the node FN10 is Vg The current I2 changes from s4 to Vgs2 (=Vref+ΔV). The transistor 47, which is connected to the transistor 48, is copied by the transistor 4. A current I2 can be passed through 8.

[0143] Transistor 42 carries a current I1, transistor 49 carries a current I3, and transistor The transistor 48 can pass a current I2, and the transistor 51 can pass a current I4. By turning on switch S1, a current I5 can be supplied to conversion circuit 15. Therefore, the multiplication result of ΔW×ΔV can be obtained as I5.

[0144] FIG. 8 shows a multiplication cell 11 having a plurality of memory cells, a reference cell 12 having a plurality of memory cells, and 7A in that it has a sensor cell 12. Based on Kirchhoff's current law, the multiple currents output from the multiplication cell 11 having The signal line NSEL2 is electrically connected to the switch S2. The signal line NSEL3 is electrically connected to the switch S3. It is preferable that the number of memory cells in the reference cell 12 is the same as that in the reference cell 1. The switch S1 may be a transistor, but more preferably is an analog switch. It is better to use analog switches. Multiplication can be performed more accurately by using analog switches.

[0145] Also different is that the transistor 49a of the first programming cell is It is preferable to increase the channel width of the transistor according to the number of stages. When n stages of memory cells are connected in the computing cell 11, the channel of the transistor 49a The width is preferably n times the channel width of the transistor 42a. , it is preferable that it is larger than n times the channel width of the transistor 42a.

[0146] The transistor 51a of the second programming cell is It is preferable to increase the channel width of the transistor. When n stages of memory cells are connected in the transistor 12, the channel width of the transistor 51a is It is preferable that the channel width of the transistor 45a is n times as large as that of the transistor 45b. It is preferable that the width is larger than n times the channel width of the transistor 45a.

[0147] FIG. 9 is a circuit diagram for explaining an arithmetic circuit 13a different from that shown in FIG. The arithmetic circuit 13a further includes a transistor 47a, a transistor 48a, and a transistor 4 9b, a capacitance element 50a, a switch S2a, a transistor 51b, a capacitance element 52a, and It has a switch S3a.

[0148] By configuring the circuit as shown in Figure 9, the saturation characteristics of the transistors used for addition processing are improved. Therefore, it is possible to copy the current using a current mirror or the like. In this case, a more accurate current can be handled. This makes it possible to improve the accuracy of the addition operation.

[0149] FIG. 10A is a circuit diagram illustrating a multiplication circuit 40a that is different from that in FIG. 7A. In FIG. 10(A), the main transistors are n-channel transistors. In addition, if the switches are also made of n-channel transistors, all the transistors In this case, the process can be simplified. It can be abbreviated.

[0150] An example of the multiplication circuit 40a is a multiplication cell 11a, a reference cell 12a, an arithmetic circuit 13b, and a conversion circuit 15. An example of the arithmetic circuit 13b is a switch S 1, a first programming cell, and a second programming cell. The multiplication circuit 40a includes a reference cell 12a, and a multiplication circuit 40a includes a reference cell 12a. Examples of the wiring Vdd, wiring Vss, signal line SL, signal line SLR, signal line WL1, and a signal line WD.

[0151] Examples of memory cells included in the multiplication cell 11a include a transistor 61 and a transistor 62 and a capacitance element 63. The arithmetic circuit 13b includes a transistor 64, a transistor 65, and a capacitance element 66. As an example, a transistor 72, a capacitor 73, a transistor 74, a capacitor 75, It includes a transistor 76, a capacitance element 77, and switches S7 to S15. Further, an example of the first programming cell includes a transistor 67, a capacitive element 68, and and switch S4. Further, as an example of the second programming cell, A transistor 69, a capacitance element 70, a transistor 71, a switch S5, and a switch S6 are It has.

[0152] In FIG. 10A, a switch S4, a switch S5, a switch S12, a switch S14, The switch S15, the transistor 61, or the transistor 64 may be, for example, an OS transistor. Since the off-state current of an OS transistor is extremely small, it is possible to hold a voltage The transistor is suitable for this purpose.

[0153] The multiply-and-accumulate circuit may be configured with Si transistors or OS transistors. In particular, since the off-state current of the OS transistor is extremely small, It is suitable as a transistor that constitutes the memory of a circuit. The multiply-and-accumulate circuit may be configured using both transistors.

[0154] One of the source and drain of the transistor 61 is electrically connected to the signal line SL. The other of the source and drain of the transistor 61 is connected to the gate of the transistor 62, The source or drain of the transistor 62 is electrically connected to one of the electrodes of the capacitor 63. One of the drains of the transistor 62 is electrically connected to the wiring Vss. The other of the drains is connected to one of the electrodes of the capacitor 68 and the source or drain of the transistor 67. one of the electrodes of the switch S1, one of the electrodes of the switch S6, and one of the electrodes of the switch S10 The gate of the transistor 67 is electrically connected to one of the electrodes of the capacitor 68. The other electrode of the transistor 67 is electrically connected to one of the electrodes of the switch S4. The other of the drains is electrically connected to the other electrode of the switch S4 and to the wiring Vdd. It is being done.

[0155] The other electrode of the switch S1 is electrically connected to the conversion circuit 15. One of the source and the drain of the transistor 64 is electrically connected to the wiring SLR. The other of the source and drain of the transistor 65 is connected to the gate of the transistor 65 and the potential of the capacitor 66. One of the source and drain of the transistor 65 is electrically connected to the The other of the source and drain of the transistor 65 is electrically connected to the line Vss. The switch S7 is electrically connected to one of the electrodes of the switch S7 and to one of the electrodes of the switch S9. The other electrode of the switch S7 is connected to one of the source and drain of the transistor 72, the capacitance element 7 The transistor S1 is electrically connected to one of the electrodes of the transistor S3 and one of the electrodes of the switch S8. The other of the source or drain of 72 is connected to one of the electrodes of the switch S15 and to the wiring Vdd The gate of the transistor 72 is electrically connected to the other electrode of the capacitor 73. The electrode is electrically connected to the other electrode of switch S15.

[0156] The other electrode of the switch S9 is connected to one of the source or drain of the transistor 74, One of the electrodes of the element 75 and one of the electrodes of the switch S11 are electrically connected. The other of the source or drain of the transistor 74 is connected to one of the electrodes of the switch S14 and The gate of the transistor 74 is electrically connected to the line Vdd. The electrode of the switch S11 is electrically connected to the other electrode of the switch S14. The other electrode of the switch S10, one electrode of the capacitance element 77, and the transistor The source or drain of the transistor 76 is electrically connected to the The other of the drains is electrically connected to one of the electrodes of the switch S12. The gate of the capacitor 76 is electrically connected to the other electrode of the capacitance element 77 and one electrode of the switch S13. The other electrode of the switch S12 is electrically connected to the other electrode of the switch S13, The other electrode of the switch S8 is electrically connected to the It is electrically connected to one of the source or drain and one of the electrodes of the switch S5. The gate of the transistor 71 is connected to one of the electrodes of the capacitance element 70, the other electrode of the switch S5, and the gate of transistor 69. The source or One of the drains of the transistor 7 is electrically connected to the other electrode of the switch S6. The other of the source or drain of the first transistor is connected to the other electrode of the capacitance element 70 and the source of the transistor 69. The source and drain of the first transistor are electrically connected to the other of the source and drain, and to the wiring Vss.

[0157] Node FN50 is connected to the other of the source or drain of transistor 61, 2 and one of the electrodes of the capacitor 63. 60 denotes the other of the source or drain of a transistor 64, the gate of a transistor 65, The node FN70 is connected to one of the electrodes of the capacitance element 66. The gate of the transistor 67, the other electrode of the capacitance element 68, and one electrode of the switch S4 The node FN80 is connected to the gate of the transistor 71, the capacitance element 7 0, the other electrode of the switch S5, and the gate of the transistor 69. It is formed by

[0158] Next, the operation of the multiplication circuit 40a will be described with reference to FIGS. 10(A), 10(B), and 11. An example will be described.

[0159] First, FIG. 10A will be described. Switch S4, switch S7, and switch The node FN50 is connected to Vgs3 (=Vre f+ΔW) is written to the transistor 62, and a current I3 flows through the node FN70. A potential corresponding to the current I3 flowing through the transistor 67 is applied via the switch S4. At the same time, Vgs4 (=Vref) is written to node FN60 via wiring SLR. The current I4 flows through the transistor 65 via the switch S7. The current also flows to the transistor 72. Therefore, the potential equivalent to the current I4 is switched in the capacitance element 73. This is given via S15.

[0160] Next, the switches S4, S7, and S15 are turned off, and the node F The potential applied to N70 and the capacitive element 73 is stored.

[0161] Next, referring to FIG. 10B, when the switch S5 and the switch S8 are turned on, A potential corresponding to the current I4 flowing through the transistor 71 is applied to the node FN80. can be.

[0162] Next, by changing the potential of the signal line WD by data ΔV, the node FN50 has a capacitance Data ΔV is applied via element 63. That is, the potential of node FN50 is Vgs3 At the same time, the node FN60 changes from Vref to Vgs1 (=Vref+ΔW+ΔV). Data ΔV is applied via element 66. That is, the potential of node FN60 is Vgs4 to Vgs2 (=Vref+ΔV).

[0163] Next, the switches S9, S11, S13, and S14 are turned on. A potential corresponding to the current I2 flowing through the transistor 74 is applied to the capacitance element 75. Since the switches S13 and S14 are in the on state, the capacitance element 77 has a capacitance The same potential as that of the capacitance element 75 is applied to the switch S14. Instead, the gate of transistor 74 and the source of transistor 74 may be connected to the The same operation can be achieved even if the other of the drains is connected to the wiring Vdd.

[0164] Next, FIG. 11 will be described. Switch S9, switch S11, switch S13, and And the switch S14 is turned off. The node FN80 stores a given potential. Next, the switches S6, S10 and S12 are turned on.

[0165] Transistor 62 carries a current I1, transistor 67 carries a current I3, and transistor The transistor 76 can pass a current I2, and the transistor 69 can pass a current I4. By turning on switch S1, a current I5 can be supplied to conversion circuit 15. Therefore, the multiplication result of ΔW×ΔV can be obtained as I5.

[0166] FIG. 12 shows a multiplication cell 11a having a plurality of memory cells, a lift cell 11b having a plurality of memory cells, 8 in that it has a reference cell 12a and an arithmetic circuit 13b. The signal line NSEL4 is electrically connected to the switch S4, and the signal line NSEL5 is electrically connected to the switch S 7, and the switch S15, and the signal line NSEL6 is electrically connected to the switch S9, The signal line NSEL7 is electrically connected to the switches S11 and S13. The signal line NSEL8 is electrically connected to the switches S1, S2, and S3. The signal is electrically connected to the switch S6, the switch S10, and the switch S12. The line NSEL4 and the signal line NSEL5 may be combined into one signal line.

[0167] However, the number of memory cells in the multiplication cell 11a and the reference cell 12a is the same. The switch S1 may be a transistor, but it is more preferable. In most cases, it is better to use an analog switch. Using an analog switch allows for more accurate Multiplication can be done.

[0168] Also different is that the transistor 67a of the first programming cell is It is preferable to increase the channel width of the transistor according to the number of stages of a. When n stages of memory cells are connected in the multiplication cell 11a, the channel of the transistor 67a Preferably, the channel width of the transistor 62a is n times the channel width of the transistor 62b. It is preferable that the width of the transistor 62a is greater than n times the channel width of the transistor 62a.

[0169] The transistor 69a of the second programming cell is connected to the reference cell 12a in accordance with the number of stages. It is preferable to increase the channel width of the transistor depending on the When n stages of memory cells are connected in cell 12a, the channel of transistor 69a The width is preferably n times the channel width of the transistor 65a. , preferably greater than n times the channel width of transistor 65a.

[0170] Similarly, transistors 71a, 72a, 74a, and The channel width of the transistor 76a is set to be greater than n times the channel width of the transistor 65a. It is preferable that

[0171] FIG. 13 shows a neural network 84c which is different from the block diagram shown in FIG. 5(B). The difference from FIG. 5 is that the neuron in FIG. 13 has a reference cell 12 and The difference is that they share the arithmetic circuit 13. The memory cells of each neuron are The memory cells are connected via any one of the switches 90(1) to 90(i). By sharing the reference cell 12 and the arithmetic circuit 13, the neurons Packaging density is improved, allowing for more calculations to be performed.

[0172] This embodiment may be modified, added, revised, or deleted in part or in whole from other embodiments. , application, superordinate conception, or subordinate conception. Part or all of the above may be freely combined with part or all of the other embodiments, or It can be implemented in a replacement manner.

[0173] (Embodiment 3) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIG. A memory device to which a transistor (OS transistor) and a capacitive element are applied (hereinafter, The OS memory device is sometimes called an OS memory device. The memory device has a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Since the off-current of the S transistor is extremely small, the OS memory device has excellent retention characteristics. , it can function as a non-volatile memory.

[0174] <Storage device configuration example>

[0175] FIG. 14 shows the memories M1 to M3 described in the first embodiment and the memories M2 to M3 described in the second embodiment. A configuration example of a memory cell MC that can be applied to a multiplication circuit will be described.

[0176] [DOSRAM] 14A to 14C show examples of circuit configurations of memory cells MC of a DRAM. In the past, DRAMs using one-transistor, one-capacitor type memory cells were RAM(Dynamic Oxide Semiconductor Random A The memory cell 147 shown in FIG. The transistor T1 is a gate. It has a gate (sometimes called a front gate) and a back gate.

[0177] The first terminal of the transistor T1 is connected to the first terminal of the capacitance element CA, and the transistor T The second terminal of the transistor T1 is connected to the wiring BIL, and the gate of the transistor T1 is connected to the wiring WOL. The back gate of the transistor T1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0178] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low-level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor T1. By applying an arbitrary potential to the wiring BGL, the transistor The threshold voltage of the transistor T1 can be increased or decreased.

[0179] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. In addition, the back gate of the transistor T1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 14 shown in FIG. As shown in FIG. 73, a transistor having a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a transistor T1.

[0180] By using an OS transistor as the transistor T1, The leakage current can be made very low. In other words, the written data is transferred to the transistor T 1 allows long-term retention, reducing the frequency of refreshing memory cells. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very low, the memory cell 1471, the memory cell 1472, and the memory cell It is possible to hold multi-value data or analog data for the cell 1473.

[0181] In addition, in the DOSRAM, although not shown in the figure, there is a memory cell 1471 overlapping therewith. By providing a sense amplifier as shown in FIG. This reduces the bit line capacitance, making it possible to reduce the storage capacitance of the memory cell.

[0182] [NOSRAM] FIG. 14(D) to (H) show a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 shown in FIG. The transistor T2 is a front The present specification and the like include a gate (sometimes simply referred to as a gate), and a back gate. In the semiconductor memory device, a gain cell type memory cell using an OS transistor as the transistor T2 is provided. The storage device that is used is called NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called uctor RAM.

[0183] The first terminal of the transistor T2 is connected to the first terminal of the capacitance element CB, and the transistor T The second terminal of the transistor T2 is connected to the wiring WBL, and the gate of the transistor T3 is connected to the wiring WOL. The back gate of the transistor T2 is connected to the wiring BGL. The second terminal of the transistor T1 is connected to the line CAL. The first terminal of the transistor T2 is connected to the line R BL, the second terminal of the transistor T3 is connected to the line SL, and the second terminal of the transistor T The gate of 3 is connected to a first terminal of the capacitance element CB.

[0184] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor T2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0185] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor T2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell shown in FIG. Like the 1476, it has a single-gate transistor, i.e. no back gate. The memory cell may be configured with a transistor T2. For example, the memory cell MC As shown in FIG. 14G, the memory cell 1477 has a wiring WBL and a wiring RBL. The wiring BIL may be integrated.

[0186] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, A transistor 41 is used as T2, a transistor 42 is used as T3, The capacitance element CB can be a capacitance element 43. By using a transistor, the leakage current of the transistor T2 is made very low. This allows the written data to be held for a long time by the transistor T2. This allows the memory cells to be refreshed less frequently. This eliminates the need for memory cell refresh operations and has very low leakage current. Therefore, multi-value data or analog data can be stored in the memory cell 1474. The same is true for memory cells 1475 to 1477.

[0187] The transistor T3 may be a Si transistor. The conductivity type may be either n-channel or p-channel. In some cases, the field effect mobility of the read transistor may be higher than that of the OS transistor. A Si transistor may be used as the transistor T3 functioning as a transistor. In addition, by using a Si transistor for transistor T3, Since the transistor T2 can be provided in the same manner, the area occupied by the memory cell can be reduced and the memory This allows for a high degree of integration of the device.

[0188] Also, the transistor T3 may be an OS transistor. When OS transistors are used for the memory cells 1474 to 1477, n-type transistors are used. It can be constructed using transistors only.

[0189] FIG. 14(H) shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 14(H) includes transistors T4 to T6 and a capacitor. The memory cell 1478 has a capacitance element CC. The capacitance element CC is provided as appropriate. Electrically connected to L, RWL, WWL, BGL, and GNDL. Wire GNDL is a wiring for applying a low-level potential. , may be electrically connected to the wirings RBL and WBL.

[0190] The transistor T4 is an OS transistor having a back gate. The back gate and gate of the transistor T4 are electrically connected to the wiring BGL. Alternatively, the transistor T4 may have a back gate. It's not necessary.

[0191] The transistors T5 and T6 are n-channel Si transistors or p-channel Alternatively, the transistors T4 to T6 may be OS transistors. In this case, the memory cell 1478 is constructed using only n-type transistors. It is possible.

[0192] Note that the memory cells 1471 to 1478 and the like shown in this embodiment have the following configuration: The above is not intended to be limiting. These circuits, wiring connected to the circuits, and circuits The arrangement or functions of elements etc. may be changed, deleted or added as required.

[0193] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0194] This embodiment may be modified, added, revised, or deleted in part or in whole from other embodiments. , application, superordinate conception, or subordinate conception. Part or all of the above may be freely combined with part or all of the other embodiments, or It can be implemented in a replacement manner.

[0195] (Embodiment 4) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. An example of the chip 1200 is shown. A plurality of circuits (systems) are implemented on the chip 1200. The technology of integrating multiple circuits (systems) onto a single chip is called system-on-chip (SCC). This is sometimes called System on Chip (SoC).

[0196] As shown in FIG. 15A, the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing A memory controller 1214, an analog arithmetic unit 1212, an analog arithmetic unit 1213, an analog arithmetic unit 1214, an analog arithmetic unit 1215, an analog arithmetic unit 1216, an analog arithmetic unit 1217, an analog arithmetic unit 1218, an analog arithmetic unit 1219, an analog arithm The GPU has a network interface 1215, a network circuit 1216, etc. It is preferable to have a global network.

[0197] The chip 1200 is provided with bumps (not shown), and as shown in FIG. Printed Circuit Board (PCB) 1201 No. 1 The first surface of the PCB 1201 is connected to the second surface of the PCB 1202. 1203 is provided and connected to the motherboard 1203.

[0198] The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0199] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. becomes possible.

[0200] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0201] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit and a digital / analog conversion circuit. The multiply-and-accumulate circuit may be provided in the

[0202] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0203] The interface 1215 includes a display device, a speaker, a microphone, a camera, a The controller has an interface circuit for connecting to external devices such as a Such interfaces include computers, mobile phones, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) There can be.

[0204] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0205] The above circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering process, and the chip 1200 can be produced at low cost.

[0206] A PCB 1201 having a chip 1200 having a GPU 1212, a DRAM 122 1, and the motherboard 1203 on which the flash memory 1222 is provided is a GPU module. It can be called module 1204.

[0207] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, its excellent image processing capabilities make it a smart device. Phones, tablet devices, laptop PCs, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep Neural Networks (DNNs), Convolutional Neural Networks (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can perform operations such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0208] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0209] (Embodiment 5) In this embodiment mode, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is used in, for example, various electronic devices (e.g., Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (e.g., D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 16 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a format and used in various storage devices and removable memory.

[0210] FIG. 16A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0211] FIG. 16(B) is a schematic diagram of the external appearance of an SD card, and FIG. 16(C) is a schematic diagram of the inside of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, the substrate 11 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, The capacity can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the host device and the SD card 1110 to wirelessly communicate with each other. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0212] FIG. 16(D) is a schematic diagram of the external appearance of the SSD, and FIG. 16(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing 54, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0213] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0214] (Embodiment 6) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. Specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention will be described.

[0215] FIG. 17A shows a monitor 830. The monitor 830 includes a display unit 831, a housing 832, It also has a speaker 833, etc. In addition, it has an LED lamp, an operation key (power switch, or an operation It may have a variety of functions, including a power switch, connection terminals, various sensors, a microphone, etc. The monitor 830 can also be operated by a remote control 834 .

[0216] The monitor 830 can also receive broadcast waves and function as a television device. Cut.

[0217] The broadcasting waves that the monitor 830 can receive include terrestrial waves and waves transmitted from satellites. There are also analog and digital broadcasts as broadcasting waves. There are broadcasts of video and audio, or audio only. For example, UHF band (300 MHz or higher) 3GHz or less) or a specific frequency in the VHF band (30MHz to 300MHz) It is possible to receive broadcast radio waves transmitted in several frequency bands. By using multiple received data, the transfer rate can be increased and more information can be This allows you to display images with resolutions that exceed full HD. For example, 4K-2K, 8K-4K, 16K-8K , or higher resolution.

[0218] In addition, the Internet, LAN (Local Area Network), Wi-Fi i (registered trademark) or other data transmission technology via a computer network. The image to be displayed on the display unit 831 may be generated using the broadcast data. In this case, the monitor 830 does not need to have a tuner.

[0219] The monitor 830 can also be connected to a computer and used as a computer monitor. In addition, the monitor 830 connected to the computer can be viewed by multiple people at the same time. This can be used for a conference system. The monitor 830 can be used as a television by displaying information on the monitor 830 and connecting to the network. It can be used in a video conferencing system.

[0220] The monitor 830 can also be used as digital signage.

[0221] For example, the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion. The semiconductor device according to one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion. This enables high-speed operation and signal processing with low power consumption.

[0222] In addition, an image processing unit of a monitor 830 in an AI system using a semiconductor device according to one embodiment of the present invention By using it, noise reduction, gradation conversion, color correction, brightness correction, and other image processing can be performed. It can also perform pixel interpolation for resolution upconversion and It is possible to perform frame interpolation processing associated with frame frequency up-conversion. In addition, the tone conversion process not only converts the number of tones in an image, but also increases the number of tones. It also supports high dynamic range, which expands the dynamic range. High dynamic range (HDR) processing is also included in the tone conversion processing.

[0223] The video camera 2940 shown in FIG. 17B includes a housing 2941, a housing 2942, a display unit 2 943, an operation switch 2944, a lens 2945, and a connection part 2946. The operation switch 2944 and the lens 2945 are provided in the housing 2941. 43 is provided in a housing 2942. Also, a video camera 2940 is provided in a housing 2941. An antenna, a battery, etc. are provided inside. The housing 2941 and the housing 2942 are connected. The angle between the housing 2941 and the housing 2942 is the angle between the housing 2941 and the housing 2942 at the connection part 2946. The structure can be changed by the housing 2942 relative to the housing 2941. Depending on the angle, the orientation of the image displayed on the display unit 2943 can be changed, and the image can be displayed / hidden. It is possible to switch between the above.

[0224] For example, the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion. The semiconductor device according to one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion. This enables high-speed operation and signal processing with low power consumption.

[0225] In addition, an AI system using the semiconductor device of one embodiment of the present invention may be used for imaging the image of a video camera 2940. By using it in the image processing section, the video camera 2940 can take pictures according to the surrounding environment. Specifically, it can take pictures with the optimal exposure according to the surrounding brightness. When shooting in different lighting conditions, such as indoors and outdoors, It is possible to shoot dynamic range (HDR) images.

[0226] The AI ​​system can also learn the photographer's habits and provide assistance with photography. In essence, the camera learns the photographer's camera shake habits and corrects camera shake during shooting to improve the quality of the images. The image can be captured with minimal camera shake. When using the zoom function, adjust the lens orientation so that the subject is always in the center of the image. etc. can be controlled.

[0227] The information terminal 2910 shown in FIG. 17C includes a housing 2911, a display unit 2912, a microphone 29 17, speaker unit 2914, camera 2913, external connection unit 2916, and operation switch The display unit 2912 includes a display panel and a touch panel using a flexible substrate. The information terminal 2910 also includes an antenna, The information terminal 2910 is, for example, a smartphone, a mobile phone, a tablet, Used as a notebook type information terminal, tablet type personal computer, e-book terminal, etc. It is possible.

[0228] For example, a memory device using the semiconductor device of one embodiment of the present invention is the above-described information terminal 2910. It is possible to retain control information, control programs, etc. for a long period of time.

[0229] In addition, an AI system using the semiconductor device of one embodiment of the present invention can be used for image processing of an information terminal 2910. By using it in the processing part, noise reduction processing, gradation conversion processing, color correction processing, brightness correction processing, etc. In addition, pixel interpolation processing associated with resolution upconversion can be performed. and frame interpolation processing associated with frame frequency up-conversion. In addition, the tone conversion process not only converts the number of tones in an image, but also increases the number of tones. It can also expand the dynamic range and improve image quality. High dynamic range (HDR) processing is also included in the tone conversion processing.

[0230] In addition, the AI ​​system learns the user's habits and assists in operating the information terminal 2910. The information terminal 2910 equipped with an AI system can recognize the movements of the user's fingers and It is possible to predict touch input from gaze direction, etc.

[0231] The laptop personal computer 2920 shown in FIG. The display unit 2922, the keyboard 2923, and the pointing device 2924 are included. The laptop personal computer 2920 is housed inside a housing 2921. Equipped with an antenna, battery, etc.

[0232] For example, a memory device using the semiconductor device of one embodiment of the present invention may be a laptop personal computer. The control information and control programs of the computer 2920 can be stored for a long period of time. .

[0233] In addition, an AI system using the semiconductor device of one embodiment of the present invention can be used as a laptop personal computer. By using it in the image processing section of the computer 2920, noise reduction processing, gradation conversion processing, color It is possible to carry out image processing such as adjustment correction and brightness correction. Interpolation between pixels due to conversion and frame rate up-conversion Interpolation processing can be performed. The gradation conversion processing converts the number of gradations of the image. In addition, it can also perform interpolation of tone values ​​when increasing the number of tones. High dynamic range (HDR) processing, which expands the dynamic range, is also included in the tone conversion process. can be.

[0234] The AI ​​system will also learn the user's habits and use the laptop computer to It can assist the operation of the 2920. Laptop equipped with AI system The type personal computer 2920 detects the movement of the user's fingers, the line of sight, etc. on the display unit 29 22. Also, when inputting text, it is possible to predict past touch inputs. It predicts input based on text input information, surrounding text, pictures, and other images, and assists with conversion. This will minimize input errors and conversion errors.

[0235] FIG. 17(E) is an external view showing an example of an automobile, and FIG. 17(F) is an external view showing a navigation device 8. 60. The automobile 2980 includes a body 2981, wheels 2982, a dashboard 2 983, and lights 2984. The car 2980 also has an antenna, a battery, The navigation device 860 includes a display unit 861, an operation button 862, and and an external input terminal 863. The automobile 2980 and the navigation device 860 are Although each may be independent, the navigation device 860 may be incorporated in the automobile 2980. It is preferable that they are configured to function in conjunction with each other.

[0236] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used in an automobile 2980 or a navigation system. The control information and control programs of the application device 860 can be stored for a long period of time. In addition, an AI system using the semiconductor device of one embodiment of the present invention can be used as a control device for an automobile 2980, etc. By using this technology, the AI ​​system can learn the driver's driving skills and habits and provide assistance for safe driving. It can assist with driving by using fuel efficiently, such as gasoline and batteries, and Yes, it can. As a safe driving assistance, it not only learns the driver's driving skills and habits, but also , the behavior of the automobile, such as the speed and the way of movement of the automobile 2980, and the navigation device 860 It learns stored road information and other information in a comprehensive manner to prevent the vehicle from drifting out of its lane while driving, and other functions. This allows the vehicle to avoid collisions with other vehicles, pedestrians, structures, etc. If a road exists, the navigation device 860 transmits the road information to the automobile 2980. It can also control the speed of the automobile 2980 and assist with steering.

[0237] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0238] (Embodiment 7)

[0239] In this embodiment, the GPU or computer described in the above embodiment can be used. USABLE SEMICONDUCTOR DEVICE AND CONFIGURATION EXAMPLE OF OS TRANSISTOR THAT CAN BE USED IN THE SEMICONDUCTOR DEVICE - Patent application This article explains:

[0240] <Example of semiconductor device configuration> The semiconductor device shown in FIG. 18 includes a transistor 300, a transistor 200, and a capacitance element. FIG. 19A is a cross-sectional view of a transistor 200 in the channel length direction. 19(B) is a cross-sectional view of the transistor 200 in the channel width direction, and FIG. ) is a cross-sectional view of a transistor 300 in the channel width direction.

[0241] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 200 is small, it is suitable for use in a semiconductor device. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operation is extremely low, Therefore, the power consumption can be sufficiently reduced.

[0242] In the semiconductor device shown in FIG. 18, the wiring 1001 is connected to the source and drain of the transistor 300. The wiring 1002 is connected to one of the source and drain of the transistor 300. The wiring 1003 is connected to the source and drain of the transistor 200. A wiring 1004 is connected to the top gate of the transistor 200. Line 1006 is connected to the bottom gate of transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitance element. A wiring 1005 is connected to one of the electrodes of the capacitor 100. It is being done.

[0243] Here, when the semiconductor device described in this embodiment is used for the memory cell described in Embodiment 3, , transistor T2 is transistor 200, and transistor T3 is transistor 300. , the capacitance element CB corresponds to the capacitance element 100. The wiring SL is connected to the wiring 1001. RBL is connected to the wiring 1002, WBL is connected to the wiring 1003, and WOL is connected to the wiring 100 4, the wiring CAL corresponds to the wiring 1005, and the wiring BGL corresponds to the wiring 1006.

[0244] In addition, when the semiconductor device described in this embodiment is used for the arithmetic circuit described in Embodiment 2, For example, transistor 42 is transistor 300, transistor 41 is transistor 200, and capacitive element 43 corresponds to capacitive element 100.

[0245] In addition, when the semiconductor device described in this embodiment is used for both the memory cell and the arithmetic circuit, Transistor T3 and transistor 42, transistor T2 and transistor 41, and capacitance element C B and the capacitance element 43 can be formed in the same process. This simplifies the process and reduces costs.

[0246] As shown in FIG. 18, a semiconductor device according to one embodiment of the present invention includes a transistor 300 and a transistor The transistor 200 is disposed above the transistor 300. The capacitance element 100 is provided above the transistor 300 and the transistor 200. It is being done.

[0247] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate 316. 11, a semiconductor region 313 that functions as a source region or a drain region. 3, the first and second low resistance regions 314a and 314b are in contact with each other.

[0248] As shown in FIG. 19C, the transistor 300 is The side surfaces in the width direction of the panel are covered with the conductor 316 via the insulator 315. By forming the transistor 300 as a fin type, the effective channel width is increased. This improves the on-characteristics of the transistor 300. Since the contribution can be increased, the off-characteristics of the transistor 300 can be improved. Cut.

[0249] The transistor 300 may be either a p-channel type or an n-channel type.

[0250] The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon is It is preferable that the semiconductor material includes a silicon-based semiconductor, and it is preferable that the semiconductor material includes single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium The insulating layer may be made of a material having a thickness of 100 nm, such as gallium aluminum arsenide (GaAlAs), or the like. By applying stress to the crystal lattice and changing the lattice spacing, we have developed silicon with controlled effective mass. Alternatively, GaAs and GaAlAs may be used to form a transistor. The 300 is a HEMT (High Electron Mobility Transistor) tor).

[0251] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that provide n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The element contains an element that imparts electrical conductivity.

[0252] The conductor 316 that functions as the gate electrode is made of an element that imparts n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon that contain elements that give them p-type conductivity, such as boron or arsenic. A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0253] Since the work function is determined by the conductor material, the conductor material can be changed to The Vth of the transistor can be adjusted. It is preferable to use a material such as tantalum. It is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor. In particular, tungsten is preferably used from the viewpoint of heat resistance.

[0254] The transistor 300 shown in FIG. 18 is merely an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the type and driving method. For example, the transistor 200 Similarly, the transistor 300 may be formed using an oxide semiconductor.

[0255] Covering the transistor 300 are an insulator 320, an insulator 322, an insulator 324, and an insulator 326. The bodies 326 are stacked in order.

[0256] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum oxynitride, aluminum nitride, or the like may be used.

[0257] The insulator 322 smoothes out the steps caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 is The surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0258] The insulator 324 is also provided with a transistor-insulating layer 324, which is connected to the substrate 311 or the transistor 300. A film having a barrier property that prevents diffusion of hydrogen and impurities is used in the region where the capacitor 200 is provided. It is preferable that

[0259] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. When hydrogen diffuses into the element, the characteristics of the semiconductor element may deteriorate. A film that suppresses hydrogen diffusion is provided between the transistors 200 and 300. Specifically, a film that suppresses hydrogen diffusion is preferably a film that reduces the amount of hydrogen desorption. The membrane.

[0260] The amount of desorption of hydrogen can be measured, for example, by thermal desorption spectroscopy (TDS). For example, The amount of hydrogen desorption from the insulator 324 was measured by TDS analysis when the surface temperature of the film was changed from 50°C to 500°C. In the range of °C, the amount of desorption converted into hydrogen atoms is converted into , 10×10 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0261] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulating material 26 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. It is more preferable to use a material with a low dielectric constant as the interlayer film to reduce the parasitic capacitance between wiring lines. It is possible.

[0262] In addition, the insulators 320, 322, 324, and 326 are provided with a capacitance element 1. 00, or the conductor 328 and the conductor 330 connected to the transistor 200 are filled in. The conductor 328 and the conductor 330 function as plugs or wiring. Conductors that function as plugs or wiring can also be used to group multiple structures together in the same In addition, in this specification, a wiring and a plug connected to the wiring may be In other words, a part of the conductor functions as a wiring, and In some cases, a portion of the conductor serves as the plug.

[0263] The materials for each plug and wiring (the conductor 328, the conductor 330, etc.) are metal materials. Conductive materials such as metal alloys, metal nitrides, or metal oxides are applied as single layers or They can be used in layers. Materials such as tungsten and molybdenum that are both heat-resistant and conductive are used. It is preferable to use a high melting point material such as tungsten. It is preferable to form the conductive layer from a low-resistance conductive material such as aluminum or copper. By using this, the wiring resistance can be reduced.

[0264] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It can be done.

[0265] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 356 has a barrier property against hydrogen. In particular, the insulator 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the resistor 300 to the transistor 200.

[0266] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the transistor 300. In this case, the tantalum nitride layer having a barrier property against hydrogen It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0267] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed in the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using similar materials.

[0268] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 366 has a barrier property against hydrogen. It is preferable that the insulating material 360 contains a conductor. In particular, the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the resistor 300 to the transistor 200.

[0269] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed in the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using similar materials.

[0270] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 376 has a barrier property against hydrogen. It is preferable that the insulating material 370 contains a conductor. In particular, the insulating material 370 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the resistor 300 to the transistor 200.

[0271] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed in the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using similar materials.

[0272] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 386 has a barrier property against hydrogen. In particular, the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the resistor 300 to the transistor 200.

[0273] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, and the conductor 376 The wiring layer including the conductor 386 and the wiring layer including the conductor 387 have been described above. However, the semiconductor device to be used is not limited to this. Alternatively, the number of wiring layers may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more. Good too.

[0274] On the insulator 384, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are formed. The insulators 210, 212, 214, and 216 are stacked in this order. It is preferable that any of the insulating bodies 216 is made of a material having a barrier property against oxygen and hydrogen. stomach.

[0275] For example, the insulator 210 and the insulator 214 may include, for example, a substrate 311 or a transistor. Hydrogen and impurities are introduced from the region where the transistor 300 is provided to the region where the transistor 200 is provided. It is preferable to use a film having a barrier property to prevent diffusion. The same materials as in 4 can be used.

[0276] As an example of a film that has a barrier property against hydrogen, silicon nitride formed by CVD method is used. Here, a semiconductor element including an oxide semiconductor such as the transistor 200 can be The diffusion of hydrogen may deteriorate the characteristics of the semiconductor device. A film that suppresses hydrogen diffusion is used between the transistor 200 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that has a small amount of hydrogen desorption. .

[0277] In addition, as a film having a barrier property against hydrogen, for example, the insulator 210 and the insulator 2 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0278] In particular, aluminum oxide is highly resistant to oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. The membrane has a high blocking effect, preventing both impurities such as oxygen and water from penetrating the membrane. Aluminum oxide is highly resistant to hydrogen, moisture, and other elements during and after the transistor manufacturing process. It is possible to prevent impurities from being mixed into the transistor 200. This can suppress the release of oxygen from the oxide that constitutes the transistor. Suitable for use as a protective film against 200.

[0279] For example, the insulator 212 and the insulator 216 are made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant as the interlayer film, the For example, the insulators 212 and 216 may be A silicon oxide film, a silicon oxynitride film, or the like can be used.

[0280] In addition, the insulators 210, 212, 214, and 216 are each provided with a conductor 2 18, and a conductor (conductor 203) constituting the transistor 200 is embedded. The conductor 218 is a plug connected to the capacitor 100 or the transistor 300. The conductor 218 functions as a conductor 328 and a conductor 3 It can be provided using the same material as 30.

[0281] In particular, the insulator 210 and the conductor 218 in the area in contact with the insulator 214 are resistant to oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 200 have a barrier property against oxygen, hydrogen, and water. The hydrogen transfer from transistor 300 to transistor 200 can be achieved by a layer that separates the Diffusion can be suppressed.

[0282] Above the insulator 216 is a transistor 200 .

[0283] As shown in FIGS. 19A and 19B, the transistor 200 includes an insulator 214 and an insulator A conductor 203 is disposed so as to be embedded in the insulator 216, and the insulator 216 and the conductor 203 are disposed so as to be embedded in the insulator 216. An insulator 220 disposed on the insulator 220, an insulator 222 disposed on the insulator 220, and an insulator An insulator 224 is disposed on the insulating layer 222, and an oxide layer 230a is disposed on the insulating layer 224. and oxide 230b disposed on oxide 230a, and oxide 230b disposed on oxide 230b. The conductor 242a and the conductor 242b are arranged in a parallel relationship. 242b, and an opening is formed between and overlapping the conductor 242a and the conductor 242b. The insulating material 280 is disposed in the opening, the conductor 260 is disposed in the opening, and the oxide 230b and the conductor 24 are disposed in the opening. 2a, conductor 242b, and an insulator disposed between insulator 280 and conductor 260. The body 250, the oxide 230b, the conductor 242a, the conductor 242b, and the insulator 280. , an insulator 250, and an oxide 230c disposed therebetween. As shown in FIG. 2B, the oxide 230a, the oxide 230b, the conductor 242a, and the conductor It is preferable that an insulator 244 is disposed between the body 242b and the insulator 280. As shown in FIG. 19(A) and FIG. 19(B), the conductor 260 is a conductor provided inside the insulator 250. A conductive body 260a and a conductive body 260b embedded inside the conductive body 260a. As shown in FIGS. 19(A) and 19(B), the insulator 280 Preferably, an insulator 274 is disposed over the conductors 260 and the insulator 250 .

[0284] In the following, oxide 230a, oxide 230b, and oxide 230c are collectively referred to as oxides 230a, 230b, and 230c. The conductor 242a and the conductor 242b are collectively referred to as oxide 230. This may be referred to as conductor 242.

[0285] In the transistor 200, the region where the channel is formed and the vicinity thereof are oxidized. The structure shown is one in which three layers of a substrate 230a, an oxide 230b, and an oxide 230c are laminated. However, the present invention is not limited thereto. For example, a single layer of oxide 230b, A two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, Alternatively, a stacked structure of four or more layers may be provided. Although the conductor 260 is shown as a two-layer laminate structure, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers. The transistor 200 illustrated in FIGS. 18 and 19(A) and (B) is just an example. The present invention is not limited to the above structure, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0286] Here, the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and The conductor 242b functions as a source electrode and a drain electrode, respectively. As shown, the conductor 260 is inserted through the opening in the insulator 280 and through the conductors 242a and 242b. The conductor 260, the conductor 242a and the conductor 242b are formed so as to be embedded in the sandwiched region. The arrangement of the conductive body 242b is selected to be self-aligned with respect to the opening of the insulator 280. In the transistor 200, the gate electrode is connected between the source electrode and the drain electrode. Therefore, the conductor 260 can be aligned with the substrate 220 by providing a margin for alignment. Since the transistor 200 can be formed without any additional steps, the area occupied by the transistor 200 can be reduced. This allows miniaturization and high integration of semiconductor devices.

[0287] Furthermore, a conductor 260 is formed in a self-aligned manner in the region between the conductors 242a and 242b. Therefore, the conductor 260 has an overlapping area with the conductor 242a or the conductor 242b. As a result, the conductive body 260 does not have a shape between the conductive body 242a and the conductive body 242b. Therefore, the parasitic capacitance of the transistor 200 can be reduced. It is possible to improve the speed and have high frequency characteristics.

[0288] The conductor 260 may function as a first gate (also called a top gate) electrode. The conductor 203 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 203 may be changed to the potential applied to the conductor 260. By changing them independently, the Vth of the transistor 200 can be controlled. In particular, applying a negative potential to the conductor 203 can turn on the transistor 200. It is possible to increase the Vth of the transistor above 0V and reduce the off-state current. Applying a negative potential to the conductor 203 reduces the amount of potential applied to the conductor 260 compared to not applying a negative potential. The drain current when the potential is 0V can be reduced.

[0289] The conductor 203 is arranged to overlap the oxide 230 and the conductor 260. Therefore, when a potential is applied to the conductor 260 and the conductor 203, The electric field generated by the conductor 203 is connected to the electric field generated by the conductor 203, and the chalcogenide formed in the oxide 230 is generated. In the present specification, the first gate electrode and the second gate electrode are The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region This is called the surrounded channel (S-channel) structure.

[0290] The conductor 203 has the same configuration as the conductor 218, and the insulators 214 and 2 A conductor 203a is formed in contact with the inner wall of the opening 16, and a conductor 203b is formed further inside. It has been made.

[0291] The insulators 220, 222, 224, and 250 serve as gate insulators. It has all the functions.

[0292] Here, the insulator 224 in contact with the oxide 230 has more oxygen than satisfies the stoichiometric composition. In other words, the insulator 224 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is connected to the oxide 230. By providing the oxide 230 in the oxide layer 230, the oxygen vacancies in the oxide layer 230 are reduced, and the reliability of the transistor 200 is improved. It is possible to improve the performance.

[0293] As an insulator having an excess oxygen region, specifically, an oxide film in which some oxygen is released by heating is used. It is preferable to use materials that release oxygen when heated. , the amount of oxygen released in terms of oxygen atoms is 1.0 × 1018 atoms / cm 3 Above, I like Or 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 a toms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide film is The surface temperature of the film during the TDS analysis was 100°C to 700°C. or in the range of 100° C. or higher and 400° C. or lower.

[0294] Also, if the insulator 224 has an excess oxygen region, the insulator 222 is oxygen-resistant (e.g., It has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the oxygen is not transmitted It is preferable that the above-mentioned

[0295] The insulator 222 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 230 is effective. The oxygen does not diffuse to the insulator 220 side, which is preferable. This can prevent the insulator 224 and the oxide 230 from reacting with oxygen.

[0296] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or silica. Co, Lead Zirconate Titanate (PZT), Strontium Titanate (SrTiO3) Alternatively, insulators containing (Ba,Sr)TiO3 (BST) etc. can be used in a single layer or multilayer. As transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using a high-k material for the gate, the physical thickness is maintained while the gate insulating film is It is possible to reduce the potential.

[0297] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen does not easily penetrate ) Insulating materials containing oxides of one or both of aluminum and hafnium Insulators containing oxides of aluminum and / or hafnium are recommended. The oxides include aluminum oxide, hafnium oxide, aluminum and hafnium. It is preferable to use oxide (hafnium aluminate) etc. When the insulator 222 is formed by the above method, the insulator 222 is resistant to oxygen release from the oxide 230 and to A layer for suppressing the intrusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230 is provided. It works like this.

[0298] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. Aluminum, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added to the insulator, or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the insulator.

[0299] In addition, the insulator 220 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are preferred because they are thermally stable. Combining an insulator with silicon oxide or silicon oxynitride makes it thermally stable. Moreover, it is possible to obtain the insulator 220 having a laminated structure with a high relative dielectric constant.

[0300] The insulators 220, 222, and 224 each have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. A laminated structure may also be used.

[0301] The transistor 200 has an oxide 230 including a channel formation region, which functions as an oxide semiconductor. It is preferable to use a metal oxide that can perform the function. For example, the oxide 230 is In-Mn-Zn. n oxides (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium , boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum Tantalum, Cerium, Neodymium, Hafnium, Tantalum, Tungsten, or Magnesium It is preferable to use a metal oxide such as one or more selected from the following. As the material 30, an In-Ga oxide or an In-Zn oxide may be used.

[0302] The metal oxide that functions as the channel forming region in the oxide 230 has a band gap of It is preferable to use one having an energy of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. This can be done.

[0303] The oxide 230 has the oxide 230a under the oxide 230b, so that the oxide 230 is thicker than the oxide 230a. It is possible to suppress the diffusion of impurities from the structure formed below into the oxide 230b. In addition, by having the oxide 230c on the oxide 230b, the oxide 230c can be more effectively removed than the oxide 230c. It is possible to suppress the diffusion of impurities from the structure formed above into the oxide 230b. .

[0304] The oxide 230 has a layered structure made of oxides having different atomic ratios of metal atoms. Specifically, it is preferable that the metal oxide used for the oxide 230a has a composition element of The atomic ratio of element M in the metal oxide used for oxide 230b is It is preferable that the atomic ratio of M is larger than that of M. In addition, the metal oxide used for the oxide 230a is In the metal oxide used for the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide, the atomic ratio of In to element M is In the metal oxide, the atomic ratio of In to the element M is preferably larger than that of In. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. can be used.

[0305] In addition, the energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the oxide is higher than the conduction band minimum energy of the oxide. The electron affinity of oxide 230a and oxide 230c is smaller than the electron affinity of oxide 230b. It is preferable.

[0306] Here, at the junctions of the oxide 230a, the oxide 230b, and the oxide 230c, The energy level of the lower band edge changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is continuous. In order to achieve this, the oxide 2 At the interface between oxide 30a and oxide 230b, and at the interface between oxide 230b and oxide 230c, In this case, the defect level density of the mixed layer formed by the above process is preferably reduced.

[0307] Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c are oxides. By having a common element other than the element (main component), a mixed layer with low defect level density is formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and oxide 230c are In-Ga-Zn oxide, Ga-Zn oxide, oxide For example, gallium nitride may be used.

[0308] At this time, the main path of the carriers is the oxide 230b. By configuring the oxide 230c as described above, the interface between the oxide 230a and the oxide 230b and the oxide The defect state density at the interface between the substrate 230b and the oxide 230c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 has a high On-current can be obtained.

[0309] On the oxide 230b, a conductor 242 ( Conductor 242a and conductor 242b are provided. The conductor 242 is made of aluminum. Aluminum, Chromium, Copper, Silver, Gold, Platinum, Tantalum, Nickel, Titanium, Molybdenum, Tungsten Stainless steel, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Selected from the group consisting of ruthenium, indium, ruthenium, iridium, strontium, and lanthanum. or an alloy containing the above-mentioned metal elements or a combination of the above-mentioned metal elements. For example, tantalum nitride, titanium nitride, tungsten nitride, etc. are preferably used. , nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing tantalum nitride, titanium nitride, titanium and aluminum nitride, tantalum and aluminum nitride, ruthenium oxide, Ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen. Therefore, it is preferable.

[0310] As shown in FIG. 19A, the oxide 230 has a conductor 242 and a conductor 242 at its interface and in the vicinity thereof. In the second embodiment, a region 243 (region 243a and region 243b) is formed as a low resistance region. In this case, the region 243a functions as either a source region or a drain region. The region 243b functions as the other of the source region and the drain region. A channel forming region is formed in the region between 43a and region 243b.

[0311] By providing the conductor 242 so as to be in contact with the oxide 230, the oxygen concentration in the region 243 In addition, the metal contained in the conductor 242 and the oxide 230 in the region 243 may be reduced. In such a case, a metal compound layer containing the above components may be formed. The carrier density increases and region 243 becomes a low resistance region.

[0312] The insulator 244 is provided to cover the conductor 242 and prevents the conductor 242 from being oxidized. At this time, the insulator 244 is set to cover the side surface of the oxide 230 and to be in contact with the insulator 224. It may be possible to do so.

[0313] The insulator 244 may be selected from hafnium, aluminum, gallium, yttrium, zirconium, and the like. Titanium, tungsten, titanium, tantalum, nickel, germanium, or magnesium A metal oxide containing one or more selected from the above can be used.

[0314] In particular, the insulator 244 may be made of oxide of one or both of aluminum and hafnium. Insulators containing aluminum oxide, hafnium oxide, aluminum and hafnium It is preferable to use oxides containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. In the treatment, it is preferable that the conductor 242 is made of a material having oxidation resistance. If the electrical conductivity does not decrease significantly when the material absorbs oxygen, the insulator 244 is not essential. It is not a matter of the configuration. It can be designed appropriately according to the desired transistor characteristics.

[0315] The insulator 250 functions as a gate insulator. The insulator 250 is formed inside the oxide 230c. It is preferable to place the insulator 250 in contact with the upper surface and the side surface. It is preferable to form the insulating material by using an insulator that emits oxygen atoms. The amount of oxygen released is 1.0×10 18 atoms / cm 3 Above, preferably 1. 0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film during the TDS analysis is in the range of 100°C to 700°C. preferable.

[0316] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, and nitrogen Silicon oxide doped with fluorine, silicon oxide doped with carbon, carbon and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0317] An insulator that releases oxygen when heated is used as the insulator 250 and is attached to the top surface of the oxide 230c. By providing the oxide 230b in the insulating layer 250, the oxide 230c passes through the oxide 230b. It is possible to effectively supply oxygen to the channel formation region. In particular, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The thickness of the edge 250 is preferably 1 nm or more and 20 nm or less.

[0318] In addition, in order to efficiently supply the excess oxygen contained in the insulator 250 to the oxide 230, A metal oxide may be provided between the body 250 and the conductor 260. The metal oxide may be an insulator. It is preferable to suppress the diffusion of oxygen from the conductive material 250 to the conductive material 260. The metal oxide prevents excess oxygen from diffusing from the insulator 250 to the conductor 260. In other words, the reduction in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In this case, the oxidation of the conductor 260 due to excess oxygen can be suppressed. Any material that can be used for the insulator 244 may be used.

[0319] The conductor 260 functioning as the first gate electrode has a two-layer structure in FIGS. However, it may have a single layer structure or a laminated structure of three or more layers.

[0320] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule ( Conductive material with the function of suppressing the diffusion of impurities such as copper atoms, NO, NO, etc. It is preferable to use a material that is low in oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of the conductive material 26. Since 0a has the function of suppressing the diffusion of oxygen, the oxygen contained in the insulator 250 Therefore, it is possible to prevent the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing the above include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium oxide or ruthenium oxide.

[0321] The conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260b also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated material. For example, a laminated structure of titanium, titanium nitride and the conductive material may be used. .

[0322] The insulator 280 is provided on the conductor 242 via the insulator 244. For example, the insulator 280 may be silicon oxide. Silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, Carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, vacancy-containing oxide It is preferable that the insulating layer 100 has a silicon oxide or a resin. In particular, silicon oxide and oxynitride are preferable. Silicon oxide is preferred because it is thermally stable. In particular, silicon oxide and oxide having vacancies are preferred. Silicon is preferred because it allows for easy formation of excess oxygen regions in a later step.

[0323] The insulator 280 preferably has an excess oxygen region. By providing the insulator 280 in contact with the oxide 230c, the oxygen in the insulator 280 is converted into the oxide 230c, the oxide 230 can be efficiently supplied to the region 243. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced.

[0324] The opening of the insulator 280 is formed to overlap the region between the conductor 242a and the conductor 242b. As a result, the conductor 260 is inserted through the opening of the insulator 280 and the conductor 242a and the conductor 242b. It is formed so as to be embedded in the region sandwiched between 242b.

[0325] In miniaturizing semiconductor devices, it is necessary to shorten the gate length. It is necessary to prevent the conductivity of the conductive material 260 from decreasing. As a result, the conductor 260 can have a shape with a high aspect ratio. In order to embed the conductor 260 in the opening of the insulator 280, the aspect ratio of the conductor 260 is set to 1. Even if the conductor 260 has a high shape, it can be formed without collapsing during the process. do.

[0326] The insulator 274 is connected to the upper surface of the insulator 280, the upper surface of the conductor 260, and the upper surface of the insulator 250. It is preferable that the insulator 274 is provided in contact with the insulating film 274 by sputtering. In this way, an excess oxygen region can be provided in the insulator 250 and the insulator 280. Oxygen can be provided into the oxide 230 from the excess oxygen region.

[0327] For example, the insulator 274 may be hafnium, aluminum, gallium, yttrium, di Zr, tungsten, titanium, tantalum, nickel, germanium, or magnesium One or more metal oxides selected from the group consisting of tungsten, tungsten, and tungsten can be used. do.

[0328] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier against impurities such as hydrogen. It can also function as a membrane.

[0329] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281, like the insulator 224, has a low impurity concentration, such as water or hydrogen, in the film. It is preferable that the amount of the ion exchange rate is reduced.

[0330] In addition, the openings formed in the insulators 281, 274, 280, and 244 Conductor 240a and conductor 240b are placed in the mouth. The conductors 240a and 240b are disposed opposite each other with the conductor 260 in between. has the same configuration as conductor 246 and conductor 248 described later.

[0331] An insulator 282 is provided on the insulator 281. The insulator 282 is resistant to oxygen and hydrogen. It is preferable to use a material having a barrier property for the insulator 282. The insulator 282 may be made of a material similar to that of the insulator 214. For example, the insulator 282 may be made of aluminum oxide. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0332] In particular, aluminum oxide is highly resistant to oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. The membrane has a high blocking effect, preventing both impurities such as oxygen and water from penetrating the membrane. Aluminum oxide is highly resistant to hydrogen, moisture, and other elements during and after the transistor manufacturing process. It is possible to prevent impurities from being mixed into the transistor 200. This can suppress the release of oxygen from the oxide that constitutes the transistor. Suitable for use as a protective film against 200.

[0333] Further, an insulator 286 is provided on the insulator 282. The insulator 286 is The same material as that of 20 can be used. In addition, a material with a relatively low dielectric constant is used as the interlayer film. By doing so, it is possible to reduce the parasitic capacitance between the wirings. A silicon oxide film, a silicon oxynitride film, or the like can be used.

[0334] In addition, the insulator 220, the insulator 222, the insulator 224, the insulator 244, the insulator 280, the insulator The body 274, the insulator 281, the insulator 282, and the insulator 286 are provided with the conductor 246, and and a conductor 248, etc. are embedded therein.

[0335] The conductor 246 and the conductor 248 are the capacitor element 100, the transistor 200, or the transistor The conductor 246 functions as a plug or wiring that connects to the transistor 300. The conductor 248 may be formed using the same material as the conductor 328 and the conductor 330. can.

[0336] Next, the capacitor 100 is provided above the transistor 200. 00 has a conductor 110, a conductor 120, and an insulator 130.

[0337] The conductor 112 may be provided on the conductor 246 and the conductor 248. Reference numeral 12 serves as a plug or wiring for connection to the transistor 200. The conductor 110 functions as an electrode of the capacitor 100. The electrical conductors 110 can be formed at the same time.

[0338] The conductor 112 and the conductor 110 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above-mentioned elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, etc.) Indium tin oxide (ITO) or tungsten nitride (Tungsten nitride) can be used. tungsten oxide-containing indium oxide; tungsten oxide-containing indium zinc oxide oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Conductive materials such as indium zinc oxide and indium tin oxide with added silicon oxide are used. It is also possible.

[0339] In FIG. 18, the conductor 112 and the conductor 110 are shown as having a single-layer structure. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors that have barrier properties and have good adhesion to highly conductive conductors. It may be made highly conductive.

[0340] The conductor 120 is provided so as to overlap with the conductor 110 with the insulator 130 interposed therebetween. The conductor 120 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is advisable to use a

[0341] An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 150 can be provided using the same material as the insulator 320. It may also function as a planarizing film that covers the uneven shape underneath.

[0342] By using this structure, a semiconductor device using a transistor having an oxide semiconductor In this way, the fluctuation of the electrical characteristics can be suppressed and the reliability can be improved. It is possible to provide a transistor including an oxide semiconductor having a large current. It is possible to provide a transistor including an oxide semiconductor and having low current. It is possible to provide a semiconductor device with reduced power consumption. In a semiconductor device using a transistor, miniaturization or high integration can be achieved.

[0343] <Transistor configuration example 1> In FIG. 18 and FIG. 19, a conductor 242 serving as a source electrode or a drain electrode is The structure example in which the oxide 230 is formed in contact with the OS transistor has been described. The configuration is not limited to this. For example, the conductor 242 is not provided, and the oxide 230 is selectively made to have a low resistance. By using a structure in which the oxide 230b is provided with a source region or a drain region, An example of the configuration of such a transistor is shown in FIG.

[0344] FIG. 20A is a cross-sectional view of a transistor 200A in the channel length direction, and FIG. 20 is a cross-sectional view of a transistor 200A in a channel width direction. The transistor 200A is a modified example of the transistor 200 shown in FIG. To avoid this, differences from transistor 200 will be mainly described.

[0345] The transistor 200A is a transistor having an oxide layer including a channel formation region, similar to the transistor 200. The layer 230 can be made of a metal oxide that functions as an oxide semiconductor.

[0346] The oxide 230 is doped with an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. By doing so, the carrier density may increase, and the resistance may be reduced. Representative elements include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, etc. fluorine, sulfur, chlorine, titanium, rare gases, etc. may be used. Representative examples of rare gases include helium, Examples of lanthanum, neon, argon, krypton, and xenon.

[0347] The concentrations of the above elements were measured using secondary ion mass spectrometry (SIMS). Measurement can be performed using a method such as n-type mass spectrometry.

[0348] In particular, boron and phosphorus are used in the manufacturing process of amorphous silicon or low-temperature polysilicon. This is preferable because the equipment in the manufacturing line can be used. This will help reduce capital investment.

[0349] The region 243 (region 243a and region 243b) shown in FIG. 20 is formed on the oxide 230b. The region 243 is a region where the above-mentioned elements are added. For example, a dummy gate is used for the region 243. It can be formed with.

[0350] For example, a dummy gate is provided on the oxide 230b, and the dummy gate is used as a mask. In this case, it is preferable to add an element that reduces the resistance of the oxide 230b. The element is added to the region not overlapping with the dummy gate, forming a region 243 . The method of adding the element is to add the ionized source gas by mass separation. The ion implantation method, the ion doping method in which ionized source gas is added without mass separation, A plasmon ion implantation method or the like can be used.

[0351] Next, an insulating film that will become the insulator 244 is formed on the oxide 230b and the dummy gate. An insulating film that will become the insulator 245 may be formed. As will be described later, before removing the dummy gate, An insulating film to be the insulator 244 and an insulating film to be the insulator 245 are laminated on the dummy gate. By providing the insulating material 242 and the insulating material 243 on the side wall of the opening after removing the dummy gate, The stack of the insulator 244 and the insulator 245 formed on the dummy gate is formed. An element that reduces the resistance of the oxide 230b is added from above the layer film. 230c and the insulator 250 overlap each other. It is possible to provide an area where

[0352] Specifically, after forming an insulating film that will become the insulator 280 on the insulating film that will become the insulator 245, The insulating film that will become the body 280 is CMP (Chemical Mechanical Polishing). By carrying out the etching process, a part of the insulating film that will become the insulator 280 is removed, and a dummy gate When the dummy gate is subsequently removed, the insulator 244 in contact with the dummy gate is exposed. Therefore, the side of the opening in the insulator 280 is also partially removed. 245 and the insulator 244 are exposed, and the bottom surface of the opening is provided with the oxide 230b. A part of the insulating region 243 is exposed. Next, an oxide film that becomes the oxide 230c is formed in the opening. After forming an insulating film that will become the insulator 250 and a conductive film that will become the conductor 260 in this order, The oxide film that becomes the oxide 230c and the insulator 250 are formed by CMP processing or the like until the insulating layer 80 is exposed. 20. By removing a part of the insulating film which will become the conductor 260 and a part of the conductive film which will become the conductor 260, A transistor can be formed.

[0353] The insulator 244 and the insulator 245 are not essential components. The design should be appropriate depending on the requirements.

[0354] The transistor 200A shown in FIG. 20 can be made from an existing device. Unlike the transistor 200, the conductor 242 is not provided, so that the cost can be reduced. do. [Explanation of symbols]

[0355] DA1: Signal line, DA2: Signal line, DAM1: Signal line, DAM2: Signal line, DAP1: Signal line Line, DAP2: Signal line, FN10: Node, FN20: Node, FN30: Node, F N40: Node, FN50: Node, FN60: Node, FN70: Node, FN80: Node, FO1: signal line, FO2: signal line, FO3: signal line, FO4: signal line, FOUT 1: Signal line, FOUT2: Signal line, I1: Current, I2: Current, I3: Current, I4: Current, I5: Current, M1: Memory, M2: Memory, M3: Memory, M4: Memory, M5: Memory , M6: memory, 21: memory, 24a: memory, 24b: memory, 31a: memory, 3 1b: memory, 31c: memory, 31d: memory, MB1: signal line, MB2: signal line, R EM1: signal line, REM2: signal line, REP1: signal line, REP2: signal line, S1: switch S1: Switch, S2: Switch, S3: Switch, S4: Switch, S5: Switch, S6: Switch switch, S7: switch, S8: switch, S9: switch, S10: switch, S11: Switch, S12: Switch, S13: Switch, S14: Switch, S15: Switch , SW0: Switch, SW1: Switch, UFM1: Signal line, UFM2: Signal line, UFP 1: signal line, UFP2: signal line, WEM1: signal line, WEM2: signal line, WEP1: signal line, WEP2: signal line, WL1: signal line, 10: addition circuit, 10a: addition circuit, 11: multiplication Calculation cell, 11a: Multiplication cell, 12: Reference cell, 12a: Reference cell, 13 : arithmetic circuit, 13a: arithmetic circuit, 15: conversion circuit, 15a: IV conversion circuit, 15b: amplification Circuit, 20: selector, 22: counter, 22a: CNP, 22b: CNM, 23: control circuit, 24: selector, 25: control circuit, 26: zero insertion circuit, 26a: zero insertion circuit, 26b: zero insertion circuit, 26c: gate circuit, 27: arithmetic circuit, 28: adder circuit, 29: gate circuit, 30: control circuit, 31: selector, 32: Control circuit, 33a: zero insertion circuit, 33b: zero insertion circuit, 40: Multiplication circuit, 40a: multiplication circuit, 41: transistor, 42: transistor, 42a: transistor 43: capacitance element, 44: transistor, 45: transistor, 45a: transistor 46: capacitance element, 47: transistor, 48: transistor, 49: transistor 49a: transistor, 50: capacitance element, 51: transistor, 51a: transistor 52: Capacitor element; 61: Transistor; 62: Transistor; 62a: Transistor , 63: capacitance element, 64: transistor, 65: transistor, 65a: transistor, 66: Capacitive element, 67: Transistor, 67a: Transistor, 68: Capacitive element, 69: transistor, 69a: transistor, 70: capacitive element, 71: transistor, 71a: Transistor, 72: transistor, 72a: transistor, 73: capacitance element, 74: 74a: transistor, 75: capacitance element, 76: transistor, 76a: Transistor, 77: Capacitor element, 80: Semiconductor device, 81: CPU, 82: Memory, 83: Imaging device, 84: neural network, 84a: multiplication cell block, 84b: neural Ron, 84c: Neural Network, 85a: Display Controller, 85b: Display device, 86: I / O bus, 90: switch

Claims

[Claim 1] a first memory, a second memory, a third memory, and a fourth memory; a step of providing first data having a code to the first memory; the second memory is provided with the first data stored in the first memory having a positive sign; the third memory is provided with the first data having a negative sign stored in the first memory; if the first data is zero, it is discarded; adding the first data having a positive sign stored in the second memory and the first data having a negative sign stored in the third memory to generate second data; storing the second data in the fourth memory; An addition method comprising the step of adding up all of the second data stored in the fourth memory when the second data having a positive sign is not stored in the fourth memory, or when the second data having a negative sign is not stored in the fourth memory.

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