ESD protection circuit

Abstract

To provide an ESD protection circuit which is not operated when a normal power supply is started and even when a power supply voltage is modulated at a normal operation.SOLUTION: An RC circuit 110 is connected serially between a VDD and a GND. An RC circuit 120 is connected serially between the VDD and the GND, and a time constant that is different from the time constant of the RC circuit 110 is set. In an inverter circuit 210, a potential between a resistance element 111 and a capacitance element 112 is set to an input. In an inverter circuit 220, a potential between a resistance element 121 and a capacitance element 122 is set to an input. In an NMOS transistor 310, an output of the inverter circuit 210 is input into a gate terminal, and a drain terminal is connected to the VDD. In an NMOS transistor 320, an output of the inverter circuit 220 is input into the gate terminal; the drain terminal is connected to a source terminal of the NMOS transistor 310; and the source terminal is connected to the GND.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an ESD protection circuit. [Background technology]

[0002] Semiconductor integrated circuits are provided with an ESD (Electrostatic Discharge) protection circuit to protect the internal circuit from damage caused by ESD noise. An RC trigger type power supply clamp type ESD protection circuit is often used as this ESD protection circuit (see, for example, Patent Document 1).

[0003] This type of ESD protection circuit is configured so that when ESD noise (ESD surge noise) occurs, a clamp MOS transistor that clamps between the power supply and ground is turned on for a period determined by the time constant of the RC series circuit, connecting the power supply and ground and protecting the internal circuitry from ESD noise. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-253241 A Summary of the Invention [Problem to be solved by the invention]

[0005] Here, if the time constant of the RC series circuit is too large, the ESD protection circuit will operate even during normal operation. Therefore, in the ESD protection circuit described above, the time constant of the RC series circuit is set to a relatively small value so that the clamp MOS transistor does not turn on during normal power-on. Also, the time that the clamp MOS transistor is in the on state becomes longer as the time constant of the RC series circuit becomes larger. Therefore, if the time constant of the RC series circuit is too large, the time that the clamp MOS transistor is in the on state becomes too long, and the clamp current flowing between the power supply and ground becomes too large, which may cause damage to the circuit elements.

[0006] However, if the time constant of the RC series circuit is too small, when noise or the like occurs in the power supply during normal operation and the power supply voltage fluctuates, the ESD protection circuit may be activated, connecting the power supply and ground and causing an unnecessary large current to flow.

[0007] An object of the present invention is to provide an ESD protection circuit that does not operate during normal power-on and that does not operate even when the power supply voltage fluctuates during normal operation. [Means for solving the problem]

[0008] In order to solve the above problems, the ESD protection circuit of the present invention includes a first RC circuit connected in series between a power supply wiring and a ground wiring; a first inverter circuit that receives as input a potential between a resistive element and a capacitive element that constitute the first RC circuit, and is connected between the power supply wiring and the ground wiring; a second RC circuit connected in series between the power supply wiring and the ground wiring, the second RC circuit having a time constant different from that of the first RC circuit; a second inverter circuit that receives as input a potential between a resistive element and a capacitive element constituting the second RC circuit and is connected between the power supply wiring and the ground wiring; a first NMOS transistor having a gate terminal to which the output of the first inverter circuit is input and a drain terminal connected to the power supply line; a second NMOS transistor having a gate terminal to which the output of the second inverter circuit is input, a drain terminal connected to the source terminal of the first NMOS transistor, and a source terminal connected to the ground wiring;

[0009] In the ESD protection circuit of the present invention, the second RC circuit may be set to a time constant larger than that of the first RC circuit so as not to react to noise mixed in the power supply wiring.

[0010] Furthermore, in the ESD protection circuit of the present invention, the drain terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor may both be configured with the salicide film removed.

[0011] In order to solve the above problems, another ESD protection circuit of the present invention includes a first CR circuit connected in series between a power supply wiring and a ground wiring; a first inverter circuit that receives as input a potential between a capacitance element and a resistance element that configure the first CR circuit, and is connected between the power supply wiring and the ground wiring; a second CR circuit connected in series between the power supply wiring and the ground wiring, the second CR circuit having a time constant different from that of the first CR circuit; a second inverter circuit that receives as input a potential between a capacitance element and a resistance element that configure the second CR circuit, and is connected between the power supply wiring and the ground wiring; a first PMOS transistor having a gate terminal to which the output of the first inverter circuit is input and a source terminal connected to the power supply line; a second PMOS transistor having a gate terminal to which the output of the second inverter circuit is input, a source terminal connected to the drain terminal of the first PMOS transistor, and a drain terminal connected to the ground wiring;

[0012] In the ESD protection circuit of the present invention, the second CR circuit may be set to a time constant larger than that of the first CR circuit so as not to react to noise mixed in the ground wiring.

[0013] Furthermore, in the ESD protection circuit of the present invention, the source terminal of the first PMOS transistor and the source terminal of the second PMOS transistor may both be configured with the salicide film removed. Effect of the Invention

[0014] According to the present invention, it is possible to provide an ESD protection circuit that does not operate during normal power-on and does not operate even when the power supply voltage fluctuates during normal operation. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of an ESD protection circuit as a comparative example. [Diagram 2] 2 is a diagram showing operational waveforms in the ESD protection circuit of the comparative example shown in FIG. 1. [Diagram 3] 1 is a diagram showing a circuit configuration of an ESD protection circuit according to a first embodiment of the present invention. [Figure 4] 4 is a diagram showing operation waveforms in the ESD protection circuit according to the first embodiment shown in FIG. 3. [Diagram 5] FIG. 4 is a diagram showing a circuit configuration of an ESD protection circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0017] Before describing the ESD protection circuit of this embodiment, a circuit configuration of a general RC trigger type power supply clamp type ESD protection circuit will be described as a comparative example.

[0018] FIG. 1 is a diagram showing a circuit configuration of the ESD protection circuit of this comparative example.

[0019] As shown in FIG. 1, this comparative example ESD protection circuit is composed of an RC circuit 600 connected in series between a power supply wiring (VDD) and a ground wiring (GND), an inverter circuit 610 connected between VDD and GND and having as input the potential between a resistive element 601 and a capacitive element (capacitor element) 602 constituting the RC circuit 600, and an NMOS transistor 620.

[0020] This ESD protection circuit functions to protect the internal circuit 400 from ESD noise applied to the power supply terminal.

[0021] In the RC circuit 600, a resistive element 601 and a capacitive element 602 are connected in series between VDD and GND. An output of an inverter circuit 610 is input to a gate terminal of an NMOS transistor 620, and the drain terminal and source terminal are connected to VDD and GND, respectively.

[0022] The inverter circuit 610 is a CMOS (Complementary Metal Oxide Semiconductor) type inverter circuit in which a PMOS transistor 611 and an NMOS transistor 612 are connected in series between VDD and GND.

[0023] Next, the operating waveforms in the ESD protection circuit of the comparative example shown in FIG. 1 are shown in FIG.

[0024] When ESD noise is applied to VDD from the outside, the potential of node A, which is the input of the inverter circuit 610, is 0V in the initial state, so that when the potential of VDD becomes equal to or higher than the threshold of the PMOS transistor 611, the PMOS transistor 611 turns on and the potential of VDD is applied to the gate terminal of the NMOS transistor 620. Therefore, the NMOS transistor 620 turns on, electrically connecting VDD and GND and clamping the ESD noise, thereby preventing the ESD noise from being applied directly to the internal circuit 400. As a result, the internal circuit 400 is protected from ESD noise by the ESD protection circuit.

[0025] In other words, when ESD noise is applied to VDD from the outside, in the operational waveform shown in FIG. 2, at time T1 when the potential of node X exceeds the threshold value of NMOS transistor 620, NMOS transistor 620 turns on and clamps the voltage between VDD and GND so that it does not exceed the withstand voltage of internal circuit 400.

[0026] Here, the potential at node A, which is the input of the inverter circuit 610, is delayed from VDD by a time constant R1×C1 determined by the resistance value R1 of the resistor element 601 and the capacitance value C1 of the capacitor element 602 in the RC circuit 600. Therefore, the potential at node A rises over time, and when the potential at node A becomes equal to or higher than the logical threshold value of the inverter circuit 610, the NMOS transistor 612 turns on and the PMOS transistor 611 turns off. As a result, the potential at node X becomes L level (low level), and the NMOS transistor 620 turns off.

[0027] Specifically, in the operational waveforms shown in FIG. 2, at time T2 when the potential of the node A becomes equal to or higher than the logical threshold value of the inverter circuit 610, the NMOS transistor 620 is turned off.

[0028] In the case of a normal rise in VDD, since the rise in VDD is not so steep, the potential at node A rises with almost no delay relative to VDD, and the NMOS transistor 620 does not turn on but transitions to a normal operating state.

[0029] However, in the ESD protection circuit having such a configuration, if some noise is mixed into VDD during normal operation when VDD is at a constant voltage, the NMOS transistor 620 may momentarily turn on. Specifically, if the noise waveform mixed into VDD is large relative to the time constant R1×C1 determined by the resistance value R1 of the resistive element 601 and the capacitance value C1 of the capacitive element 602, the RC circuit 600 reacts. As a result, as shown in FIG. 2, the potential of the node A becomes smaller than the logical threshold value of the inverter circuit 610 at time T3, and the potential of the node X, which is the output of the inverter circuit 610, becomes H level (high level). Therefore, the NMOS transistor 620 turns on, and an unnecessary large current flows between the power supply (VDD) and ground (GND), which causes problems such as increased power consumption of the semiconductor integrated circuit and destruction of circuit elements due to the large current flow.

[0030] Such problems in normal operation can be solved by increasing the time constant R1×C1 in the RC circuit 600. However, if the time constant R1×C1 of the RC circuit 600 is set too large, problems may occur in which the ESD protection circuit operates even during normal operation, or the time that the NMOS transistor 620 remains on when ESD noise occurs may become too long, causing the clamp current flowing between the power supply and ground to become too large, which may result in destruction of circuit elements.

[0031] Therefore, in the first embodiment of the present invention, by using a circuit configuration as described below, an ESD protection circuit is realized that does not operate during normal power-on and does not operate even if the power supply voltage fluctuates during normal operation.

[0032] [First embodiment] Next, an ESD protection circuit according to a first embodiment of the present invention will be described. The circuit configuration of the ESD protection circuit according to the first embodiment of the present invention is shown in FIG.

[0033] The ESD protection circuit in this embodiment is composed of RC circuits 110 and 120, inverter circuits 210 and 220, and two NMOS transistors 310 and 320, as shown in FIG.

[0034] In the RC circuit 110, a resistive element 111 and a capacitive element 112 are connected in series between a power supply wiring VDD and a ground wiring GND.

[0035] In the RC circuit 120, a resistive element 121 and a capacitive element 122 are connected in series between VDD and GND. The time constant R2×C2 in the RC circuit 120 is set to a value different from the time constant R1×C1 in the RC circuit 110. In this embodiment, the time constant R2×C2 in the RC circuit 120 is set to a value larger than the time constant R1×C1 in the RC circuit 110 and is set to a value that does not react to noise mixed in VDD. The time constant R1×C1 in the RC circuit 110 is set to the same value as the time constant of the RC circuit 600 in the ESD protection circuit of the comparative example shown in FIG.

[0036] The inverter circuit 210 is a CMOS type inverter circuit in which the potential between the resistive element 111 and the capacitive element 112 constituting the RC circuit 110 is input, and a PMOS transistor 211 and an NMOS transistor 212 are connected in series between VDD and GND.

[0037] The inverter circuit 220 is a CMOS type inverter circuit in which the potential between the resistive element 121 and the capacitive element 122 constituting the RC circuit 120 is input, and a PMOS transistor 221 and an NMOS transistor 222 are connected in series between VDD and GND.

[0038] The NMOS transistors 310 and 320 are connected in series between VDD and GND. Specifically, the output of the inverter circuit 210 is input to the gate terminal of the NMOS transistor 310, and the drain terminal is connected to VDD. The output of the inverter circuit 220 is input to the gate terminal of the NMOS transistor 320, and the drain terminal is connected to the source terminal of the NMOS transistor 310, and the source terminal is connected to GND.

[0039] In the ESD protection circuit of this embodiment, two NMOS transistors 310, 320 are connected in series between VDD and GND, and thus, VDD and GND are connected only when the two NMOS transistors 310, 320 are simultaneously turned on.

[0040] Next, the operation waveforms of the ESD protection circuit of this embodiment shown in FIG. 3 are shown in FIG.

[0041] When a voltage with a steep rise such as ESD noise is applied from the outside to VDD, the voltages of node B and node C both rise gradually relative to the rise of VDD due to the presence of RC circuits 110 and RC 120. Furthermore, since the time constant R2×C2 of RC circuit 120 is larger than the time constant R1×C1 of RC circuit 110, the potential of node C rises more gradually relative to the potential of node B.

[0042] The potential of node Y1, which is the output of inverter circuit 210, continues to rise with the rise in the potential of VDD until the potential of node B becomes equal to or higher than the logical threshold of inverter circuit 210. Furthermore, the potential of node Y2, which is the output of inverter circuit 220, also continues to rise with the rise in the potential of VDD until the potential of node C becomes equal to or higher than the logical threshold of inverter circuit 220.

[0043] Therefore, at time T4 when the potential of node Y1 becomes equal to or higher than the threshold of NMOS transistor 310 and the potential of node Y2 becomes equal to or higher than the threshold of NMOS transistor 320, both NMOS transistors 310, 320 are turned on.

[0044] As a result, the ESD protection circuit in this embodiment operates such that VDD and GND are connected and a current flows from VDD to GND, thereby reducing the potential difference between VDD and GND and clamping the ESD noise so that the ESD noise is not directly applied to the internal circuit 400. As a result, the internal circuit 400 is protected from ESD noise by the ESD protection circuit.

[0045] As time passes, the potential of node B increases, and at time T5, when the potential of node B becomes equal to or higher than the logical threshold of inverter circuit 210, NMOS transistor 212 turns on and PMOS transistor 211 turns off. As a result, the potential of node Y1 becomes an L level, and NMOS transistor 310 turns off.

[0046] Moreover, as time passes, the potential of node C rises, and at time T6, when the potential of node C becomes equal to or higher than the logical threshold of inverter circuit 220, NMOS transistor 222 turns on and PMOS transistor 221 turns off. As a result, the potential of node Y2 becomes L level, and NMOS transistor 320 turns off.

[0047] Then, the voltage between VDD and GND is clamped only during the period from time T4 to T5 when both the NMOS transistors 310 and 320 are in the on state.

[0048] Here, if the time constant R1×C1 of the RC circuit 600 in the ESD protection circuit of the comparative example shown in Fig. 1 and the time constant R1×C1 of the RC circuit 110 in the ESD protection circuit of this embodiment have the same value, the period from time T1 to T2 in Fig. 2 will have the same length as the period from time T4 to T5 in Fig. 4. In other words, it can be seen that the ESD protection circuit of this embodiment also achieves a protection function against ESD noise equivalent to that of the ESD protection circuit of the comparative example shown in Fig. 1.

[0049] Next, an operation will be described when noise is mixed into VDD during normal operation with a normal voltage applied to VDD.

[0050] 4, when noise is mixed into VDD during normal operation, if the mixed noise waveform is large relative to the time constant R1×C1 determined by the resistance value R1 of the resistive element 111 and the capacitance value C1 of the capacitive element 112, the RC circuit 110 reacts. As a result, the potential of the node B becomes smaller than the logical threshold value of the inverter circuit 210 at time T7, and the potential of the node Y1, which is the output of the inverter circuit 210, rises from the GND level to the H level. Therefore, the NMOS transistor 310 is turned on.

[0051] However, since the time constant R2×C2 of the RC circuit 120 is set to a value larger than the time constant R1×C1 of the RC circuit 110, the RC circuit 102 is less likely to react to the voltage change of VDD even if the same amount of noise is mixed into VDD. Therefore, even if the potential of the node B becomes smaller than the logical threshold of the inverter circuit 210 at time T7 as shown in the operation waveform of Figure 4, the potential of the node C does not become smaller than the logical threshold of the inverter circuit 220. Therefore, the potential of the node Y2 is maintained at the L level, and the NMOS transistor 320 also remains in the off state.

[0052] By the above operation, even if noise is mixed into VDD, the NMOS transistor 310 is turned on, but the NMOS transistor 320 is maintained in the off state. In the ESD protection circuit of this embodiment, the circuit configuration is such that the VDD-GND is not connected unless both of the two NMOS transistors 310 and 320 are turned on. Therefore, when noise that does not react to the RC circuit 120 is mixed into VDD, VDD-GND is not connected, and it is possible to maintain normal operation without being affected by noise.

[0053] As described above, the ESD protection circuit of this embodiment has a circuit configuration in which two RC circuits 110, 120 with different time constants are connected in parallel between VDD and GND, and the potentials of the RC circuits 110, 120 (potentials of nodes B and C) are applied to the gate terminals of the NMOS transistors 310, 320 via the inverter circuits 210, 220. The NMOS transistors 310, 320 are connected in series between VDD and GND, so that the ESD protection function operates only when the two NMOS transistors 310, 320 are simultaneously turned on.

[0054] As a result, when ESD noise is applied to VDD, the two NMOS transistors 310, 320 are simultaneously turned on and a current flows between the power supply (VDD) and ground (GND), thereby reducing the potential difference between VDD and GND; the role of so-called ESD protection is similar to that of the ESD protection circuit of the comparative example.

[0055] On the other hand, if noise is mixed into VDD during normal operation and causes it to fluctuate, the RC circuit 120, which has a larger time constant, operates so as not to respond to such VDD fluctuations, and the NMOS transistor 320 connected to the RC circuit 120 is also maintained in the off state.

[0056] In other words, according to the ESD protection circuit of this embodiment, even if VDD fluctuates due to noise contamination, it is possible to prevent problems such as an unnecessary large current flowing between the power supply (VDD) and ground (GND), which would increase the power consumption of the semiconductor integrated circuit, or the breakdown of circuit elements due to the flow of a large current.

[0057] [Second embodiment] Next, an ESD protection circuit according to a second embodiment of the present invention will be described. The circuit configuration of the ESD protection circuit according to the second embodiment of the present invention is shown in Fig. 5. In Fig. 5, the same components as those shown in Fig. 3 are denoted by the same reference numerals, and the description thereof will be omitted.

[0058] The ESD protection circuit in this embodiment is composed of CR circuits 410 and 420, inverter circuits 210 and 220, and two PMOS transistors 510 and 520, as shown in FIG.

[0059] In the CR circuit 410, a capacitance element 112 and a resistance element 111 are connected in series between a power supply wiring VDD and a ground wiring GND.

[0060] In the CR circuit 420, a capacitance element 122 and a resistance element 121 are connected in series between VDD and GND. The time constant R2×C2 in the CR circuit 420 is set to a value different from the time constant R1×C1 in the CR circuit 410. In this embodiment, the time constant R2×C2 in the CR circuit 420 is set to a value larger than the time constant R1×C1 in the CR circuit 410 and is set to a value that does not react to noise mixed in GND. In addition, the time constant R1×C1 in the RC circuit 110 is set to a value equal to the time constant of the RC circuit 600 in the ESD protection circuit of the comparative example shown in FIG. 1 and the time constant of the RC circuit 110 in the ESD protection circuit of the first embodiment shown in FIG. 3.

[0061] The inverter circuit 210 is a CMOS type inverter circuit in which the potential between the capacitance element 112 and the resistance element 111 constituting the CR circuit 410 is input, and a PMOS transistor 211 and an NMOS transistor 212 are connected in series between VDD and GND.

[0062] The inverter circuit 220 is a CMOS type inverter circuit in which the potential between the capacitance element 122 and the resistance element 121 constituting the CR circuit 420 is input, and a PMOS transistor 221 and an NMOS transistor 222 are connected in series between VDD and GND.

[0063] The PMOS transistors 510 and 520 are connected in series between VDD and GND. Specifically, the PMOS transistor 310 has a gate terminal to which the output of the inverter circuit 210 is input, and a source terminal to which VDD is connected. The PMOS transistor 520 has a gate terminal to which the output of the inverter circuit 220 is input, a source terminal to which the drain terminal of the PMOS transistor 510 is connected, and a drain terminal to which GND is connected.

[0064] In the ESD protection circuit of this embodiment, two PMOS transistors 510, 520 are connected in series between VDD and GND, and therefore, VDD and GND are connected only when these two PMOS transistors 510, 520 are simultaneously turned on.

[0065] The ESD protection circuit of this embodiment has a circuit configuration in which the RC circuits 110 and 210 of the ESD protection circuit of the first embodiment shown in FIG. 3 are replaced with CR circuits 410 and 420, respectively, and the NMOS transistors 310 and 320 are replaced with PMOS transistors 510 and 520, respectively.

[0066] In the ESD protection circuit of this embodiment, when ESD noise is applied to VDD, the operation is the same as that of the ESD protection circuit of the first embodiment shown in FIG. 3, except that the logic is reversed.

[0067] In the ESD protection circuit of this embodiment, when some noise is mixed into GND, the CR circuit 410 has a small time constant C1×R1, so that the potential of node D may become equal to or higher than the logical threshold of the inverter circuit 210 in response to the noise mixed into GND. However, the time constant C2×R2 of the CR circuit 420 is set to a large value, so that the potential of node E can be prevented from becoming equal to or higher than the logical threshold of the inverter circuit 220.

[0068] Therefore, even if the potential of node Z1, which is the output of inverter circuit 210, drops due to noise mixed into GND and PMOS transistor 510 turns on, the potential of node Z2, which is the output of inverter circuit 220, remains at the H level. Therefore, PMOS transistor 520 remains in the off state, making it possible to prevent VDD and GND from being connected together due to noise mixed into GND.

[0069] [others] The NMOS transistors 310 and 320 in the first embodiment and the PMOS transistors 510 and 520 in the second embodiment operate to protect the internal circuit 400 from ESD noise by passing the ESD noise as an on-current.

[0070] Here, the drain terminals of the NMOS transistors 310 and 320 in the first embodiment and the source terminals of the PMOS transistors 510 and 520 in the second embodiment may have a low resistance film called a salicide film, which is a general MOS structure. However, in order to further increase ESD resistance, the drain terminals of the NMOS transistors 310 and 320 may be configured with the salicide film removed. Similarly, the source terminals of the PMOS transistors 510 and 520 may be configured with the salicide film removed.

[0071] By using a device having a configuration in which the salicide film has been removed in this way, it is possible to operate a parasitic NPN transistor or a parasitic PNP transistor of the MOS transistor, thereby improving the ESD protection function. [Explanation of symbols]

[0072] 110, 120 RC circuit 111, 121 Resistance element 112, 122 Capacitive element 210, 220 Inverter circuit 211, 221 PMOS transistors 212, 222 NMOS transistors 310, 320 NMOS transistors 400 Internal circuit 410, 420 RC circuit 510, 520 PMOS transistors 600 RC circuit 601 Resistance element 602 Capacitive element 610 Inverter Circuit 611 PMOS Transistor 612 NMOS Transistor 620 NMOS Transistor

Claims

1. a first RC circuit connected in series between the power supply wiring and the ground wiring; a first inverter circuit that receives as input a potential between a resistive element and a capacitive element constituting the first RC circuit and is connected between the power supply wiring and the ground wiring; a second RC circuit connected in series between the power supply wiring and the ground wiring, the second RC circuit having a time constant different from that of the first RC circuit; a second inverter circuit that receives as input a potential between a resistive element and a capacitive element constituting the second RC circuit and is connected between the power supply wiring and the ground wiring; a first NMOS transistor having a gate terminal to which the output of the first inverter circuit is input and a drain terminal connected to the power supply line; a second NMOS transistor having a gate terminal to which the output of the second inverter circuit is input, a drain terminal connected to the source terminal of the first NMOS transistor, and a source terminal connected to the ground wiring; An ESD protection circuit comprising:

2. 2. The ESD protection circuit according to claim 1, wherein the second RC circuit has a time constant set to a value larger than that of the first RC circuit so as not to react to noise mixed in a power supply wiring.

3. 2. The ESD protection circuit according to claim 1, wherein the drain terminal of said first NMOS transistor and the drain terminal of said second NMOS transistor are both configured with the salicide film removed.

4. a first CR circuit connected in series between a power supply line and a ground line; a first inverter circuit that receives as input a potential between a capacitance element and a resistance element constituting the first CR circuit and is connected between the power supply wiring and the ground wiring; a second CR circuit connected in series between the power supply wiring and the ground wiring, the second CR circuit having a time constant different from that of the first CR circuit; a second inverter circuit that receives as input a potential between a capacitance element and a resistance element constituting the second CR circuit and is connected between the power supply wiring and the ground wiring; a first PMOS transistor having a gate terminal to which the output of the first inverter circuit is input and a source terminal connected to the power supply line; a second PMOS transistor having a gate terminal to which the output of the second inverter circuit is input, a source terminal connected to the drain terminal of the first PMOS transistor, and a drain terminal connected to the ground wiring; An ESD protection circuit comprising:

5. 5. The ESD protection circuit according to claim 4, wherein the second CR circuit has a time constant set to a value larger than that of the first CR circuit so as not to react to noise mixed in a ground wiring.

6. 5. The ESD protection circuit according to claim 4, wherein the source terminal of said first PMOS transistor and the source terminal of said second PMOS transistor are both configured with the salicide film removed.

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