Semiconductor device

Abstract

To suppress the interference of electric conduction between pads by an oxide layer on a pad surface.SOLUTION: A semiconductor device of an embodiment comprises a first chip including a first insulation layer and a second chip including a second insulation layer and bonded to the first chip. The semiconductor device also comprises a pad provided on a bonding surface between the first chip and the second chip and including a first metal layer containing a first metal, a second metal layer arranged between the first metal layer and the first insulation layer, and a third metal layer arranged between the first metal layer and the second insulation layer. One or both of the second metal layer and the third metal layer include a second metal having lower oxidation energy than the first metal. The first metal layer further includes the second metal.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Some semiconductor devices are manufactured by forming different elements on different substrates and then bonding the substrates together. Pads are formed on the bonding surfaces of the substrates to be electrically connected to the respective elements. By bonding the substrates together, the pads are also bonded to each other, and the different elements are also electrically connected to each other. However, when bonding the pads together, an oxide layer formed on the surfaces of the pads by natural oxidation or the like may inhibit electrical conduction between the pads. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-040975 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor device capable of suppressing the inhibition of electrical continuity between pads caused by an oxide layer on the surface of the pad. [Means for solving the problem]

[0005] A semiconductor device of an embodiment is a semiconductor device having a first chip including a first insulating layer and a second chip including a second insulating layer and bonded to the first chip, the semiconductor device comprising a pad provided on the bonding surface between the first chip and the second chip, the pad having a first metal layer including a first metal, a second metal layer arranged between the first metal layer and the first insulating layer, and a third metal layer arranged between the first metal layer and the second insulating layer, one or both of the second and third metal layers including a second metal having a lower oxidation energy than the first metal, and the first metal layer further including the second metal. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment. [Diagram 2] FIG. 2 is an equivalent circuit diagram showing an example of a configuration of a memory cell array included in the semiconductor memory device according to the embodiment. [Diagram 3] 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 4] FIG. 1 is a diagram showing an example of a configuration of a semiconductor memory device according to an embodiment. [Diagram 5] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 11] 6A to 6C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to a first modified example of the embodiment. [Figure 12] FIG. 11 is a cross-sectional view of a bonding portion of an insulating layer of a semiconductor memory device according to a second modification of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiment. In addition, the components in the following embodiment include those that a person skilled in the art can easily imagine or that are substantially the same.

[0008] (Example of the configuration of a semiconductor memory device) 1 is a block diagram of a semiconductor memory device 1 according to an embodiment. As shown in FIG. 1, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generating circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0009] The input / output circuit 310 controls input / output of a signal DQ to / from an external device such as a memory controller (not shown) that controls the semiconductor memory device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0010] The input circuit transmits data DAT, such as write data WD received from an external device, to the data register 540 , transmits an address ADD to the address register 340 , and transmits a command CMD to the command register 350 .

[0011] The output circuit transmits the status information STS received from the status register 330, the data DAT such as the read data RD received from the data register 540, and the address ADD received from the address register 340 to an external device.

[0012] The logic control circuit 320 receives, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from an external device. The logic control circuit 320 also controls the input / output circuit 310 and the sequencer 360 in response to the received signals.

[0013] The status register 330 temporarily holds status information STS for, for example, data write, read, and erase operations, and notifies an external device as to whether or not the operation has ended normally.

[0014] The address register 340 temporarily holds an address ADD received from an external device via the input / output circuit 310. The address register 340 also transfers a row address RA to a row decoder 520 and a column address CA to a column decoder 550.

[0015] The command register 350 temporarily stores a command CMD received from an external device via the input / output circuit 310 , and transfers the command CMD to the sequencer 360 .

[0016] The sequencer 360 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generating circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550 in response to the command CMD held by the command register 350, and executes a write operation, a read operation, an erase operation, and the like.

[0017] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device according to the operating status of the sequencer 360 .

[0018] The voltage generation circuit 380 generates voltages necessary for write, read, and erase operations under the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0019] The memory cell array 510 includes a plurality of blocks BLK (BLK0 to BLKn), where n is an integer equal to or greater than 2. A block BLK is a set of a plurality of memory cells associated with bit lines and word lines, and serves as, for example, a data erase unit. The memory cells are configured as, for example, transistors, and hold non-volatile data.

[0020] By including such memory cells, the semiconductor memory device 1 of the embodiment is configured as, for example, a NAND type nonvolatile memory.

[0021] The row decoder 520 decodes the row address RA, selects one of the blocks BLK based on the result of the decoding, and applies a required voltage to the block BLK.

[0022] During a read operation, the sense amplifier module 530 senses data read from the memory cell array 510. In addition, the sense amplifier module 530 transmits read data RD to the data register 540. During a write operation, the sense amplifier module 530 transmits write data WD to the memory cell array 510.

[0023] The data register 540 includes a plurality of latch circuits. The latch circuits hold write data WD and read data RRD. For example, in a write operation, the data register 540 temporarily holds the write data WD received from the input / output circuit 310 and transmits it to the sense amplifier module 530. For example, in a read operation, the data register 540 temporarily holds the read data RD received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0024] The column decoder 550 decodes a column address CA during, for example, a write operation, a read operation, or an erase operation, and selects a latch circuit in the data register 540 according to the decoded result.

[0025] The group of circuits arranged around the memory cell array 510 is also called peripheral circuits. The peripheral circuits include at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuits may include a status register 330, an address register 340, a command register 350, and a sequencer 360, and may further include an input / output circuit 310, a logic control circuit 320, a ready / busy circuit 370, and a voltage generation circuit 380.

[0026] Thus, the semiconductor memory device 1 of the embodiment includes the memory cell array 510 including a plurality of memory cells, and a peripheral circuit that operates the plurality of memory cells.

[0027] FIG. 2 is an equivalent circuit diagram showing an example of the configuration of the memory cell array 510 included in the semiconductor memory device 1 according to the embodiment.

[0028] As described above, the memory cell array 510 includes a plurality of blocks BLK. Each of the plurality of blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to a peripheral circuit such as a sense amplifier module 530 via a bit line BL. The other end of each of the plurality of memory strings MS is connected to the peripheral circuit via a common source line SL.

[0029] The memory string MS includes a drain select transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC, and a source select transistor STS. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as select transistors (STD, STS).

[0030] The memory cells MC are, for example, field effect transistors (FETs) that include a charge storage layer in a gate insulating layer. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage layer. By providing one or more threshold voltages, the memory cells MC may be able to store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one block BLK.

[0031] The selection transistors (STD, STS) are, for example, field effect transistors. Selection gate lines (SGD, SGS) are connected to the gate electrodes of the selection transistors (STD, STS), respectively. The drain selection line SGD connected to the drain selection transistor STD is provided corresponding to the string unit SU, and is commonly connected to all the memory strings MS in one string unit SU. The source selection line SGS connected to the source selection transistor STS is commonly connected to all the memory strings MS in one block BLK.

[0032] One end of each of the word lines WL and the select gate lines (SGD, SGS) is connected to peripheral circuits such as a row decoder 520.

[0033] 3 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment, in which hatching is omitted for ease of viewing.

[0034] 3, the semiconductor memory device 1 has a configuration in which two chips 2 and 3 are joined at insulating layers 40 and 50 provided on the chips 2 and 3, respectively. The chip 3 as the first chip includes, from the bottom of the page, an electrode film EL, a source line SL, a plurality of word lines WL, and selection gate lines SGD and SGS. The chip 3 as the second chip is disposed above the selection gate line SGD, and includes a peripheral circuit CBA provided on the semiconductor substrate SB.

[0035] The source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 150, and the source line SL and the electrode film EL are kept electrically conductive via the plugs PG. This allows a source potential to be applied to the source line SL from the above-mentioned voltage generating circuit 380 (see FIG. 1) via the electrode film EL and the plugs PG.

[0036] On the source line SL, one or more select gate lines SGS, a plurality of word lines WL, and one or more select gate lines SGD are stacked in this order. A memory region MR is arranged in the center in the direction in which the plurality of word lines WL extend, and a staircase region SR is arranged at the end in the direction in which the plurality of word lines WL extend.

[0037] In the memory region MR, a plurality of pillars PL are arranged, which penetrate the word lines WL in the stacking direction. A plurality of memory cells MC (see FIG. 2) are formed at the intersections between the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which the memory cells MC are arranged three-dimensionally in the memory region MR.

[0038] Thus, the memory region MR is an example of a physical configuration corresponding to the above-mentioned memory cell array 510 (see FIG. 2). Also, the pillar PL is an example of a physical configuration corresponding to the above-mentioned memory string MS (see FIG. 2) in which memory cells MC and the like are connected in series.

[0039] In the physical configuration of the semiconductor memory device 1, the pillars PL are electrically connected to the peripheral circuit CBA via bit lines BL arranged above the pillars PL.

[0040] In the staircase region SR, a staircase section SP is arranged where a plurality of word lines WL and select gate lines SGD, SGS are processed into a staircase shape and terminate. Contacts CC connected to the word lines WL of each layer are arranged in the terrace portion of each step of the staircase section SP, which is formed by the individual word lines WL, etc.

[0041] The word lines WL and the select gate lines SGD and SGS, which are stacked in multiple layers, are individually drawn out by these contacts CC. A write voltage, a read voltage, etc. are applied from these contacts CC to the memory cells MC included in the memory region MR in the center of the word lines WL via the word lines WL at the same height as the memory cells MC.

[0042] The word lines WL, the select gate lines SGD, SGS, the pillars PL, and the contacts CC are covered with an insulating layer 50 as a first insulating layer. The insulating layer 50 also extends to a peripheral region PR around the word lines WL, etc. A contact C3 is disposed in the peripheral region PR, which penetrates the insulating layer 50 and is connected to a source line SL.

[0043] Furthermore, on the surface of the insulating layer 50, pads PDm are arranged as a plurality of first pads, and the above-mentioned pillars PL, contacts CC, C3, etc. are electrically connected to these pads PDm through vias, wiring, etc.

[0044] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate, etc. On the surface of the semiconductor substrate SB, the peripheral circuits CBA such as the row decoder 520 including the transistors TR and wiring, the sense amplifier module 530 (see FIG. 1), etc. are arranged.

[0045] Various voltages applied to the memory cells MC from the contacts CC are controlled by a peripheral circuit CBA electrically connected to these contacts CC. Data read from the memory cells MC aligned in the height direction of the pillar PL is read to a sense amplifier module 530 of the peripheral circuit CBA. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells MC.

[0046] The peripheral circuit CBA is covered with an insulating layer 40 as a second insulating layer. On the surface of the insulating layer 40, pads PDc as a plurality of second pads are arranged, and the above-mentioned transistors TR etc. are electrically connected to these pads PDc through vias, wiring etc.

[0047] The semiconductor memory device 1 of the embodiment is configured to include a plurality of word lines WL, pillars PL, source lines SL, contacts CC, etc., and a peripheral circuit CBA, by joining an insulating layer 40 covering the peripheral circuit CBA and an insulating layer 50 covering a plurality of word lines WL, etc.

[0048] These components are electrically connected to each other by bonding the pads PDc, PDm together due to bonding of the insulating layers 40, 50. That is, the pillars PL are connected to the peripheral circuit CBA via the bit lines BL and the pads PDm, PDc, etc. The word lines WL, etc. are connected to the peripheral circuit CBA via the contacts CC and the pads PDm, PDc, etc. The source lines SL are connected to the peripheral circuit CBA via the contacts C3 and the pads PDm, PDc, etc.

[0049] The semiconductor memory device 1 configured as above is an example of a semiconductor device including chips 2 and 3 having a bonding surface between the insulating layer 50 and the insulating layer 40. These chips 2 and 3 are obtained by bonding together substrates on which a plurality of word lines WL, pillars PL, source lines SL, contacts CC, etc., and peripheral circuits CBA are respectively formed, and then dicing the substrates into individual chips.

[0050] In this specification, of pads PDm connected to multiple word lines WL, pillars PL, source lines SL, and contacts CC, etc., and pads PDc connected to peripheral circuits CBA, the side on which pads PDm are arranged is defined as the lower side of the semiconductor memory device 1, and the side on which pads PDc are arranged is defined as the upper side of the semiconductor memory device 1.

[0051] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 4. Fig. 4 is a diagram showing an example of the configuration of the semiconductor memory device 1 according to an embodiment.

[0052] More specifically, Figure 4(a) is a cross-sectional view along the Y direction including the memory region MR of the semiconductor memory device 1. In Figure 4(a), the structure below the insulating layer 60 and above the insulating layer 54 are omitted.

[0053] Fig. 4(b) is an XY cross-sectional view of a pillar PL at the height of any word line WL, and Fig. 4(c) is an XY cross-sectional view of a pillar PL at the height of any select gate line SGD, SGS.

[0054] 4(d) is a cross-sectional view of a bonding portion between the insulating layers 40 and 50. FIG. 4(e) is an XY cross-sectional view of a pad PDm provided on the insulating layer 50.

[0055] In this specification, the X direction and the Y direction are both directions along the direction of the plane of the word line WL, and are perpendicular to each other.

[0056] 4(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. Note that the intermediate source line BSL is not disposed below the staircase region SR of the stack LM.

[0057] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0058] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0059] The laminate LMa is disposed above the source line SL. A plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the laminate LMa, below the word line WL in the bottom layer of the laminate LMa, with an insulating layer OL interposed therebetween. The laminate LMb is disposed on the laminate LMa. A plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the laminate LMb, above the word line WL in the top layer of the laminate LMb, with an insulating layer OL interposed therebetween.

[0060] However, the number of stacked word lines WL and select gate lines SGD, SGS as these conductive layers in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0061] The uppermost insulating layer OL of each of the laminates LMa and LMb is, for example, thicker than the other insulating layers OL in the laminates LMa and LMb. However, each insulating layer OL of the laminates LMa and LMb may have substantially the same thickness. The uppermost insulating layer OL of the laminate LMa is in contact with the lowermost word line WL of the laminate LMb, and insulating layers 52, 53, 54, etc. are arranged in this order on the uppermost insulating layer OL of the laminate LMb.

[0062] The insulating layers 52, 53, 54, etc. constitute a part of the insulating layer 50 described above, and the insulating layer 50 has an uppermost surface not shown in FIG. 4(a) that contacts the lower surface of the insulating layer 40 on the peripheral circuit CBA side, as described above.

[0063] The laminate LM is also divided in the Y direction by a plurality of plate-shaped portions PT.

[0064] That is, the plate-shaped portions PT are arranged side by side in the Y direction and extend in the stacking direction and the X direction of the laminate LM. In this manner, the plate-shaped portions PT extend continuously within the laminate LM from one end to the other end in the X direction of the laminate LM. The plate-shaped portions PT also pass through the laminate LM and the upper source line DSLb, and reach the intermediate source line BSL in the memory region MR. Each of the plate-shaped portions PT is formed as a single unit of an insulating layer 55 such as a silicon oxide layer.

[0065] The plate-like portion PT has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bow shape in which the width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0066] In the memory region MR, a plurality of isolation layers SHE are disposed between the plate-like portions PT adjacent in the Y direction, penetrating the upper layer portion of the laminate LM and extending in the X direction. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0067] In other words, these separation layers SHE penetrating the upper part of the laminate LM extend in the X direction through the memory region MR between adjacent plate-shaped portions PT, thereby dividing the upper part of the laminate LM into the above-mentioned select gate lines SGD0, SGD1.

[0068] The region between adjacent plate-like portions PT in the Y direction is an example of a physical configuration corresponding to one block BLK (see FIG. 2) described above. Also, the region between adjacent plate-like portions PT, partitioned by the separation layer SHE into the patterns of the select gate lines SGD0, SGD1, is an example of a physical configuration corresponding to the string unit SU (see FIG. 2) described above.

[0069] In the memory region MR, a plurality of pillars PL are distributed and arranged, penetrating the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0070] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, for example, a circular, elliptical, oval, or the like, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0071] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at a portion penetrating the laminate LMa and at a portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area are maximum at a predetermined position between the upper layer side and the lower layer side at a portion penetrating the laminate LMa and at a portion penetrating the laminate LMb.

[0072] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP at the upper end of the pillar PL, and a core layer CR that forms the core material of the pillar PL.

[0073] 4(b) and (c), the memory layer ME has a multi-layer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is disposed on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also disposed on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0074] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, and reaches the depth of the lower source line DSLa. More specifically, the channel layer CN is disposed on the side and bottom surface of the pillar PL via the memory layer ME. However, a part of the channel layer CN contacts the intermediate source line BSL on the side, and is thereby electrically connected to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0075] Each of the pillars PL has a cap layer CP at its upper end, which is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stack LM in a direction, for example, along the Y direction, so as to intersect with the lead-out direction of the word line WL.

[0076] In Fig. 4(a), in each section separated by the separation layer SHE, a plug CH is connected to only one of the pillars PL. The other pillars PL are connected to other bit lines BL extending in the Y direction parallel to the bit lines BL shown in Fig. 4(a) at positions different from the cross section shown in Fig. 4(a) via plugs CH not shown in Fig. 4(a).

[0077] The block insulating layer BK and the tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and the cap layer CP are, for example, semiconductor layers such as a polysilicon layer or an amorphous silicon layer.

[0078] As shown in Fig. 4(b), the above configuration forms memory cells MC on the side surfaces of the pillars PL facing each word line WL. When a predetermined voltage is applied from the word line WL, data is written to and read from the memory cells MC.

[0079] 4(c), the above-mentioned configuration forms select gates STD on the side surfaces of the pillars PL facing select gate lines SGD0 and SGD1 arranged above the word lines WL, and select gates STS on the side surfaces of the pillars PL facing select gate lines SGS0 and SGS1 arranged below the word lines WL.

[0080] By applying a predetermined voltage from the select gate lines SGD, SGS, respectively, the select gates STD, STS are turned on or off, so that the memory cell MC of the pillar PL to which the select gates STD, STS belong can be placed in a selected or unselected state.

[0081] In addition, by distributing the pillars PL, when the stack LM is formed from a stack of the sacrificial layer and the insulating layer, as described below, the stack is supported in the memory region MR. On the other hand, in the staircase region SR, instead of the pillars PL, a plurality of columnar parts (not shown) are distributed. As a result, when the stack LM is formed from a stack of the sacrificial layer and the insulating layer, the stack is supported in the staircase region SR.

[0082] 4(d) and (e), the pad PDm has, for example, a rectangular upper surface and is disposed on the insulating layer 50, which covers the laminate LM, at the bonding surface between the insulating layer 50 and the insulating layer 40. However, the shape of the pad PDm as viewed from above may be a shape other than a rectangle, such as a circle or an ellipse.

[0083] As described above, the insulating layer 50 is the insulating layers 52, 53, 54, etc. stacked on the upper surface of the laminate LM. The insulating layer 50 has a structure in which, for example, silicon oxide layers are stacked. However, in the stacked structure of the insulating layer 50, other insulating layers such as a silicon nitride layer and a silicon oxynitride layer may be interposed, and these other insulating layers may be disposed on the bonding surface of the insulating layer 50.

[0084] The pad PDm has a tapered shape in which the cross-sectional area in the direction along the XY plane decreases from the bonding surface of the insulating layer 50 toward the depth direction of the insulating layer 50.

[0085] A via VAm having, for example, a circular cross section along the XY plane is connected to the lower end of the pad PDm located at a predetermined depth in the insulating layer 50. The via VAm as a first via has a tapered shape in which the cross-sectional area along the XY plane and the diameter become smaller from the upper end connected to the pad PDm toward the depth direction of the insulating layer 50.

[0086] An arbitrary number of vias and wirings, etc. are further connected below the via VAm, and electrically connect the above-mentioned pillars PL, word lines WL, select gate lines SGD, SGS, source lines SL, etc. to different pads PDm.

[0087] The pad PDm and the via VAm have a conductive layer 21m containing a predetermined metal as a core material. The conductive layer 21m is, for example, a Cu layer, and in this case, the Cu contained in the pad PDm and the via VAm is an example of a first metal.

[0088] The pad PDm and the via VAm also have a conductive layer 22m containing a predetermined metal as a liner. That is, the conductive layer 22m is disposed on the side surface of the conductive layer 21m of the pad PDm, the lower surface of the conductive layer 21m of the pad PDm excluding the connection portion with the via VAm, and between the side surface of the conductive layer 21m of the via VAm and the insulating layer 50. The conductive layer 22m is, for example, a Ti layer, and in this case, the Ti contained in the conductive layer 22m is an example of the second metal.

[0089] At this time, the metal contained in the conductive layer 22m is a metal that is easily diffused into the conductive layer 21m and has a lower oxidation energy than the metal contained in the conductive layer 21m. In addition, the conductive layer 22m, which is a Ti layer or the like, functions as a barrier metal layer that suppresses the diffusion of the conductive layer 21m, which is a Cu layer or the like, into the insulating layer 50.

[0090] The pad PDc has, for example, a rectangular lower surface and is disposed on the insulating layer 40 at the joint surface of the insulating layer 40 covering the peripheral circuit CBA with the insulating layer 50. However, the shape of the pad PDc as viewed from above may be a shape other than a rectangle, such as a circle or an ellipse.

[0091] Here, the insulating layer 40 has a structure in which, for example, silicon oxide layers are generally stacked, similarly to the above-mentioned insulating layer 50. However, in the stacked structure of the insulating layer 40, other insulating layers such as a silicon nitride layer and a silicon oxynitride layer may be interposed, and these other insulating layers may be disposed on the bonding surface of the insulating layer 40.

[0092] The pad PDc has a tapered shape in which the cross-sectional area in the direction along the XY plane decreases from the bonding surface of the insulating layer 40 toward the depth direction of the insulating layer 40.

[0093] A via VAc having, for example, a circular cross section in the direction along the XY plane is connected to the upper end of the pad PDc located at a predetermined depth in the insulating layer 40. The via VAc as a second via has a tapered shape in which the cross-sectional area in the direction along the XY plane and the diameter become smaller from the lower end connected to the pad PDc toward the depth direction of the insulating layer 40.

[0094] An arbitrary number of vias, wirings, and the like are further connected above the via VAc, and electrically connect the above-mentioned peripheral circuits CBA to different pads PDm, respectively.

[0095] The pad PDc and the via VAc have a conductive layer 21c containing a predetermined metal as a core material. The conductive layer 21c is, for example, a Cu layer, similar to the conductive layer 21m of the pad PDm described above. That is, the pad PDc and the via VAc also contain, for example, Cu as a first metal, similar to the pad PDm and the via VAm.

[0096] The pad PDm and the via VAm also have a conductive layer 22m containing a predetermined metal as a liner layer. That is, a conductive layer 22c is disposed on the side surface of the conductive layer 21c of the pad PDc, the upper surface of the conductive layer 21c of the pad PDc excluding the connection portion with the via VAc, and between the side surface of the conductive layer 21c of the via VAc and the insulating layer 40. The conductive layer 22c is, for example, a Ti layer or the like, similar to the conductive layer 22m of the pad PDm and the via VAm described above.

[0097] At this time, the metal contained in the conductive layer 22c is also a metal that easily diffuses into the conductive layer 21c and has a lower oxidation energy than the metal contained in the conductive layer 21c. In addition, the conductive layer 22c, which is a Ti layer or the like, also functions as a barrier metal layer that suppresses the diffusion of the conductive layer 21c, which is a Cu layer or the like, into the insulating layer 40.

[0098] Furthermore, at least a portion of the metal such as Ti contained in the conductive layers 22m and 22c is diffused into the conductive layers 21m and 21c. More specifically, the metal originating from the conductive layers 22m and 22c is unevenly distributed in the conductive layers 21m and 21c mainly at the crystal grain boundaries 21g of the metal such as Cu contained in the conductive layers 21m and 21c.

[0099] Here, when elemental analysis or the like is performed on the conductive layers 21m and 21c, metal originating from the conductive layers 22m and 22c and oxygen are detected at the crystal grain boundaries 21g of the metal contained in the conductive layers 21m and 21c. Therefore, it is considered that the metal originating from the conductive layers 22m and 22c coexists with oxygen at the crystal grain boundaries 21g of the metal contained in the conductive layers 21m and 21c.

[0100] 4(d) shows the interface between the conductive layers 21m, 22m of the pad PDm and the conductive layers 21c, 22c of the pad PDc. However, the pads PDm and PDc are bonded by, for example, a Cu-Cu bond, and there may be cases where the interface therebetween is not observed.

[0101] Even in this case, it is possible to determine that a bonding surface exists between these pads PDm and PDc from any one of the following points.

[0102] That is, when these pads PDm, PDc are bonded, the insulating layers 50, 40 are also bonded to each other, but the interface between these insulating layers 50, 40 is often observable.

[0103] Moreover, the directions of the tapered shapes of the pads PDm and PDc are often different. This is because, as described later, the pad PDm is processed from the outermost surface side of the insulating layer 50, that is, the bonding surface side with the insulating layer 40, and the pad PDc is processed from the outermost surface side of the insulating layer 40, that is, the bonding surface side with the insulating layer 50. As a result, the pad PDm has a tapered shape whose cross-sectional area becomes smaller toward the via VAm side on the lower side of the paper, and the pad PDc has a tapered shape whose cross-sectional area becomes smaller toward the via VAc side on the upper side of the paper.

[0104] (Method of manufacturing semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 5 to 10. Figures 5 to 10 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0105] First, Fig. 5 shows the laminate LMsa, which is the lower layer of the laminate LM before the word lines WL are formed, and how various components are formed in the laminate LMsa. Fig. 5 is a cross-sectional view along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0106] As shown in FIG. 5(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order on a supporting substrate SS.

[0107] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate, etc. The above-mentioned insulating layer 60 (see FIG. 3) may be formed on the upper surface side of the support substrate SS.

[0108] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the staircase region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0109] In addition, a laminate LMsa is formed on the upper source line DSLb, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately laminated one by one. The insulating layer NL is, for example, a silicon nitride layer, and functions as a sacrificial layer that is later replaced with a conductive material to become the word line WL or the select gate line SGS.

[0110] 5(b), in a partial region of the laminate LMsa, the insulating layers NL and OL are processed into a staircase shape to form a staircase portion SPsa. The staircase portion SPsa is formed by repeatedly slimming a mask pattern such as a photoresist layer and etching the insulating layers NL and OL of the laminate LMsa multiple times.

[0111] That is, a mask pattern is formed on the upper surface of the laminate LMsa, and for example, the insulating layers NL and OL in the exposed portions are etched away one by one. Then, the ends of the mask pattern are recessed by a process using oxygen plasma or the like to newly expose the upper surface of the laminate LMsa, and the insulating layers NL and OL are further etched away one by one. By repeating such a process multiple times, the step portion SPsa is formed.

[0112] 5(c), an insulating layer 51 is formed to cover the stepped portion SPsa and reach the height of the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the stepped portion SPsa.

[0113] As shown in FIG. 5(d), a plurality of memory holes MHa and a plurality of holes HLa extending in the stacking direction of the stacked body LMsa are formed, for example, collectively.

[0114] The memory holes MHa penetrate the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa are formed in a region that will later become the memory region MR, and are parts that will become the lower structure of the pillar PL.

[0115] The holes HLa penetrate the insulating layer 51, the stack LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa. These holes HLa are formed in a region that will later become the staircase region SR, and are parts that will become the lower structure of the columnar part. As described above, the lower structure of the columnar part supports these components in the staircase region SR when the stack LMa is formed from the stack LMsa.

[0116] As shown in FIG. 5(e), the memory holes MHa and holes HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer.

[0117] As a result, in the region that will later become the memory region MR, a pillar PLc is formed in which the memory holes MHa are filled with the sacrificial layer 26. Also, in the region that will later become the staircase region SR, a columnar portion HRc is formed in which the holes HLa are filled with the sacrificial layer 26.

[0118] Next, Figures 6 and 7 show the laminate LMsb, which is the upper layer part of the laminate LM before the word lines WL are formed, and how various components are formed in the laminate LMsb. Figures 6 and 7 are cross-sectional views along the X direction of the region that will later become the memory region MR and the staircase region SR, similar to Figure 5 described above.

[0119] 6(a), a laminate LMsb is formed by covering the laminate LMsa and the insulating layer 51 of the stepped portion SPsa and by stacking a plurality of insulating layers NL and a plurality of insulating layers OL one by one alternately. The sacrificial layer NL of the laminate LMsb is later replaced with a conductive layer to become the word line WL or the select gate line SGD.

[0120] As shown in Fig. 6(b), in a partial region of the laminate LMsb, the insulating layers NL and OL are processed into a staircase shape to form a staircase portion SPsb. The staircase portion SPsb is formed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the process shown in Fig. 5(b) above.

[0121] At this time, the uppermost step of the staircase portion SPsa and the lowermost step of the staircase portion SPsb are brought close to each other to form the staircase portion SPsb. As a result, the staircase portions SPsa and SPsb are arranged so as to be continuously connected from the lower layer side to the upper layer side of the laminates LMsa and LMsb. In addition, the laminate LMsb on the insulating layer 51 covering the staircase portion SPsb is removed, so that the upper end of the columnar portion HRc formed in the staircase portion SPsa is exposed on the upper surface of the insulating layer 51.

[0122] 6(c), an insulating layer 51 is formed to cover the staircase portion SPsb and to cover the insulating layer 51 already formed on the staircase portion SPsa. As a result, the insulating layer 51 reaches the height of the upper surface of the laminated body LMsb.

[0123] As shown in FIG. 7A, a plurality of memory holes MHb and a plurality of holes HLb extending in the stacking direction at the height position of a stacked body LMsb are formed, for example, all at once.

[0124] The memory holes MHb penetrate the multilayer body LMsb and reach the upper ends of the pillars PLc formed in the multilayer body LMsa. These memory holes MHb are arranged in a region that will later become the memory region MR, and are parts that will become the upper structure of the pillars PL.

[0125] The holes HLb penetrate the insulating layer 51 and the laminate LMsb, and reach the upper end of the columnar portion HRc formed in the laminate LMsa. The holes HLb are arranged at positions overlapping with the staircase portions SPsa and SPsb in the stacking direction, and are portions that form the upper structure of the columnar portion. As described above, the upper structure of the columnar portion supports these components in the staircase region SR when the laminate LMsb is formed from the laminate LMb.

[0126] As shown in FIG. 7(b), the sacrificial layer 26 is removed from the pillar PLc and the columnar portion HRc connected to the bottom ends of the memory holes MHb and holes HLb, respectively.

[0127] This results in the formation of multiple memory holes MHb, each opening at the bottom of the memory holes MHa, penetrating the insulating layer 51, the stacks LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, and reaching the lower source line DSLa.

[0128] Furthermore, holes HLa are opened at the bottoms of the holes HLb, respectively, and a plurality of holes HL are formed which penetrate the insulating layer 51, the stacked bodies LMsb and LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0129] As shown in FIG. 7(c), an insulating layer 58 such as a silicon oxide layer is filled into each of the multiple holes HL to form multiple columnar portions HR that penetrate the insulating layer 51, the stacked bodies LMsb, LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0130] When filling the insulating layer 58 into the holes HL, the memory holes MH already formed in the region that will later become the memory region MR are protected with a photoresist layer or the like.

[0131] Next, a state in which a pillar PL is formed by forming a multilayer structure or the like in the memory hole MH is shown in Fig. 8. Fig. 8 is an enlarged cross-sectional view of the memory hole MH at the height position of the intermediate sacrificial layer SCN.

[0132] As shown in FIG. 8(a), a block insulating layer BK such as a silicon oxide layer is formed on the side walls of the memory holes MH and holes HL.

[0133] As shown in FIG. 8(b), a charge storage layer CT is formed on the side wall of the memory hole MH via a block insulating layer BK.

[0134] As shown in FIG. 8(c), a tunnel insulating layer TN is formed on the side wall of the memory hole MH via a block insulating layer BK and a charge storage layer CT.

[0135] As a result of the above, a memory layer ME including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN is formed in this order from the outer periphery side of the memory hole MH.

[0136] As shown in FIG. 8(d), a channel layer CN is formed on the side wall of the memory hole MH via a memory layer ME.

[0137] As shown in FIG. 8(e), the void remaining in the memory hole MH is filled with the core layer CR.

[0138] Thereafter, the core layer CR at the upper end of the memory hole MH is removed and filled with a semiconductor layer to form a cap layer CP (see FIG. 4(a)).

[0139] In addition, a slit (not shown) is formed so as to extend in the stacked bodies LMsa and LMsb in the X-direction, penetrate the stacked bodies LMsa and LMsb and the upper source line DSLb, and reach the intermediate sacrificial layer SCN or the intermediate insulating layer SCO. The slit is later filled with the insulating layer 55 to become the plate-shaped portion PT.

[0140] As shown in Fig. 8(f), a chemical solution such as hot phosphoric acid is injected through the slit to remove the intermediate sacrificial layer SCN, and a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. As a result, a part of the block insulating layer BK formed on the side wall of the memory hole MH is exposed in the gap layer GPs.

[0141] At this time, a protective layer such as a silicon oxide layer is formed on the side walls of the slits to prevent the insulating layer NL in the stacks LMsa and LMsb from being removed. The intermediate sacrificial layer SCN is removed solely by the chemical solution injected through the lower end of the slit. Moreover, the intermediate insulating layer SCO formed in place of the intermediate sacrificial layer SCN in the region that will later become the staircase region SR is not removed by the chemical solution. Therefore, the gap layer GPs is not formed in the region that will later become the staircase region SR.

[0142] As shown in Fig. 8(g), different chemical solutions are injected through the slits to sequentially remove the block insulating layer BK, the charge storage layer CT, and the tunnel insulating layer TN exposed in the gap layer GPs, thereby exposing a part of the side surface of the channel layer CN in the gap layer GPs.

[0143] As shown in FIG. 8(h), a source gas such as polysilicon is injected through the slit to fill the gap layer GPs with a polysilicon layer, thereby forming an intermediate source line BSL between the lower source line DSLa and the upper source line DSLb.

[0144] In this manner, a pillar PL is formed, which is connected to the source line SL at a portion of the side surface of the channel layer CN.

[0145] After that, the protective layer on the sidewall of the slit is removed, and a chemical solution such as hot phosphoric acid is injected through the slit to remove the insulating layer NL in the laminates LMsa and LMsb. Also, a source gas such as tungsten is injected through the slit to fill the gap in the laminates LMsa and LMsb from where the insulating layer NL was removed with a tungsten layer or the like.

[0146] As a result of the above, a laminate LM is formed in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated, and further comprising the select gate lines SGD, SGS.

[0147] The insulating layer NL is removed, and the laminated bodies LMsa and LMsb having gaps in the multiple layers have a fragile structure. In the region that will later become the memory region MR, a plurality of pillars PL support the fragile laminated bodies LMsa and LMsb. On the other hand, in the stepped portions SPsb and SPsa, a plurality of columnar portions HR support the laminated bodies LMsa and LMsb.

[0148] This prevents the insulating layers OL remaining in the laminates LMsa and LMsb from bending, and prevents the laminates LMsa and LMsb themselves having gaps from being distorted or broken.

[0149] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also called a replacement process.

[0150] Thereafter, the slits are filled with an insulating layer 54 to form the plate-like portion PT. A groove penetrating one or more layers including the top layer of the laminate LMb is formed, and the groove is filled with an insulating layer 56 to form a separation layer SHE that divides one or more upper layers of the laminate LMb into the pattern of the select gate line SGD.

[0151] In addition, a plurality of contacts CC are formed which penetrate the insulating layer 51 and reach the word lines WL and the select gate lines SGD, SGS which constitute the steps of the staircase portion SP, respectively.

[0152] Next, an insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the laminate LM and the staircase region SR, and plugs CH are formed through the insulating layer 52 to be connected to the pillars PL. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and bit lines BL and the like connected to the plugs CH are formed. After this, insulating layers 54... and the like are formed in sequence, and plugs, wiring, and the like are formed for an arbitrary number of stacked layers.

[0153] 9 shows how a via VAm and a pad PDm are formed in the insulating layer 50 and then bonded to a pad PDc on the insulating layer 40 side covering the peripheral circuit CBA. FIG. 9 is a cross-sectional view of a bonding portion of the insulating layer 50 bonded to the insulating layer 40.

[0154] 9(a), a via hole VH and a trench GR connected to the upper end of the via hole VH are formed by performing etching or the like from the outermost surface side of the insulating layer 50. The via hole VH reaches other wirings, etc. (not shown) already formed in the insulating layer 50.

[0155] The via hole VH and the trench GR are obtained, for example, by forming a via hole VH that reaches a predetermined depth from the outermost surface of the insulating layer 50, and then expanding the upper end of the via hole VH into the shape of the trench GR. Alternatively, for example, after forming a trench GR that reaches a predetermined depth from the outermost surface of the insulating layer 50, a via hole VH that extends from the bottom surface of the trench GR to a deeper position in the insulating layer 50 may be formed.

[0156] In either processing technique, by performing etching or the like from the outermost surface side of the insulating layer 50, both the trench GR and the via hole VH have a tapered shape in which the cross-sectional area along the XY plane becomes smaller from the upper end side to the lower end side.

[0157] 9(b), a conductive layer 22m such as a Ti layer is formed to cover the side and bottom surfaces of the trench GR and the side surfaces of the via hole VH. At this time, the conductive layer 22m is also formed on the upper surface of the insulating layer 50.

[0158] As shown in Fig. 9(c), the gaps remaining in the trench GR and the via hole VH are filled with a Cu material or the like to form a conductive layer 21m. At this time, the Cu material is filled into the trench GR and the via hole VH by plating or the like, and the conductive layer 21m is formed to have crystal grain boundaries 21g of a metal such as Cu. At this time, the conductive layer 21m is also formed on the upper surface of the insulating layer 50 via the conductive layer 22m. However, thereafter, the conductive layers 21m and 22m on the upper surface of the insulating layer 50 are sequentially removed by CMP (Chemical Mechanical Polishing) or the like.

[0159] As a result, a pad PDm having an upper surface exposed on the outermost surface of the insulating layer 50 and a via VAm having an upper end connected to a lower end of the pad PDm are formed. Note that the method of forming the pad PDm and the via VAm at the same time in this manner is also called a dual damascene method.

[0160] In addition, metals such as Cu in the pad PDm may be chemically oxidized by performing a CMP process or the like on the surface of the conductive layer 21m filled in the trench GR and the via hole VH. In addition, when the above-mentioned configuration is formed and then placed in the atmosphere for a predetermined time, metals such as Cu in the pad PDm exposed on the surface of the insulating layer 50 may be naturally oxidized.

[0161] An oxide layer 57m on the upper surface of the pad PDm shown in FIG. 9(d) is an oxide layer formed by chemical oxidation, natural oxidation, or the like.

[0162] Meanwhile, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminate LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw out the peripheral circuit CBA to the surface of the insulating layer 40, and the outermost surface of the insulating layer 40 is connected to the pads PDc and vias VAc formed on the side.

[0163] At this time, the pads PDc and vias VAc in the insulating layer 40 are also formed in the same manner as in Figures 9(a) to 9(c). These pads PDc and vias VAc are formed by etching or the like from the outermost surface side of the insulating layer 40, and thus have a tapered shape in which the cross-sectional area along the XY plane decreases in the direction in which the depth increases from the outermost surface side of the insulating layer 40.

[0164] 9(e), the insulating layer 50 on the support substrate SS side and the insulating layer 40 on the semiconductor substrate SB side are bonded. These insulating layers 50, 40 can be bonded by, for example, activating them in advance by plasma treatment or the like. At this time, the support substrate SS and the semiconductor substrate SB are aligned so that the pad PDm formed on the insulating layer 50 and the pad PDc formed on the insulating layer 40 overlap in the vertical direction.

[0165] At the time when the insulating layers 50 and 40 are joined together, an oxide layer 57c is also formed on the surface of the pad PDc.

[0166] 9(f), after the insulating layers 50 and 40 are bonded together, an annealing process is performed to bond the pads PDm and PDc together. The annealing process causes a part of the metal such as Ti in the conductive layers 22m and 22c to diffuse into the conductive layers 21m and 21c.

[0167] In addition, the annealing process causes the oxide layers 57m, 57c on the top surfaces of the pads PDm, PDc to disappear. This is presumably because the metal from the conductive layers 22m, 22c that has diffused into the conductive layers 21m, 21c reduces the oxide layers 57m, 57c on the top surfaces of the pads PDm, PDc. The results of the elemental analysis described above show that the metal from the conductive layers 22m, 22c is unevenly distributed, together with oxygen, at the crystal grain boundaries 21g of the metal in the conductive layers 21m, 21c.

[0168] A part of the metal in the conductive layers 22m and 22c diffuses into the conductive layers 21m and 21c while reducing the oxide layers 57m and 57c, so that the thickness of the conductive layers 22m and 22c may become slightly thinner in a part or overall.

[0169] After the oxide layers 57m and 57c on the surfaces have disappeared, the annealing process is continued, whereby the pads PDm and PDc are bonded together by, for example, Cu-Cu bonding.

[0170] In this manner, the support substrate SS and the semiconductor substrate SB are bonded together.

[0171] Thereafter, the support substrate SS is ground and removed to expose the source lines SL, and the electrode films EL are connected via the insulating layer 60 in which the plugs PG are formed. The semiconductor substrate SB is diced into individual pieces to obtain the semiconductor memory device 1 in which the above-mentioned chips 2 and 3 (see FIG. 3) are bonded to each other.

[0172] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0173] In addition, as described above, by bonding the pads PDm, PDc to each other, the interface between the pads PDm, PDc may disappear. Even in this case, the bonding interface between the insulating layers 50, 40 may be observable, and the bonding surface between the pads PDm, PDc may be distinguishable by observing the direction of the tapered shapes of the pads PDm, PDc.

[0174] A method for identifying the bonding surfaces of the pads PDm and PDc other than those mentioned above will be described below with reference to Fig. 10. Fig. 10 is a cross-sectional view of the bonding portion between the insulating layer 50 and the insulating layer 40, similar to Fig. 9 described above.

[0175] As shown in FIG. 10(a), there may be a case where a positional deviation occurs in the overlap between the pads PDm and PDc in the vertical direction.

[0176] As described above, when bonding the pads PDm and PDc to each other, the support substrate SS and the semiconductor substrate SB are aligned so that they overlap in the vertical direction. However, due to an alignment error or the like at this time, the pads PDm and PDc may be bonded to each other with a slight misalignment.

[0177] In this way, for example, by observing the pads PDm and PDc in which a positional deviation has occurred, it is possible to determine that a bonding surface exists between these pads PDm and PDc.

[0178] As shown in Fig. 10(b), the size of the pad PDm may differ from the size of the pad PDc. The reason for the difference in size between the pads PDm and PDc is that the pads PDm and PDc have different design sizes. Alternatively, since the pads PDm and PDc are formed separately, the pads PDm and PDc may be formed to have different sizes due to processing errors during formation, etc.

[0179] In this way, by observing that the pads PDm and PDc have different sizes, it is possible to determine that a bonding surface exists between these pads PDm and PDc.

[0180] (Overview) Some semiconductor devices are constructed by forming different elements on different substrates and bonding these substrates together. To electrically connect these elements, pads electrically connected to each element are formed on the bonding surfaces. By bonding these pads when bonding the substrates together, the different elements can be electrically connected to each other.

[0181] However, after the pads are formed, an oxide layer may be formed on the surface of the pads before they are bonded to each other. When bonding the pads, the oxide layer on the surface may become a factor that inhibits electrical conduction between the pads.

[0182] On the other hand, in addition to the pads that electrically connect different elements, the semiconductor device also has a number of contacts, vias, wiring, etc., and a barrier metal layer may be used in combination to suppress the diffusion of the metal material that constitutes these into the insulating layer. When the metal material is Cu, a Ta layer is generally used as the barrier metal layer.

[0183] The inventors have focused on this barrier metal layer and investigated the use of a metal that has high diffusivity in Cu and high reducibility as a constituent material of the barrier metal layer, and have found that this allows the oxide layer on the pad surface to disappear during the annealing process when bonding the pad.

[0184] According to the semiconductor memory device 1 of the embodiment, the pads PDm, PDc have the conductive layers 22m, 22c disposed between the pads PDm, PDc and the insulating layers 50, 40, respectively, and the conductive layers 22m, 22c contain a metal having a lower oxidation energy than the metal of the conductive layers 21m, 21c of the pads PDm, PDc. This makes it possible to suppress the conduction between the pads PDm, PDc from being hindered by the oxide layers on the pad surfaces PDm, PDc.

[0185] According to the semiconductor memory device 1 of the embodiment, the metal contained in the conductive layers 22m and 22c is titanium, and the conductive layers 22m and 22c are barrier metal layers. By using Ti as the metal for the conductive layers 22m and 22c, the conductive layers 22m and 22c can function as barrier metal layers.

[0186] According to the semiconductor memory device 1 of the embodiment, a pillar PL having a channel layer CN penetrating the laminate LM is provided in the stacking direction of the laminate LM arranged in the insulating layer 50, and the pillar PL is electrically connected to a pad PDm. A peripheral circuit CBA including a plurality of transistors TR is provided in the insulating layer 40, and the peripheral circuit CBA is electrically connected to a pad PDc.

[0187] In this manner, by forming different elements on different substrates such as the support substrate SS and the semiconductor substrate SB and bonding them together, a semiconductor device having advanced and complicated functions can be configured in a small space.

[0188] In the above embodiment, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limited to the above. For example, the pillar may be configured to remove the memory layer at the bottom of the pillar and connect to the source line at the lower end of the channel layer. In this case, the source line may be formed after bonding the support substrate SS and the semiconductor substrate SB.

[0189] More specifically, when grinding and removing the support substrate SS after bonding the support substrate SS and the semiconductor substrate SB, grinding can be continued until the lower ends of the pillars PL are exposed, and the source lines can be formed so as to cover the exposed lower ends of the pillars PL. At this time, the source lines may be formed of a metal layer instead of a polysilicon layer or the like.

[0190] In the above embodiment, the laminate LM has a two-tier structure including two laminates LMa and LMb. However, the number of tiers in the laminate may be one tier, or three or more tiers.

[0191] In the above embodiment, the staircase region SR is disposed at the end of the laminate LM in the X direction. However, the staircase region may be disposed in the center of the laminate when viewed from the stacking direction by digging the center of the laminate in a staircase shape.

[0192] (Variation 1) Next, a semiconductor memory device according to a first modification of the embodiment will be described with reference to Fig. 11. In the semiconductor memory device according to the first modification, the procedure for forming the pads PDma and the vias VAma is different from that of the above-described embodiment.

[0193] In the following drawings, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0194] 11 is a diagram illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to Modification 1 of an embodiment. More specifically, FIG. 11 is a cross-sectional view of a bonding portion of an insulating layer 50 bonded to an insulating layer 40 in a semiconductor memory device in the middle of manufacturing the modification 1.

[0195] 11(a) is formed by sequentially stacking the above-mentioned insulating layers 52, 53, 54, etc., covering the laminate LM and the pillar PL, etc. In the insulating layer 50n, wiring (not shown) directly below the via VAma connected to the pad PDma to be formed later has already been formed, and the wiring has a thickness equivalent to the height of the via VAma to be formed later.

[0196] As shown in FIG. 11(a), via holes VH are formed by performing etching or the like from the outermost surface side of the insulating layer 50n.

[0197] As shown in Fig. 11(b), a conductive layer 22mv is formed to cover the side surface of the via hole VH. The conductive layer 22mv as the fifth metal layer is, for example, a Ti layer containing Ti, similar to the conductive layer 22m in the above-mentioned embodiment. The conductive layer 22mv is also formed on the upper surface of the insulating layer 50n.

[0198] 11(c), the gap remaining in the via hole VH is filled with a Cu material or the like to form a conductive layer 21mv as a fourth metal layer. The conductive layer 21mv is also formed on the upper surface of the insulating layer 50n via a conductive layer 22mv. These conductive layers 21mv, 22mv are sequentially removed by CMP or the like. As a result, a via VAma is formed as a first via.

[0199] 11(d), an insulating layer such as a silicon oxide layer having a thickness equivalent to the height of the pad PDma to be formed later is stacked so as to cover the via VAma, thereby obtaining an insulating layer 50. Further, etching or the like is performed from the top surface side of the insulating layer 50 to form a trench GR in the stacked portion of the insulating layer 50.

[0200] 11(e), a conductive layer 22mp is formed to cover the side and bottom surfaces of the trench GR. At this time, the conductive layer 22mp is formed to cover the upper end of the via VAma, and the conductive layer 22mp is also formed on the upper surface of the insulating layer 50. The conductive layer 22mp as the second metal layer is, for example, a Ti layer containing Ti, similar to the conductive layer 22m in the above-mentioned embodiment.

[0201] 11(f), a conductive layer 21mp is formed as a first metal layer by filling a gap remaining in the trench GR with a Cu material or the like. The conductive layer 21mp is also formed on the upper surface of the insulating layer 50 via a conductive layer 22mp. These conductive layers 21mp, 22mp are sequentially removed by CMP or the like. As a result, a pad PDma is formed as a first pad having a lower end connected to a via VAma.

[0202] Incidentally, such a method of forming the pad PDma and the via VAma in separate steps is also called a single damascene method, etc. According to such a formation method, the conductive layer 22mp of the pad PDma is interposed between the pad PDma and the via VAma.

[0203] Thereafter, the pad PDm is bonded to a pad formed on the insulating layer 40, similar to the above-described embodiment. The pad on the insulating layer 40 side may be formed by a dual damascene method, similar to the above-described embodiment, or may be formed by a single damascene method, similar to the pad PDma of the first modified example.

[0204] The semiconductor memory device of the first modification provides the same effects as the semiconductor memory device 1 of the above embodiment.

[0205] (Variation 2) Next, a semiconductor memory device according to a second modification of the embodiment will be described with reference to Fig. 12. In the semiconductor memory device according to the second modification, the pads PDcb, PDmd, and PDcd and the vias VAcb, VAmc, VAcc, VAmd, and VAcd, etc. have layers different from those of the pads PDm, PDc and the vias VAm, VAc of the above-mentioned embodiment, respectively.

[0206] In the following drawings, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0207] FIG. 12 is a cross-sectional view of a bonding portion between insulating layers 40 and 50 of a semiconductor memory device according to the second modification of the embodiment.

[0208] 12(a), the pads PDm and vias VAm provided in the insulating layer 50 have the same configuration as in the above-described embodiment. That is, the pads PDm and vias VAm are formed by the dual damascene method, and have a conductive layer 22m containing a metal such as Ti.

[0209] On the other hand, the pad PDcb and the via VAcb provided on the insulating layer 40 have, as a barrier metal layer, a conductive layer 23c different from the conductive layer 22c of the above-described embodiment. More specifically, the pad PDcb and the via VAcb are formed by the dual damascene method, and have the conductive layer 23c containing a metal such as Ta as a third metal.

[0210] As described above, a conductive layer containing Ta or the like is often used as a barrier metal layer in combination with a Cu material. On the other hand, Ta or the like does not have a high diffusibility into a Cu material, and does not have the property of reducing an oxide layer formed on the surface of, for example, the pads PDm and PDcb.

[0211] However, by having at least one of the pads PDm and PDcb, the pad PDm on one side, have the conductive layer 22m containing Ti or the like, it is possible to eliminate the oxide layer formed on the surface of the pads PDm and PDcb.

[0212] 12(b), the pad PDma and the via VAmc provided in the insulating layer 50, and the pad PDcc and the via VAcc provided in the insulating layer 40 are each formed by a single damascene method. Similarly to the conductive layers 21m, 22m, 21c, and 22c in the above-described embodiment, the pads PDma and PDcc each have a conductive layer 21mp or 21cp containing a metal such as Cu, and a conductive layer 22mp or 22cp containing a metal such as Ti.

[0213] On the other hand, the vias VAmc, VAcc provided in the insulating layers 50, 40, respectively, have conductive layers 21mv, 21cv containing a metal such as Cu, and conductive layers 23mv, 23cv containing a metal such as Ta instead of the conductive layers 22m, 22c of the above-mentioned embodiment.

[0214] As described above, when the pad PDma and the via VAmc, or the pad PDcc and the via VAcc, etc. are formed by the single damascene method, the pad PDmc, the pad PDcc and the via VAmc, VAcc can be provided with liners of conductive layers containing different metal materials. Also, at this time, as described above, if at least one of the pads PDma, PDcc has the conductive layers 22mp, 22cp containing a metal such as Ti, the oxide layer on the surface of the pads PDma, PDcc can be eliminated.

[0215] Therefore, as shown in the example of Figure 12(b), for example, liners of conductive layers 22mp, 22cc containing a metal such as Ti can be formed on pads PDma, PDcc, and conductive layers 23mv, 23cv not containing Ti, such as Ta, can be formed on vias VAma, VAcc.

[0216] In this case, instead of or in addition to using the conductive layers 23mv, 23cv that do not contain Ti for the liner layers of the vias VAma, VAcc, at least one of the conductive layers 21mv, 21cv that are the core materials of the vias VAma, VAcc can be configured to contain another metal such as tungsten instead of Cu. In this way, the combination of materials for the liner layers and core materials in the pads PDma and vias VAmc, or in the pads PDcc and vias VAcc when the single damascene method is used can be changed in various ways.

[0217] The conductive layer 21cp is an example of a first metal layer, the conductive layer 22cp is an example of a third metal layer, the conductive layer 21cv is an example of a sixth metal layer, and the conductive layer 23cv is an example of a seventh metal layer.

[0218] In the example shown in FIG. 12(c), the pads PDmd and vias VAmd provided in the insulating layer 50, and the pads PDcd and vias VAcd provided in the insulating layer 40 are each formed by the dual damascene method.

[0219] Moreover, the pads PDmd, PDcd have, inside the conductive layers 23m, 23c containing a metal such as Ta, conductive layers 24m, 24c containing a metal other than Ti that is likely to diffuse into the conductive layers 21m, 21c of the pads PDmd, PDcd, such as a Cu material, and has a lower oxidation energy than the Cu material of the conductive layers 21m, 21c. That is, the conductive layers 24m, 24c are interposed between the conductive layers 23m and 21m and between the conductive layers 23c and 21c in the respective pads PDmd, PDcd.

[0220] Examples of metals that are easily diffused into the Cu material of the conductive layers 21m and 21c and have a lower oxidation energy than the Cu material of the conductive layers 21m and 21c include Mn, Al, Mg, etc., in addition to Ti. Therefore, the conductive layers 24m and 24c as the second and third metal layers can contain at least one of Mn, Al, and Mg.

[0221] However, these elements Mn, Al, and Mg do not function as a barrier metal layer, at least by themselves. Therefore, the pads PDmd and PDcd have, in addition to the conductive layers 24m and 24c, conductive layers 23m and 23c containing Ti or the like that function as a barrier metal layer.

[0222] As described above, in addition to the configurations shown in FIG. 12 above, various combinations of conductive layers containing various metal materials can be used as the pads and vias in insulating layer 50 and the liners of the pads and vias in insulating layer 40.

[0223] The semiconductor memory device of the second modification provides the same effects as the semiconductor memory device 1 of the above-described embodiment.

[0224] In the above-mentioned embodiment and modifications 1 and 2, the semiconductor device is the semiconductor memory device 1 obtained by bonding elements including memory cells MC and elements such as a peripheral circuit CBA that controls the electrical operation of the memory cells MC. However, the semiconductor device to which the pads of the embodiment and modifications 1 and 2 can be applied is not limited to this, and may be an image sensor in which pixels and circuit elements are bonded together, a semiconductor device in which a memory element and a logic element different from the semiconductor memory device 1 are bonded together, etc.

[0225] In the above-mentioned embodiment and modified examples 1 and 2, a Ti layer is used as a liner for the conductive layers 22m, 22c, etc., which have a function as a barrier metal layer and a function of reducing an oxide layer. However, it is known that a Ti-Mn alloy also has a barrier property. Therefore, it is possible to use a Ti-Mn alloy as a liner that has a function as a barrier metal layer and a function of reducing an oxide layer.

[0226] In this way, in the semiconductor device of the embodiment, a conductive layer that contains at least one of elemental or alloyed Ti, Mn, Al, and Mg and that may or may not function as a barrier metal layer can be appropriately used as the conductive layer covering the Cu material that serves as the core material of the pad.

[0227] In this case, when a layer containing a metal that does not function as a barrier metal layer is used as the conductive layer covering the Cu material or the like that is the core material of the pad, a separate barrier metal layer can be provided on the outside of the conductive layer. The separate barrier metal layer may be a single metal layer such as a Ta layer, as in the modification 2 shown in Fig. 12(c) above, or may be a metal nitride layer such as a TaN layer or a TiN layer.

[0228] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0229] 1...semiconductor memory device, 21c, 21cp, 21cv, 21m, 21mp, 21mv...conductive layer, 22c, 22cp, 22m, 22mp, 22mv, 23c, 23cv, 23m, 23mv, 24c, 24m...conductive layer, CN...channel layer, LM, LMa, LMb, LMsa, LMsb...laminated body, MC...memory cell, MR...memory region, NL, OL...insulating layer, PDc, PDcb, PDcc, PDcd, PDm, PDma, PDmd...pad, PL...pillar, SR...staircase region, SGD, SGS...select gate line, STD, STS...select gate, VAc, VAcb, VAcc, VAcd, VAm, VAmc, VAmd...via, WL...word line.

Claims

1. a first chip including a first insulating layer; A semiconductor device including a second insulating layer and a second chip bonded to the first chip, a pad provided on a bonding surface between the first chip and the second chip, the pad having a first metal layer including a first metal, a second metal layer disposed between the first metal layer and the first insulating layer, and a third metal layer disposed between the first metal layer and the second insulating layer; one or both of the second and third metal layers includes a second metal having a lower oxidation energy than the first metal; the first metal layer further comprises the second metal; Semiconductor device.

2. At least a portion of the second metal in the first metal layer is unevenly distributed in the crystal grain boundaries of the first metal layer. The semiconductor device according to claim 1 .

3. the first metal is copper; the second metal is one or more of titanium, manganese, aluminum, and magnesium; The semiconductor device according to claim 1 .

4. The second metal is contained in at least the second metal layer, the second metal is at least titanium; the second metal layer is a barrier metal layer; The semiconductor device according to claim 3 .

5. The second metal is contained in at least the second metal layer, The pad is a barrier metal layer interposed between the second metal layer and the first insulating layer; The semiconductor device according to claim 3 .

6. a first via disposed in the first insulating layer and connected to the pad, the first via having a fourth metal layer and a fifth metal layer disposed between the fourth metal layer and the first insulating layer; a second via disposed in the second insulating layer and connected to the pad, the second via having a sixth metal layer and a seventh metal layer disposed between the sixth metal layer and the first insulating layer; The semiconductor device according to claim 1 .

7. The second metal layer is also interposed between the pad and the first via. The semiconductor device according to claim 6.

8. In the first insulating layer, a laminate in which a plurality of conductive layers are laminated one by one at a distance from each other; A pillar having a semiconductor layer penetrating the stack in a stacking direction of the stack, The pillar is electrically connected to the pad. The semiconductor device according to claim 1 .

9. further comprising a plurality of transistors disposed in the second insulating layer; the plurality of transistors are electrically connected to the pad; The semiconductor device according to claim 8.

10. a first chip including a first insulating layer; A semiconductor device including a second insulating layer and a second chip bonded to the first chip, a first pad provided on a bonding surface of the first chip to be bonded to the second chip; a second pad provided on a bonding surface of the second chip to be bonded to the first chip; the first and second pads have a first metal layer including a first metal; the first pad further comprises a second metal layer disposed between the first metal layer and the first insulating layer; the second pad further comprises a third metal layer disposed between the first metal layer and the second insulating layer; one or both of the second and third metal layers includes a second metal having a lower oxidation energy than the first metal; the first metal layer further comprises the second metal; Semiconductor device.

Images