Semiconductor device, testing device for semiconductor device, and multi-chip package

Abstract

To provide a semiconductor device that can shorten a test time, a testing device for the semiconductor device, and a multi-chip package.SOLUTION: A semiconductor device includes a first transistor, a first wire connected to the first transistor, a first terminal connected to the first transistor through the first wire, a second transistor, a second wire connected to the second transistor, a second terminal connected to the second transistor through the second wire, and a switch provided between the first wire and the second wire. Switches of the first terminal and the second terminal are on at a test, and the switches of the first terminal and the second terminal are off not at the test.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a test device for the semiconductor device, and a multi-chip package. [Background technology]

[0002] Patent Document 1 discloses a technique for inspecting the state of a plurality of terminals provided in an integrated circuit. In the conventional technique of Patent Document 1, the integrated circuit to be inspected includes a plurality of transistors, output terminals connected to each of these transistors, and a common wiring provided between the transistors and the output terminal. In order to inspect whether the plurality of terminals and the wiring extending from the terminals to the transistors are properly connected to the transistors, a test device called a tester may be connected to each of the plurality of terminals in sequence, and a voltage may be applied from the test device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-261126 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, as the number of terminals provided on an integrated circuit increases, the number of times that a test device must be reconnected to the terminals also increases, and therefore, in the conventional technology, the time required to complete testing of all terminals may increase. Also, in a multi-chip package circuit including multiple integrated circuits, after the multiple integrated circuits are mounted on the multi-chip package, only some of the multiple terminals may be located outside (on the surface) of the multi-chip package, and therefore, it may not be possible to test all terminals individually. Thus, in the conventional technology, there is room for improvement in terms of shortening the test time of an integrated circuit or multi-chip package having multiple terminals.

[0005] In consideration of the above circumstances, an object of the present disclosure is to provide a semiconductor device, a testing device for the semiconductor device, and a multi-chip package that can reduce the test time. [Means for solving the problem]

[0006] In order to solve the above problems, the semiconductor device disclosed herein comprises a first transistor, a first wiring connected to the first transistor, a first terminal connected to the first transistor via the first wiring, a second transistor, a second wiring connected to the second transistor, a second terminal connected to the second transistor via the second wiring, and a switch provided between the first wiring and the second wiring, wherein the switch is in an on state when the first terminal and the second terminal are being tested, and the switch is in an off state when the first terminal and the second terminal are not being tested.

[0007] In order to solve the above problem, a testing apparatus for a semiconductor device according to the present disclosure includes a semiconductor device comprising: a first transistor, a first wiring connected to the first transistor, a first terminal connected to the first transistor via the first wiring, a second transistor, a second wiring connected to the second transistor, and a second terminal connected to the second transistor via the second wiring; and the testing apparatus comprises a third wiring connected to the first terminal and provided inside the testing apparatus, a fourth wiring connected to the second terminal and provided inside the testing apparatus, and a switch provided between the third wiring and the fourth wiring, wherein the switch is in an on state when the first terminal and the second terminal are being tested, and the switch is in an off state when the first terminal and the second terminal are not being tested.

[0008] In order to solve the above problem, the multi-chip package of the present disclosure is a multi-chip package having at least a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a first transistor, a first wiring connected to the first transistor, and a first terminal connected to the first transistor via the first wiring, and the second semiconductor device comprises a second transistor, a second wiring connected to the second transistor, and a second terminal connected to the second transistor via the second wiring, and a switch provided between the first wiring and the second transistor is in an on state when the first terminal and the second terminal are being tested, and is in an off state when the first terminal and the second terminal are not being tested. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a semiconductor device, a testing device for the semiconductor device, and a multi-chip package that can reduce the test time. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram for explaining a method of testing the semiconductor device 100-1. [Diagram 3] FIG. 3 is a diagram showing a configuration of a semiconductor device according to a comparative example. [Figure 4] FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing a configuration of a test device according to the third embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing a configuration of a multi-chip package according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0012] [First embodiment] FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device 100-1 may be interpreted as an LSI (Large Scale Integration). The semiconductor device 100-1 may include a plurality of transistors. Specifically, the semiconductor device 100-1 may include a first transistor 1 and a second transistor 2. More specifically, the semiconductor device 100-1 may include a first transistor 1 constituting a push-pull circuit and a second transistor 2 constituting a push-pull circuit. The number of transistors included in the semiconductor device 100-1 is not limited to two, and the semiconductor device 100-1 may include three or more transistors. The first transistor 1 and the second transistor 2 may be interpreted as transistors constituting a circuit other than a push-pull circuit.

[0013] The first transistor 1 may be interpreted as a circuit including a first switch element P1 and a second switch element N1 connected in series. Specifically, the first transistor 1 may be interpreted as a circuit including a first switch element P1 on a first potential side, and a second switch element N1 on a second potential side lower than the first potential connected in series to the first switch element P1. The first transistor 1 may output a signal obtained by amplifying an input signal by the first switch element P1 and the second switch element N1 operating in a complementary manner. The first potential may be interpreted as the potential of a power supply VD, and the second potential may be interpreted as the potential of a ground GND.

[0014] The second transistor 2 may be interpreted as a circuit having a similar configuration to the first transistor 1. Specifically, the second transistor 2 may be interpreted as a circuit including a first switch element P2 and a second switch element N2 connected in series. The second transistor 2 may be interpreted as a circuit including a first switch element P2 on a first potential side, and a second switch element N2 on a second potential side connected in series to the first switch element P2. The second transistor 2 may output a signal obtained by amplifying an input signal by the first switch element P2 and the second switch element N2 operating in a complementary manner.

[0015] The first switch element P1, the first switch element P2, the second switch element N1, and the second switch element N2 have their on / off operations controlled by a control circuit (not shown).

[0016] In addition to a first transistor 1 and a second transistor 2, the semiconductor device 100-1 may include a first wiring W1 connected to the first transistor 1, and a first terminal T1 connected to the first transistor 1 via the first wiring W1.

[0017] The first wiring W1 may be interpreted as a wiring connected to the first switch element P1 and the second switch element N1 of the first transistor 1. The first terminal T1 may be interpreted as an output terminal that connects a lead (not shown) to the semiconductor device 100-1.

[0018] The semiconductor device 100-1 may include a second wiring W2 connected to the second transistor 2, a second terminal T2 connected to the second transistor 2 via the second wiring W2, and a first switch SW1 and a second switch SW2 arranged between the first wiring W1 and the second wiring W2.

[0019] The second terminal T2 may be interpreted as an output terminal that connects a lead (not shown) to the semiconductor device 100-1. The second wiring W2 may be interpreted as a wiring connected to the first switch element P2 and the second switch element N2 of the second transistor 2.

[0020] The first switch SW1 and the second switch SW2 may be considered as switch elements whose on / off operations are controlled by a control circuit (not shown).

[0021] The first switch SW1 may be in an ON state when the first terminal T1 and the second terminal T2 are being tested, and in an OFF state when the first terminal T1 and the second terminal T2 are not being tested.

[0022] The second switch SW2 may be interpreted as a switch element provided between the second wiring W2 and the wiring W. The second switch SW2 may be in an on state when the second terminal T2 and the third terminal T3 are being tested, and in an off state when the second terminal T2 and the third terminal T3 are not being tested. The third terminal T3 may be interpreted as a terminal connected to a third transistor (not shown) via the wiring W.

[0023] In FIG. 1, the first switch SW1 and the second switch SW2 are in an on state.

[0024] (Testing of Semiconductor Device 100-1) Next, a method for testing the semiconductor device 100-1 will be described with reference to Fig. 2. Fig. 2 is a diagram for explaining the method for testing the semiconductor device 100-1. As shown in Fig. 2, a test device 200 is connected to the semiconductor device 100-1. Specifically, a first terminal T1 of the semiconductor device 100-1 is connected to a terminal Tt of the test device 200.

[0025] When inspecting the states of the first terminal T1 and the second terminal T2, the test apparatus 200 measures the current flowing through the first terminal T1.

[0026] Specifically, when the test mode is set with the potential of the first terminal T1 set to the ground level (i.e., L level), the first switch SW1 is changed from OFF to ON, and the second switch SW2 is maintained in the OFF state.

[0027] By setting the potential of the first terminal T1 to the ground level, a current from the power supply VD flows to the first terminal T1 via the first switch SW1 in the on state. That is, a current C1 flows through the switch element P1 of the first transistor 1, and a current C2 flows through the switch element P2 of the second transistor 2. The test apparatus 200 measures a current C3 obtained by combining these currents, that is, the current flowing through the first terminal T1.

[0028] The test apparatus 200 holds in advance a standard value for testing that assumes that a current C3 flows when the first switch SW1 is in an ON state and the second switch SW2 is in an OFF state. The test apparatus 200 may compare the current C3 with the standard value for testing, and may determine that the first terminal T1 and the second terminal T2 are normally provided when the current C3 measured is within a certain range from the standard value for testing. "Normally provided" may be interpreted as a state in which the first transistor 1 and the second transistor 2 are not damaged by static electricity or the like, and may be interpreted as a state in which wiring, terminals, etc. connected to the first transistor 1 and the second transistor 2 are not damaged.

[0029] Specifically, the test apparatus 200 may determine that the first terminal T1 and the first wiring W1 are electrically connected to the first switch SW1, and the second terminal T2 and the second wiring W2 are normally electrically connected to the second switch SW2. More specifically, the test apparatus 200 may determine that the first terminal T1 and the second terminal T2, which are multiple terminals, and the first wiring W1 and the second wiring W2, which are wirings connected to these terminals, are normally mounted on the semiconductor device 100-1.

[0030] According to the semiconductor device 100-1 of the embodiment of the present disclosure, by measuring the current flowing through N output terminals, it is possible to determine whether the states of N+1 or more output terminals and the states of the wiring connected to the output terminals are normal or not. N may be interpreted as a natural number equal to or greater than 1.

[0031] On the other hand, if the measured current C3 exceeds a certain range from the standard value for testing, the test apparatus 200 may determine that the first terminal T1 and the second terminal T2 are not normally mounted on the semiconductor device 100-1.

[0032] According to the above test, it is possible to confirm that the second terminal T2 and the second wiring W2 are normally connected to the second switch SW2 without reconnecting the test device 200 from the first terminal T1 to the second terminal T2, so that a test of connecting the test device 200 to the second terminal T2 to check the second terminal T2 and the second wiring W2 can be omitted.

[0033] When checking the states of more output terminals at once, for example, with the first switch SW1 and the second switch SW2 in the on state, measurements can also be taken including the current flowing through a switching element (not shown) connected to the third terminal T3.

[0034] (Comparative Example) Fig. 3 is a diagram showing the configuration of a semiconductor device according to a comparative example. The semiconductor device 100A according to the comparative example does not include the first switch SW1 and the second switch SW2 shown in Fig. 1. Therefore, when checking the states of the first terminal T1 and the second terminal T2 using the semiconductor device 100A, it is necessary to connect the test device 200 to the first terminal T1, measure the current C1 flowing through the switch element P1 of the first transistor 1, and then reconnect the test device 200 to the second terminal T2 to measure the current C2 flowing through the switch element P2 of the second transistor 2.

[0035] As the number of terminals provided in the semiconductor device 100A increases, the number of times the test device 200 needs to be reconnected to other terminals also increases, so in the semiconductor device 100A of the comparative example, it may take a long time to complete testing of all of the terminals.

[0036] (Action and effect) The semiconductor device 100-1 of the present disclosure includes a switch provided between the first wiring and the second wiring, and the switch is turned on when testing the first terminal and the second terminal, and by connecting the test device 200 to one terminal, the states of two or more terminals and the wiring connected to the terminal can be confirmed. Therefore, the states of multiple terminals can be confirmed without switching the connection of the test device 200 from the first terminal to the second terminal. As a result, the work of switching the connection of the test device 200 from a specific terminal to another terminal can be reduced, and the time required to complete testing of all terminals can be significantly reduced.

[0037] [Second embodiment] FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device 100-2 according to the second embodiment is different from the semiconductor device 100-1 shown in FIG. 1 in that the semiconductor device 100-2 according to the second embodiment includes an input side circuit. Specifically, the semiconductor device 100-2 may include a first transistor 1A, a first transistor 1B, a second transistor 2A, and a second transistor 2B that configure the input side circuit. These transistors may be interpreted as protection circuits for static electricity countermeasures. The first transistor 1B and the second transistor 2B are normally in an off state, and the test device 200 can measure the leakage current flowing from the source to the drain in these transistors. Note that the number of transistors included in the semiconductor device 100-2 is not limited to two, and the semiconductor device 100-2 may include three or more transistors.

[0038] The first transistor 1A may be interpreted as a circuit including a first switch element P3 and a second switch element N3 connected in series. Specifically, the first transistor 1A may be interpreted as a circuit including a first switch element P3 on a first potential side, and a second switch element N3 on a second potential side lower than the first potential, connected in series to the first switch element P3. The first transistor 1A may output a signal obtained by amplifying an input signal by the first switch element P3 and the second switch element N3 operating in a complementary manner. The second transistor 2A is configured similarly to the first transistor 1A, and therefore a description thereof will be omitted.

[0039] The first transistor 1B may be interpreted as a circuit including a first switch element P1 and a second switch element N1 connected in series. Specifically, the first transistor 1B may be interpreted as a circuit including a first switch element P1 on a first potential side, and a second switch element N1 on a second potential side lower than the first potential, connected in series to the first switch element P1. The first transistor 1B may release a surge current that has entered the first terminal T1 by the first switch element P1 and the second switch element N1 operating in a complementary manner. The second transistor 2B is configured similarly to the first transistor 1B, and therefore a description thereof will be omitted.

[0040] The first switch elements P1 to P4 and the second switch elements N1 to N4 have their on / off operations controlled by a control circuit (not shown).

[0041] The semiconductor device 100-2 may include a first wiring W1 connected to the first transistor 1B and a first terminal T1 connected to the first transistor 1B via the first wiring W1. The first wiring W1 may be interpreted as a wiring connected to the first switch element P1 and the second switch element N1 of the first transistor 1B. The first wiring W1 may be interpreted as a wiring connected to the first switch element P3 and the second switch element N3 of the first transistor 1A. The first terminal T1 may be interpreted as an input terminal for connecting a lead (not shown) to the semiconductor device 100-2.

[0042] The semiconductor device 100-2 may include a second wiring W2 connected to the second transistor 2B, a second terminal T2 connected to the second transistor 2B via the second wiring W2, and a first switch SW1 and a second switch SW2 provided between the first wiring W1 and the second wiring W2. The second terminal T2 may be interpreted as an output terminal that connects a lead (not shown) to the semiconductor device 100-2. The second wiring W2 may be interpreted as a wiring that connects to the first switch element P2 and the second switch element N2 of the second transistor 2B. The second terminal T2 may be interpreted as a wiring that connects to the first switch element P4 and the second switch element N4 of the second transistor 2A. The second terminal T2 may be interpreted as an input terminal that connects a lead (not shown) to the semiconductor device 100-2.

[0043] The first switch SW1 and the second switch SW2 may be considered as switch elements whose on / off operations are controlled by a control circuit (not shown). The first switch SW1 may be in an on state when the first terminal T1 and the second terminal T2 are being tested, and in an off state when the first terminal T1 and the second terminal T2 are not being tested.

[0044] The second switch SW2 may be in an on state when the second terminal T2 and the third terminal T3 are being tested, and in an off state when the second terminal T2 and the third terminal T3 are not being tested. The third terminal T3 may be interpreted as a terminal connected to a third transistor (not shown) via a wiring W.

[0045] In FIG. 4, the first switch SW1 and the second switch SW2 are in an on state.

[0046] (Testing of Semiconductor Device 100-2) As shown in Fig. 4, the semiconductor device 100-2 may be tested in the same manner as the semiconductor device 100-1 according to the first embodiment. Specifically, first, the test device 200 shown in Fig. 2 is connected to the first terminal T1 of the semiconductor device 100-2. Next, in a state where the potential of the first terminal T1 is set to the ground level (i.e., L level), the first switch SW1 is set to an ON state and the second switch SW2 is set to an OFF state. In this state, the test device 200 measures a current C3 obtained by combining a leakage current C1 flowing through the switch element P1 of the first transistor 1B and a leakage current C2 flowing through the switch element P2 of the second transistor 2B.

[0047] The test apparatus 200 stores in advance a standard value for testing that assumes that a current C3 flows when the first switch SW1 is in an ON state and the second switch SW2 is in an OFF state. The test apparatus 200 may compare the standard value for testing with the current C3, and determine that the first terminal T1 and the second terminal T are normally provided when the measured current C3 is within a certain range from the standard value for testing.

[0048] Specifically, it may be determined that the first terminal T1 and the first wiring W1 are electrically connected to the first switch SW1, and the second terminal T2 and the second wiring W2 are normally electrically connected to the second switch SW2.

[0049] More specifically, the test apparatus 200 may determine that a first terminal T1 and a second terminal T2, which are multiple terminals, and a first wiring W1 and a second wiring W2, which are wirings connected to these terminals, are electrically connected to each other.

[0050] According to the semiconductor device 100-2 of the embodiment of the present disclosure, by connecting the test device 200 to M input terminals, it is possible to determine whether the states of M+1 or more output terminals and the states of the wiring connected to the output terminals are normal or not. N may be interpreted as a natural number equal to or greater than 1.

[0051] According to the semiconductor device 100-2, it is possible to confirm that the second terminal T2 and the second wiring W2 are normally connected to the second switch SW2 without reconnecting the test device 200 from the first terminal T1 to the second terminal T2, so that a test of connecting the test device 200 to the second terminal T2 to check the second terminal T2 and the second wiring W2 can be omitted.

[0052] When checking the states of more input terminals at once, for example, with the first switch SW1 and the second switch SW2 in the on state, measurements can also be taken including the current flowing through a switching element (not shown) connected to the third terminal T3.

[0053] [Third embodiment] Fig. 5 is a diagram showing a configuration of a test device according to a third embodiment of the present disclosure. The test device 200 may include a switch SW similar to the switch included in the semiconductor device 100-1 of the first embodiment and the semiconductor device 100-2 of the second embodiment. Although Fig. 5 illustrates the semiconductor device 100-1 of the first embodiment, the semiconductor device 100A shown in Fig. 3 may be used instead of the semiconductor device 100-1.

[0054] The test apparatus 200 may include a third wiring W3 connected to the first terminal T1 and provided inside the test apparatus 200, a fourth wiring W4 connected to the second terminal T2 and provided inside the test apparatus 200, and a switch SW provided between the third wiring W3 and the fourth wiring. When the first terminal T1 and the second terminal T2 are being tested, the switch SW is in an on state, and when the first terminal T1 and the second terminal T2 are not being tested, the switch SW is in an off state.

[0055] When checking the states of the first terminal T1 and the second terminal T2 using the test device 200 shown in Fig. 5, the test device 200 is connected to the first terminal T1 and the second terminal T2 as shown in Fig. 5, and then the test mode is set with the potentials of the first terminal T1 and the second terminal T2 set to the ground level (i.e., L level). This changes the switch SW from the OFF state to the ON state.

[0056] By setting the potential of each terminal to the ground level, a current from the power supply VD flows to the first terminal T1 and the second terminal T2 via the first switch SW1 and the second switch SW2 in the on state. That is, a current C1 flows through the switch element P1 of the first transistor 1, and a current C2 flows through the switch element P2 of the second transistor 2. The test apparatus 200 can measure a current C3 obtained by combining these currents, that is, the currents flowing through multiple terminals in a single test.

[0057] As described above, the test apparatus 200 stores in advance a test standard value that assumes that a current C3 will flow. Therefore, by comparing the test standard value with the current C3, if the measured current C3 is within a certain range of the test standard value, it may be determined that the first terminal T1 and the second terminal T2 are installed normally.

[0058] According to the test apparatus 200 of the third embodiment, it is possible to omit the step of switching the connection of the test apparatus 200 from the first terminal T1 to the second terminal T2, and therefore the time required to complete testing of all terminals can be significantly shortened.

[0059] [Fourth embodiment] 6 is a diagram showing a configuration of a multi-chip package according to a fourth embodiment of the present disclosure. A multi-chip package 300 according to a fourth modified example may include a plurality of semiconductor devices 100-1. The multi-chip package 300 may be interpreted as a device including a plurality of LSIs. The multi-chip package 300 may include a plurality of semiconductor devices 100-2 instead of the semiconductor device 100-1.

[0060] The first semiconductor device of the multi-chip package 300 may include a first transistor, a first wiring connected to the first transistor, and a first terminal connected to the first transistor via the first wiring.

[0061] The first semiconductor device may be interpreted as the upper semiconductor device 100-1 of the two semiconductor devices 100-1 shown in Fig. 6. The first transistor may be interpreted as the first transistor 1 included in the upper semiconductor device 100-1. The first wiring may be interpreted as the first wiring W1 included in the upper semiconductor device 100-1. The first terminal may be interpreted as the first terminal T1 included in the upper semiconductor device 100-1.

[0062] The second semiconductor device of the multi-chip package 300 may include a second transistor, a second wiring connected to the second transistor, and a second terminal connected to the second transistor via the second wiring. The second semiconductor device may be interpreted as the lower semiconductor device 100-1 of the two semiconductor devices 100-1 shown in FIG.

[0063] The second transistor may be interpreted as the first transistor 1 included in the lower semiconductor device 100-1. The second wiring may be interpreted as the wiring WC included in the lower semiconductor device 100-1. The second terminal may be interpreted as the terminal Tb included in the lower semiconductor device 100-1.

[0064] 6, the upper semiconductor device 100-1 may include a switch SW. One end of the switch SW is connected to the first switch SW1 and the second wiring W2. The other end of the switch SW is connected to the terminal Ta via the wiring Wa.

[0065] The terminal Ta may be interpreted as an internal terminal of the multi-chip package. The terminal Ta is connected to a terminal Tb of the lower semiconductor device 100-1 via a wiring Wb.

[0066] The terminal Tb may be interpreted as an internal terminal of the multi-chip package. The terminal Tb is connected to the first transistor 1 via the wiring Wc in the lower semiconductor device 100-1.

[0067] In this manner, the switch SW is provided between the first wiring W1 and the second transistor (the first transistor 1 included in the lower semiconductor device 100-1). The switch SW is in an on state when the first terminal T1 and the second terminal (terminal tb) are being tested, and is in an off state when the first terminal T1 and the second terminal (terminal tb) are not being tested.

[0068] The first terminal T1 is connected to a first external terminal To1 of the multi-chip package 300. The second terminal T2 is connected to a second external terminal To2 of the multi-chip package 300. The terminal Tb is connected to the first external terminal To1 via the terminal Ta, the switch SW, the first switch SW1, the first wiring W1, and the first terminal T1. The terminal Tb is connected to the second external terminal To2 via the terminal Ta, the switch SW, the second wiring W2, and the second terminal T2.

[0069] When checking the states of the first terminal T1 and the second terminal (terminal Tb) of the multi-chip package 300, after connecting the test device 200 to the first external terminal To1, the test mode is set with the potentials of the first terminal T1 and the second terminal (terminal Tb) set to the ground level (i.e., L level), thereby changing the switch SW from the OFF state to the ON state.

[0070] By setting the potential of each terminal to the ground level, a current C1 flows through the switch element P1 of the upper first transistor 1, and a current C2 flows through the switch element P1 of the lower first transistor 1. The test apparatus 200 can measure a current C3 obtained by combining these currents, that is, the currents flowing through multiple terminals in a single test.

[0071] As described above, the test apparatus 200 stores in advance a test standard value that assumes that a current C3 will flow. Therefore, by comparing the test standard value with the current C3, if the measured current C3 is within a certain range of the test standard value, it may be determined that the first terminal T1 and the second terminal (terminal Tb) are installed normally.

[0072] According to the test apparatus 200 of the third embodiment, it is possible to omit the step of switching the connection of the test apparatus 200 from the first external terminal To1 to the second external terminal To2, and therefore the time required to complete testing of all terminals can be significantly shortened.

[0073] In the above embodiment, the state of the terminal is inspected by measuring the current, but it is also possible to inspect the state of the terminal by measuring the voltage instead of the current.

[0074] In addition, the following supplementary notes are provided in relation to the above description.

[0075] Appendix 1: A semiconductor device comprising: A first transistor; a first wiring connected to the first transistor; a first terminal connected to the first transistor via the first wiring; A second transistor; a second wiring connected to the second transistor; a second terminal connected to the second transistor via the second wiring; a switch provided between the first wiring and the second wiring; Equipped with When testing the first terminal and the second terminal, the switch is in an on state, The semiconductor device, wherein the switch is in an off state when the first terminal and the second terminal are not being tested. Appendix 2: the first terminal is a first input terminal connected to the first transistor constituting an input side circuit of the semiconductor device, 2. The semiconductor device according to claim 1, wherein the second terminal is a second input terminal connected to the second transistor that constitutes an input side circuit of the semiconductor device. Appendix 3: the first terminal is a first output terminal connected to the first transistor constituting an output side circuit of the semiconductor device, 3. The semiconductor device according to claim 1, wherein the second terminal is a second output terminal connected to the second transistor that constitutes an output side circuit of the semiconductor device. Note 4: A test apparatus for a semiconductor device, comprising: The semiconductor device includes: A first transistor; a first wiring connected to the first transistor; a first terminal connected to the first transistor via the first wiring; A second transistor; a second wiring connected to the second transistor; a second terminal connected to the second transistor via the second wiring; Equipped with The test device comprises: a third wiring connected to the first terminal and provided inside the test device; a fourth wiring connected to the second terminal and provided inside the test device; a switch provided between the third wiring and the fourth wiring, When testing the first terminal and the second terminal, the switch is in an on state, The test device for a semiconductor device, wherein the switch is in an off state when the first terminal and the second terminal are not being tested. Note 5: A multi-chip package having at least a first semiconductor device and a second semiconductor device, The first semiconductor device includes: A first transistor; a first wiring connected to the first transistor; a first terminal connected to the first transistor via the first wiring; Equipped with The second semiconductor device includes: A second transistor; a second wiring connected to the second transistor; a second terminal connected to the second transistor via the second wiring; Equipped with The switch provided between the first wiring and the second transistor is The first terminal and the second terminal are in an on state during testing, The multi-chip package is in an off state when the first terminal and the second terminal are not being tested. [Explanation of symbols]

[0076] 1 First transistor 1A 1st transistor 1B First transistor 2 Second transistor 2A Second Transistor 2B Second transistor 100-1 Semiconductor device 100-2 Semiconductor device 100A Semiconductor Device 200 Test Equipment 300 Multi-chip Package

Claims

1. A semiconductor device comprising: A first transistor; a first wiring connected to the first transistor; a first terminal connected to the first transistor via the first wiring; A second transistor; a second wiring connected to the second transistor; a second terminal connected to the second transistor via the second wiring; a switch provided between the first wiring and the second wiring; Equipped with When testing the first terminal and the second terminal, the switch is in an on state, When the first terminal and the second terminal are not being tested, the switch is in an off state.

2. the first terminal is a first input terminal connected to the first transistor constituting an input side circuit of the semiconductor device, 2. The semiconductor device according to claim 1, wherein the second terminal is a second input terminal connected to the second transistor that constitutes an input side circuit of the semiconductor device.

3. the first terminal is a first output terminal connected to the first transistor constituting an output side circuit of the semiconductor device, 2. The semiconductor device according to claim 1, wherein said second terminal is a second output terminal connected to said second transistor constituting an output side circuit of said semiconductor device.

4. A test apparatus for a semiconductor device, comprising: The semiconductor device includes: A first transistor; a first wiring connected to the first transistor; a first terminal connected to the first transistor via the first wiring; A second transistor; a second wiring connected to the second transistor; a second terminal connected to the second transistor via the second wiring; Equipped with The test device comprises: a third wiring connected to the first terminal and provided inside the test device; a fourth wiring connected to the second terminal and provided inside the test device; a switch provided between the third wiring and the fourth wiring, When testing the first terminal and the second terminal, the switch is in an on state, The test device for a semiconductor device, wherein the switch is in an off state when the first terminal and the second terminal are not being tested.

5. A multi-chip package having at least a first semiconductor device and a second semiconductor device, The first semiconductor device includes: A first transistor; a first wiring connected to the first transistor; a first terminal connected to the first transistor via the first wiring; Equipped with The second semiconductor device includes: A second transistor; a second wiring connected to the second transistor; a second terminal connected to the second transistor via the second wiring; Equipped with The switch provided between the first wiring and the second transistor is The first terminal and the second terminal are in an on state during testing, The multi-chip package is in an off state when the first terminal and the second terminal are not being tested.

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