Semiconductor device

Abstract

To manufacture a semiconductor device having a transistor using an oxide semiconductor with high reliability, capable of solving the problem that the reliability of a transistor using an oxide semiconductor is deteriorated as compared with a transistor using amorphous silicon.SOLUTION: An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a sputtering target and a method for producing the same. An oxide semiconductor film formed by sputtering using a sputtering target, and the oxide semiconductor The present invention relates to a semiconductor device using a conductor film.

[0002] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor thin film materials that can be used in transistors are Silicon-based semiconductor materials are widely known as semiconductor materials, but oxide semiconductors are also attracting attention as other materials. It has been done.

[0004] For example, a semiconductor with an electron carrier concentration of 10 18 / cm 3 is less than A transistor using an oxide semiconductor containing In, Ga, and Zn is disclosed. The sputtering method is considered to be the most suitable method for forming a compound semiconductor film (see Patent Document 1). .). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] Transistors using oxide semiconductors have the following characteristics compared to transistors using amorphous silicon: Therefore, the present invention provides a transistor using an oxide semiconductor having high reliability. The object is to manufacture a semiconductor device having a transistor.

[0007] The present invention also provides a method for forming an oxide semiconductor that can provide a highly reliable transistor. The purpose is to [Means for solving the problem]

[0008] A sputtered film made of an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface An oxide semiconductor film is formed by a sputtering method using a ring target.

[0009] In this way, the crystal state of the sputtering target is transferred to the substrate, and the c-axis is aligned on the top surface. In this way, it becomes easy to obtain an oxide semiconductor film having a crystal region in which the crystal vector is parallel to the normal vector of the crystal.

[0010] A sputtered film made of an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface The raw materials for the ring target are mixed so that the composition ratio is the same as when it becomes a single crystal. and prepare it.

[0011] When ions collide with the surface of the sputtering target, The crystalline regions in the ab plane are cleaved from the ab plane and have a shape along the layer parallel to the ab plane (flat or Sputtering particles (in the form of a powder or pellets) peel off from the sputtering target. The plate-shaped sputtered particles reach the substrate surface while maintaining their crystalline state, This makes it easier to obtain an oxide semiconductor film having a crystalline region whose axis is parallel to a normal vector of the top surface.

[0012] When an In-Ga-Zn-O compound is used as a sputtering target, The outermost surface layer of a flat sputtered particle often contains Ga and Zn.

[0013] The higher the density of the sputtering target, the more preferable it is. The high density of the sputtering layer also increases the density of the film that is formed. - The relative density of the target is 90% or more, preferably 95% or more, and more preferably 99% or more. The relative density of the sputtering target is defined as the The density of the target and the density of a material of the same composition as the sputtering target in a pore-free state. It refers to the ratio of

[0014] In addition, if the following conditions are applied, the crystal whose c-axis is parallel to the normal vector of the top surface will be This is preferable because an oxide semiconductor film having a region can be easily obtained.

[0015] First, the surface temperature of the sputtering target must be sufficiently low. Preferably around room temperature. To be.

[0016] For sputtering equipment that can handle large-area substrates, a large-area sputtering target is used. However, there are many sputtering targets that are large enough to handle large areas. It is difficult to fabricate a seamless target. Although they are arranged as small as possible to minimize gaps, there are still some small gaps. These tiny gaps can cause the surface temperature of the sputtering target to rise. As the Zn and other substances evaporate, the gaps may gradually widen. The materials of the bonding plate and the adhesive may be sputtered, resulting in impurities. Therefore, the sputtering target must be cooled sufficiently. It is preferable that

[0017] Next, the influx of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) from the deposition chamber was reduced. and.

[0018] Next, impurities in the gas used during film formation must be reduced.

[0019] By reducing the impurities contained during film formation, the crystal state is prevented from being destroyed by impurities. Therefore, it is easy to obtain an oxide semiconductor film having a crystalline region in which the c-axis is parallel to the normal vector of the upper surface. It becomes.

[0020] Next, the flatness of the underlying film must be improved.

[0021] If the upper surface of the base film has minute irregularities, this can hinder crystal growth. Therefore, if the underlying film is flat, it will have crystalline regions whose c-axes are parallel to the normal vector of the top surface. In this way, an oxide semiconductor film having a high conductivity can be easily obtained.

[0022] Next, the substrate heating temperature is increased during film formation.

[0023] By increasing the substrate heating temperature, migration of sputtered particles occurs on the substrate surface. Due to this action, the sputtering particles are flat and slightly disintegrate after reaching the substrate surface. The c-axis is aligned with the normal to the top surface. This makes it easier to obtain an oxide semiconductor film having crystal regions parallel to the line vector.

[0024] Next, the oxygen ratio in the gas used during film formation is increased.

[0025] Next, the power for film formation is optimized.

[0026] By increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. Therefore, it is possible to form a crystal domain in which the c-axis is parallel to the normal vector of the top surface. An oxide semiconductor film is easily obtained.

[0027] Such an oxide semiconductor film having a crystal region in which the c-axis is parallel to the normal vector of the top surface is By using this, a highly reliable transistor can be obtained.

[0028] This is because an oxide semiconductor film having a crystal region in which the c-axis is parallel to the normal vector of the upper surface is used. As a result, defects in the oxide semiconductor film and at the interface between the oxide semiconductor film and an insulating film in contact with the oxide semiconductor film can be reduced. This is because the defect levels and impurity levels are reduced, and the reliability of the transistor can be improved. be.

[0029] In addition, it is preferable to perform heat treatment after the film formation to reduce the impurity concentration in the oxide semiconductor film. Heat treatment is highly effective in reducing impurity concentrations when carried out in an inert atmosphere or reduced pressure atmosphere. In addition, after heat treatment in an inert atmosphere or reduced pressure atmosphere, heat treatment in an oxidizing atmosphere may be performed. This is preferably achieved by a heat treatment carried out in an inert atmosphere or a reduced pressure atmosphere. As the impurity concentration in the oxide semiconductor film decreases, oxygen vacancies occur in the oxide semiconductor film. By performing heat treatment in an oxidizing atmosphere, the oxide semiconductor film This can reduce oxygen vacancies in the glass.

[0030] As an example of an oxide semiconductor film having a crystalline region in which the c-axis is parallel to the normal vector of the top surface, CAAC-OS (C Axis Aligned Crystallinity) of oxide semiconductors Alternatively, a thin film of eOxide Semiconductor may be used.

[0031] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor having a crystalline-amorphous mixed phase structure in which the amorphous phase has crystalline and amorphous regions. The crystal region is a size that fits within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) The observation image by a tron ​​microscope shows that the amorphous The boundary between the crystalline and amorphous regions is not clear. The grain boundaries cannot be confirmed. In this case, the decrease in electron mobility caused by grain boundaries is suppressed.

[0032] The c-axis of the crystalline region in the CAAC-OS film is the normal vector of the CAAC-OS surface. The triangle is aligned parallel to the normal vector of the top surface or the top of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Note that the a-axis is aligned between different crystal regions. The direction of the a and b axes may be different. In this specification, when it is simply described as being vertical, The range of 85° to 95° is also included. The range of 5° or more and 5° or less is also included.

[0033] In the CAAC-OS film, the distribution of the crystalline regions may not be uniform. In the process of forming the AC-OS film, when crystal growth is performed from the top surface side of the oxide semiconductor film, The proportion of crystalline regions may be higher near the top surface than near the formation surface. By adding impurities to the CAAC-OS film, a crystalline region is formed in the region where the impurities are added. may become amorphous.

[0034] The c-axis of the crystalline region in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film (the shape of the film) is Depending on the cross-sectional shape of the mating surface or the cross-sectional shape of the surface, they may face in different directions. The c-axis direction of the crystalline region is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the vector normal to the top surface. Alternatively, the insulating film is formed by performing a crystallization treatment such as a heat treatment after the film formation.

[0035] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0036] An example of a crystal structure contained in the CAAC-OS film will be described in detail with reference to FIGS. 22 to 25. In addition, unless otherwise specified, the upward direction in FIG. 22 to FIG. 25 is the c-axis direction, and The plane perpendicular to the direction is the ab plane. When simply referring to the upper half and lower half, the ab plane is used as the boundary. In addition, in Figure 22, the circled O represents a 4-coordinate O. The double circled O indicates a three-coordinate O.

[0037] In Figure 22(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 22(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group with four coordinates. The small group shown in Figure 22(A) has a zero charge.

[0038] In Figure 22(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom are shown. The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. There are four of them, one each in the upper and lower halves of Figure 22(B). In addition, since In also has a 5-coordination, the structure shown in Figure 22(B) can be formed. The small group shown in FIG. 22(B) has a charge of 0.

[0039] FIG. 22(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 22(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 22(C) has a charge of 0.

[0040] FIG. 22(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 22(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 22(D) has a charge of +1.

[0041] Figure 22(E) shows a small group containing two Zn atoms. The upper half of Figure 22(E) shows one Zn atom. The small group shown in Figure 22(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0042] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0043] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the 6-coordinate In have three adjacent In atoms downward, and the lower half The three O atoms each have three adjacent In atoms in the upward direction. Each O in the upper half of a has one adjacent Ga in the downward direction, and each O in the lower half has one adjacent Ga in the upward direction. In FIG. 22(C), one O atom in the upper half of the 4-coordinate Zn atom faces downward. It has one adjacent Zn, and the three Os in the lower half have three adjacent Zns each in the upward direction. In this way, the number of tetracoordinated O atoms above a metal atom and the number of adjacent metal atoms below that O The number of O atoms in the four-coordinated group below the metal atom is equal to the number of neighboring O atoms above the O atom. The number of metal atoms is equal. Since O is 4-coordinated, the number of adjacent metal atoms below is equal to the number of adjacent metal atoms above. The sum of the number of neighboring metal atoms is 4. Therefore, the number of 4-coordinated O atoms above the metal atom is When the sum of the number of O atoms and the number of O atoms with 4 coordinates below another metal atom is 4, it has a metal atom. Two small groups can be bonded together. For example, a six-coordinate metal atom (In or When Sn) is bonded through the lower half of the tetracoordinate O, there are three tetracoordinate Os, so 5 It bonds to either a 4-coordinate metal atom (Ga or In) or a 4-coordinate metal atom (Zn). This will be the case.

[0044] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0045] Figure 23(A) shows a model of the middle group that constitutes the layer structure of the In-Sn-Zn-O compound. FIG. 23(B) shows a large group consisting of three medium groups. FIG. 3(C) shows the atomic arrangement of the layer structure of FIG. 23(B) when viewed from the c-axis direction.

[0046] In FIG. 23(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 23(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 23 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0047] In FIG. 23(A), the middle group constituting the layer structure of the In-Sn-Zn-O compound is From the top, Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and Sn has one tetracoordinate O atom in each half. The In is bonded to the In in the upper half and the lower half, and the In is bonded to the In in the upper half. It bonds to the Zn atom, and three tetracoordinate O atoms are bonded to the upper half of the Zn atom via one tetracoordinate O atom in the lower half of the Zn atom. The In is bonded to the In in the upper half and lower half of the Z atom, which has one tetracoordinate O in the upper half. It bonds to a small group of n2 atoms, and through one tetracoordinate O in the lower half of this small group. The structure is such that three tetracoordinate O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0048] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, the layer structure containing Sn is formed. To do this, we need a charge of -1 to cancel out the charge of +1. The structure that can take the charge of -1 is as follows: As shown in FIG. 22(E), a small group containing two Zn atoms is shown. For example, Sn is If there is one small group containing 2 Zn atoms for every small group containing 1 Zn atom, the charges will cancel out. Therefore, the total charge of the layer structure can be made zero.

[0049] Specifically, the large group shown in FIG. 23(B) is repeated to form In-Sn-Zn In-O compound crystals (In2SnZn3O8) can be obtained. The layered structure of the crystal of the Sn-Zn-O compound is In2SnZnO6(ZnO). m (m is 0 or is a natural number.)

[0050] In addition, there are other compounds such as In-Sn-Ga-Zn-O and In-Ga-Zn-O. compound, In-Al-Zn-O compound, Sn-Ga-Zn-O compound, Al-Ga-Zn-O Compounds, Sn-Al-Zn-O compounds, In-Hf-Zn-O compounds, In-La-Z nO compound, In-Ce-Zn-O compound, In-Pr-Zn-O compound, In-Nd -Zn-O compound, In-Sm-Zn-O compound, In-Eu-Zn-O compound, In- Gd-Zn-O compound, In-Tb-Zn-O compound, In-Dy-Zn-O compound, I n-Ho-Zn-O compounds, In-Er-Zn-O compounds, In-Tm-Zn-O compounds , In-Yb-Zn-O compounds, In-Lu-Zn-O compounds, and In-Zn-O compounds , Sn-Zn-O compound, Al-Zn-O compound, Zn-Mg-O compound, Sn-Mg- The same is true for materials such as In-O compounds, In-Mg-O compounds, and In-Ga-O compounds. It seems that.

[0051] For example, in Figure 24(A), the middle group of the In-Ga-Zn-O compound layer structure is A model diagram is shown.

[0052] In FIG. 24(A), the middle group constituting the layer structure of the In-Ga-Zn-O compound is From the top, In has three tetracoordinate O atoms in the upper half and three in the lower half, and In has one tetracoordinate O atom on top. It bonds to the Zn in the lower half of the Zn, and the tetracoordinate O is bonded to the Zn via the three tetracoordinate O in the lower half of the Zn. One is bonded to Ga in the upper half and the other to Ga in the lower half. The structure is such that three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the These medium groups are then combined to form large groups.

[0053] Figure 24(B) shows a large group consisting of three medium groups. 24(B) shows the atomic arrangement when the layer structure of FIG. 24(B) is observed from the c-axis direction.

[0054] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0055] The middle group, which constitutes the layer structure of the In-Ga-Zn-O compound, is shown in FIG. The combination of middle groups with different arrangements of In, Ga, and Zn is not limited to the same middle group. Large groups are also possible.

[0056] Specifically, the large group shown in FIG. 24(B) is repeated to form an In-Ga-Zn In addition, the resulting In-Ga-Zn-O compound layer can be The structure is InGaO3(ZnO) n (n is a natural number.)

[0057] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in FIG. 25(A) can be obtained. In the crystal structure shown in FIG. 25(A), as explained in FIG. 22(B), Ga and Since Ga and In have five-coordination, it is also possible to have a structure in which Ga is replaced by In.

[0058] In the case of n=2 (InGaZn2O5), for example, the crystal structure shown in FIG. 25(B) In the crystal structure shown in FIG. 25(B), as explained in FIG. Since Ga and In have five-coordinate groups, it is also possible for Ga to be replaced by In.

[0059] The sputtering target preferably contains In, Ga and Zn.

[0060] The sputtering target is prepared, for example, by the following method. X raw material, G aO Y Raw materials and ZnO Z The raw materials are mixed in a specified ratio, the mixture is fired, and then powdered. The In-Ga-Zn-O compound powder is then crushed to produce In-Ga-Zn-O compound powder, which is then spread in a mold and molded. After the compound film is formed, it is pressed and baked. The compound powder is spread again, molded, sintered, and then pressure treated to form a compound film. By carrying out the compound film thickening process n times (n is a natural number), the compound film will become thicker than 2 mm. A plate-shaped compound with a thickness of 20 mm or less was prepared, and the plate-shaped compound was attached to a backing plate. The sputtering target is prepared by bonding the two layers together. Note that X, Y, and Z are arbitrary. It is a positive number.

[0061] The backing plate is a plate-shaped component on which the sputtering target is placed. It has high electrical conductivity and A metal material having high heat dissipation properties is used. Specifically, Cu is preferable. However, However, even if Cu is used for the backing plate, the cooling capacity may not be sufficient. Otherwise, the top surface of the sputtering target will become extremely hot during sputtering. In order to provide sufficient strength and sufficient cooling capacity, water is placed inside the backing plate. The sputtering target can be efficiently cooled by the cooling water passing through the water channel. In addition, it is preferable that the adhesion between the backing plate and the sputtering target is good. It is also important to increase the thermal conductivity and the melting point of the material sufficiently to increase the cooling capacity. Some metals (such as In) form a barrier between the backing plate and the sputtering target. It is important to bond the parts without any gaps.

[0062] In this specification, the sputtering target refers to the material itself to be sputtered. However, for simplicity, the term refers to a backing plate and a spa installed on the backing plate. The material to be sputtered may also be referred to as a sputtering target.

[0063] InO X Raw material, GaO Y Raw materials and ZnO Z The raw materials are mixed in a specified ratio and the mixed material When the mixture is sintered, polycrystalline In-Ga-Zn-O compound is obtained. is an arbitrary positive number. The polycrystal contains many layered crystal structures when viewed in a direction perpendicular to the c-axis. Therefore, the compound powder obtained by pulverization contains many flat crystal grains. When flat crystal grains are laid out in a mold and vibration is applied from the outside during molding, the flat surface is pressed up. The crystal grains are then aligned toward the center of the crystal grains. The resulting compound powder is then spread out and molded, then sintered and By applying pressure to the crystal, a layered crystal structure is formed when viewed perpendicular to the c-axis. The ratio of overlapping layers in the direction perpendicular to the direction of the magnet increases. The treatment may be repeated, so that the layered structure gradually appears when viewed perpendicular to the c-axis. The proportion of the crystalline structure can be increased.

[0064] The following shows that the In-Ga-Zn-O compound has a layered crystal structure when viewed perpendicular to the c-axis. Explain that it includes.

[0065] In the equilibrium shape of a crystal, the area of ​​the face with the lowest surface energy is larger. Also, the cleavage of a crystal is Similarly, this is likely to occur on surfaces with low surface energy. The calculation results are shown below.

[0066] Here, the surface energy is calculated by subtracting the energy of the crystal structure from the energy of the surface structure. The value is divided by the surface area.

[0067] The calculation was performed using the first-principles calculation software CASTEP based on density functional theory, and the pseudopotential The ion beam was ultrasoft and the cutoff energy was 400 eV.

[0068] The crystal structure and surface structure used in the calculation are shown in Fig. 40 to Fig. 43. In the surface structure shown in Fig. 1, the voids represent vacuum. The surface is the surface. Surfaces exist above and below, but for simplicity, the lower space is omitted in the illustration. vinegar.

[0069] The surface energy of the surface structure (1) shown in FIG. 40 is the (001) surface of In and O. The average surface energy of the (001) surface of Ga and O is The surface energy of the surface structure (2) is the same as that of the (001) surface consisting of Ga and O. The average surface energy of the (001) plane consisting of Zn and O. The surface energy of the surface structure (3) is the same as that of the (001) surface consisting of Zn and O. The average surface energy of the (001) surface consisting of In and O. The surface energies of the obtained surface structures (1), (2) and (3) are By simultaneously calculating the surface energy of the (001) surface consisting of In and O, G The surface energy of the (001) surface consisting of Zn and O, and the surface energy of the (0 The surface energy of the ab plane is calculated as (00 1) face. Other faces (such as (100) face and (10-1) face) Similar statements may also be made about.

[0070] The surface structure (4) shown in FIG. 41 is a (001) surface with a mixture of Ga and Zn. It has a similar surface.

[0071] The structures shown in FIG. 42 and FIG. 43 are (100) and (10-1) planes, respectively. In addition, the (100) and (10-1) faces have multiple types of surface energy. Since all elements are present on the top surfaces of the (00) and (10-1) planes, we will focus on the two most representative The average surface energy of the side of each surface was taken as the surface energy of each surface. For the sake of simplicity, we have prepared different surfaces for the surface structure (7) and (1 These are written as (0-1) surface_a and (10-1) surface_b.

[0072] The surface energy of surface structure (1) is 1.54 J / m 2 It was.

[0073] The surface energy of surface structure (2) is 1.24 J / m 2 It was.

[0074] The surface energy of surface structure (3) is 1.57 J / m 2 It was.

[0075] Simultaneous calculation of the surface energies of surface structure (1), surface structure (2), and surface structure (3) Then, the surface energy of the (001) surface consisting of In and O is 1.88 J / m 2 Yes Ta.

[0076] Simultaneous calculation of the surface energies of surface structure (1), surface structure (2), and surface structure (3) Then, the surface energy of the (001) surface consisting of Ga and O is 1.21 J / m 2 Yes Ta.

[0077] Simultaneous calculation of the surface energies of surface structure (1), surface structure (2), and surface structure (3) Then, the surface energy of the (001) surface consisting of Zn and O is 1.26 J / m 2 Yes Ta.

[0078] The surface energy of surface structure (4) is 0.35 J / m 2 It was.

[0079] The surface energy of surface structure (5) is 1.64 J / m 2 It was.

[0080] The surface energy of surface structure (6) is 1.72 J / m 2 It was.

[0081] The surface energy of surface structure (7) is 1.79 J / m 2 It was.

[0082] From the above calculation results, it was found that the surface energy of surface structure (4) is the smallest. In other words, it was found that the surface energy of the surface structure perpendicular to the c-axis is the smallest. .

[0083] Therefore, the crystal of the In-Ga-Zn-O compound has a surface structure perpendicular to the c-axis. It can be seen that the percentage of those who are

[0084] Here, the predetermined ratio is InO X Raw material, GaO Y Raw materials and ZnO Z The ingredients are 2:2:1 , 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 molar ratio. do.

[0085] The raw materials and their mixing ratios may be changed depending on the sputtering target to be produced. Just change it.

[0086] Before bonding the plate-shaped compound to the backing plate, the plate-shaped compound was heated at 1000℃. The heat treatment may be performed at a temperature of 1500° C. or higher.

[0087] An oxide semiconductor film was formed using the sputtering target prepared as described above. By doing so, a highly reliable transistor can be obtained. Effect of the Invention

[0088] A sputtered film made of an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface Targets for rings can be provided.

[0089] By using the sputtering target mentioned above, the c-axis is parallel to the normal vector of the upper surface. An oxide semiconductor film having a crystal region can be formed, and the oxide semiconductor film can be used to form a A highly reliable transistor can be obtained. [Brief description of the drawings]

[0090] [Figure 1] FIG. 2 is a flow diagram showing an example of a method for producing a sputtering target. [Diagram 2] 1A to 1C are diagrams showing an example of a method for manufacturing a sputtering target. [Diagram 3] 1A to 1C are diagrams showing an example of a method for manufacturing a sputtering target. [Figure 4] 1A to 1C are diagrams showing an example of a method for manufacturing a sputtering target. [Diagram 5]EBSD image of sample A. [Figure 6] FIG. 2 shows an XRD spectrum of sample A. [Figure 7] FIG. 2 is a top view showing an example of a film forming apparatus. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. 2 is a diagram showing an example of a heat treatment chamber. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 17] FIG. 1 is a circuit diagram illustrating an example of a display device. [Figure 18] 1A to 1C are a cross-sectional view, a circuit diagram, and a diagram showing electrical characteristics of an example of a semiconductor device. [Figure 19] 1A to 1C are a cross-sectional view, a circuit diagram, and a diagram showing electrical characteristics of an example of a semiconductor device. [Figure 20] 1A and 1B are a block diagram and a partial circuit diagram illustrating a specific example of a CPU including a transistor according to one embodiment of the present invention. [Figure 21] 1 is a perspective view illustrating an example of an electronic device according to one embodiment of the present invention. [Figure 22] 1A to 1C are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Diagram 23] 1A to 1C are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Diagram 25] 1A to 1C are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 26] 1A to 1C are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 27] FIG. 13 is a graph for explaining the Vgs dependence of the field-effect mobility obtained by calculation. [Figure 28] FIG. 13 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Figure 29] FIG. 13 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Diagram 30] FIG. 13 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Diagram 31] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Diagram 32] 13 shows Vgs-Ids characteristics and field-effect mobility of the transistors of Sample 1 and Sample 2. [Diagram 33] FIG. 13 shows Vgs-Ids characteristics of a transistor as Sample 1 before and after a BT test. [Diagram 34] FIG. 13 shows Vgs-Ids characteristics of a transistor of Sample 2 before and after a BT test. [Diagram 35] 13 shows the relationship between the threshold voltage and the field-effect mobility of the transistor in Sample 2 and the substrate heating temperature. [Diagram 36] 13A to 13C show off-state current of a transistor including an oxide semiconductor film. [Figure 37] FIG. 13 shows XRD spectra of Samples 4 to 6. [Figure 38] FIG. 13 shows XRD spectra of Samples 7 to 10. [Figure 39] FIG. 1 shows XRD spectra of Samples 11 to 16. [Diagram 40] 1A to 1C are diagrams illustrating a crystal structure and a surface structure. [Diagram 41] 1A to 1C are diagrams illustrating a crystal structure and a surface structure. [Diagram 42] 1A to 1C are diagrams illustrating a crystal structure and a surface structure. [Diagram 43] 1A to 1C are diagrams illustrating a crystal structure and a surface structure. [Diagram 44] A diagram showing the crystal structure before and after calculation. [Diagram 45] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0091] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and it is understood by those skilled in the art that various modifications can be made to the form and details of the present invention. It will be easily understood. In addition, the present invention is not limited to the description of the embodiment shown below. In explaining the configuration of the invention using the drawings, the same symbols are used The numbers are used commonly across different drawings. When referring to similar objects, the hatch pattern is used instead. Similarly, there are cases where no particular reference numeral is given.

[0092] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the present specification does not refer to a specific name as a matter for identifying the invention. This does not indicate a title.

[0093] (Embodiment 1) In this embodiment, an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface is A method for producing a sputtering target made of a body is described.

[0094] First, referring to FIG. 1 to FIG. 4, a crystal region having a c-axis parallel to the normal vector of the upper surface is shown. This paper describes a method for manufacturing a sputtering target made of an oxide semiconductor.

[0095] First, the raw materials are weighed (step S101).

[0096] Here, InO is used as the raw material for the sputtering target.X Raw material, GaO Y Raw materials and and ZnO Z Prepare the raw materials. X, Y, and Z are any positive numbers. For example, X is 1. 5, Y is 1.5, and Z is 1. Of course, the above raw materials are only examples, and the desired compound can be obtained by To obtain the desired product, the raw materials should be selected appropriately. For example, GaO Y Instead of raw materials, MO Y raw material M may be Sn, Hf or Al. Alternatively, M may be lanthanum. The tantalum metals La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, It may be Tm, Yb or Lu. In this embodiment, an example using three kinds of raw materials is shown. The present embodiment is not limited to this. For example, the present embodiment may be applied to a case where four or more kinds of raw materials are used. This may be applied when one or two types of raw materials are used.

[0097] Next, InO X Raw material, GaO Y Raw materials and ZnO Z The ingredients are mixed in a specified ratio.

[0098] The predetermined ratio is, for example, InO X Raw material, GaO Y Raw materials and ZnO Z Ingredients: 2: 2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4 The molar ratio is 3:1:2. By using a mixed material with such a ratio, A sputtered film made of an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface It is easier to obtain targets for the ring. Y Instead of raw materials, MO Y Made with raw materials In the case of InO X Raw materials, MO YRaw materials and ZnO Z The raw materials are 2:2:1, 8:4:3, 3 :1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4 or 3:1:2 mol It can be expressed as a numerical ratio.

[0099] InO mixed at a specified ratio X Raw material, GaO Y Raw materials and ZnO Z The first firing of the raw materials In this way, an In-Ga-Zn-O compound is obtained (step S102).

[0100] Next, the compound is pulverized to obtain compound powder 5002 (step S103).

[0101] The In-Ga-Zn-O compound contains many layered crystal structures when viewed perpendicular to the c-axis. Therefore, the resulting compound powder 5002 contains many plate-like crystal grains.

[0102] The first firing is carried out in an inert atmosphere, an oxidizing atmosphere, or a reduced pressure atmosphere at a temperature of 400° C. or higher. The temperature of the first firing is set to 1700° C. or less, preferably 900° C. or more and 1500° C. or less. For example, from 3 minutes to 24 hours, preferably from 30 minutes to 17 hours, more preferably The first baking may be performed for 30 minutes or more and 5 hours or less. By performing the first baking under the above conditions, the main reaction This suppresses unnecessary reactions other than those mentioned above, and reduces the concentration of impurities contained in the compound powder 5002. The sputtering process is carried out using an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface. This makes it easier to obtain targets for targeting.

[0103] The first baking may be performed multiple times by changing the temperature and / or atmosphere. For example, After the mixed material is held at a first temperature in a first atmosphere, it is heated at a second temperature in a second atmosphere. It's okay to keep it.

[0104] Specifically, the first atmosphere is an inert atmosphere or a reduced pressure atmosphere, and the second atmosphere is an oxidizing atmosphere. This is because the first atmosphere is preferably a reactive atmosphere, and the impurities contained in the mixed material are reduced. This is because oxygen vacancies may occur in the compound when the second atmosphere is used. It is preferable to reduce oxygen vacancies in the compound obtained by the above method. In the case of using oxide semiconductors, impurities such as hydrogen and oxygen vacancies are the source of carrier generation. This causes deterioration in the electrical characteristics and reliability of the transistor. In order to reduce impurities and oxygen vacancies in the sputtering target itself, It is also preferable to reduce oxygen deficiencies.

[0105] Next, as shown in FIG. 2(A), compound powder 5002 is spread in a mold 5001 and molded ( Step S104) Molding refers to spreading the compound powder evenly in a mold. Alternatively, compound powder can be introduced into the mold and then molded by applying vibration from the outside. Then, the mixture can be formed into a uniform thickness using a roller or the like.

[0106] Compound powder 5002 containing many flat crystal grains is spread in mold 5001 and molded. The flat surfaces of the crystal grains are arranged facing upwards. By forming the material in the same way, the proportion of layered crystal structures when viewed perpendicular to the c-axis is further increased. It is possible.

[0107] The mold 5001 may be made of metal or oxide and has a rectangular or round top surface shape. do.

[0108] Next, the compound powder 5002 is subjected to a second firing (step S105). The compound powder 5002 thus synthesized is subjected to a first pressure treatment (step S106). The second baking is performed under the same conditions and in the same manner as the first baking. By carrying out the second baking, the crystallinity of the compound can be increased.

[0109] The first pressurization process is sufficient if it can compress and harden the compound powder 5002. For example, This can be done by using a weight made of the same material as the mold 5001. Alternatively, the first pressure treatment may be carried out by using a known technique. The first pressure treatment may be carried out simultaneously with the second baking.

[0110] A planarization process may be performed after the first pressure treatment. The planarization process may be performed by chemical mechanical polishing (CMP). Chemical Mechanical Polishing (CMP) treatment can be used. good.

[0111] The compound film 5012 thus obtained has a high proportion of c-axes parallel to the normal vector of the upper surface. It has crystalline regions.

[0112] Next, the thickness of the obtained compound film 5012 is confirmed (step S107). If the thickness is smaller than the desired thickness, compound powder 5002 is added to compound film 5002 as shown in FIG. The compound film 5012 is spread over the substrate 5012 and shaped (step S104). If the plate-like compound 5032 is obtained (if the plate-like compound 5032 is obtained), the process proceeds to step S113, and the plate-like compound 5032 is obtained. 032 is attached to the backing plate 5003. The following describes how the compound film 5012 is grown to a desired thickness. The case where the thickness is thinner than the thickness shown in FIG.

[0113] The backing plate is preferably made of a metal material with high electrical conductivity and high heat dissipation. Specifically, Cu is used. In addition, a water channel is formed in the backing plate. It is preferable to cool the sputtering target by passing cooling water. In order to improve the adhesion between the king plate and the sputtering target, the thermal conductivity is It is recommended to bond them without any gaps using a metal with a sufficiently high and low melting point (such as In).

[0114] Next, the compound powder 5002 and the compound film 5012, including the mold 5001, are subjected to a third Then, the compound powder 5002 and the compound powder 5003 subjected to the third firing are heated (step S105). Then, a second pressure treatment is performed on the compound film 5012 (step S106), As a result, a compound film 5022 thicker than the compound film 5021 is obtained (see FIG. 2(D)). Since it is grown by using 5012 as a seed crystal, the c-axis is highly likely to be aligned along the normal vector of the top surface. The crystal regions are parallel to the torsion.

[0115] By carrying out the third baking, the crystallinity of the compound powder and the compound film can be improved. The third firing may be carried out under the same conditions and by the same method as the first firing.

[0116] The second pressure treatment may be carried out under the same conditions and by the same method as the first pressure treatment. By carrying out the above steps, the compound film 5022 obtained has a higher crystal orientation than the compound film 5012. That is, a higher proportion of crystal regions have their c-axes parallel to the normal vector of the top surface. This is because the flat surfaces of the plate-like crystal grains are oriented upwards by the pressure treatment. The second pressure treatment may be performed simultaneously with the third baking. .

[0117] The thickness of the resulting compound film 5022 is again confirmed (step S107).

[0118] As described above, the compound film can be gradually thickened while improving the crystal orientation.

[0119] By repeating this compound film thickening process n times (n is a natural number), the desired thickness (t) is reached. For example, the plate-shaped compound 503 has a diameter of 2 mm or more and 20 mm or less, preferably 3 mm or more and 20 mm or less. 2 can be obtained (see Figure 2(E)).

[0120] After that, a planarization process may be performed.

[0121] Next, as shown in FIG. 4(A), the obtained plate-like compound 5032 is attached to a backing plate 500. 3 (step S113). A low melting point material such as In may be used. A sputtering target made of an oxide semiconductor having parallel crystal regions is prepared. That's good.

[0122] Alternatively, the obtained plate-like compound 5032 is subjected to a fourth firing to obtain a plate-like compound 5042. The resulting plate-like compound 5042 is then bonded to a backing plate 5003 (FIG. 4(B) (See FIG. 13.) Note that In may be provided on the surface of the backing plate 5003 as an adhesive. The fourth firing may be performed under the same conditions and by the same method as the first firing. A sputtering laser consisting of an oxide semiconductor having a crystal region in which the vector of A target for ion beam irradiation can be prepared.

[0123] Similarly, referring to FIG. 1 and FIG. 3, a process different from steps S101 to S107 may be performed. A method for producing a plate-like compound 5132 similar to the plate-like compound 5032 will be described.

[0124] The steps up to step S102 are similar and therefore will be omitted.

[0125] The compound obtained in step S102 is pulverized to obtain a compound powder. The powder, water, a dispersant, and a binder are mixed together to form a slurry (step S108).

[0126] Next, the slurry 5102 is poured into a mold 5101 on which a moisture-permeable filter is laid (FIG. 3(A). The mold 5101 is made of the same material as the mold 5001, for example, and has a small hole in the bottom. By providing a plurality of holes, the slurry can be quickly can be dried.

[0127] Then, the mold 5101 containing the slurry 5102 is filtered through a filter and poured into the bottom of the mold 5101. The mold 5101 is sucked and molded to form a flat plate-shaped mold (step S109). The grains containing the most crystals are arranged with the flat side facing upwards.

[0128] Next, the obtained molded body is dried to remove the binder. The drying is carried out by natural drying. This is preferable because the molded body is less likely to crack. After drying, heat at a temperature of 300°C to 700°C. Heat treatment removes residual moisture that could not be removed by natural drying and removes the binder. .

[0129] Next, the dried molded body is fired (step S110). The firing is performed under the same conditions and conditions as the second firing. This can be done by the following method.

[0130] Next, as shown in FIG. 3(B), the fired compact is subjected to a pressure treatment to form a compound film 511 The compound film 5112 thus obtained has a high degree of c-axis oriented in a direction perpendicular to the normal to the upper surface. The pressure treatment is carried out under the same conditions and conditions as the first pressure treatment. This will be done in a specific manner.

[0131] After that, a planarization process may be performed.

[0132] Next, the thickness of the obtained compound film 5112 is confirmed (step S112). If the thickness of the film 5112 is less than the desired thickness, return to step S109. If the desired thickness is obtained (if a plate-like compound 5132 is obtained), proceed to step S113. The plate-shaped compound 5132 is bonded to the backing plate 5003. A case where 12 is thinner than the desired thickness will be described.

[0133] In step S109, the obtained molded body is stacked on the compound film 5112 and sintered. By subjecting the compound film 5112 to a pressure treatment (step S110) and a pressure treatment (step S111), A compound film 5122 having a good adhesion can be obtained (see FIG. 3(C)). The pressure treatment may be carried out under the same conditions and methods as those for the first pressure treatment. This can be done under the conditions and methods described above.

[0134] By repeating the above steps, a plate-like compound 5132 having a desired thickness can be obtained (FIG. 3(D) reference.).

[0135] After that, a planarization process may be performed.

[0136] The obtained plate-like compound 5132 may be subjected to a firing similar to the fourth firing.

[0137] The obtained plate-like compound 5132 is adhered to a backing plate 5003 (step S113 ).

[0138] Here, the In2O3 raw material, Ga2O3 raw material and ZnO raw material are mixed, crushed and made into a slurry. The resulting mixture was molded, dried, degreased, and then fired at 1400°C in an oxygen atmosphere. The crystalline state of sample A) is shown.

[0139] The surface crystal state of specimen A was measured using electron backscatter diffraction (EBSD). The results are shown in Figure 5(A). FIG. 5(B) shows an image quality map and FIG. 5(B) shows an inverse pole figure orientation map.

[0140] Sample A is found to be polycrystalline by EBSD. Therefore, each crystal grain is a diffraction electron beam (Kikuchi line) pattern of InGaZnO4. In addition, the raw materials In2O3 and Ga2O3 were It was found that the crystal grains of the ZnO raw material were not included.

[0141] Next, X-ray diffraction (XRD) was performed on sample A. The crystal state was evaluated. The XRD was performed using ATX-G manufactured by Rigaku Corporation. The conditions were Out- The scanning range is 5deg.~100deg. by the 2θ / ω scan using the of-plane method. The step width was 0.02 deg., and the scanning speed was 3.0 deg. / min.

[0142] As shown in Fig. 6, sample A is a crystal of InGaZnO4, and the (009) plane has the highest intensity ratio. That is, the compound of sample A has a high proportion of c-axes aligned with the normal vector of the upper surface. It can be seen that the crystal domains are parallel to

[0143] Therefore, the compound shown in this embodiment is repeatedly subjected to pulverization, molding, firing and pressure treatment. This suggests that the c-axis orientation gradually increases.

[0144] The sputtering target thus produced can be made highly dense. The high density of the sputtering target allows the density of the deposited film to be high. Specifically, the relative density of the sputtering target is 90% or more, 95% or more, or 9 It can be 9% or more.

[0145] In the above-described method, a high-density crystal structure having a crystal region in which the c-axis is parallel to the normal vector of the upper surface is obtained. A sputtering target made of an oxide semiconductor can be obtained.

[0146] (Embodiment 2) In this embodiment, an oxide semiconductor having a crystal region in which the c-axis is parallel to the normal vector of the upper surface is A film forming apparatus for forming a body film will be described.

[0147] First, the configuration of a film formation apparatus that reduces the inclusion of impurities during film formation will be described with reference to FIG.

[0148] FIG. 7(A) shows a multi-chamber film-forming apparatus. The film-forming apparatus includes a cassette for accommodating a substrate. The substrate supply chamber 11 has three feed ports 14, and the load lock chamber 12a and the load lock The film forming chamber 10a is connected to the substrate heating chamber 12b, the transfer chamber 13, the substrate heating chamber 15, the film forming chamber 10a, the film forming chamber 10b, and the film forming chamber 10c. The substrate supply chamber includes a load lock chamber 12a and a load lock chamber 10c. The load lock chamber 12a and the load lock chamber 12b are connected to the transfer chamber 13. The substrate heating chamber 15, the film formation chamber 10a, the film formation chamber 10b, and the film formation chamber 10c are connected to the transfer chamber 1. The connection between each chamber is provided with a gate valve, and each chamber is connected independently. Although not shown, the transfer chamber 13 may be equipped with one or more substrate transfer robots. Here, it is preferable that the substrate heating chamber 15 also serves as a plasma processing chamber. The film deposition equipment of the chamber can transport the substrate between processes without exposing it to the atmosphere. This prevents impurities from being adsorbed on the substrate. The number of deposition chambers, load lock chambers and substrate heating chambers can be set according to the above. There is no limit to the number, and it can be determined appropriately according to the installation space and process.

[0149] The exhaust of the film formation chamber (sputtering chamber) shown in FIG. 7(A) will be described with reference to FIG. The film chamber 10 contains a sputtering target 32 ​​and a support for the sputtering target. and a target holder 34 .

[0150] The film formation chamber 10 shown in FIG. 8 is connected to a transfer chamber 13 via a gate valve. is connected to the load lock chamber 12 via a gate valve.

[0151] The film formation chamber 10 shown in FIG. 8 is connected to a refiner 54 via a mass flow controller 60. The number of refiners 54 and mass flow controllers 60 provided is equal to the number of gas species. For simplicity, only one is shown and the rest are omitted.

[0152] The film formation chamber 10 shown in FIG. 8 is connected to a cryopump 58a via a valve.

[0153] The transfer chamber 13 shown in FIG. 8 is connected to a cryopump 58b via a valve.

[0154] The load lock chamber 12 shown in FIG. 8 is connected to a vacuum pump 59 via a valve.

[0155] The vacuum pump 59 may be, for example, a dry pump and a mechanical booster pump. In this case, the mechanical booster of the vacuum pump 59 is connected in series. The pump is connected to the film forming chamber 10 and the transfer chamber 13 via valves. With this configuration, the vacuum pump can be used from atmospheric pressure to low vacuum (approximately 0.1 Pa to 10 Pa). Pump 59 was used to evacuate the chamber, and the valve was switched from low to high vacuum (1×10 -4 Pa~1× 10 -7 The cryopump 58a or the cryopump 58b is used to pump up to 100 Pa. It is possible.

[0156] Similarly, evacuation of an example of the film formation chamber shown in FIG. 7(A) will be described with reference to FIG.

[0157] The film formation chamber 10 shown in FIG. 9 is connected to a transfer chamber 13 via a gate valve. is connected to the load lock chamber 12 via a gate valve.

[0158] The film formation chamber 10 shown in FIG. 9 is connected to a mass flow controller 60 via a gas heating mechanism 62. The gas heating mechanism 62 is connected to the refiner 54 via a mass flow controller 60. The gas to be introduced into the deposition chamber 10 is heated to a temperature of 40° C. or higher and 400° C. or lower by the gas heating mechanism 62. Preferably, the gas can be heated to a temperature of 50° C. or higher and 200° C. or lower. The number of gas flow controllers 54 and mass flow controllers 60 is the same as the number of gas types. Only the first one is shown and the rest are omitted.

[0159] The film formation chamber 10 shown in FIG. 9 is connected to a turbo molecular pump 58c via a valve. The turbo molecular pump 58c is provided with a vacuum pump 59a via a valve as an auxiliary pump. The vacuum pump 59a may have the same configuration as the vacuum pump 59.

[0160] Further, the film formation chamber 10 shown in FIG.

[0161] The turbo molecular pump 58c stably pumps large molecules and requires little maintenance. It is known that the productivity is excellent because of its low temperature, but the exhaust capacity of hydrogen and water is low. Cryotrap 66 has high pumping capacity for molecules with relatively high melting points such as water. The temperature of the cryotrap 66 refrigerator is 100K or less. The temperature is set to a temperature lower than 80K, preferably 80K or lower. Also, the cryotrap 66 has multiple refrigerators. In this case, it is preferable to change the temperature for each refrigerator, since this allows for efficient exhaust. For example, the temperature of the first stage refrigerator is set to 100K or less, and the temperature of the second stage refrigerator is set to 20K or less. This can be done as follows.

[0162] The transfer chamber 13 shown in FIG. 9 includes a cryopump 58d and a cryopump 58e. It is connected through a valve. If there is one cryopump, regenerate the cryopump. However, by connecting two or more cryopumps in parallel, Even if one cryopump is regenerating, the remaining cryopump can be used to pump the gas. The regeneration of a cryopump is the process of releasing the molecules trapped inside the cryopump. If too many molecules accumulate in a cryopump, its pumping capacity will decrease. , and regeneration occurs periodically.

[0163] The load lock chamber 12 shown in FIG. 9 includes a cryopump 58f and a vacuum pump 59c. Each is connected via a valve.

[0164] The vacuum pump 59b is connected to the film forming chamber 10 and the transfer chamber 13 via valves. The vacuum pump 59b may have the same configuration as the vacuum pump 59.

[0165] Similarly, evacuation of an example of the substrate heating chamber shown in FIG. 7(A) will be described with reference to FIG.

[0166] The substrate heating chamber 15 shown in FIG. 10 is connected to the transfer chamber 13 via a gate valve. The transfer chamber 13 is connected to the load lock chamber 12 via a gate valve, but the description is omitted. The load lock chamber 12 is evacuated in the same manner as in FIG.

[0167] The substrate heating chamber 15 shown in FIG. 10 is connected to a refiner 54 via a mass flow controller 60. The number of refiners 54 and mass flow controllers 60 is equal to the number of gas types. However, for simplicity, only one is shown and the rest are omitted.

[0168] The substrate heating chamber 15 shown in FIG. 10 is connected to a vacuum pump 59b via a valve.

[0169] The substrate heating chamber 15 may have a stage on which multiple substrates can be placed. The heat chamber 15 may be heated, for example, by a resistive heating element or by a heated gas. It may be heated by thermal conduction or thermal radiation from a medium such as GR. TA (Gas Rapid Thermal Anneal), LRTA (Lamp R Rapid Thermal Anneal (RTA) Anneal) can be used. LRTA can be used with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water The workpiece is heated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. TA is a thermal treatment using high-temperature gas, typically an inert gas.

[0170] The back pressure of the film forming chamber 10 and the substrate heating chamber 15 is 1×10 -4 Pa or less, preferably 3 ×10 -5 Pa or less, more preferably 1×10 -5 Pa or less.

[0171] In addition, the film forming chamber 10 and the substrate heating chamber 15 are heated to a partial pressure of a gas molecule (atom) having m / z=18. is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0172] In addition, the film forming chamber 10 and the substrate heating chamber 15 are heated to a partial pressure of a gas molecule (atom) having m / z=28. is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0173] In addition, the film forming chamber 10 and the substrate heating chamber 15 are heated to a partial pressure of a gas molecule (atom) having m / z=44. is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0174] The film formation chamber 10 and the substrate heating chamber 15 have a leak rate of 3×10 -6 Pa·m 3 / s Less than or equal to 1×10 -6 Pa·m 3 / s or less.

[0175] In addition, the film forming chamber 10 and the substrate heating chamber 15 are connected to a lead-type ion source for a gas molecule (atom) having m / z=18. 1x10 Crate -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or later Below.

[0176] In addition, the film forming chamber 10 and the substrate heating chamber 15 are connected to a lead-type ion source of a gas molecule (atom) having m / z=28. 1x10 Crate -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or later Below.

[0177] In addition, the film forming chamber 10 and the substrate heating chamber 15 are connected to a lead of a gas molecule (atom) having m / z=44. 3×10 crates -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or later Below.

[0178] The total pressure and partial pressure can be measured using a mass spectrometer. Lubac quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 The leak rate can be calculated by using the total leak rate measured by the mass spectrometer mentioned above. It may be derived from the pressure and partial pressure.

[0179] The leak rate depends on external and internal leaks. External leaks occur due to tiny holes or seals. An internal leak is when gas flows into the vacuum system from outside due to a valve failure or other reasons. This is caused by leakage from partitions such as valves and gas released from internal components. In order to keep the above values ​​or less, measures must be taken to prevent both external and internal leaks. There is.

[0180] For example, it is advisable to seal the opening and closing parts of the deposition chamber with a metal gasket. , using a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have a higher adhesion than O-rings and can reduce external leakage. In addition, the impurities of metal materials coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using the dynamics, the gas released from the metal gasket containing impurities is suppressed. , internal leakage can be reduced.

[0181] The materials that make up the film deposition equipment are aluminum, chromium, Titanium, zirconium, nickel or vanadium are used. The above materials can also be used in combination with iron, chromium or vanadium. It may be used by coating an alloy material containing iron, chromium and nickel. The alloy material containing galvanized steel is rigid, heat-resistant, and easy to process. In order to reduce the area, the surface irregularities of the components can be reduced by polishing, etc. It can be reduced.

[0182] Alternatively, the components of the aforementioned film forming apparatus are coated with iron fluoride, aluminum oxide, chromium oxide, etc. This is also fine.

[0183] It is preferable that the members of the film forming apparatus are made of metal materials as much as possible, for example, quartz. When installing a viewing window, etc., the surface should be coated with iron fluoride or alumina to suppress gas emission. It is advisable to coat it thinly with aluminum or chromium oxide.

[0184] In addition, when a refiner is provided immediately before the introduction of the deposition gas, the length of the piping from the refiner to the deposition chamber is The length of the pipe is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length to 10m or less, 5m or less, or 1m or less, the effect of gas released from the piping is reduced depending on the length. It can be reduced accordingly.

[0185] In addition, the inside of the piping for the deposition gas is coated with iron fluoride, aluminum oxide, chromium oxide, etc. It is recommended to use metal piping that is covered with a protective film. The above piping is, for example, SUS316L-EP piping. Therefore, the amount of gas containing impurities released is small, and the amount of impurities mixed into the deposition gas can be reduced. For piping joints, it is recommended to use high-performance ultra-compact metal gasket joints (UPG joints). In addition, by using only metal materials for the piping, the generated heat is reduced compared to when resin or other materials are used. This is preferable because it can reduce the effects of released gas and external leakage.

[0186] The adsorbates present in the deposition chamber are adsorbed to the inner walls, etc., and do not affect the pressure in the deposition chamber. This causes gas emission when the deposition chamber is evacuated. Therefore, the leak rate is proportional to the evacuation speed. Although there is no relation between the amount of adsorbed matter and the amount of the adsorbed matter, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to desorb the adsorbed material and evacuate the gas beforehand. The deposition chamber may be baked. This will increase the desorption rate of adsorbed substances by about 10 times. Baking can be performed at temperatures between 100℃ and 450℃. When removing adsorbed substances while introducing an inert gas into the deposition chamber, the substances cannot be desorbed by simply evacuating the chamber. The desorption rate of water and other impurities can be further increased. By heating the mixture to the same temperature as the heating, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a rare gas as the inert gas. Instead of the inert gas, oxygen or the like may be used. For example, when forming an oxide film, In some cases, it may be preferable to use oxygen as the main component.

[0187] Alternatively, the pressure in the deposition chamber can be increased by introducing an inert gas such as a heated rare gas or oxygen. It is preferable to increase the pressure and evacuate the deposition chamber again after a certain period of time has elapsed. By introducing the gas, it is possible to desorb the adsorbed substances in the film formation chamber, and the impurities present in the film formation chamber are reduced. This treatment can be repeated 2 to 30 times, preferably 5 to 15 times. It is effective to repeat the process within the following range: By introducing an inert gas or oxygen, preferably at a temperature of 50° C. or higher and 200° C. or lower, The pressure in the deposition chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less. More preferably, the pressure is set to 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or more. The film formation chamber is then heated for 5 to 300 minutes, preferably for 5 to 120 minutes. Thereafter, evacuation is preferably performed for a period of 10 minutes or more and 120 minutes or less.

[0188] Also, the desorption speed of the adsorbed substances can be further increased by forming a dummy film. The film formation is performed by forming a film on a dummy substrate using a method such as sputtering. A film is deposited on the plate and the inner wall of the deposition chamber, and impurities in the deposition chamber and substances adsorbed on the inner wall of the deposition chamber are removed from the film. The dummy substrate is preferably made of a material that emits less gas. The same material as the substrate 100 may be used. The impurity concentration in the film can be reduced. The dummy film is formed at the same time as baking. This is also fine.

[0189] FIG. 7B shows a film forming apparatus having a different configuration from that shown in FIG. 7A. chamber 22a, substrate heating chamber 25, film formation chamber 20a, film formation chamber 20b, and load lock chamber 22 The load lock chamber 22a is connected to the substrate heating chamber 25, which is constituted by a substrate heating chamber 25b. The film forming chamber 20a is connected to the film forming chamber 20b, and the film forming chamber 20b is connected to the load lock. The connection between each chamber is provided with a gate valve, and each chamber is isolated. The film forming chamber 20a and the film forming chamber 20b are maintained in a vacuum state by the vacuum chamber 20a and the vacuum chamber 20b. The film forming chambers 10a, 10b and 10c in FIG. The heating chamber 25 has the same structure as the substrate heating chamber 15 shown in FIG. The board is transported in only one direction, as shown by the arrow in the figure, and the entrance and exit of the board are different. Unlike multi-chamber deposition equipment, it does not have a transfer chamber, so the footprint can be made smaller. The numbers of the film-forming chambers, the load lock chambers, and the substrate heating chambers are not limited to the above numbers. Instead, it is sufficient to select an appropriate size according to the installation space and the process. b may be omitted, or the second substrate heating chamber or the third film forming chamber connected to the film forming chamber 20b may be omitted. may be provided.

[0190] By forming an oxide semiconductor film using the above-described film formation apparatus, impurities in the oxide semiconductor film can be prevented. Furthermore, the above-described film formation apparatus can be used to form a film in contact with the oxide semiconductor film. By forming the oxide semiconductor film, impurities are prevented from being mixed into the oxide semiconductor film from a film in contact with the oxide semiconductor film. This can suppress the following.

[0191] Next, a method for forming an oxide semiconductor film having a crystal region in which the c-axis is parallel to the normal vector of the top surface is described. Explain the law.

[0192] In the formation of the oxide semiconductor film, the c-axis shown in Embodiment 1 is parallel to the normal vector of the top surface. A sputtering target made of an oxide semiconductor having a crystal region is used.

[0193] The surface temperature of the sputtering target is 100° C. or less, preferably 50° C. or less, and In a sputtering apparatus for a large-area substrate, the temperature is preferably about room temperature. Sputtering targets are often used. However, It is difficult to manufacture a seamless sputtering target. The sputtering targets are arranged with as few gaps as possible to create a large shape. However, small gaps inevitably occur. These small gaps cause the sputtering - As the surface temperature of the target rises, Zn and other substances evaporate, gradually widening the gap. If the gap widens, the backing plate material and the adhesive material will spatter. This can lead to an increase in the impurity concentration. The get is preferably sufficiently cooled.

[0194] Specifically, the backing plate is made of a metal material having high electrical conductivity and high heat dissipation. In addition, a water channel is formed in the backing plate, and the water channel is filled sufficiently with By flowing a sufficient amount of cooling water, the sputtering target can be cooled efficiently. A sufficient amount of cooling water is required depending on the size of the sputtering target, for example, a target with a diameter of For a 300mm circular target, 3L / min or more, 5L / min or more should be 10 L / min or more.

[0195] Here, the In-Ga-Zn-O compound (In:Ga:Zn=1:1:1 [atomic ratio]) The collision of a single argon atom with a crystal was evaluated using classical molecular dynamics calculations. The results are shown in Figure 44.

[0196] The calculations were performed using Materials Explorer 5.0 from Fujitsu Ltd. The temperature was 300K, the time step size was 0.01fs, and the number of steps was 10 million.

[0197] The calculations were performed using a single crystal of the In-Ga-Zn-O compound with 2688 atoms. In addition, argon atoms having an energy of 300 eV were irradiated from a direction parallel to the c-axis of the single crystal. The fixed layer shown in Figure 44 is a layer that is fixed so that its position does not change. The temperature control layer shown in FIG. 44 is a layer that is always kept at a constant temperature (300K).

[0198] Figure 44 shows the state before and 100 ps after the argon atom collision. vinegar.

[0199] As shown in Figure 44, 100 ps after the argon atom hit, the In-Ga-Zn-O compound The crystal is cleaved along the ab plane, specifically, along the plane containing Ga and Zn. do.

[0200] That is, when ions collide with the surface of the sputtering target, The crystalline region in the target is cleaved from the ab plane, and the plate-shaped sputtering particles are peeled off. It can be seen that.

[0201] The oxide semiconductor film is heated at a substrate heating temperature of 100° C. or higher and 600° C. or lower, preferably 150° C. or higher. The film is formed in an oxygen gas atmosphere at 550°C or less, more preferably 200°C to 500°C. The thickness of the oxide semiconductor film is 1 nm to 40 nm, preferably 3 nm to 20 nm. The higher the substrate heating temperature during film formation, the lower the impurity concentration of the resulting oxide semiconductor film. In addition, migration of sputtered particles is more likely to occur on the surface on which the film is to be formed. Therefore, the atomic arrangement in the oxide semiconductor film is ordered, the density is increased, and the oxide semiconductor film is formed as a polycrystalline or CAAC-O Furthermore, by forming the film in an oxygen gas atmosphere, plasma damage is reduced. Since the lattice structure is reduced and no extra atoms such as rare gases are included, it is possible to obtain a polycrystalline or CAAC- However, a mixed atmosphere of oxygen gas and rare gas may be used. In this case, the ratio of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably Note that the thinner the oxide semiconductor film, the shorter the channel length of the transistor. As the time becomes shorter, the phenomenon that the threshold voltage shifts in the negative direction is reduced. However, However, if the thickness is too thin, the effect of interface scattering becomes stronger, which may result in a decrease in field effect mobility. .

[0202] In addition, when the sputtering target contains Zn, deposition is performed in an oxygen gas atmosphere. This reduces plasma damage and makes it possible to obtain a film in which Zn is less likely to volatilize.

[0203] The oxide semiconductor film is formed under a deposition pressure of 0.8 Pa or less, preferably 0.4 Pa or less. The distance between the target and the substrate is set to 40 mm or less, preferably 25 mm or less. By forming the oxide semiconductor film under such conditions, the sputtering particles and other This can reduce the frequency of collisions between the sputtered particles, gas molecules or ions. That is, the distance between the sputtering target and the substrate is adjusted according to the deposition pressure. The impurities are incorporated into the film by making the impurities smaller than the mean free path of the electrons, gas molecules, or ions. The concentration of pure substances can be reduced.

[0204] For example, the mean free path at a pressure of 0.4 Pa and a temperature of 25°C (absolute temperature of 298 K) is The hydrogen molecule (H2) is 48.7 mm, the helium atom (He) is 57.9 mm, and the water molecule ( H2O) is 31.3 mm, ethane molecule (CH4) is 13.2 mm, neon atom (Ne) 42.3mm, nitrogen molecule (N2) 23.2mm, carbon monoxide molecule (CO) 16.0m m, oxygen molecule (O2) 26.4 mm, argon atom (Ar) 28.3 mm, carbon dioxide The elementary molecule (CO2) is 10.9 mm, the krypton atom (Kr) is 13.4 mm, and the xenon atom The electron (Xe) is 9.6 mm. If the pressure is doubled, the mean free path will be halved. Therefore, if the absolute temperature doubles, the mean free path doubles.

[0205] The mean free path is determined by pressure, temperature, and the diameter of the molecule (atom). When the diameter of a molecule (atom) is fixed, the mean free path becomes shorter as the diameter of the molecule (atom) becomes larger. The diameter of the atom is 0.218 nm for H2, 0.200 nm for He, and 0.27 nm for H2O. 2nm, CH4 is 0.419nm, Ne is 0.234nm, N2 is 0.316nm, CO is 0.380nm, O2 is 0.296nm, Ar is 0.286nm, CO2 is 0.460 nm, Kr is 0.415 nm, and Xe is 0.491 nm.

[0206] Therefore, the larger the diameter of a molecule (atom), the shorter the mean free path and the easier it is to incorporate into the film. When the molecules (atoms) are absorbed into the material, the large diameter of the molecules (atoms) inhibits the growth of the crystal region. Therefore, for example, molecules (atoms) with a diameter larger than that of Ar are likely to become impurities.

[0207] Here, when CO2 is added between the layers of the In-Ga-Zn-O crystal, the crystal structure cannot be maintained. We evaluated the molecular dynamics properties of the nucleoid by classical molecular dynamics calculations.

[0208] Figure 26 is a schematic diagram of an In-Ga-Zn-O crystal, and CO2 is added to the layer indicated by the arrow in Figure 26. The amount of CO2 added was 0.07% (5 .19×10 19 pieces / cm 3 ), 0.15% (1.04 × 10 20 pieces / cm 3 ), 0.2 2% (1.65 × 10 20 pieces / cm 3), 0.30% (2.08 × 10 20 pieces / cm 3 ) , 0.37% (2.60 × 10 20 pieces / cm 3 ), 0.44% (3.11 × 10 20 pieces / cm 3 ), 0.52% (3.63 × 10 20 pieces / cm 3 ), 0.59% (4.15 × 10 20 pieces / cm 3 ) or 0.67% (4.67 × 10 20 pieces / cm 3 ) as a percentage.

[0209] The calculations were performed using Materials Explorer 5.0 from Fujitsu Ltd. The temperature is 298K, the pressure is 1 atm, the time step is 0.2 fs, and the number of steps is 5 million. did.

[0210] As a result, when the CO2 addition ratio was 0.07% to 0.52%, the In-Ga-Zn- The In-GaO crystals were maintained, and when the CO2 addition rate was 0.59% to 0.67%, the In-Ga -Zn-O crystals could not be retained.

[0211] In other words, in order to obtain In-Ga-Zn-O crystals, all atoms of the In-Ga-Zn-O crystals must be It is clear that the ratio of CO2 to greenhouse gases needs to be below 0.52% or less than 0.59%.

[0212] Next, a heat treatment is performed. The heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. By the heat treatment, the impurity concentration in the oxide semiconductor film can be reduced.

[0213] The heat treatment is carried out in a reduced pressure or inert atmosphere, and then the temperature is maintained while degassing the material in an acid bath. It is preferable to switch to a chemical atmosphere and carry out further heat treatment. When heat treatment is performed in an active atmosphere, the impurity concentration in the oxide semiconductor film can be reduced. However, at the same time, oxygen vacancies are also generated. This can be reduced by heat treatment in air.

[0214] The oxide semiconductor film is formed by heating the substrate and by subjecting the film to heat treatment, so that the impurity concentration in the film can be reduced. It is possible to reduce

[0215] Specifically, the hydrogen concentration in the oxide semiconductor film was measured by secondary ion mass spectrometry (SIMS). 5×10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferable: is 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / c m 3 It can be as follows:

[0216] The nitrogen concentration in the oxide semiconductor film was 5×10 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following It is possible.

[0217] The carbon concentration in the oxide semiconductor film was found to be 5×10 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following It is possible.

[0218] In addition, the oxide semiconductor film was analyzed by thermal desorption spectroscopy (TDS). Spectroscopy analysis of m / z=2 (e.g., hydrogen molecule) A gas molecule (atom) with m / z=18, a gas molecule (atom) with m / z=28 The amount of gas molecules (atoms) with m / z = 44 released was 1 × 10 19 pieces / cm 3 Less than or equal to 1×10 18 pieces / cm 3 It can be as follows:

[0219] For the method of measuring the amount of released oxygen atoms using TDS analysis, see the section on measuring the amount of released oxygen atoms below. Please refer to the method for determining the

[0220] Here, when the oxide semiconductor film is formed in the film formation chamber of the film formation apparatus described in this embodiment, The partial pressure of each molecule will be described. The total pressure and partial pressure during film formation are measured by ULVAC, Inc. The measurements were performed using a quadrupole mass spectrometer, Qulee CGM-051, manufactured by Qulee.

[0221] The oxide semiconductor film was formed by heating the substrate at 150° C. and sputtering the target as In-Ga -Zn-O compound target (In:Ga:Zn=1:1:1 [atomic ratio]), argon and oxygen 50sccm, power 9kW(AC), substrate-target distance The film is formed at a distance of 150 mm.

[0222] Figure 45 shows the total pressure, the partial pressure of m / z=2, the partial pressure of m / z=18, and the m The partial pressures are m / z=28, m / z=40 and m / z=44.

[0223] From FIG. 45, when the film formation apparatus shown in this embodiment is used, the partial pressure of m / z=2 during film formation, The partial pressures of m / z=18, m / z=28, and m / z=44 were 1.5 ×10 -4 Pa, 5×10 -5 Pa, 3×10 -5 Pa and 8 × 10 -5 Pa and small It can be seen that impurities are less likely to be mixed in during film formation.

[0224] By using the above-mentioned film formation apparatus, a crystal region in which the c-axis is parallel to the normal vector of the upper surface can be formed. In the present invention, a crystal having a c-axis parallel to the normal vector of the top surface can be obtained. Since the oxide semiconductor film having the region has excellent semiconductor characteristics, Sometimes it is highly reliable.

[0225] This embodiment mode can be used in appropriate combination with the other embodiment modes.

[0226] (Embodiment 3) The sputtering target shown in the first embodiment and the film forming apparatus shown in the second embodiment 11 to 16 are used for a transistor including an oxide semiconductor film formed by using the above-mentioned device. I will explain this in more detail.

[0227] The transistors shown in FIGS. 11 to 14 have low productivity due to the small number of photolithography steps. The transistors shown in FIGS. 11 to 14 are relatively large in size. This is suitable for use in display devices.

[0228] First, the structure of the transistor shown in FIG. 11 will be described. FIG. 11(A) shows a transistor. 11(A) is a cross-sectional view of the motor shown in FIG. It is.

[0229] The transistor shown in FIG. 11B includes a substrate 100 and a base insulating film provided over the substrate 100. the oxide semiconductor film 102, the oxide semiconductor film 106 provided over the base insulating film 102, and the oxide semiconductor film A pair of electrodes provided over the oxide semiconductor film 106 and at least partially in contact with the oxide semiconductor film 106 116, and a gate insulating film provided to cover the oxide semiconductor film 106 and the pair of electrodes 116. A gate insulating film 112 is provided so as to overlap with the oxide semiconductor film 106 with the gate insulating film 112 interposed therebetween. and a gate electrode 104.

[0230] Here, in the oxide semiconductor film 106, the c-axis shown in Embodiment 1 is parallel to the normal vector of the top surface. The sputtering target is made of an oxide semiconductor having a crystal region in a row. The oxide semiconductor film 106 is formed using the film formation apparatus described in Embodiment 2. do.

[0231] The oxide semiconductor film 106 has a thickness of 1 nm to 50 nm. In particular, for transistors with a channel length of 30 nm or less, By setting the thickness of the compound semiconductor film 106 to about 5 nm, the channel length of the transistor is shortened. As the temperature increases, the threshold voltage shifts in the negative direction, and stable electrical characteristics are obtained. It has sexuality.

[0232] The oxide semiconductor film 106 preferably contains at least In and Zn. The semiconductor film 106 contains In and Zn, as well as other elements that reduce the variation in the electrical characteristics of the transistors. It is preferable to have Ga, Sn, Hf or Al in order to reduce the amount of the impurity.

[0233] Alternatively, the oxide semiconductor film 106 may contain, in addition to In and Zn, a material that improves the electrical characteristics of the transistor. To reduce variability, the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G d, Tb, Dy, Ho, Er, Tm, Yb and Lu. stomach.

[0234] For the oxide semiconductor film 106, for example, In-Z nO compounds, Sn-Zn-O compounds, Al-Zn-O compounds, Zn-Mg-O compounds, Sn-Mg-O compounds, In-Mg-O compounds, In-Ga-O compounds, In-Al-Z nO compounds, In-Sn-Zn-O compounds, Sn-Ga-Zn-O compounds, Al-Ga -Zn-O compounds, Sn-Al-Zn-O compounds, In-Hf-Zn-O compounds, In- La-Zn-O compound, In-Ce-Zn-O compound, In-Pr-Zn-O compound, I n-Nd-Zn-O compounds, In-Sm-Zn-O compounds, In-Eu-Zn-O compounds , In-Gd-Zn-O compounds, In-Tb-Zn-O compounds, In-Dy-Zn-O compounds compound, In-Ho-Zn-O compound, In-Er-Zn-O compound, In-Tm-Zn- O compound, In-Yb-Zn-O compound, In-Lu-Zn-O compound, In-Sn-G a-Zn-O compounds, In-Hf-Ga-Zn-O compounds, In-Al-Ga-Zn-O Compound, In-Sn-Al-Zn-O compound, In-Sn-Hf-Zn-O compound, In In this case, the above-mentioned compound may be used. Refer to the method for making a sputtering target and change the raw materials accordingly to make a sputtering target. A target can be created.

[0235] For example, transistors using In-Sn-Zn-O compounds can easily achieve high field efficiency. Specifically, the field effect mobility of the transistor is 31 cm 2 / Vs or later Top, 40cm 2 / Vs or more, 60cm 2 / Vs or more, 80cm 2 / Vs or more or 100 cm 2 / Vs or more. In the case of In-Ga-Zn-O compounds, the field effect mobility can be increased by reducing the defect density. It can be done.

[0236] When an In-Zn-O compound is used as the oxide semiconductor film 106, the atomic ratio is In / Zn n=0.5 to 50, preferably In / Zn=1 to 20, more preferably I n / Zn = 1.5 to 15. By setting the atomic ratio of Zn in the above range, The field effect mobility of the transistor can be improved. When Zn:O=X:Y:Z, it is preferable that Z>1.5X+Y.

[0237] The oxide semiconductor film 106 is formed of a material having the chemical formula InMO3(ZnO) m Materials expressed as (m>0) Here, M is selected from Zn, Ga, Al, Mn, Sn, Hf and Co. represents one or more selected metallic elements. For example, M is Ga, Ga and Al, G A and Mn or Ga and Co, etc. may also be used.

[0238] The oxide semiconductor film 106 has a band gap of 2 A material having a refractive index of 0.5 eV or more, preferably 2.8 eV or more, and more preferably 3.0 eV or more is selected. Select.

[0239] Note that alkali metals, alkaline earth metals, and the like are reduced in the oxide semiconductor film 106. The oxide semiconductor film 106 preferably has an extremely low impurity concentration. When the above-mentioned impurities are present, recombination occurs within the band gap due to the levels formed by the impurities. As a result, the off-state current of the transistor increases.

[0240] The alkali metal concentration in the oxide semiconductor film 106 was measured by SIMS. Degree is 5×10 16 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 Similarly, lithium The concentration is 5 x 10 15 atoms / cm 3 Less than or equal to 1×10 15 atoms / c m 3 Similarly, the potassium concentration is 5×10 15 atoms / cm 3 The following are the preferred Or 1×10 15 atoms / cm 3 The following applies.

[0241] By using the above-described oxide semiconductor film 106, the off-state current of the transistor can be reduced. For example, the off-state current when the channel length of a transistor is 3 μm and the channel width is 1 μm is 1×10 -18 Below A, 1×10 -21 A or less, or 1×10 -24 Must be A or below Therefore, it is possible to fabricate a memory cell that has excellent data retention characteristics and consumes little power. It is possible.

[0242] There is no particular limitation on the substrate 100, but it should have at least sufficient heat resistance to withstand subsequent heat treatments. For example, glass substrates, ceramic substrates, quartz substrates, and sapphire substrates. Alternatively, a single crystal semiconductor such as silicon or silicon carbide may be used as the substrate 100. Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI ( It is also possible to apply a silicon on insulator substrate. It is preferable to use such a substrate having a semiconductor element provided thereon as the substrate 100 .

[0243] A flexible substrate may be used as the substrate 100. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 100. A release layer may be provided between the non-flexible substrate and the transistor.

[0244] The base insulating film 102 is made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, iridium oxide Tritium oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium oxide The above may be selected and used in a single layer or a laminated layer.

[0245] It is preferable that the base insulating film 102 has sufficient flatness. Specifically, the average surface roughness (R a) is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. The base insulating film 102 is provided so as to have a thickness of 100 nm or less. The crystal region is easily formed at 106. Ra is defined in JIS B0601. This is a three-dimensional extension of the centerline average roughness, which is currently used, so that it can be applied to surfaces. It can be expressed as "the average of the absolute values ​​of the deviation from a surface to a specified surface" and is defined by Equation 1.

[0246]

number

[0247] In addition, in the formula 1, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y 1) The area of ​​the rectangular region represented by the four points (x2, y2), and Z0 is the average of the measurement surface Ra refers to the height of the object measured by an atomic force microscope (AFM). It can be evaluated using cope.

[0248] Silicon oxynitride is a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less. Silicon is between 25 atomic % and 35 atomic % and hydrogen is between 0 atomic % and 10 atomic %. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen in its composition. For example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 20 % to 55%, silicon is 25% to 35%, hydrogen is 10 % or more and 25 atomic % or less. However, the above range is based on the Rutherford method. Rutherford Backscattering Spectrum (RBS) rometry and Hydrogen Forward Scattering (HFS) The results are based on measurements using ion scattering spectrometry (ICS). The composition of the constituent elements does not exceed 100 atomic % in total.

[0249] The base insulating film 102 is preferably an insulating film that releases oxygen by heat treatment.

[0250] "Oxygen is released by heat treatment" means that the amount of oxygen released is converted to oxygen atoms by TDS analysis. The emission amount is 1.0×10 18 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 This means that the above is the case.

[0251] Here, the method for measuring the amount of released oxygen converted into oxygen atoms in TDS analysis is as follows: will explain.

[0252] The amount of gas released during TDS analysis is proportional to the integral value of the ion intensity. The amount of released gas is calculated from the ratio of the integral value of the ion intensity measured to the reference value of the standard sample. The reference value of a standard sample is the value of the atom in a sample containing atoms of a given density. It is the ratio of the density of the atom to the integral value of the corresponding ion intensity.

[0253] For example, the results of a TDS analysis of a silicon wafer containing a standard sample of hydrogen with a given density, From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is calculated using formula 2. Here, all of the gases detected at mass number 32 in the TDS analysis are acids. We assume that it is derived from an elementary molecule. There is another molecule with mass number 32, CH3OH, but it may exist. The possibility of this is low, so it is not considered here. The abundance of oxygen atoms and oxygen molecules containing the oxygen atom with mass number 18 in nature is also The rate is so small that it is not taken into consideration.

[0254]

number

[0255] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the insulating film is analyzed by TDS. α is a coefficient that affects the ion intensity in TDS analysis. For details of Equation 2, For details, see Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the insulating film is calculated by the following equation: A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. 1×10 16 atoms / cm 3 The measurement is performed using a silicon wafer containing hydrogen atoms.

[0256] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It can be estimated based on the above.

[0257] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released in terms of oxygen atoms is This is twice the amount released.

[0258] In the above-mentioned structure, the film that releases oxygen by heat treatment is silicon oxide (S iO X (X>2)) or silicon oxide (SiO X (X>2) It contains more than twice as many oxygen atoms as silicon atoms per unit volume. The number of silicon atoms and oxygen atoms per volume was measured by Rutherford backscattering spectrometry. This is the value.

[0259] When oxygen is supplied from the base insulating film 102 to the oxide semiconductor film 106, the oxide semiconductor film The interface state density between the insulating film 106 and the insulating film 102 can be reduced. Due to the action of the oxide semiconductor film 106 and the base insulating film 102, carriers are captured at the interface between the oxide semiconductor film 106 and the base insulating film 102. This can suppress the occurrence of the problem, thereby providing a highly reliable transistor.

[0260] Further, charge may be generated due to oxygen vacancies in the oxide semiconductor film 106. The oxygen vacancies in the oxide semiconductor film 106 may act as donors and emit electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. In this case, oxygen is sufficiently supplied from the base insulating film 102 to the oxide semiconductor film 106. The excessive oxygen content of the semiconductor film 106 causes the threshold voltage to shift in the negative direction. In this way, oxygen vacancies in the oxide semiconductor film 106, which are a cause of the temperature shift to 100° C., can be reduced.

[0261] The excess oxygen is mainly oxygen present between the lattices of the oxide semiconductor film 106, and the oxygen concentration is 1 ×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 The range is as follows: By setting the concentration of oxygen present between the lattices of the oxide semiconductor film 106 within the above range, the crystal is not distorted. This is preferable because it does not cause cracks or the like and does not destroy the crystalline regions.

[0262] The pair of electrodes 116 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T One or more selected from a and W, their nitrides, oxides and alloys, in a single layer or laminated form Alternatively, an oxide or oxynitride containing at least In and Zn may be used. For example, an In-Ga-Zn-ON compound may be used.

[0263] The gate insulating film 112 may be formed using a material similar to that of the base insulating film 102 .

[0264] The gate electrode 104 may be formed using a material similar to that of the pair of electrodes 116 .

[0265] Next, the structure of the transistor shown in FIG. 12 will be described. FIG. 12(A) shows a transistor 12(A) is a cross-sectional view of the device shown in FIG. 12(B). be.

[0266] The transistor shown in FIG. 12B includes a substrate 100 and a base insulating film provided over the substrate 100. A film 102, a pair of electrodes 216 provided on the base insulating film 102, and and is provided in contact with at least a portion of the pair of electrodes 216 and the base insulating film 102. The oxide semiconductor film 206 and a pair of electrodes 216 and a metal oxide film 216 are provided to cover the oxide semiconductor film 206. The gate insulating film 212 overlaps with the oxide semiconductor film 206 with the gate insulating film 212 interposed therebetween. and a gate electrode 204 provided between the gate electrode 202 and the first insulating film 203 .

[0267] The pair of electrodes 216, the oxide semiconductor film 206, the gate insulating film 212, and the gate electrode 204 is a pair of electrodes 116, an oxide semiconductor film 106, a gate insulating film 112, and The insulating film 104 may be formed by the same method and using the same material as the gate electrode 104 .

[0268] Next, the structure of the transistor shown in FIG. 13 will be described. FIG. 13(A) shows a transistor 13(A) is a top view of the device shown in FIG. 13(B). be.

[0269] The transistor shown in FIG. 13B includes a substrate 100 and a gate electrode provided on the substrate 100. a gate insulating film 312 provided to cover the gate electrode 304; An oxide semiconductor film 306 overlapping with the gate electrode 304 with an oxide semiconductor film 312 interposed therebetween; A semiconductor film 306 is provided over the semiconductor film 306 and is at least partially in contact with the oxide semiconductor film 306. A pair of electrodes 316 and a protective film provided to cover the oxide semiconductor film 306 and the pair of electrodes 316 and a protective insulating film 318.

[0270] The pair of electrodes 316, the oxide semiconductor film 306, the gate insulating film 312, and the gate electrode 304, a pair of electrodes 116, an oxide semiconductor film 106, a gate insulating film 112, and The insulating film 104 may be formed by the same method and using the same material as the gate electrode 104 .

[0271] The protective insulating film 318 may be formed using a material similar to that of the base insulating film 102 .

[0272] Next, the structure of the transistor shown in FIG. 14 will be described. FIG. 14(A) shows a transistor 14(A) is a top view of the device shown in FIG. 14(B). be.

[0273] The transistor shown in FIG. 14B includes a substrate 100 and a gate electrode provided on the substrate 100. a gate insulating film 312 provided to cover the gate electrode 304; A pair of electrodes 416 provided on the pair of electrodes 312 and a pair of electrodes 41 6 and an oxide semiconductor film 406 provided at least partially in contact with the gate insulating film 312 A protective insulating film 418 is provided to cover the pair of electrodes 416 and the oxide semiconductor film 406. And, it has.

[0274] Note that the pair of electrodes 416, the oxide semiconductor film 406, and the protective insulating film 418 are each formed in the same The counter electrode 116, the oxide semiconductor film 106, and the protective insulating film 318 are formed in the same manner and in the same manner. The above-mentioned material may be used.

[0275] The transistors shown in FIGS. 15 and 16 are compared with the transistors shown in FIGS. Although this makes the process somewhat complicated, the parasitic capacitance is reduced, and the channel length is shortened. As the temperature increases, the threshold voltage is less likely to shift in the negative direction, making it an excellent This structure is suitable for miniaturized transistors that require specific electrical characteristics.

[0276] Next, the structure of the transistor shown in FIG. 15 will be described. FIG. 15(A) shows a transistor A cross-sectional view corresponding to the dashed line AB shown in FIG. and Figure 15(C).

[0277] The transistor shown in FIG. 15B includes a substrate 100 and a base insulating film provided over the substrate 100. A protective film 520 provided around the base insulating film 502 and the base insulating film 502 are and a high resistance region 506a and a low resistance region 506b provided on the protective film 520. an oxide semiconductor film 506; a gate insulating film 512 provided over the oxide semiconductor film 506; A gate electrode 50 is provided overlapping the oxide semiconductor film 506 with a gate insulating film 512 interposed therebetween. 4, a sidewall insulating film 524 provided in contact with the side surface of the gate electrode 504, and an oxide semiconductor film A pair of electrodes provided over the oxide semiconductor film 506 and in contact with at least a portion of the oxide semiconductor film 506 516, and a gate electrode 504, a sidewall insulating film 524, and a pair of electrodes 516 are provided to cover the gate electrode 504, the sidewall insulating film 524, and the pair of electrodes 516. A pair of electrodes 51 are formed through an opening in the protective insulating film 518. 6 and a wiring 522 provided in contact with the wiring 522.

[0278] The pair of electrodes 516, the gate insulating film 512, the protective insulating film 518, and the gate electrode 50 4 respectively include a pair of electrodes 116, a gate insulating film 112, a protective insulating film 318 and a gate The electrode 104 may be provided using the same method and materials as those of the electrode 104 .

[0279] The oxide semiconductor film 506 is formed by etching using the gate electrode 504 as a mask and a gate insulating film therebetween. An impurity having a function of reducing the resistance of the oxide semiconductor film is added to the low-resistance region 506b. In this case, the region to which the impurity is not added is the high resistance region 50. The impurity may be phosphorus, nitrogen, boron, or the like. After the heating, the material is activated by heating at a temperature between 250 and 650°C. When doped using ion implantation, the amount of This is preferable because the amount of hydrogen mixed into the oxide semiconductor film is reduced. This does not exclude the use of smearing methods.

[0280] The oxide semiconductor film 506 is formed by using the gate electrode 504 and the sidewall insulating film 524 as a mask. and adding an impurity having a function of reducing the resistance of the oxide semiconductor film through the gate insulating film. Alternatively, the low resistance region 506b may be formed. Specifically, the region overlapping the sidewall insulating film 524 is a low-resistance region 506a. This results in a high resistance region 506a rather than a resistance region 506b (see FIG. 15(C)).

[0281] Note that the impurities are added through the gate insulating film, so that the impurities can be added to the oxide semiconductor film. However, the damage caused when the gate insulating film is not interposed can be reduced. It is also acceptable to inject pure material.

[0282] The base insulating film 502 is formed by the same method and using the same material as the base insulating film 102. The insulating film may be processed to provide a groove.

[0283] The protective film 520 is formed by depositing an insulating film so as to fill the grooves formed in the base insulating film 502. Then, the CMP process is performed to form the insulating film.

[0284] The protective film 520 may be silicon oxynitride, silicon nitride, aluminum oxide, or aluminum nitride. , hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide One or more of aluminum, tantalum oxide and magnesium oxide are selected and used in a single layer or laminated layer. That's good.

[0285] The protective film 520 is heated at a temperature of 250° C. or higher and 450° C. or lower, preferably 150° C. or higher and 800° C. or lower. It is preferable that the material has a property of not allowing oxygen to pass therethrough even after heat treatment for, for example, one hour in a temperature range. I wish.

[0286] Due to the above-mentioned properties, when the protective film 520 is provided around the base insulating film 502, At this time, oxygen released from the base insulating film 502 by heat treatment flows outwardly from the transistor. In this way, oxygen is held in the base insulating film 502, , preventing a decrease in the field effect mobility of a transistor and reducing the variation in threshold voltage; Furthermore, the reliability can be improved.

[0287] However, a structure in which the protective film 520 is not provided may also be adopted.

[0288] The sidewall insulating film 524 is formed by providing an insulating film covering the gate electrode 504 and then etching the insulating film. The etching is performed by etching the sidewall. The insulating film 524 is formed in a self-aligned manner by performing a highly anisotropic etching process on the insulating film. For example, it is preferable to use a dry etching method. The etching gas used in the process is, for example, trifluoromethane, octafluorocyclohexane, etc. Gases containing fluorine such as butane and tetrafluoromethane are examples of etching gases. In the dry etching method, a high frequency voltage is applied to the substrate. It is preferable to use a reactive ion etching method (RIE method) for adding a thin film.

[0289] The wiring 522 may be formed using a material similar to that of the gate electrode 104 .

[0290] Next, the structure of the transistor shown in FIG. 16 will be described. FIG. 16(A) shows a transistor 16(A) is a top view of the device shown in FIG. 16(B). be.

[0291] The transistor shown in FIG. 16B has a substrate 100 and a groove provided on the substrate 100. A pair of electrodes 616 are provided in the grooves of the base insulating film 602. A high resistance region 606a and a low resistance region 606b are provided on the insulating film 602 and the pair of electrodes 616. The oxide semiconductor film 606 having the region 606b and the gate insulating film 606 provided over the oxide semiconductor film 606 A gate insulating film 612 is provided to overlap with the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. A gate electrode 604 is formed on the gate insulating film 612 and a gate electrode 604 is formed on the gate insulating film 612. The protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film A wiring 622 is provided in contact with the pair of electrodes 616 through an opening provided in 606; has.

[0292] Note that the gate insulating film 612, the protective insulating film 618, the oxide semiconductor film 606, the wiring 622, and the The gate electrode 604 is formed of the gate insulating film 112, the protective insulating film 318, and the oxide semiconductor The film 506, the wiring 522 and the gate electrode 104 are constructed in the same manner and with the same materials. That's good.

[0293] The base insulating film 602 is formed by the same method and using the same material as the base insulating film 102. The insulating film may be processed to provide a groove.

[0294] The pair of electrodes 616 are formed by forming a conductive film so as to fill a groove provided in the base insulating film 602. The insulating film 11 may be formed by forming a film and then performing a CMP process.

[0295] The field-effect mobility of a transistor will be described below with reference to FIGS.

[0296] The field-effect mobility of transistors, not limited to oxide semiconductors, is often lower than expected for various reasons. The field effect mobility measured is lower than the expected field effect mobility. Examples of defects include defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using the Vinson model, the field effect mobility assuming there are no defects inside the semiconductor is calculated as Derived theoretically.

[0297] The field effect mobility of a conventional transistor is μ0, and there is some potential barrier in the semiconductor. The measured field effect mobility μ when assuming the presence of (grain boundaries, etc.) is expressed by Equation 3. .

[0298]

number

[0299] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In the Levinson model, it is assumed that the height of the potential barrier E comes from defects. This is expressed by Equation 4.

[0300]

number

[0301] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the The dielectric constant, n, is the carrier density per unit area of ​​the channel, C ox is the gate per unit area Insulating film capacitance, V gs is the gate voltage, and t is the channel thickness. In the case of the following semiconductor layers, the thickness of the channel may be the same as the thickness of the semiconductor layer.

[0302] Drain current in the linear region I ds is expressed by Equation 5.

[0303]

number

[0304] Here, L is the channel length and W is the channel width. Here, L and W are set to 10 μm. Also, V ds is the drain voltage.

[0305] Taking the logarithm of both sides of Equation 5 gives Equation 6.

[0306]

number

[0307] The right side of Equation 6 is V gs Since it is a function of ln(Ids / V gs ), the horizontal axis is 1 / V gs The defect density N can be calculated from the slope of the line obtained by plotting the measured values ​​as That is, the V gs -I ds The characteristic gives the defect density N in the semiconductor.

[0308] The defect density N in a semiconductor depends on the substrate heating temperature during semiconductor film formation. In-Sn-, where the ratio of Sn and Zn is In:Sn:Zn=1:1:1 [atomic ratio] When an oxide semiconductor film formed using a Zn-O sputtering target is used, the oxidation The defect density N in semiconductors is 1×10 12 / cm 2 It will be about that amount.

[0309] Based on the above-mentioned defect density N in the oxide semiconductor, the following calculation is made using Equation 3 and Equation 4: The field effect mobility of the original transistor is 120 cm 2 / Vs. Therefore, There are no defects in the oxide semiconductor or at the interface between the oxide semiconductor and the gate insulating film, making this an ideal The field effect mobility μ0 of a transistor is 120 cm 2 However, the defect In many oxide semiconductors, the field-effect mobility of a transistor is 30 cm 2 / Vs .

[0310] Even if there are no defects inside the semiconductor, the transistors can be generated by scattering at the interface between the channel and the gate insulating film. The transport properties of the transistor are affected. The current at a distance x from the gate-insulator interface is The field effect mobility μ1 is expressed by Equation 7.

[0311]

number

[0312] Here, D is the electric field strength due to the gate electrode, B is a constant, and l is the depth at which the effect of interface scattering occurs. B and l can be obtained by measuring the electrical characteristics of the transistor. From actual measurements of the electrical characteristics of transistors using semiconductors, B = 4.75 × 10 7 cm / s, l = 10 nm. When D increases, that is, V gs When the value of It can be seen that the field effect mobility μ1 decreases as the term increases.

[0313] An ideal structure with no defects in the oxide semiconductor and at the interface between the oxide semiconductor and the gate insulating film The results of calculating the field effect mobility μ2 of such a transistor are shown in FIG. Using the Sentaurus Device manufactured by Nopsis, the band gap of oxide semiconductors The bias voltage was 2.8 eV, the electron affinity was 4.7 eV, the relative dielectric constant was 15, and the thickness was 15 nm. In addition, the work function of the gate is set to 5.5 eV, and the work functions of the source and drain are set to 4.6 eV. The thickness of the gate insulating film was 100 nm, and the relative dielectric constant was 4.1. The length and width of the channel are both 10 μm. ds was set to 0.1V.

[0314] As shown in Figure 27, V gs is around 1V, and the field effect mobility μ2 is 100cm 2 / Vs It has a peak of more than V gs If the temperature increases further, the effect of interface scattering increases, and the It can be seen that the field effect mobility μ2 decreases.

[0315] The results of calculations for miniaturizing such an ideal transistor are shown in Figs. This is shown in Figure 30. Note that the calculation is based on the assumption that the transistor has the structure shown in Figure 15.

[0316] Here, the resistivity of the low resistance region 506b is set to 2×10 -3 Ωcm, and the width of the gate electrode 504 is set to 3 The width of the sidewall insulating film 524 is 5 nm, and the channel width is 40 nm. For convenience, the region is referred to as a high resistance region 506a. It is assumed to be an intrinsic semiconductor.

[0317] The calculation was performed using the Sentaurus Device manufactured by Synopsys. I of the transistor with the structure shown in FIG. 5(B) ds (solid line) and field-effect mobility μ (dotted line) )V gs It is a dependency. ds is V ds is 1V, and the field effect mobility μ is V ds The calculation is performed with a gate insulating film thickness of 15 nm. 28(A), 10 nm is shown in FIG. 28(B), and 5 nm is shown in FIG. 28(C). are shown in the figures.

[0318] From Figure 28, the thinner the gate insulating film, the lower the off-state (here, V gs -3V to 0V The drain current I ds On the other hand, the peak of the field effect mobility μ value and on state (here V gs refers to the range from 0V to 3V.) Drain current I ds There is no noticeable change in V gs is close to 1V and I ds The semiconductor device This exceeds the 10 μA required for devices such as mori.

[0319] Similarly, calculations are performed for the transistor shown in FIG. The transistor shown in FIG. 1 is an oxide semiconductor having a high resistance region 507a and a low resistance region 507b. 15B in that it has a semiconductor film 507. Specifically, the transistor shown in FIG. 15C has an oxide semiconductor layer overlapping the sidewall insulating film 524. The region of the conductor film 507 is included in the high resistance region 507a. This transistor has an offset region as wide as the film 524. The width is also called the offset length (Loff) (see FIG. 15(A)). Note that Loff is conveniently The width is the same on the top, left and right.

[0320] In the transistor shown in FIG. 15(C), Loff is set to 5 nm, and the drain current I ds (solid line) and field-effect mobility μ (dotted line) gs The dependency is shown in Figure 29. Note that I ds V ds is 1V, and the field effect mobility μ is V ds is calculated as 0.1V. Here, FIG. 29(A) shows the case where the thickness of the gate insulating film is 15 nm, and FIG. FIG. 29B shows the case where the thickness is set to 5 nm, and FIG. 29C shows the case where the thickness is set to 5 nm.

[0321] FIG. 30 shows the case where Loff is set to 15 nm from the structure of the transistor shown in FIG. The drain current I ds (solid line) and field-effect mobility μ (dotted line) gs dependence In addition, I ds V dsis 1V, and the field effect mobility μ is V ds to 0.1V The calculation is performed with the gate insulating film thickness set to 15 nm as shown in Figure 30(A). The case where the thickness is set to 10 nm is shown in FIG. 30(B), and the case where the thickness is set to 5 nm is shown in FIG. 30(C). vinegar.

[0322] From the calculation results shown in Fig. 29 and Fig. 30, as in Fig. 28, it is found that the gate insulating film is thin The lower the voltage, the more the off-state (V gs The drain voltage at Flow I ds On the other hand, the peak value of the field-effect mobility μ and the on-state (here, V gs but The drain current I ds It can be seen that there is no significant change in .

[0323] In addition, the peak of the field effect mobility μ is 80 cm in FIG. 2 / Vs, as shown in Figure 29. So 60cm 2 / Vs, 40cm in Figure 30 2 As / Vs and Loff increase, In addition, the I ds It can be seen that the same tendency is observed. On the other hand, in the on state, I ds decreases with increasing offset length Loff, but in the off state I ds The decrease in V is much slower than that in V. gs but At around 1V, I ds This exceeds the 10μA required for memory, etc.

[0324] Next, the electrical characteristics of a transistor including an oxide semiconductor will be described.

[0325] FIG. 31 shows a top view and a cross-sectional view of the structures of the fabricated transistors (samples 1 and 2). FIG. 31(A) is a top view of a transistor. FIG. 31(B) is a top view of a transistor. FIG. 2 is a cross-sectional view corresponding to dashed line AB in FIG.

[0326] The transistor shown in FIG. 31B includes a substrate 700 and a base insulating film provided over the substrate 700. a base insulating film 702, an oxide semiconductor film 706 provided over the base insulating film 702, and an oxide semiconductor film A pair of electrodes 716 in contact with the oxide semiconductor film 706 and a pair of electrodes 716 A gate insulating film 712 is provided, and the oxide semiconductor film 706 is provided with the gate insulating film 712 interposed therebetween. The gate electrode 704 is provided so as to overlap with the gate insulating film 712 and the gate electrode 704. The insulating interlayer 718 is provided to cover the semiconductor substrate 101 and is connected to the semiconductor substrate 101 through an opening provided in the insulating interlayer 718. A wiring 722 connected to the pair of electrodes 716 and a layer insulating film 718 and a layer insulating film 722 are provided to cover the wiring 722. and a protective insulating film 728 formed thereon.

[0327] The substrate 700 is a glass substrate, the insulating base film 702 is a silicon oxide film, and the oxide The semiconductor film 706 is an In-Sn-Zn-O film, and the pair of electrodes 716 is a tungsten The gate insulating film 712 is a silicon oxide film, and the gate electrode 704 is a nitride film. The interlayer insulating film 718 is a silicon oxynitride film. The laminated structure is made of a composite film and a polyimide film. The wiring 722 is made of a titanium film, an aluminum film, A laminated structure in which a titanium film is formed in this order is formed, a polyimide film is formed as a protective insulating film 728, Each was used.

[0328] In the transistor having the structure shown in FIG. 31A, the gate electrode 704 and a pair of electrodes The width of the overlap with the oxide semiconductor film 706 is referred to as Lov. The protrusion of pole 716 is called dW.

[0329] A method for manufacturing the transistors (samples 1 and 2) having the structure shown in FIG. 31B will be described below. do.

[0330] First, a plasma treatment was performed on the surface of the substrate 700 in an argon atmosphere. A sputtering apparatus was used, and a bias power of 200 W (RF) was applied to the substrate 700 side. This was done for three minutes.

[0331] Next, while maintaining the vacuum state, a silicon oxide film, which is the base insulating film 702, is formed to a thickness of 300 nm. The film was deposited to a thickness of 100 nm.

[0332] The silicon oxide film was formed using a sputtering device in an oxygen atmosphere at 1500W (RF) power. The sputtering target was a quartz sputtering target. The substrate heating temperature during film formation was 100°C.

[0333] Next, the upper surface of the base insulating film 702 was subjected to CMP processing and flattened to approximately Ra=0.2 nm.

[0334] Next, an In-Sn-Zn-O film, which is an oxide semiconductor film, was formed to a thickness of 15 nm.

[0335] The In-Sn-Zn-O film was formed using a sputtering device with a volume ratio of argon:oxygen=2:3. The deposition was performed in a mixed atmosphere of 100 W (DC). The In-Sn-Zn-O sputtering was performed with an atomic ratio of In:Sn:Zn=1:1:1. The substrate heating temperature during film formation was 200°C.

[0336] Next, only sample 2 was subjected to heat treatment at a temperature of 650°C. The heat treatment was first performed in a nitrogen atmosphere. Heat treatment was performed for 1 hour at 400°C, and then heat treatment was performed for another 1 hour in an oxygen atmosphere while maintaining the temperature. went.

[0337] Next, the oxide semiconductor film is processed by a photolithography process to form an oxide semiconductor film 70. 6 was formed.

[0338] Next, a tungsten film was formed to a thickness of 50 nm.

[0339] The tungsten film was formed by sputtering in an argon atmosphere at a power of 1000 W (D The substrate heating temperature during film formation was 200°C.

[0340] Next, the tungsten film is processed by a photolithography process to form a pair of electrodes 716. Formed.

[0341] Next, a silicon oxide film serving as a gate insulating film 712 was formed to a thickness of 100 nm. The relative dielectric constant of the silicon oxide film was set to 3.8.

[0342] The silicon oxide film, which is the gate insulating film 712, was formed in the same manner as the base insulating film 702. .

[0343] Next, a tantalum nitride film and a tungsten film were deposited in this order at 15 nm and 13 nm, respectively. The film was deposited to a thickness of 5 nm.

[0344] The tantalum nitride film was formed using a sputtering device in a mixed atmosphere of argon:nitrogen = 5:1. The film was formed with a power of 1000 W (DC). Note that the substrate was not heated during film formation.

[0345] The tungsten film was formed by sputtering in an argon atmosphere at a power of 4000 W (D The substrate heating temperature during film formation was 200°C.

[0346] Next, the tantalum nitride film and the tungsten film are processed by a photolithography process. Then, a gate electrode 704 was formed.

[0347] Next, a silicon oxynitride film serving as an interlayer insulating film 718 was formed to a thickness of 300 nm.

[0348] The silicon oxynitride film that becomes the interlayer insulating film 718 is formed by a PCVD apparatus using a monosilane: subacid The film was formed in a mixed atmosphere of 1:200 fluorine and nitrogen at a power of 35 W (RF). The substrate heating temperature was set to 325°C.

[0349] Next, a silicon oxynitride film that will become the interlayer insulating film 718 is applied by a photolithography process. I did the work.

[0350] Next, a photosensitive polyimide film that will become the interlayer insulating film 718 was formed to a thickness of 1500 nm.

[0351] Next, the film used in the photolithography process of the silicon oxynitride film that will become the interlayer insulating film 718 is The photosensitive polyimide that will become the interlayer insulating film 718 is exposed to light using a photomask, and then developed. Next, a heat treatment is performed to harden the photosensitive polyimide film and combine it with the silicon oxynitride film. The heat treatment was performed in a nitrogen atmosphere at a temperature of 300° C. went.

[0352] Next, a titanium film, an aluminum film and a titanium film were deposited in this order at 50 nm, 10 The films were deposited to thicknesses of 0 nm and 5 nm.

[0353] The titanium film was formed using a sputtering device for both layers in an argon atmosphere at a power of 1000 W. The film was deposited as DC. The substrate was not heated during deposition.

[0354] The aluminum film was formed by sputtering in an argon atmosphere at a power of 1000 W (D C) was deposited. Note that the substrate was not heated during deposition.

[0355] Next, the titanium film, the aluminum film, and the titanium film are processed by a photolithography process. Thus, the wiring 722 was formed.

[0356] Next, a photosensitive polyimide film serving as a protective insulating film 728 was formed to a thickness of 1500 nm.

[0357] Next, a photosensitive polyimide film is formed by using the photomask used in the photolithography process of the wiring 722. The mide film is exposed to light and then developed to form an opening in the protective insulating film 728 that exposes the wiring 722. Successful.

[0358] Next, a heat treatment was performed to harden the photosensitive polyimide film. The heat treatment was carried out in the same manner as for the photosensitive polyimide film used for the film 718 .

[0359] Through the above steps, a transistor having the structure shown in FIG.

[0360] Next, the electrical characteristics of the transistor having the structure shown in FIG.

[0361] V in the transistor with the structure shown in FIG. gs -I ds The characteristics of sample 1 were measured. The results are shown in FIG. 32(A) and the results for sample 2 are shown in FIG. 32(B). The transistor has a channel length L of 3 μm, a channel width W of 10 μm, and Lov of 3 μm on each side. m (total 6 μm), dW is 3 μm on each side (total 6 μm). ds is 10V Ta.

[0362] In addition, when Sample 1 and Sample 2 are compared, the oxide semiconductor film is formed after heat treatment. The inventors believe that this is due to the heat treatment. It was considered that this was because the impurity concentration in the oxide semiconductor film was reduced by the oxidation. A heat treatment is performed after the formation of the oxide semiconductor film to reduce the impurity concentration in the oxide semiconductor film. As a result, the field effect mobility of the transistor can be brought closer to the ideal field effect mobility. I know it's coming.

[0363] In this manner, by performing heat treatment after the oxide semiconductor film is formed, impurities in the oxide semiconductor film can be reduced. It can be seen that the dopant concentration is reduced, resulting in an increased field effect mobility of the transistor.

[0364] Next, a BT test was performed on Sample 1 and Sample 2. The BT test will be described below.

[0365] First, the substrate heating temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds Special The properties were measured. ds indicates the drain voltage (potential difference between the drain and source). The substrate heating temperature was set to 150°C, and V ds Next, the gate insulating film 712 V so that the electric field strength applied to is 2MV / cm gs Apply 20V to the Time was then held. Next, V gsNext, the substrate heating temperature was set to 25°C, and V ds 1 0V, and the V of the transistor gs -I ds This measurement was called the Plus BT test.

[0366] Similarly, first, the substrate heating temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs - I ds Next, the substrate heating temperature was set to 150°C, and V ds is set to 0.1V Next, V was set so that the electric field strength applied to the gate insulating film was -2MV / cm. gs To - A voltage of 20 V was applied and held for 1 hour. gs was set to 0 V. Next, the substrate was heated At a temperature of 25°C, V ds is set to 10V, and the V of the transistor gs -I ds Measurements were carried out. This is called a negative BT test.

[0367] The results of the positive BT test of sample 1 are shown in Figure 33(A), and the results of the negative BT test are shown in Figure 33(B). The results of the positive BT test of sample 2 are shown in FIG. 34(A), and the results of the negative BT test are shown in FIG. The results are shown in Figure 34(B). Note that the figure shows the V before and after the BT test. gs -I ds Variation in characteristics Arrows are provided for ease of understanding.

[0368] The threshold voltage shifts of sample 1 due to the positive BT test and the negative BT test are 1.80V and -0.42V. In addition, the positive BT test and negative BT test of sample 2 The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively.

[0369] Samples 1 and 2 showed little change in threshold voltage before and after the BT test, and were therefore highly reliable. It can be seen that this is a high-performance transistor.

[0370] Next, the relationship between the substrate heating temperature and the electrical characteristics of the transistor of Sample 2 was evaluated. Ta.

[0371] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov was 3 μm on one side (total 6 μm), and dW was 0 μm. ds The voltage was set to 10V. The substrate heating temperatures were -40°C, -25°C, 25°C, 75°C, 125°C, and 150°C. Ta.

[0372] Figure 35(A) shows the relationship between the substrate heating temperature and the threshold voltage, and Figure 35(B) shows the relationship between the substrate heating temperature and the voltage The relationship between field effect and mobility is shown.

[0373] From FIG. 35(A), it can be seen that the higher the substrate heating temperature, the lower the threshold voltage. The range was -40°C (0.38V) to 150°C (-1.08V).

[0374] In addition, from FIG. 35(B), it is clear that the higher the substrate heating temperature, the lower the field effect mobility. The range is -40°C (37.4cm 2 / Vs) ~150℃(33.4cm 2 / Vs).

[0375] Thus, it can be seen that the variation in electrical characteristics of Sample 2 is small within the above-mentioned temperature range. .

[0376] It is clear that the above-described transistor has high field-effect mobility and high reliability.

[0377] Similarly, a transistor that can be used in a memory element according to one embodiment of the present invention has a channel width of 1 μm. The off-state current per m was evaluated.

[0378] The sample was prepared in the same manner as sample 2. The transistor used for the measurement had an L of 3 μm. , W is 10 cm, Lov is 2 μm, and dW is 0 μm.

[0379] Figure 36 shows the relationship between the off-state current of a transistor and the inverse of the substrate heating temperature (absolute temperature) during measurement. For simplicity, the value shown here is the reciprocal of the substrate heating temperature multiplied by 1000 during measurement (1 000 / T) is plotted on the horizontal axis.

[0380] The method for measuring the off-state current of a transistor is briefly explained below. The transistor that becomes this state is called a first transistor.

[0381] The drain of the first transistor is connected to the floating gate FG. The gate FG is connected to the gate of the second transistor.

[0382] First, the first transistor is turned off, and then a charge is applied to the floating gate FG. It should be noted that a constant drain voltage is applied to the second transistor.

[0383] At this time, the charge on the floating gate FG gradually leaks through the first transistor. When the charge on the floating gate FG is released, the source potential of the second transistor becomes The amount of change in the source potential over time is used to determine the leakage current from the first transistor. The amount of charge can be estimated and the off current can be measured.

[0384] As shown in Figure 36, when the substrate heating temperature during measurement was 85°C, the channel The off-state current per 1 μm of width is 2 × 10 -21 A / μm (2zA / μm).

[0385] As described above, it is found that the off-state current of the fabricated transistor is extremely small.

[0386] As described above, the oxide semiconductor film has a crystal region in which the c-axis is parallel to the normal vector of the top surface. By using this, a transistor having high reliability can be obtained.

[0387] In addition, a transistor with excellent electrical characteristics can be obtained.

[0388] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0389] (Embodiment 4) In this embodiment, a liquid crystal display device manufactured using the transistor described in Embodiment 3 will be described. Note that in this embodiment, a transistor according to one embodiment of the present invention is used in a liquid crystal display device. An example of applying the EL( A transistor according to an embodiment of the present invention is used in a display device. It would be easily conceivable for a person skilled in the art to apply the same to the above-mentioned embodiments.

[0390] FIG. 17 shows a circuit diagram of a liquid crystal display device that uses an active matrix driving method. , source lines SL_1 to SL_a, gate lines GL_1 to GL_b, and and a plurality of pixels 2200. The pixel 2200 includes a transistor 2230 and a capacitor. The pixel 2200 includes a pixel 2200 and a liquid crystal element 2210. The pixel 2200 is arranged in a matrix. The pixel portion of a liquid crystal display device is formed by arranging the source lines or gate lines. In such a case, the line is referred to as a source line SL or a gate line GL.

[0391] The transistor described in Embodiment 3 can be used as the transistor 2230. By using a transistor according to one embodiment of the present invention, a display with high display quality and high reliability can be obtained. A display device can be obtained.

[0392] The gate line GL is connected to the gate of the transistor 2230, and the source line SL is connected to the gate of the transistor 2230. The drain of the transistor 2230 is connected to the source of the capacitor 2220. The capacitor electrode of the capacitor 2220 is connected to one of the pixel electrodes of the liquid crystal element 2210. The other capacitance electrode and the other pixel electrode of the liquid crystal element 2210 are connected to a common electrode. The common electrode may be provided in the same layer and made of the same material as the gate lines GL.

[0393] The gate lines GL are connected to a gate drive circuit. The transistor may include the transistors shown in FIG.

[0394] The source line SL is connected to a source driver circuit as described in the third embodiment. The transistor may include the transistors shown in FIG.

[0395] Either or both of the gate driver circuit and the source driver circuit are provided by a separately prepared substrate. Formed on a board and then processed by COG (Chip On Glass), wire bonding, or T Even if you use a method such as AB (Tape Automated Bonding) good.

[0396] In addition, since transistors are easily damaged by static electricity, it is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element.

[0397] When a potential is applied to the gate line GL so as to be equal to or higher than the threshold voltage of the transistor 2230, The charge supplied from the source line SL becomes the drain current of the transistor 2230. After one row is charged, the transistor 2230 in that row When the capacitor 2220 is turned off, the voltage is no longer applied from the source line SL. The charge stored in the capacitors on the next row can then maintain the required voltage. The bottom 2220 is charged. In this manner, charging is performed on rows 1 to b.

[0398] Note that the transistor 2230 has a low off-state current and therefore The charge held in the capacitor 2220 is less likely to escape, making it possible to reduce the capacitance of the capacitor 2220. Therefore, the power consumption required for charging can be reduced.

[0399] As described above, by using a transistor according to one embodiment of the present invention, display quality can be improved. Therefore, a highly reliable liquid crystal display device can be obtained.

[0400] This embodiment mode can be used in appropriate combination with other embodiment modes.

[0401] (Embodiment 5) In this embodiment, a memory cell which is a semiconductor device is formed using the transistor described in Embodiment 3. An example of fabricating a rib will be described.

[0402] A typical example of a volatile memory is a memory element that is made up of transistors and has a capacitance. By storing electric charges in the bottom, information is stored in the DRAM (Dynamic Random Access Memory). It uses circuits such as flip-flops to store memory contents. There is SRAM (Static Random Access Memory).

[0403] The transistor described in Embodiment 3 can be used as part of a transistor included in a memory. This can be done.

[0404] For example, the memory element to which the transistor described in Embodiment 3 is applied will be described with reference to FIG. I will explain it below.

[0405] FIG. 18A shows a cross-sectional view of a memory cell which is a memory element. A plate 3100, a base insulating film 3102 provided on the substrate 3100, and a base insulating film 3102 A protective film 3120 is provided around the insulating base film 3102 and a protective film 3120 is provided on the insulating base film 3102 and the protective film 3120. The oxide semiconductor film 31 has a high resistance region 3106a and a low resistance region 3106b. 3106, a gate insulating film 3112 provided over the oxide semiconductor film 3106, and a gate insulating film a gate electrode 3104 overlapping with the oxide semiconductor film 3106 with a gate electrode 3112 interposed therebetween; A sidewall insulating film 3124 in contact with the side surface of the gate electrode 3104 and at least an oxide semiconductor film 3 106 and a pair of electrodes 3116 in contact with each other.

[0406] Here, a substrate 3100, a base insulating film 3102, a protective film 3120, and an oxide semiconductor film 3106 , a gate insulating film 3112, a gate electrode 3104, a sidewall insulating film 3124, and a pair of electrodes 3 116 are the substrate 100, the base insulating film 502, the protective film 520, and the oxide semiconductor film 50 6, a gate insulating film 512, a gate electrode 504, a sidewall insulating film 524 and a pair of electrodes 516 It may be provided by the same method and using the same materials as those in the above.

[0407] The transistor 3340 is covered with an interlayer insulating film 3 328 and an electrode 3326 provided on the interlayer insulating film 3328. One of the electrodes 3116, the interlayer insulating film 3328, and the electrode 3326 form a capacitor. 3330. Note that the figure shows a parallel plate type capacitor, but it is possible to increase the capacitance by Therefore, the capacitor may be a stack type or a trench type. The electrode 3326 may be formed using a material similar to that of the protective insulating film 518. The electrode 516 may be formed from a material selected from the materials used for the electrode 516 .

[0408] Further, the transistor 3340 is provided to cover the interlayer insulating film 3328 and the electrode 3326. and a second insulating film 3328 formed on the first insulating film 3118. and a wiring 3122 that connects to the other of the pair of electrodes 3116 through the opening. Although not shown, a protective film is provided to cover the interlayer insulating film 3118 and the wiring 3122. By providing the protective film, the surface conduction of the interlayer insulating film 3118 can be prevented. This can reduce the minute leakage current caused by the above problem, thereby reducing the off-state current of the transistor. The wiring 3122 may be provided in the same manner and with the same materials as the wiring 522. stomach.

[0409] FIG. 18B is a circuit diagram corresponding to the memory cell shown in FIG. 18A. , a bit line BL, a word line WL, a sense amplifier SAmp, a transistor Tr, The transistor Tr corresponds to the transistor 3340. Capacitor C corresponds to capacitor 3330.

[0410] The change in the potential held in the capacitor over time is caused by the off-current of the transistor Tr as shown in FIG. It is known that the charge gradually decreases as shown in (C). Initially, the charge is increased from V0 to V1. As time passes, the potential decreases to VA, which is the limit point at which data1 can be read out. This period is called the retention period T_1. In other words, in the case of a binary memory cell, during the retention period T_1 A refresh operation needs to be performed.

[0411] Here, by applying the transistor 3340 to the transistor Tr, the transistor Since the off-current of Tr can be made extremely small, the hold period T_1 can be extended. In other words, it is possible to take a longer interval between refresh operations, so that the memory cells Power consumption can be reduced. In addition, the high reliability of the transistor Tr ensures high reliability. Therefore, a memory cell with high performance can be obtained.

[0412] The off-current shown in the third embodiment is 1×10 -18 Below A, 1×10 -21 A or below or 1×10 -24 If a memory cell is configured with transistors with a capacity of 0.01A or less, the refresh operation The interval between shots can range from a few tens of seconds to a few decades.

[0413] As described above, by using a transistor according to one embodiment of the present invention, it is possible to improve reliability. Therefore, a memory element with low power consumption can be obtained.

[0414] Next, another example of a memory element to which the transistor described in Embodiment 3 is applied will be described with reference to FIG. I will use this to explain.

[0415] FIG. 19A shows a cross-sectional view of a memory cell which is a memory element. A substrate 3100, a base insulating film 3382 provided on the substrate 3100, and a base insulating film 338 A first resistor region 3384a, a second resistor region 3384b, and a third resistor region 3384c provided on the second A semiconductor film 3384 having a resistance region 3384c and a gate electrode provided on the semiconductor film 3384. A gate insulating film 3386 overlaps the first resistor region 3384a via the gate insulating film 3386. A gate electrode 3392 is provided on the side of the gate electrode 3392. A sidewall insulating film 33 In the semiconductor film 3384, a first resistor region 3384a, a second resistor region 3384b, and a The resistance decreases in the order of the first resistance region 3384b and the third resistance region 3384c. In the region 3384a, a voltage equal to or higher than the threshold voltage of the transistor 3350 is applied to the gate electrode 3392. When a voltage is applied, a channel is formed. Although not shown, the third resistor region 3384c is in contact with the third resistor region 3384c. A pair of electrodes may be provided.

[0416] The transistor 3350 may be formed using a semiconductor film other than an oxide semiconductor film, for example, polycrystalline silicon. Group 14 elements such as silicon films, single crystal silicon films, polycrystalline germanium films, and single crystal germanium films A transistor using a semiconductor film having an oxide layer may be used. A transistor using a compound semiconductor film may also be used.

[0417] In addition, an interlayer insulating film 3396 is provided in contact with the transistor 3350. Since the insulating film 3396 is also a surface on which the transistor 3340 is formed, The upper surface is made as flat as possible. Specifically, the upper surface of the interlayer insulating film 3396 has a Ra of 1 nm. It is preferable that the thickness is not more than 0.3 nm, and more preferably not more than 0.1 nm.

[0418] The interlayer insulating film 3396 may have a single layer or a stacked structure. The layer in contact with the insulating film is preferably an insulating film that releases oxygen by heat treatment.

[0419] The transistor 3340 is provided on the interlayer insulating film 3396. One of the pair of electrodes 3116 of the transistor 3350 is connected to the gate electrode 3351 of the transistor 3350. 392. In addition, the pair of electrodes 3116 of the transistor 3340 A capacitor 3330 is formed by one of the electrodes, an interlayer insulating film 3328, and an electrode 3326. Although the figure shows a parallel plate type capacitor, a stator type is used to increase the capacitance. The capacitor may be of the block or trench type.

[0420] FIG. 19B is a circuit diagram corresponding to the memory cell shown in FIG. 19A. , a transistor Tr_1, and a gate line GL_1 connected to the gate of the transistor Tr_1. a source line SL_1 connected to the source of the transistor Tr_1; 2, a source line SL_2 connected to the source of the transistor Tr_2, and a transistor Tr A drain line DL_2 connected to the drain of the capacitor C, The capacitance line CL connected to the other end of the capacitor C, the drain of the transistor Tr_1, and and a floating gate FG connected to the gate of the transistor Tr_2. , transistor Tr_1 corresponds to transistor 3340, and transistor Tr_2 corresponds to It corresponds to transistor 3350 , and capacitor C corresponds to capacitor 3330 .

[0421] In addition, in the above-mentioned memory element, the transistor Tr This utilizes the fact that the apparent threshold voltage of _2 fluctuates. For example, C) is the potential V of the capacitance line CL CL and the drain current I flowing through transistor Tr_2 ds This is a diagram explaining the relationship with _2.

[0422] Here, the floating gate FG adjusts the potential via the transistor Tr_1. For example, the potential of the source line SL_1 is set to VDD. The potential of L_1 is set to a potential equal to or higher than the threshold voltage Vth of the transistor Tr_1 plus VDD. By doing so, the potential of the floating gate FG can be set to HIGH. By setting the potential of the gate line GL_1 to be equal to or lower than the threshold voltage Vth of the transistor Tr_1, The potential of the floating gate FG can be set to LOW.

[0423] Therefore, V shown with FG=LOW CL -I ds _2 curve and FG=HIGH V CL -I ds _2 curves can be obtained. That is, when FG=LOW, V CL I at 0V ds Since _2 is smaller, the data is 0. Also, when FG=HIGH, V CLI at 0V ds Since _2 is larger, it becomes data 1. In this way, It can be memorized.

[0424] Here, by applying the transistor 3340 to the transistor Tr_1, Since the off-current of the transistor Tr_1 can be made extremely small, the flow shown in FIG. The charge stored in the ground gate FG is unintentionally leaked through the transistor Tr_1. This can prevent data from being read and written to the hard disk. This allows data to be stored for a long period of time. In addition, since the field effect mobility of the transistor Tr_1 is high, the memory element can be operated at high speed. can be done.

[0425] As described above, when a transistor according to one embodiment of the present invention is used as at least a part of a memory element, By doing so, it is possible to realize a semiconductor device that is highly reliable, consumes little power, and is capable of high-speed operation. can be obtained.

[0426] This embodiment mode may be used in combination with other embodiment modes.

[0427] (Embodiment 6) At least the transistor described in Embodiment 3 and the semiconductor device described in Embodiment 5 Also used in part to configure the CPU (Central Processing Unit) It is possible.

[0428] FIG. 20A is a block diagram showing a specific configuration of a CPU. The PU is a logic unit (ALU) on a board 1190. nit) 1191, ALU controller 1192, instruction decoder 1193 , an interrupt controller 1194, a timing controller 1195, and a register 11 96, register controller 1197, bus interface (Bus I / F) 119 8. Rewritable ROM1199 and ROM interface (ROM I / F) The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 20(A) is merely an example showing a simplified configuration. However, actual CPUs have a wide variety of configurations depending on their applications.

[0429] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0430] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes to register 1196 according to the CPU state.

[0431] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generator CLK2 is provided to generate the clock signal CLK2. Supply to the circuit.

[0432] In the CPU shown in FIG. 20A, the semiconductor device according to the fifth embodiment is provided in a register 1196. It is being done.

[0433] In the CPU shown in FIG. 20A, the register controller 1197 controls the ALU 1191. The holding operation in the register 1196 is selected according to the instruction from the register 1 In the semiconductor device of 196, data is held by a phase inversion element or a capacitance Select whether to hold the data by the phase inversion element. In this case, the power supply voltage is supplied to the semiconductor device in the register 1196. When data is to be held, the data is rewritten to the capacitor and the register 119 The supply of power supply voltage to the semiconductor device in the power supply circuit 6 can be stopped.

[0434] Regarding the power supply shutdown, as shown in FIG. 20(B) or FIG. 20(C), A switching element is connected between the nodes to which the power supply potential VDD or VSS is applied. The circuits in FIG. 20(B) and FIG. 20(C) are explained below. Make a statement.

[0435] In FIG. 20B and FIG. 20C, a switch for controlling the supply of a power supply potential to a semiconductor device is shown. FIG. 1 is a configuration example of a memory circuit including a transistor using an oxide semiconductor as an active layer in a switching element. Shows.

[0436] The memory device shown in FIG. 20B includes a switching element 1141 and a semiconductor device 1142. Specifically, each of the semiconductor devices 114 The semiconductor device group 1143 can be the semiconductor device described in Embodiment 5. Each semiconductor device 1142 has a high-level The power supply potential VDD of the semiconductor device group 1143 is supplied to each of the The semiconductor device 1142 has a potential of a signal IN and a potential of a low-level power supply potential VSS. It is given.

[0437] In FIG. 20B, the transistor shown in the third embodiment is used as the switching element 1141. The transistor is driven by a signal SigA applied to its gate. The switching is controlled by this.

[0438] In FIG. 20B, the switching element 1141 has only one transistor. However, the present invention is not limited to this configuration, and a plurality of transistors may be included. In the case where the switching element 1141 has a plurality of transistors functioning as switching elements, In this case, the plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0439] FIG. 20C shows each of the semiconductor devices 1142 included in the semiconductor device group 1143. A low-level power supply potential VSS is supplied to the 1 shows an example of a memory device. A semiconductor device group 1143 is enabled by a switching element 1141. 11. Controlling the supply of a low-level power supply potential VSS to each of the semiconductor devices 1142 It is possible.

[0440] A switch is provided between a group of semiconductor devices and a node to which a power supply potential VDD or a power supply potential VSS is applied. When a switching element is installed to temporarily stop the CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, which reduces power consumption. For example, a user of a personal computer may input information into an input device such as a keyboard. The CPU can be stopped while the It is possible.

[0441] In addition, the transistor described in Embodiment 3 and the semiconductor device described in Embodiment 5 can be used. This makes it possible to obtain a CPU that is capable of high-speed operation with low power consumption.

[0442] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor). processor), custom LSI, FPGA (Field Programmable Gauge It can also be applied to LSIs such as MOSFET's (MOSFET gate arrays).

[0443] This embodiment mode may be used in combination with other embodiment modes.

[0444] (Embodiment 7) In this embodiment mode, the semiconductor device described in any of the embodiments 3 to 6 can be applied. Examples of possible electronic devices will now be described.

[0445] FIG. 21A shows a portable information terminal. The portable information terminal includes a housing 4300 and a button 4301. , a microphone 4302, a display unit 4303, a speaker 4304, and a camera 430 5 and has the function of a mobile phone.

[0446] FIG. 21B shows a display. The display includes a housing 4310 and a display portion 431. 1 and

[0447] FIG. 21C shows a digital still camera. The digital still camera has a housing 4320. The terminal 4320 includes a button 4321, a microphone 4322, and a display unit 4323.

[0448] With the use of a semiconductor device according to one embodiment of the present invention, an electronic device with high quality can be obtained. Cut.

[0449] This embodiment mode can be used in appropriate combination with other embodiment modes. EXAMPLES

[0450] In this example, the crystalline state of the oxide semiconductor film was evaluated by XRD.

[0451] In this example, the oxide semiconductor films of all the samples have the c-axis orientation shown in Embodiment 1. A sputtering method using an oxide semiconductor having a crystal domain parallel to the normal vector of the surface The target is used, and the deposition apparatus shown in the second embodiment is used to deposit the film by sputtering. It is membraned.

[0452] First, a difference in crystallinity of an oxide semiconductor film depending on the flatness of a base film was evaluated. The method for preparing the sample is as follows.

[0453] Sample 4 is a silicon wafer with a 300 nm thick silicon oxide film deposited by sputtering. The upper surface of the silicon oxide film had a thickness Ra of 0.9 nm.

[0454] Sample 5 is a silicon wafer with a 300 nm thick silicon oxide film deposited by sputtering. A silicon oxide film was formed and the top surface was flattened by CMP. The surface had an Ra of 0.2 nm.

[0455] For sample 6, a thermal oxide film with a thickness of 300 nm was formed on a silicon wafer. The surface had an Ra of 0.2 nm.

[0456] Next, on each of the samples 4 to 6, a 100 nm thick In-Ga The atomic ratio of In:Ga:Zn was 1:1:1. A sputtering target of In-Ga-Zn-O compound was used, and the power was set at 0.5 kW ( DC), oxygen gas 45sccm, pressure 0.4Pa, substrate heating temperature 250℃ The membrane was

[0457] FIG. 37 shows XRD spectra of Samples 4 to 6. XRD was performed by Bruke r Using the AXS X-ray diffraction device D8 ADVANCE, the out-of-plane method was measured.

[0458] As shown in FIG. 37, the peak intensity indicating crystallinity near 2θ=30° is greater in Sample 5 and Sample 4 than in Sample 4. It was found that the thickness of the sample 6 was larger than that of the sample 7. In other words, the flatness of the underlying film is high, and the obtained thickness is It can be seen that the crystallinity of the oxide semiconductor film is improved.

[0459] Next, the difference in crystallinity of the oxide semiconductor film depending on the substrate heating temperature during film formation was evaluated. The method for preparing the material is shown below.

[0460] Each sample was prepared by sputtering a 200 nm thick In-Ga-Z The compound was prepared by depositing an In:Ga:Zn=1:1:1 [atomic ratio] The sputtering target for In-Ga-Zn-O compound was used, and the power was set at 5 kW (DC), argon gas at 50sccm and oxygen gas at 50sccm, pressure at 0. 6 Pa, and the substrate heating temperature was room temperature (sample 7), 120°C (sample 8), 150°C (sample 9), and The film was formed at 170° C. (sample 10).

[0461] FIG. 38 shows the XRD spectra of Samples 7 to 10. Using the AXS X-ray diffraction device D8 ADVANCE, The measurement was performed by the method.

[0462] As shown in FIG. 38, the peak intensity indicating crystallinity near 2θ=30° was larger in Sample 10, Sample 9, Sample 8, and In other words, the higher the substrate heating temperature during film formation, the higher the It can be seen that the crystallinity of the oxide semiconductor film is improved.

[0463] Next, the difference in crystallinity of the oxide semiconductor film depending on the ratio of oxygen gas during film formation was evaluated. The method for preparing the sample is as follows.

[0464] Each sample was prepared by sputtering a 200 nm thick In-Ga-Z The compound was prepared by depositing an In:Ga:Zn=1:1:1 [atomic ratio] The sputtering target for In-Ga-Zn-O compound was used, and the power was set at 5 kW (DC), oxygen gas ratio (oxygen gas flow rate is the ratio of oxygen gas flow rate and argon gas flow rate) (divided by the total) was 10% (sample 11), 20% (sample 12), 30% (sample 13), 50% (sample 14), 70% (sample 15), 100% (oxygen only, sample 16) The film was formed at a pressure of 0.6 Pa and a substrate heating temperature of 170°C.

[0465] FIG. 39 shows the XRD spectra of Samples 11 to 16. Out-of-Plan analysis was performed using the X-ray diffraction device D8 ADVANCE manufactured by Ker AXS. Measured using method e.

[0466] As shown in FIG. 39, the peak intensity indicating crystallinity is higher in Sample 16, Sample 15, Sample 14, Sample 13, and Sample In other words, the ratio of oxygen gas during film formation was high. It can be seen that the crystallinity of the resulting oxide semiconductor film is improved.

[0467] From this example, it was found that the higher the flatness of the underlying film and the higher the substrate heating temperature during film formation, the better the film formation. It has been found that the higher the ratio of oxygen gas during deposition, the higher the crystallinity of the resulting oxide semiconductor film. do. [Explanation of symbols]

[0468] 10 Deposition chamber 10a Deposition chamber 10b Deposition chamber 10c Deposition chamber 11 Substrate supply room 12 Load lock chamber 12a Load lock chamber 12b Load lock chamber 13 Transport Room 14 Cassette port 15 Substrate heating chamber 20a Deposition chamber 20b Deposition chamber 22a Load lock chamber 22b Load lock chamber 25 Substrate heating chamber 32 Sputtering targets 34 Target Holder 54 Refiner 58a Cryopump 58b Cryopump 58c Turbomolecular Pump 58d Cryopump 58e Cryopump 58f Cryopump 59 Vacuum Pump 59a Vacuum pump 59b Vacuum pump 59c Vacuum Pump 60 Mass Flow Controller 62 Gas heating mechanism 66 Cryotrap 100 Substrates 102 Undercoat insulating film 104 Gate electrode 106 Oxide semiconductor film 112 Gate insulating film 116 Pair of Electrodes 204 Gate electrode 206 Oxide Semiconductor Film 212 Gate insulating film 216 Pair of Electrodes 304 Gate electrode 306 Oxide Semiconductor Film 312 Gate insulating film 316 Pair of Electrodes 318 Protective insulating film 406 Oxide Semiconductor Film 416 Pair of Electrodes 418 Protective insulating film 502 Undercoat insulating film 504 Gate electrode 506 Oxide Semiconductor Film 506a High resistance area 506b Low resistance region 507 Oxide Semiconductor Film 507a High resistance area 507b Low resistance region 512 Gate insulating film 516 Pair of Electrodes 518 Protective insulating film 520 Protective film 522 Wiring 524 Sidewall insulating film 602 Undercoat insulating film 604 Gate electrode 606 Oxide Semiconductor Film 606a High resistance area 606b Low resistance region 612 Gate insulating film 616 Pair of Electrodes 618 Protective insulating film 622 Wiring 700 Substrates 702 Undercoat insulating film 704 Gate electrode 706 Oxide Semiconductor Film 712 Gate insulating film 716 Pair of Electrodes 718 Interlayer insulating film 722 Wiring 728 Protective insulating film 1141 Switching element 1142 Semiconductor devices 1143 Semiconductor Devices 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 pixels 2210 Liquid crystal element 2220 Capacitor 2230 Transistor 3100 Substrate 3102 Undercoat insulating film 3104 Gate electrode 3106 Oxide semiconductor film 3106a High resistance area 3106b Low resistance region 3112 Gate insulating film 3116 Pair of electrodes 3118 Interlayer insulating film 3120 Protective film 3122 Wiring 3124 Sidewall insulating film 3326 Electrode 3328 Interlayer insulating film 3330 Capacitor 3340 Transistor 3350 Transistor 3382 Undercoat insulating film 3384 Semiconductor film 3384a First Resistance Region 3384b Second Resistance Zone 3384c Third Resistance Zone 3386 Gate insulating film 3392 Gate electrode 3394 Sidewall insulating film 3396 Interlayer insulating film 4300 Chassis 4301 Button 4302 Microphone 4303 Display section 4304 Speaker 4305 Camera 4310 Case 4311 Display section 4320 Case 4321 Button 4322 Microphone 4323 Display section 5001 Series 5002 Compound powder 5012 Compound film 5022 Compound film 5032 Plate-shaped compound 5042 Plate-shaped compound Type 5101 5102 Slurry 5112 Compound film 5122 Compound film 5132 Plate compounds

Claims

[Claim 1] InO Ｘ Raw materials, MO Ｙ Raw materials (M is Sn, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu) and ZnO Ｚ The raw materials are mixed in a specified ratio, The mixed material is fired and then pulverized to prepare an In-M-Zn-O compound powder; A part of the In-M-Zn-O compound powder is spread in a mold and molded, and then the molded product is fired and pressurized to form a compound film; a different part of the In-M-Zn-O compound powder is spread on the compound film in the mold and molded, and then the compound film is increased in thickness by firing and pressure treatment; The step of increasing the thickness of the compound film is carried out n times (n is a natural number) to form the compound film into a plate-like compound having a thickness of 2 mm or more and 20 mm or less; A method for producing a sputtering target, comprising bonding the plate-like compound to a backing plate.

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