Method for manufacturing circuit member and method for manufacturing semiconductor package

Abstract

To suppress falling of a filler by grinding when a circuit member including semiconductor chips is manufactured by a method including a step of forming a flat surface by grinding and polishing a sealing resin layer containing the filler.SOLUTION: A method for manufacturing a circuit member includes steps of: preparing a sealing structure 10 having a sealing resin layer 1 which has a first surface and a second surface and forms the first surface, and semiconductor chips 2 which are arranged inside the first surface and have chip bodies 2A and connection terminals 2B provided on the chip bodies; grinding the sealing resin layer from a first surface side by a grindstone including abrasive grains having a maximum value of a particle diameter of 30 μm or less, and thereby exposing the connection terminals to the first surface; flattening the ground first surface by chemical mechanical polishing; and forming a re-wiring layer 3a including wiring 30 connected to the semiconductor chips on the first surface, and thereby obtaining a circuit member 15 having the sealing resin layer, the semiconductor chips and the re-wiring layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to methods of manufacturing circuit components and methods of manufacturing semiconductor packages. [Background technology]

[0002] Electronic components may be manufactured by a method including polishing an encapsulation layer containing a filler such as fused silica, and forming a redistribution layer on the polished surface (eg, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 225599 [Patent Document 2] US Patent Application Publication No. 2019 / 0115320 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to form a fine rewiring layer on the encapsulating resin layer with high accuracy, it is desirable for the encapsulating resin layer to have a sufficiently flat surface. When a flat surface is formed by grinding and polishing an encapsulating resin layer containing a filler, according to the findings of the present inventors, the loss of the filler during the grinding step may affect the formation of a flat surface after polishing.

[0005] The present disclosure relates to suppressing the fall-off of filler due to grinding when manufacturing a circuit component including a semiconductor chip by a method that includes forming a flat surface by grinding and polishing an encapsulating resin layer containing a filler. [Means for solving the problem]

[0006] The present disclosure includes the following. [1] A plate-shaped sealing structure having a first surface and a second surface on the reverse side of the first surface, the sealing structure including a sealing resin layer containing a filler and forming the first surface, and one or more semiconductor chips having a chip body and a connection terminal provided on the body, the chip body being disposed on the inner side of the first surface; grinding the sealing resin layer from the first surface side with a grindstone containing abrasive grains, thereby exposing the connection terminals on the first surface; planarizing the ground first surface by chemical mechanical polishing; forming a rewiring layer including wiring connected to the semiconductor chip on the first surface, thereby obtaining a circuit member having the sealing resin layer, the semiconductor chip, and the rewiring layer; Including, The maximum particle size of the abrasive grains is 30 μm or less. A method for manufacturing a circuit component. [2] The method according to [1], wherein the maximum grain size of the abrasive grains is 10 μm or less. [3] The method according to [1] or [2], wherein the average grain size of the abrasive grains is 3.40 μm or less. [4] The method according to any one of [1] to [3], wherein the maximum particle size of the filler is 50 μm or less. [5] The method according to any of [1] to [4], wherein the semiconductor chip is exposed on the second surface, and the method further comprises forming a backside redistribution layer on the second surface, the backside redistribution layer including wiring connected to the semiconductor chip. [6] The method according to any one of [1] to [5], wherein the circuit member is an interposer for a semiconductor package. [7] Preparing a circuit member by a method according to any one of [1] to [6]; mounting a plurality of semiconductor components on the rewiring layer; Including, Two or more of the semiconductor components are electrically connected to each other via the semiconductor chip and the rewiring layer. A method for manufacturing a semiconductor package. Effect of the Invention

[0007] In the case of manufacturing a circuit component including a semiconductor chip by a method including forming a flat surface by grinding and polishing an encapsulating resin layer including a filler, it is possible to suppress the fall-off of the filler due to grinding, and as a result, a sufficiently flat surface can be efficiently formed by polishing after grinding. [Brief description of the drawings]

[0008] [Figure 1] 1A to 1C are process diagrams showing an example of a method for manufacturing a circuit member. [Diagram 2] 1A to 1C are process diagrams showing an example of a method for manufacturing a circuit member. [Diagram 3] 1A to 1C are process diagrams showing an example of a method for manufacturing a circuit member. [Figure 4] 5A to 5C are schematic diagrams showing an example of a method for grinding an encapsulating resin layer. [Diagram 5] FIG. 1 is a cross-sectional view showing an example of a semiconductor package. [Figure 6] 13 is an image of the surface of the sealing resin layer after grinding. [Figure 7] 13 is an image of the surface of the sealing resin layer after grinding. [Figure 8] 13 is an image of the surface of the sealing resin layer after grinding. [Figure 9] 13 is an image of the surface of the sealing resin layer after grinding. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present invention is not limited to the following examples.

[0010] 1 and 2 are process diagrams showing an example of a method for manufacturing a circuit member. The method shown in FIG. 1 and FIG. 2 includes the steps of preparing a plate-shaped sealing structure 10 having a first surface S1 and a second surface S2 on the back side thereof, the sealing structure 10 including a sealing resin layer 1 containing a filler and forming the first surface S1, and two or more semiconductor chips 2 having a chip body 2A and a connection terminal 2B (e.g., copper terminals) provided on the chip body 2A, arranged inside the first surface S1, grinding the sealing resin layer 1 from the first surface S1 side with a grindstone containing abrasive grains, thereby exposing the connection terminals on the first surface S1, planarizing the ground first surface S1 by chemical mechanical polishing, and forming a rewiring layer 3a including wiring 30 connected to the semiconductor chip 2 on the first surface S1, thereby obtaining a circuit member 15 having the sealing resin layer 1, the semiconductor chip 2, and the rewiring layer 3a. The sealing structure 10 may have a through via 5 arranged around the semiconductor chip 2 and sealed by the sealing resin layer 1.

[0011] In the example of FIG. 1, the sealing structure 10 is formed on a temporary fixing material 75 provided on a support 70. The sealing structure 10 is formed by a method including, for example, temporarily fixing a semiconductor chip 2 and a through via 5 on the temporary fixing material 75 as shown in FIG. 1(a) and forming a sealing resin layer 1 that seals the semiconductor chip 2 and the through via 5 as shown in FIG. 1(b). The sealing resin layer 1 is formed so that the semiconductor chip 2 and the through via 5 are sealed on the inside of the first surface S1. In this example, in the sealing structure 10 thus formed, the surface of the semiconductor chip 2 on the temporary fixing material 75 side is exposed to the second surface S2 of the sealing structure 10.

[0012] The encapsulating resin layer 1 can be formed, for example, by compression molding of an encapsulating material containing a filler. The encapsulating material may be a thermosetting resin composition containing an epoxy resin, a curing agent for the epoxy resin, and a filler. The filler may contain an inorganic filler. The inorganic filler may be, for example, particles containing one or more inorganic materials selected from aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride, and silica, and may in particular be a silica filler containing silica.

[0013] The maximum particle size of the filler contained in the encapsulating resin layer 1 or the encapsulating material for forming the same may be 50 μm or less, 30 μm or less, or 20 μm or less, or 5 μm or more, or 10 μm or more. The maximum particle size of the filler means the maximum particle size in the cumulative particle size distribution of the filler measured by a laser diffraction method.

[0014] The content of the filler (e.g., silica filler) in the sealing resin layer 1 may be, for example, 50 mass% or more, 60 mass% or more, 70 mass% or more, or 80 mass% or more, or 90 mass% or less, based on the mass of the sealing resin layer 1.

[0015] Next, the encapsulating resin layer 1 of the encapsulating structure 10 is ground from the first surface S1 side. FIG. 4 is a schematic diagram showing an example of a method for grinding the encapsulating resin layer. In the case of the method shown in FIG. 4, a plurality of grindstones 82 are pressed against the first surface S1 of the encapsulating structure 10 temporarily fixed to the temporary fixing material 75. The plurality of grindstones 82 are attached to an annular base 81 along the circumferential direction of the base 81. A grinding wheel 80 having the base 81 and the grindstones 82 is attached to a mount portion 87 of a grinding device 85. The mount portion 87 is fixed to a tip of a spindle 86 of the grinding device 85. By rotating the spindle 86, the grindstone 82 rotates and moves on the first surface S1 around the axial direction of the spindle 86. The rotation speed of the spindle 86 may be, for example, 2000 rpm or more and 3000 rpm or less. The sealing resin layer 1 is usually ground until the connection terminals 2B of the semiconductor chip 2 are exposed on the first surface S1, as shown in (c) of Fig. 2. By grinding, the through vias 5 are also usually exposed on the first surface S1.

[0016] The grindstone 82 is an aggregate of a plurality of abrasive grains, and the abrasive grains may be, for example, diamond. The maximum grain size of the abrasive grains constituting the grindstone 82 may be 30 μm or less. If the maximum grain size of the abrasive grains is small, the fall-off of the filler due to grinding is suppressed. If the fall-off of the filler due to grinding is small, a sufficiently flat surface can be efficiently formed by polishing following grinding. From the same viewpoint, the maximum grain size of the abrasive grains may be 25 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less. The maximum grain size of the abrasive grains may be 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, or 5 μm or more. A grindstone having a grain size in the desired range can be selected from those commercially available as grinding wheels.

[0017] In this specification, the grain size of the abrasive grains means the maximum value of the distance between two parallel lines sandwiching an enlarged two-dimensional image of the abrasive grains constituting the grindstone. The enlarged image including the two-dimensional image of the abrasive grains can be obtained, for example, by a scanning electron microscope. The grain size of the abrasive grains is obtained by binarizing the enlarged image so that the two-dimensional image of the abrasive grains can be identified, and measuring the distance between two parallel lines sandwiching the two-dimensional image of each abrasive grain observed in the binarized image. The maximum value of the grain size measured for the multiple abrasive grains constituting the grindstone is regarded as the maximum grain size of the abrasive grains. For example, the maximum value of the grain size when the grain size of 100 or more abrasive grains obtained from the grindstone is measured can be regarded as the maximum grain size of the abrasive grains constituting the grindstone.

[0018] The average grain size of the abrasive grains constituting the grindstone may be 3.40 μm or less. A small average grain size of the abrasive grains may also contribute to suppression of the filler from falling off due to grinding. The average grain size of the abrasive grains is the average grain size measured for a plurality of abrasive grains observed within a predetermined range, measured by the same method as that for measuring the maximum grain size of the abrasive grains. The average grain size of the abrasive grains may be 3.00 μm or less, 2.50 μm or less, 2.00 μm or less, 1.80 μm or less, or 1.60 μm or less, or may be 1.00 μm or more.

[0019] The arithmetic mean roughness Ra of the first surface S1 before grinding and polishing may be 0.15 μm or less, 0.10 μm or less, or 0.07 μm or less, or 0.01 μm or more. The maximum height roughness Rz of the first surface S1 before grinding and polishing may be 0.70 μm or less, 0.60 μm or less, 0.50 μm or less, or 0.40 μm or less, or 0.10 μm or more. The arithmetic mean height Sa of the first surface S1 before grinding and polishing may be 0.30 μm or less, 0.20 μm or less, 0.10 μm or less, or 0.01 μm or more. The maximum height Sz of the first surface S1 before grinding and polishing may be 6.0 μm or less, 5.0 μm or less, 4.0 μm or less, or 3.0 μm or less, or 1.0 μm or more.

[0020] The ground first surface S1 usually has fine irregularities. The first surface S1 is polished by chemical mechanical polishing (CMP) so that the fine irregularities are removed to flatten the first surface S1. The conditions for the chemical mechanical polishing are adjusted within the range of normal conditions for polishing an encapsulating resin layer. Since little filler falls off during the grinding stage, a sufficiently flat polished surface (first surface S1) can be efficiently formed by chemical mechanical polishing (CMP).

[0021] The arithmetic mean roughness Ra of the first surface S1 after polishing may be 0.03 μm or less, 0.02 μm or less, or 0.01 μm or less, or may be 0.001 μm or more. The maximum height roughness Rz of the first surface S1 after polishing may be 0.15 μm or less, 0.10 μm or less, 0.05 μm or less, 0.04 μm or less, or 0.03 μm or less, or may be 0.01 μm or more. The arithmetic mean height Sa of the first surface S1 after polishing may be 0.20 μm or less, 0.15 μm or less, 0.10 μm or less, 0.05 μm or less, 0.04 μm or less, 0.03 μm or less, 0.02 μm or less, or 0.01 μm or less, or may be 0.001 μm or more. The maximum height Sz of the first surface S1 after polishing may be 4.0 μm or less, 3.0 μm or less, 2.0 μm or less, 1.5 μm or less, or 1.0 μm or less, or may be 0.1 μm or more.

[0022] On the first surface S1 after polishing, a rewiring layer 3a including wiring 30 connected to the semiconductor chip 2 and an insulating resin layer 35 filling the periphery of the wiring 30 is formed. As a result, as shown in (d) of FIG. 2, a circuit member 15 including the sealing resin layer 1, the semiconductor chip 2, and the rewiring layer 3a is formed on the temporary fixing material 75. The rewiring layer 3a can be formed by a normal method including photolithography and plating. If the first surface S1 after polishing is sufficiently flat, the rewiring layer 3a including fine wiring can be formed efficiently with high accuracy. The minimum value of the width of the wiring may be, for example, 5.0 μm or less, 4.0 μm or less, 3.0 μm or less, 2.5 μm or less, or 2.0 μm or less. The width of the wiring here means the width of the wiring when the rewiring layer is viewed from its thickness direction.

[0023] 3, after the formation of the redistribution layer 3a, the circuit member 15 may be separated from the temporary fixing material 75, and a back-side redistribution layer 3b may be formed on the second surface S2. The back-side redistribution layer 3b also includes wiring 30 connected to the semiconductor chip 2, and an insulating resin layer 35 that fills the periphery of the wiring 30. The wiring 30 in the redistribution layer 3a and the wiring 30 in the back-side redistribution layer 3b may be connected to each other via a through via 5 that penetrates the semiconductor chip 2.

[0024] A semiconductor package can be manufactured by a method including mounting a plurality of semiconductor components on the rewiring layer 3a of the obtained circuit member 15. In this case, the obtained circuit member 15 is used, for example, as an interposer for a semiconductor package. Two or more of the plurality of semiconductor components are electrically connected to each other via the semiconductor chip 2 and the rewiring layer 3a.

[0025] FIG. 5 is a cross-sectional view showing an example of a semiconductor package having a circuit member 15 as an interposer. The semiconductor package 100 shown in FIG. 5 includes a wiring board 50, a circuit member 15 as an interposer, and a first semiconductor component 21 and a second semiconductor component 22 mounted on the circuit member 15. The circuit member 15 is disposed between the wiring board 50 and the first semiconductor component 21 and the second semiconductor component 22. In the example of FIG. 5, the circuit member 15 includes a sealing resin layer 1, a first semiconductor chip 2a, a second semiconductor chip 2b, a through via 5, a rewiring layer 3a, and a backside rewiring layer 3b. The semiconductor package 100 further includes a sealing layer 40 provided on the circuit member 15 and sealing the first semiconductor component 21 and the second semiconductor component 22. The through via 5 electrically connects the wiring of the rewiring layer 3a and the wiring of the backside rewiring layer 3b. An underfill material 45 may be filled between the circuit member 15 and the wiring board 50.

[0026] A plurality of connection parts 61 that electrically connect the first semiconductor component 21 and the second semiconductor component 22 to the circuit member 15 are provided between them. A plurality of connection parts 62 that electrically connect the wiring board 50 to the circuit member 15 are provided between them. A plurality of bumps 65 are provided on the surface of the wiring board 50 opposite to the circuit member 15 (interposer).

[0027] The first semiconductor component 21 and the second semiconductor component 22 are electrically connected to each other via the first semiconductor chip 2a and the rewiring layer 3a. For example, the first semiconductor component 21 may be a system on chip (SoC), and the second semiconductor component 22 may be a memory chip. The second semiconductor chip 2b may be an integrated passive device (IPD).

[0028] Verification Test Below, a verification test was conducted in which an encapsulating resin layer formed on a silicon wafer was ground with a grinding wheel containing diamond abrasive grains, and the surface of the encapsulating resin layer after grinding was polished to verify the relationship between the size of the abrasive grains of the grinding wheel, the detachment of filler from the encapsulating resin layer, and the surface roughness of the encapsulating resin layer. Grindstone

[0029] Grinding wheels A, B, C and D were prepared. Abrasive grains collected from the grinding wheels were observed with a laser microscope (Evident Co., Ltd.) and multiple images of a rectangular area of ​​258 μm in length and 259 μm in width were obtained. The obtained images were binarized. In the binarized images, the maximum value of the distance between two parallel lines sandwiching the two-dimensional image of each abrasive grain was recorded as the grain size of the abrasive grain. The grain sizes of all abrasive grains observed in the multiple images were measured and their maximum, minimum and average values ​​were calculated. The results are shown in Table 1. The number of measurement points is the total number of grains confirmed in the multiple binarized images.

[0030] [Table 1]

[0031] Formation of sealing resin layer A sealing resin layer covering the entire surface of one side of a silicon wafer was formed by compression molding of a sealing material, which was a thermosetting resin composition containing an epoxy resin and a silica filler. The content of the silica filler in the sealing material was 76% by volume based on the volume of the sealing material. The top cut diameter (maximum particle diameter) of the silica filler in the sealing material was 20 μm.

[0032] grinding A disk-shaped laminate consisting of a silicon wafer and an encapsulating resin layer was attached to a grinding device, and the encapsulating resin layer was ground using grinding wheels A, B, C, or D attached to the grinding holes. The surface roughness of the encapsulating resin layer after grinding (arithmetic mean roughness Ra and maximum height roughness Rz according to JIS B0601:2013, arithmetic mean height Sa and maximum height Sz according to ISO 25178) was measured using a non-contact measurement method. The type of grinding wheel and the measured surface roughness are shown in Table 2. be.

[0033] The surface of the encapsulating resin layer after grinding was observed with a laser microscope. Figures 6, 7, 8, and 9 are images of the encapsulating resin layer surface after polishing in tests #1, #2, #3, and #4, respectively. In test #4, a large amount of silica filler was found to have fallen off due to grinding, but in tests #1, #2, and #3, almost no large depressions due to the falling off of silica filler were found.

[0034] polishing The ground surfaces of the encapsulating resin layers #1, #3, and #4 were polished by chemical mechanical polishing for 5 minutes. The surface roughness of the encapsulating resin layer after polishing was measured in the same manner as the surface roughness after grinding. The measurement results are shown in Table 2. From a comparison of the surface roughness after polishing of #1 and #3 with the surface roughness after polishing of #4, it was confirmed that a sufficiently flat surface can be efficiently formed by a method including grinding with a grindstone having a maximum grain size of 30 μm or less.

[0035] [Table 2] [Explanation of symbols]

[0036] 1...encapsulating resin layer, 2...semiconductor chip, 2a...first semiconductor chip, 2b...second semiconductor chip, 2A...chip body, 2B...connecting terminal, 3a...rewiring layer, 3b...rear side rewiring layer, 5...through via, 10...encapsulating structure, 15...circuit member (interposer), 21...first semiconductor component, 22...second semiconductor component, 30...wiring, 35...insulating resin layer, 40...encapsulating layer, 45...underfill material, 50...wiring board, 61, 62...connecting portion, 65...bump, 70...support, 75...temporary fixing material, 80...grinding wheel, 81...base, 82...grinding stone, 85...grinding device, 86...spindle, 87...mounting portion, 100...semiconductor package, S1...first surface, S2...second surface.

Claims

1. preparing a plate-like sealing structure having a first surface and a second surface on the back side thereof, the sealing structure including a sealing resin layer containing a filler and forming the first surface, and one or more semiconductor chips having a chip body and a connection terminal provided on the chip body, the semiconductor chip being disposed inside the first surface; grinding the sealing resin layer from the first surface side with a grindstone containing abrasive grains, thereby exposing the connection terminals on the first surface; planarizing the ground first surface by chemical mechanical polishing; forming a rewiring layer including wiring connected to the semiconductor chip on the first surface, thereby obtaining a circuit member having the sealing resin layer, the semiconductor chip, and the rewiring layer; Including, The maximum particle size of the abrasive grains is 30 μm or less. A method for manufacturing a circuit component.

2. The method according to claim 1 , wherein the maximum grain size of the abrasive grains is 10 μm or less.

3. The method of claim 1 , wherein the abrasive grains have an average grain size of 3.40 μm or less.

4. The method according to claim 1 , wherein the maximum particle size of the filler is 50 μm or less.

5. 10. The method of claim 1, wherein the semiconductor chip is exposed on the second surface, the method further comprising forming a backside redistribution layer on the second surface including wiring connected to the semiconductor chip.

6. The method of claim 1 , wherein the circuit member is an interposer for a semiconductor package.

7. Providing a circuit member according to the method of claim 1; mounting a plurality of semiconductor components on the rewiring layer; Including, Two or more of the semiconductor components are electrically connected to each other via the semiconductor chip and the rewiring layer. A method for manufacturing a semiconductor package.

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