Semiconductor device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A resistance element Rg is embedded in a trench TR formed in a well region PW of a semiconductor substrate. The resistance element Rg and the trench RT have an endless shape in a plan view. The resistance element Rg is connected to a first contact member PG electrically connected to a gate pad GP and a second contact member PG electrically connected to a gate wire GW. A third contact member PG electrically connecting an emitter electrode EE to a well region PW is disposed in a region surrounded by an inner periphery of the endless resistance element Rg between the first contact member PG and the second contact member PG in a Y direction.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a resistive element electrically connected to a gate pad. [Background technology]

[0002] As a power device, an IGBT (Insulated Gate Bipolar Transistor) that uses a vertical trench gate structure is known. In a semiconductor device (semiconductor chip) that includes a power device, a resistive element is connected to the gate pad as part of a protection circuit for protecting the semiconductor device from a surge voltage applied to the gate pad.

[0003] For example, Patent Document 1 discloses a semiconductor device including an IGBT and a resistive element connected to a gate pad. The resistive element is formed in a polysilicon film provided on a semiconductor substrate via an insulating film (silicon oxide film). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-82244 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in a motor control system using a three-phase motor, an IGBT is used as a driver for the motor. The emitter electrode of the high-side IGBT and the collector electrode of the low-side IGBT are connected in series.

[0006] As disclosed in Patent Document 1, defects may occur in the p-type collector region formed on the underside of the semiconductor substrate of the high-side IGBT due to damage during dicing, etc. In that case, when the low-side IGBT is switched at high speed, impact ionization occurs in the high-side IGBT, causing carriers (holes) to be discharged to the surface side of the semiconductor substrate.

[0007] That is, when an emitter potential higher than the potential of the collector electrode is applied to the emitter electrode, the body diode operates and a large number of carriers are generated in the semiconductor substrate. In this state, when the applied potential state is changed and a collector potential higher than the potential of the emitter electrode is applied to the collector region, holes are discharged to the upper surface side of the semiconductor substrate. When the collector potential is increased, the remaining carriers make it difficult for the depletion layer to spread in the semiconductor substrate. When the collector potential is further increased, a high electric field is created inside the semiconductor substrate, and impact ionization occurs. The holes generated by impact ionization are discharged to the surface side of the semiconductor substrate.

[0008] At this time, a high potential rise occurs in the p-type well region near the resistive element for the gate pad, which can cause a problem of dielectric breakdown in the silicon oxide film formed under the resistive element.

[0009] In the IGBT studied by the present inventors, a trench is formed in a p-type well region, and a thin silicon oxide film is interposed in the trench to form a resistive element for the gate. The thin silicon oxide film has a thickness equal to that of the gate insulating film of the IGBT. Compared to the technology described in Patent Document 1, the parasitic resistance of the p-type well region increases in the trench formation portion, so a higher potential rise occurs in the p-type well region. In addition, since the silicon oxide film separating the resistive element and the p-type well region is thin, dielectric breakdown of the silicon oxide film is more likely to occur. This causes a problem of reduced reliability of the semiconductor device.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0011] A brief outline of a representative embodiment of the present invention will be described below.

[0012] A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type having a first main surface, a gate pad, a gate wiring, and an emitter electrode formed on the first main surface, a well region of a second conductivity type different from the first conductivity type formed on the first main surface, a trench formed endlessly in a plan view in the well region, and a resistive element endless in a plan view embedded in the trench through an insulating film. The semiconductor device further includes a first contact member connected to the resistive element, a second contact member arranged at a predetermined interval from the first contact member in a first direction which is the longitudinal direction of the resistive element and connected to the resistive element, and a third contact member located between the first contact member and the second contact member in the first direction in a plan view, arranged in a region surrounded by the inner periphery of the resistive element, and connected to the well region. The gate pad is electrically connected to the resistive element through the first contact member, the gate wiring is electrically connected to the resistive element through the second contact member, and the emitter electrode is electrically connected to the well region through the third contact member. Effect of the Invention

[0013] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0014] [Figure 1] 1 is a plan view showing an entire semiconductor device in a first embodiment. [Diagram 2] 1 is an equivalent circuit diagram of a semiconductor device in a first embodiment. [Diagram 3] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 6] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 7] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 8] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 9] FIG. 11 is a plan view of a main portion of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a plan view of a main portion of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a plan view of a main portion of a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 13 is a plan view of a main portion of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0016] Furthermore, in order to facilitate understanding of the shape of each element, Figures 3, 4, 9, 10, 11 and 12 do not accurately depict the hierarchical relationships of each element in some places.

[0017] In addition, for the sake of simplicity, in the reference symbols in Figs. 4, 9, 10, 11 and 12, CH3(PG) is referred to as CH3, and CH4(PG) is referred to as CH4.

[0018] (Embodiment 1) <Structure of Semiconductor Device> A semiconductor device 100 according to a first embodiment will be described below with reference to Figures 1 to 8. Figure 1 is a plan view showing a semiconductor chip which is the semiconductor device 100.

[0019] As shown in Fig. 1, the semiconductor device 100 includes a cell region 1A and a peripheral region 1B. A plurality of cells constituting an IGBT are formed in the cell region 1A. The plurality of cells are divided into, for example, three cell groups, and the plurality of IGBTs in each cell group are covered with an emitter electrode EE. As shown in Fig. 1, the three emitter electrodes EE formed on the first main surface SUBa of the semiconductor substrate SUB extend in the X direction and are spaced apart from each other in the Y direction. The X direction and the Y direction are perpendicular to each other.

[0020] The peripheral region 1B is provided with a gate pad GP, a gate wiring GW, and a resistive element region RGA. The gate wiring GW is arranged to surround the three emitter electrodes EE, the gate pad GP, and the resistive element region RGA, except for the side of the emitter electrode EE opposite to the gate pad GP. The three emitter electrodes EE are connected to each other on the side opposite to the gate pad GP. In addition, between the emitter electrodes EE adjacent to each other in the Y direction, the gate wiring GW crosses in the X direction and is connected to the ring-shaped gate wiring GW. As shown in FIG. 1, the gate pad GP and the resistive element region RGA are formed in a region surrounded by the gate wiring GW and the emitter electrode EE. In the resistive element region RGA, a resistive element Rg, which will be described later, is formed, and the gate pad GP and the gate wiring GW are electrically connected via the resistive element Rg.

[0021] Although not shown, on the first main surface SUBa of the semiconductor substrate SUB, multiple annular field plates are formed outside the gate wiring so as to surround the annular gate wiring GW. The emitter electrode EE, gate pad GP, gate wiring GW, and field plates are formed by patterning a metal layer formed in the same manufacturing process on an interlayer insulating film IL described later. Therefore, in a plan view, the emitter electrode EE, gate pad GP, and gate wiring GW are separated from each other without overlapping. The innermost field plate is integrated with the emitter electrode EE in a portion where the three emitter electrodes EE are connected to each other on the opposite side to the gate pad GP, and is separated from the gate wiring GW without overlapping each other.

[0022] Although not shown, the emitter electrode EE, the gate pad GP, the gate wiring GW, and the resistive element region RGA are covered with a protective film such as a polyimide film. Openings OPE and OPG are formed in the protective film on parts of the emitter electrode EE and the gate pad GP, respectively. External connection terminals are connected to parts of the emitter electrode EE and the gate pad GP exposed from the openings OPE and OPG, respectively, so that the semiconductor device 100 is electrically connected to a lead frame, another semiconductor chip, a wiring board, or the like. The external connection terminals are, for example, bonding wires made of gold, copper, or aluminum, or clips made of a copper plate.

[0023] 2 is an equivalent circuit diagram of the semiconductor device 100. As shown in FIG. 2, the IGBT includes a gate electrode GE1, a collector region PC, and an emitter region NE. A collector electrode CE is connected to the collector region PC, and an emitter electrode EE is connected to the emitter region NE. The gate electrode GE1 is electrically connected to a gate pad GP via a resistive element Rg. Specifically, the gate electrode GE1 is connected to the resistive element Rg via a gate wiring GW, and the gate pad GP is connected to the resistive element Rg via a gate pad wiring GPW.

[0024] <Structure of IGBT> FIG. 3 is a plan view of the main part of the cell region 1A and the peripheral region 1B. FIG. 5 is a cross-sectional view taken along the line A-A of FIG. 3. FIG. 6 is a cross-sectional view taken along the line B-B of FIG. 3. The cell region 1A of the semiconductor device 100 has an active cell AC for performing the main operation of the IGBT and an inactive cell IAC other than the active cell AC. In FIG. 3, the shapes of the trenches TR (gate electrodes GE1, GE2, and resistor element Rg), holes CH1, CH2, CH3, and CH4 (contact member PG), emitter electrode EE, gate pad GP, gate pad wiring GPW, gate wiring GW, and well region PW are shown.

[0025] As shown in FIG. 3, in the cell region 1A, a plurality of trenches TR extend in the Y direction and are adjacent to each other in the X direction. A gate electrode GE1 is formed inside the trench TR of the active cell AC. A gate electrode GE2 is formed inside the trench TR of the inactive cell IAC. The trench TR formed in the active cell AC and the gate electrode GE1 formed therein constitute a gate trench. The trench TR formed in the inactive cell IAC and the gate electrode GE2 formed therein constitute an emitter trench.

[0026] A pair of adjacent gate electrodes GE1 of the active cell AC extend in the Y direction into the peripheral region 1B and are electrically connected to the gate wiring GW through the contact member PG formed in the hole CH3. And a gate potential is supplied to the pair of gate electrodes GE1 during the operation of the IGBT. The gate electrode GE2 of the inactive cell IAC is electrically connected to the emitter electrode EE through the contact member PG formed in the hole CH2, and an emitter potential is supplied during the operation of the IGBT.

[0027] As shown in Fig. 5, the semiconductor device 100 includes an n-type semiconductor substrate SUB having a first main surface (upper surface) SUBa and a second main surface (lower surface) SUBb. The semiconductor substrate SUB is made of n-type silicon and has a drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In that case, the n-type silicon layer having a lower impurity concentration than the n-type silicon substrate constitutes the drift region NV.

[0028] An n-type field stop region (impurity region) NS is formed in the semiconductor substrate SUB on the second main surface SUBb side of the semiconductor substrate SUB. The impurity concentration of the field stop region NS is higher than the impurity concentration of the drift region NV. The field stop region NS is provided to prevent a depletion layer extending from the pn junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off.

[0029] A p-type collector region (impurity region) PC is formed in the semiconductor substrate SUB on the second main surface SUBb side of the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0030] A collector electrode CE is formed under the second main surface SUBb of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector electrode CE is a single-layer metal film such as an Au film, a Ni film, a Ti film, or an AlSi film, or a laminated metal film in which these films are appropriately laminated. The field stop region NS, the collector region PC, and the collector electrode CE are formed over the entire semiconductor substrate SUB, including not only the cell region 1A but also the peripheral region 1B.

[0031] A trench TR is formed in the semiconductor substrate SUB on the first main surface SUBa side of the semiconductor substrate SUB. The trench TR penetrates an emitter region NE and a base region PB, which will be described later, and reaches the inside of the semiconductor substrate SUB. The depth of the trench TR is, for example, 2 μm or more and 5 μm or less.

[0032] A gate insulating film GI is formed inside the trench TR. Gate electrodes GE1 and GE2 are buried inside the trench TR via the gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film. The gate electrodes GE1 and GE2 are conductive films, for example, polycrystalline silicon films (polysilicon films) doped with n-type impurities. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.

[0033] A hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between the pair of trenches TR (the pair of gate electrodes GE1) on the first main surface SUBa side of the semiconductor substrate SUB of the active cell AC. The impurity concentration of the hole barrier region NHB is higher than the impurity concentration of the drift region NV.

[0034] A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The impurity concentration of the emitter region NE is higher than the impurity concentration of the drift region NV. The base region PB is formed to be shallower than the depth of the trench TR, and the emitter region NE is formed to be shallower than the depth of the base region PB.

[0035] As shown in FIG. 5, the multiple emitter regions NE are formed between a pair of trenches TR (a pair of gate electrodes GE1), and the base region PB located below the emitter regions NE is used as a channel region.

[0036] On the first main surface SUBa side of the semiconductor substrate SUB of the inactive cell IAC, a hole barrier region NHB is formed in the semiconductor substrate SUB between the pair of trenches TR (the pair of gate electrodes GE2). Also, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between the gate electrodes GE1 and GE2. In the inactive cell IAC, a floating region PF is formed in the semiconductor substrate SUB in the cell region 1A other than between the pair of trenches TR. A p-type base region PB is formed in the hole barrier region NHB and the floating region PF. The depth of the floating region PF from the first main surface SUBa is slightly deeper than the depth of the trench TR from the first main surface SUBa.

[0037] The floating region PF and the base region PB formed within the floating region PF are not electrically connected to the gate wiring GW and the emitter electrode EE, and are in an electrically floating state.

[0038] In the active cells AC and the inactive cells IAC, an interlayer insulating film IL is formed on the first main surface SUBa of the semiconductor substrate SUB so as to cover each trench TR. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, not less than 600 nm and not more than 1500 nm. In addition, the interlayer insulating film IL is subjected to a planarization process for planarizing the upper surface of the interlayer insulating film IL.

[0039] In the active cell AC, the hole CH1 penetrates the interlayer insulating film IL and the emitter region NE and reaches the inside of the base region PB. The hole CH1 is formed so as to contact the emitter region NE and the base region PB.

[0040] In the inactive cell IAC, the hole CH2 penetrates the interlayer insulating film IL and reaches the inside of the base region PB. The hole CH2 is formed so as to overlap the gate electrode GE2 in a plan view. Therefore, the hole CH2 in the inactive cell IAC is formed so as to contact the gate electrode GE2 and the base region PB.

[0041] In the active cell AC and the inactive cell IAC, a p-type high-concentration diffusion region (impurity region) PR is formed in the base region PB around the bottom of the hole CH1 and the hole CH2. The impurity concentration of the high-concentration diffusion region PR is higher than the impurity concentration of the base region PB. The high-concentration diffusion region PR is provided mainly to reduce the contact resistance with the contact member PG.

[0042] A contact member PG is embedded in each of the holes CH1 and CH2. The contact member PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.

[0043] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, the high-concentration diffusion region PR, and the gate electrode GE2 via a contact member PG, and supplies an emitter potential to these regions. Although not shown here, a gate wiring GW, a gate pad wiring GPW, and a gate pad GP, which are formed in the same manufacturing process as the emitter electrode EE, are also formed on the interlayer insulating film IL. The gate wiring GW is electrically connected to the gate electrode GE1 via a contact member PG embedded in a hole CH3, and supplies a gate potential to the gate electrode GE1.

[0044] The emitter electrode EE, the gate wiring GW, the gate pad wiring GPW, and the gate pad GP include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film to which copper or silicon is added. The aluminum alloy film is a main conductor film of the emitter electrode EE and the gate wiring GW, and is sufficiently thicker than the TiW film.

[0045] As described in FIG. 3, the pair of gate electrodes GE1 are linked to each other and electrically connected to the gate wiring GW in the peripheral region 1B. As shown in FIG. 6, the peripheral region 1B is provided with a well region PW, which is a p-type semiconductor region. The gate electrode GE1 formed in the trench TR provided in the well region PW is electrically connected to the gate wiring GW via a contact member PG formed in the hole CH3. The well region PW is formed in the same process as the floating region PF of the cell region 1A, and therefore has the same depth as the floating region PF. However, in a plan view, the well region and the floating region PF are physically separated.

[0046] <Resistance element and surrounding structure> Fig. 4 is a plan view of the resistive element region RGA shown in Fig. 3. Fig. 7 is a cross-sectional view taken along line CC in Fig. 4. Fig. 8 is a cross-sectional view taken along line DD in Fig. 4. The resistive element and its surrounding structure will be described with reference to Figs. 3, 4, 7 and 8.

[0047] As shown in Fig. 1, two resistive element regions RGA are formed in the semiconductor device 100 in the Y direction so as to sandwich the gate pad GP therebetween. Fig. 3 shows the structure of the resistive element region RGA located below the gate pad GP. The resistive element region RGA located above the gate pad GP has the same structure as that shown in Fig. 3, and the two resistive element regions RGA are in a line-symmetrical relationship in the Y direction with respect to the X-axis passing through the center of the gate pad GP.

[0048] As shown in FIG. 3, the semiconductor device 100 includes the cell region 1A and the peripheral region 1B adjacent to the cell region 1A in the X direction. The peripheral region 1B is formed in the well region PW in a plan view. In the boundary region between the cell region 1A and the peripheral region 1B, the emitter electrode EE formed in the cell region 1A extends to the peripheral region 1B and is electrically connected to the well region PW via a contact member PG formed in a hole CH4. For example, in the center of FIG. 3, the well region PW is electrically connected to the emitter electrode EE via a contact member PG formed in a hole CH4 extending long in the Y direction. In this way, the region in which the emitter electrode EE is electrically connected to the well region PW via the contact member PG is called a well power supply section. That is, the carriers (holes) generated by the impact ionization described above enter the well region PW and flow to the emitter electrode EE via the well power supply section. Therefore, the more distant the region is from the well power supply section, the greater the potential rise in the well region PW.

[0049] As shown in FIG. 3, the peripheral region 1B has, in the Y direction, a gate pad GP, a resistive element region RGA arranged below the gate pad GP, and a gate wiring GW arranged below the resistive element region RGA. The gate pad GP has a quadrangle (such as a square or a rectangle) in a plan view and has an opening OPG at its center. The gate pad wiring GPW is connected to the gate pad GP and extends into the resistive element region RGA. The gate pad wiring GPW is a wiring extending from the gate pad GP, and the wiring width of the gate pad wiring GPW is smaller than the length of a side of the gate pad GP (for example, the side from which the gate pad wiring GPW protrudes). The gate wiring GW is arranged around the gate pad GP and the resistive element region RGA, and extends into the resistive element region RGA.

[0050] The resistive element region RGA is formed in the well region PW in plan view. The resistive element region RGA includes a plurality of resistive elements Rg, a plurality of emitter electrodes EE (sometimes called wiring), a gate pad wiring GPW, and a gate wiring GW. As will be described later, the resistive elements Rg are embedded in the trenches TR via the gate insulating film GI. In the description of FIG. 3, the trenches TR in which the gate electrodes GE1 are embedded are referred to as gate trenches, but the trenches TR in which the resistive elements Rg are embedded may be referred to as resistive trenches.

[0051] As shown in FIG. 4, the resistor element Rg has an inner circumference and an outer circumference in a plan view, and has an endless shape with the Y direction as the longitudinal direction and the X direction as the transverse direction. The resistor element Rg can also be said to have an annular shape. The resistor element Rg has two straight line parts SP extending in the Y direction and spaced apart in the X direction, and two folded parts WP connecting the two straight line parts SP. For example, the two straight line parts SP extending in the Y direction are arranged parallel to each other in the X direction, and each of the two folded parts WP has a loop shape (arc shape) that is convex in a direction away from the straight line parts SP. The multiple resistor elements Rg are arranged at a predetermined interval in the X direction. Four resistor elements Rg are shown in FIG. 3 and FIG. 4. As shown in FIG. 4, the resistor element Rg and the trench TR have the same shape in a plan view, so the description of the planar shape of the resistor element Rg can be replaced with the description of the planar shape of the trench TR.

[0052] As shown in FIG. 4, in a plan view, the gate pad wiring GPW and the gate wiring GW extend in the X direction, are arranged at a predetermined interval in the Y direction, and intersect with a plurality of resistive elements Rg. Although not particularly limited, the gate pad wiring GPW and the gate wiring GW intersect with the straight portion SP of the resistive element Rg. At the intersection of the gate pad wiring GPW and the resistive element Rg, the resistive element Rg is electrically connected to the gate pad wiring GPW via the contact member PG formed in the hole CH3. Similarly, at the intersection of the gate wiring GW and the resistive element Rg, the resistive element Rg is electrically connected to the gate wiring GW via the contact member PG formed in the hole CH3. The region of the resistive element Rg between the contact member PG connected to the gate pad wiring GPW and the contact member PG connected to the gate wiring GW is the resistive region. As shown in FIG. 8, in the resistive trench, the resistive element Rg is embedded in the trench TR formed in the well region PW via the gate insulating film GI. The thickness of the gate insulating film GI of this resistive trench is equal to the thickness of the gate insulating film GI of the above-mentioned gate trench. The depth of the trench TR of the resistive trench is equal to the depth of the trench TR of the gate trench described above. As shown in FIG. 8, the gate pad wiring GPW and the gate wiring GW are connected to the resistive element Rg via the contact member PG. The contact member PG is embedded in a hole CH3 penetrating the interlayer insulating film IL formed on the first main surface SUBa of the semiconductor substrate SUB. As shown in FIG. 4, two resistive regions are formed in the resistive element Rg, and the two resistive regions are connected in parallel between the gate pad wiring GPW and the gate wiring GW. Since four resistive elements are arranged in the resistive element region RGA, eight resistive regions are connected in parallel between the gate pad wiring GPW and the gate wiring GW. However, the number of resistive elements Rg and the number of resistive regions can be freely selected. Note that, in the case of a linear resistive element having both ends, rather than an endless resistive element Rg, the inventors of the present application have confirmed that a decrease in the withstand voltage of the gate insulating film GI or aging deterioration occurs at the ends of the resistive element. Therefore, by using the endless resistive element Rg, it is possible to prevent a decrease in the breakdown voltage between the resistive element Rg and the well region PW and deterioration over time.

[0053] As shown in Fig. 3 and Fig. 4, in the resistive element region RGA, three emitter electrodes EE extend in the X direction, are arranged at a predetermined interval in the Y direction, and intersect with a plurality of resistive elements Rg. For convenience of explanation, the three emitter electrodes EE are referred to as a first emitter electrode EE, a second emitter electrode EE, and a third emitter electrode EE. That is, in the resistive element region RGA, in the Y direction, the first emitter electrode EE, the gate pad wiring GPW, the second emitter electrode EE, the gate wiring GW, and the third emitter electrode EE are arranged in this order from the gate pad GP side. In the Y direction, the first emitter electrode EE is located between the gate pad GP and the gate pad wiring GPW, the second emitter electrode EE is located between the gate pad wiring GPW and the gate wiring GW, and the third emitter electrode EE is located on the opposite side of the second emitter electrode EE with respect to the gate wiring GW. That is, in the Y direction, the first emitter electrode EE and the second emitter electrode EE sandwich the gate pad wiring GPW, and the second emitter electrode EE and the third emitter electrode EE sandwich the gate wiring GW. Each of the three emitter electrodes EE is electrically connected to the well region PW via a contact member PG formed in the hole CH4 in a region surrounded by the inner periphery of the endless resistance element Rg and a region adjacent to the outer periphery.

[0054] As shown in FIG. 7, the resistance element Rg is embedded in a trench TR formed in the well region PW via a gate insulating film GI. In the Z direction, the trenches TR extend from the first main surface SUBa of the semiconductor substrate SUB toward the inside of the semiconductor substrate SUB (in other words, the second main surface SUBb). Here, the Z direction is a direction perpendicular to the first main surface SUBa. The depth of the trench TR is shallower than the depth of the well region PW, but a thin well region PW exists below the trench TR. Compared with the thickness of the well region PW in the region where the trench TR does not exist, the thickness of the well region PW below the trench TR is very thin. Furthermore, in the Z direction, the impurity concentration at the bottom of the well region PW is lower than the impurity concentration at the surface or center of the well region PW. This is because the well region PW is formed by using an ion implantation method and a thermal diffusion method from the first main surface SUBa side. That is, the parasitic resistance of the well region PW located below the trench TR is higher than the parasitic resistance at the surface or center of the well region PW. Therefore, a potential difference is likely to occur between the well regions PW on both sides of the trench TR in the X direction. In the first embodiment, as shown in Fig. 7, in the regions on both sides of the trench TR in the X direction, the well region PW is electrically connected to the second emitter electrode EE via the contact member PG embedded in the hole CH4. In this way, the potential difference of the well region PW is reduced in the regions on both sides of the trench TR in the X direction.

[0055] Similarly, in the regions on both sides of the trench TR in the X direction, the well region PW is electrically connected to the first emitter electrode EE via the contact member PG embedded in the hole CH4. Also, in the regions on both sides of the trench TR in the X direction, the well region PW is electrically connected to the third emitter electrode EE via the contact member PG embedded in the hole CH4. That is, the contact member PG embedded in the hole CH4 is disposed in the region surrounded by the inner periphery of the endless resistor element Rg and in the region adjacent to the outer periphery, and the well region PW is connected to the emitter electrode EE, thereby reducing the potential difference of the well region PW in the regions on both sides of the trench TR. Also, the dielectric breakdown of the gate insulating film GI in the trench TR in which the resistor element Rg is embedded is prevented.

[0056] As shown in FIG. 4, the length in the Y direction of the holes CH4 and the contact members PG formed in the region surrounded by the inner circumference of the endless resistance element Rg will be described. In the Y direction, the length of the holes CH4 and the contact members PG arranged in the central portion is preferably more than twice the length of the holes CH4 and the contact members PG arranged adjacent to the folded portion WP. In FIG. 4, the length of the contact members PG (in other words, the holes CH4) connected to the second emitter electrode EE in the Y direction is more than twice the length of the contact members PG (in other words, the holes CH4) connected to the first emitter electrode EE. The carriers caused by the above-mentioned impact ionization are discharged to the emitter electrode EE through the contact members PG, but when focusing on the inner circumference region of the endless resistance element Rg, the amount of carriers discharged in the central portion needs to be more than twice the amount of carriers discharged in the folded portion WP. In the central portion, carriers need to be discharged from the upper and lower directions in the Y direction, but in the folded portion WP, carriers can be discharged downward or upward.

[0057] <Features of the first embodiment> The semiconductor device of the first embodiment has a gate trench in which a gate electrode GE1 constituting an IGBT is embedded, and a resistor trench in which a resistor element Rg is embedded. The depth of the resistor trench TR is equal to the depth of the gate trench TR. The thickness of the gate insulating film GI of the resistor trench is equal to the thickness of the gate insulating film GI of the gate trench. Since the resistor trench has the same structure as the gate trench, and the gate electrode GE1 and the resistor element Rg are formed in the same manufacturing process, manufacturing costs are reduced.

[0058] In plan view, the resistance element Rg and the trench TR are formed to have an endless (for example, annular) shape, thereby preventing a decrease in the breakdown voltage between the resistance element Rg and the well region PW and deterioration over time.

[0059] In a region surrounded by the inner periphery of the endless resistor element Rg formed in the well region PW, the well region PW is electrically connected to the emitter electrode EE via the contact member PG formed in the hole CH4. In this way, potential fluctuations in the well region PW in the region surrounded by the inner periphery of the endless resistor element Rg are suppressed, and dielectric breakdown of the gate insulating film GI provided in the trench TR in which the resistor element Rg is formed is prevented.

[0060] Similarly, in a region adjacent to the periphery of the endless resistor element Rg formed in the well region PW, the well region PW is electrically connected to the emitter electrode EE via a contact member PG formed in the hole CH4. In this way, potential fluctuations in the well region PW in the region adjacent to the periphery of the endless resistor element Rg are suppressed, and dielectric breakdown of the gate insulating film GI provided in the trench TR in which the resistor element Rg is formed is prevented. Here, the region adjacent to the periphery also includes a region sandwiched between two adjacent endless resistor elements Rg.

[0061] In the region surrounded by the inner circumference of the endless resistor Rg formed in the well region PW, the contact members PG formed in the holes CH4 are disposed in the region adjacent to the straight portion SP of the resistor Rg and the region adjacent to the turn-back portion WP. As shown in FIG. 4, the length of the holes CH4 and the contact members PG disposed in the region adjacent to the straight portion SP (center portion) in the Y direction is at least twice the length of the holes CH4 and the contact members PG adjacent to the turn-back portion WP. By increasing the amount of carriers discharged by the impact ionization described above in the center portion relative to the turn-back portion WP, it is possible to suppress the potential fluctuation of the well region PW in the region surrounded by the inner circumference of the endless resistor Rg.

[0062] (Embodiment 2) The second embodiment is a modification of the first embodiment, and relates to the arrangement of the hole CH4 and the contact member PG provided in the first emitter electrode EE. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted. Figure 9 is a plan view of a main part of the semiconductor device 100 of the second embodiment, showing the resistive element region RGA.

[0063] As shown in FIG. 9, the width (width in the Y direction) of the first emitter electrode EE is larger than that of the first emitter electrode EE in the first embodiment described above. In the Y direction, a hole CH4 and a contact member PG are disposed between the folded portion WP of the resistor element Rg and the gate pad GP, and the well region PW is connected to the first emitter electrode EE. Since the gate pad GP has a wide area, the well region PW below the gate pad GP has an area away from the well power supply portion. Due to the impact ionization described above, a potential rise occurs in the well region PW in the area away from the well power supply portion. In the Y direction, a hole CH4 and a contact member PG are disposed between the folded portion WP of the resistor element Rg and the gate pad GP, and the potential of the well region PW between the folded portion WP and the gate pad GP is fixed to the emitter potential. Then, the gate insulating film GI present in the folded portion WP is prevented from being broken down due to the influence of the above-mentioned potential rise.

[0064] (Embodiment 3) The third embodiment is a modification of the first embodiment, in which the first emitter electrode EE and the third emitter electrode EE are omitted. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted. Fig. 10 is a plan view of a main part of a semiconductor device 100 according to the third embodiment, showing a resistive element region RGA.

[0065] As shown in FIG. 10, in the Y direction, the gate pad GP, the gate pad wiring GPW, the second emitter electrode EE, the extension part GWE, and the gate wiring GW are arranged in this order. In the Y direction, the gate pad wiring GPW extends from the gate pad GP to the resistive element region RGA, and the gate pad wiring GPW covers one of the folded parts WP and a part of the straight part SP of the resistive element Rg. In the Y direction, the extension part GWE extends from the gate wiring GW extending in the X direction to the resistive element region RGA, and the extension part GWE covers the other folded part WP and a part of the straight part SP of the resistive element Rg. In the Y direction, the second emitter electrode EE extending in the X direction is arranged between the gate pad wiring GPW and the extension part GWE of the gate wiring GW. The second emitter electrode EE is electrically connected to the well region PW via the contact member PG formed in the hole CH4 in the region surrounded by the inner periphery of the endless resistive element Rg and the region adjacent to the outer periphery. The gate pad wiring GPW is electrically connected to the resistive element Rg via a contact member PG formed in the hole CH3. The gate pad wiring GPW is electrically connected to the gate pad GP. In addition, the extension portion GWE of the gate wiring GW is electrically connected to the resistive element Rg via a contact member PG formed in the hole CH3. The extension portion GWE of the gate wiring GW is electrically connected to the gate wiring GW.

[0066] By omitting the above-mentioned first emitter electrode EE and third emitter electrode EE, the wiring width of the gate pad wiring GPW and the wiring width of the gate wiring GW (including the extension portion GWE) can be made wider in the Y direction compared to embodiment 1. Therefore, the variable range of the length of the resistance region of the resistance element Rg in the Y direction can be increased.

[0067] In addition, in the resistive element region RGA in which the multiple resistive elements Rg are arranged, the second emitter electrode EE includes a first portion that crosses the center of the resistive element Rg in the longitudinal direction (Y direction) in the short direction (X direction) and a second portion that extends along the longitudinal direction of the resistive element Rg in the peripheral portion of the resistive element region RGA. The second portion branches off from the first portion and extends in the Y direction beyond the position where the gate pad wiring GPW and the resistive element Rg are connected and the position where the extension portion GWE of the gate wiring GW and the resistive element Rg are connected. The wiring width in the Y direction of the second portion is larger than the wiring width in the Y direction of the first portion. In the first portion of the second emitter electrode EE, a multiple number of holes CH4 and a multiple number of contact members PG are arranged in the X direction. The first portion of the second emitter electrode EE is electrically connected to the well region PW via the multiple contact members PG formed in the multiple holes CH4. Similarly, a plurality of holes CH4 and a plurality of contact members PG extending in the Y direction are disposed in the second portion of the second emitter electrode EE. The second portion of the second emitter electrode EE is electrically connected to the well region PW via the plurality of contact members PG formed in the plurality of holes CH4. In this manner, by providing the second portion extending in the Y direction in the second emitter electrode EE and bringing the well power supply portion close to the folded portion WP of the resistor element Rg, dielectric breakdown of the gate insulating film GI in the resistor trench is prevented.

[0068] (Embodiment 4) The fourth embodiment is a modification of the first embodiment, in which the first emitter electrode EE and the gate pad wiring GPW are omitted. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted. Fig. 11 is a plan view of a main part of a semiconductor device 100 according to the fourth embodiment, showing a resistive element region RGA.

[0069] As shown in Fig. 11, in the Y direction, the gate pad GP, the second emitter electrode EE, the gate wiring GW, and the third emitter electrode EE are arranged in this order. In the Y direction, the gate pad GP covers one of the folded portions WP and a part of the straight portion SP of the resistor element Rg. The gate pad GP is electrically connected to the resistor element Rg via a contact member PG formed in a hole CH3. In a plan view, one of the folded portions WP and a part of the straight portion SP of the resistor element Rg may be located within an opening OPG.

[0070] By omitting the first emitter electrode EE and the gate pad wiring GPW described above, the width of the second emitter electrode EE can be made wider in the Y direction compared to the first embodiment. In addition, the length of the contact member PG formed in the hole CH4 electrically connected to the second emitter electrode EE and the well region PW is increased in the Y direction. This improves the carrier ejection capability of the second emitter electrode EE in the impact ionization described above, and prevents dielectric breakdown of the gate insulating film GI at the folded portion WP of the resistor element Rg located under the gate pad GP.

[0071] However, in the well region PW below the gate pad GP, there is a region away from the well power supply portion (in other words, a region where the potential rise is large). Therefore, in the Y direction, it is preferable to dispose the folded portion WP of the resistive element Rg in a region 300 μm or less from the contact member PG connected to the second emitter electrode EE. Considering the parasitic resistance of the well region PW, it is possible to prevent dielectric breakdown of the gate insulating film GI in a region 300 μm or less from the well power supply portion.

[0072] Furthermore, by extending the endless resistor element Rg up to under the gate pad GP, the straight portion SP of the resistor element Rg can be lengthened in the Y direction, and the variable range of the resistance region can be increased.

[0073] (Embodiment 5) The fifth embodiment is a modification of the first embodiment, and relates to the shape of the resistive element Rg. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted. Fig. 12 is a plan view of a main part of the semiconductor device 100 of the fifth embodiment, showing the resistive element region RGA.

[0074] As in the first embodiment, in the resistive element region RGA, a first emitter electrode EE, a gate pad wiring GPW, a second emitter electrode EE, a gate wiring GW, and a third emitter electrode EE are arranged in this order from the gate pad GP side in the Y direction. As shown in Fig. 12, the resistive element Rg has a first straight portion SP and a second straight portion SP that continuously extend from the first emitter electrode EE to the third emitter electrode EE in the Y direction. The first straight portion SP and the second straight portion SP are parallel to each other and are spaced apart by a predetermined distance in the X direction.

[0075] Furthermore, the resistor element Rg has a third straight portion SP and a fourth straight portion SP arranged adjacent to each other in parallel between the first straight portion SP and the second straight portion SP. The third straight portion SP and the fourth straight portion SP extend continuously in the Y direction from the first emitter electrode EE to the second emitter electrode EE. Furthermore, the resistor element Rg has a fifth straight portion SP and a sixth straight portion SP arranged adjacent to each other in parallel between the first straight portion SP and the second straight portion SP. The fifth straight portion SP and the sixth straight portion SP extend continuously in the Y direction from the second emitter electrode EE to the third emitter electrode EE. In the Y direction, the third straight portion SP and the fifth straight portion SP are arranged linearly, and the fourth straight portion SP and the sixth straight portion SP are arranged linearly.

[0076] Furthermore, the resistive element Rg has a first folded portion WP, a second folded portion WP, a third folded portion WP, a fourth folded portion WP, a fifth folded portion WP, and a sixth folded portion WP. The first folded portion WP connects the first straight portion SP and the third straight portion SP. The second folded portion WP connects the third straight portion SP and the fourth straight portion SP in a region overlapping with the second emitter electrode EE. The third folded portion WP connects the fourth straight portion SP and the second straight portion SP. The fourth folded portion WP connects the first straight portion SP and the fifth straight portion SP. The fifth folded portion WP connects the fifth straight portion SP and the sixth straight portion SP in a region overlapping with the second emitter electrode EE. The sixth folded portion WP connects the sixth straight portion SP and the second straight portion SP. Each of the first folded portion WP and the third folded portion WP is disposed in a region overlapping with the first emitter electrode EE or in a region adjacent to the first emitter electrode EE. Each of the first folded portion WP and the third folded portion WP may be disposed straddling from the region overlapping with the first emitter electrode EE to the region adjacent to the first emitter electrode EE. Each of the fourth folded portion WP and the sixth folded portion WP is disposed in a region overlapping with the third emitter electrode EE or in a region adjacent to the third emitter electrode EE. Each of the fourth folded portion WP and the sixth folded portion WP may be disposed straddling from the region overlapping with the third emitter electrode EE to the region adjacent to the third emitter electrode EE.

[0077] In the region surrounded by the inner periphery and adjacent to the outer periphery of the resistor element Rg, the well region PW is electrically connected to the first emitter electrode EE via the contact member PG formed in the hole CH4 in the region adjacent to the first and third fold portions WP. In the region surrounded by the inner periphery and adjacent to the outer periphery of the resistor element Rg, the well region PW is electrically connected to the second emitter electrode EE via the contact member PG formed in the hole CH4 in the region adjacent to the second and fifth fold portions WP. In the region surrounded by the inner periphery and adjacent to the outer periphery of the resistor element Rg, the well region PW is electrically connected to the third emitter electrode EE via the contact member PG formed in the hole CH4 in the region adjacent to the fourth and sixth fold portions WP.

[0078] The resistive element Rg is electrically connected to the gate pad wiring GPW through a contact member PG formed in a hole CH3 at the first straight portion SP or the third straight portion SP in a region overlapping with the gate pad wiring GPW. Also, the resistive element Rg is electrically connected to the gate wiring GW through a contact member PG formed in a hole CH3 at the first straight portion SP or the fifth straight portion SP in a region overlapping with the gate wiring GW. FIG. 12 shows an example in which the gate pad wiring GPW is electrically connected to the third straight portion SP, and the gate wiring GW is connected to the fifth straight portion SP. In the resistive element Rg, the region where the gate pad wiring GPW and the gate wiring GW are electrically connected can be varied, so that the variable range of the resistance region can be increased.

[0079] While the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0080] For example, in the above embodiment, an IGBT is exemplified as a device formed in the cell region 1A, but the technology disclosed in the above embodiment is not limited to an IGBT and can also be applied to a power MOSFET having a vertical trench gate structure.

[0081] Moreover, the material used for the semiconductor substrate SUB is not limited to silicon (Si) and may be silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or the like. [Explanation of symbols]

[0082] 100 Semiconductor device 1A Cell Area 1B Surrounding Area AC Active Cell CE collector electrode CH1~CH4 holes EE Emitter electrodes (first emitter electrode, second emitter electrode, third emitter electrode) GE1, GE2 gate electrodes GI Gate Insulator GP Gate Pad GPW Gate pad wiring GW Gate wiring GWE extension IAC Inactive Cell IL Interlayer insulating film NE emitter region NHB Hole Barrier Region NS field stop region NV drift region OPE, OPG opening PB Base Area PC Collector Area PF floating area PG Contact Material PR high concentration diffusion region PW Well Region RGA resistor area Rg Resistance element SP straight section SUB Semiconductor Substrate SUBa First principal surface SUBb Second principal surface TR Trench WP Folded part

Claims

1. a semiconductor substrate of a first conductivity type having a first main surface; a gate pad, a gate wiring, and an emitter electrode formed on the first main surface; a well region of a second conductivity type different from the first conductivity type formed in the first main surface; a first trench formed in the well region so as to have no end in a plan view; a first resistor element having an endless shape in a plan view, the first resistor element being embedded in the first trench via a first insulating film; a first contact member connected to the first resistor element; a second contact member that is disposed at a predetermined interval from the first contact member in a first direction that is a longitudinal direction of the first resistor element and that is connected to the first resistor element; a third contact member located between the first contact member and the second contact member in the first direction in a plan view, disposed in a region surrounded by an inner periphery of the first resistor element, and connected to the well region; having the gate pad is electrically connected to the first resistor element via the first contact member; the gate wiring is electrically connected to the first resistor element via the second contact member; The emitter electrode is electrically connected to the well region via the third contact member.

2. 2. The semiconductor device according to claim 1, moreover, A semiconductor device comprising: a fourth contact member located between the first contact member and the second contact member in the first direction in a plan view, disposed in a region adjacent to an outer periphery of the first resistance element, and connected to the well region.

3. 3. The semiconductor device according to claim 2, moreover, a fifth contact member electrically connecting the gate pad and the first resistor element; a sixth contact member electrically connecting the gate wiring and the first resistor element and disposed at a predetermined distance from the fifth contact member in the first direction; having the first resistor element includes a first straight portion and a second straight portion extending in the first direction in a plan view and arranged adjacent to each other in a second direction which is a short-side direction of the first resistor element, and a first folded portion and a second folded portion arranged spaced apart from each other in the first direction and connecting the first straight portion and the second straight portion; the first contact member is connected to the first folded portion or the first straight portion, the second contact member is connected to the second folded portion or the first straight portion, the fifth contact member is connected to the first folded portion or the second straight portion, The sixth contact member is connected to the second folded portion or the second straight portion.

4. 4. The semiconductor device according to claim 3, A semiconductor device, wherein in the first direction in a plan view, the third contact member and the fourth contact member are arranged at a position adjacent to the first linear portion of the first resistor element.

5. 4. The semiconductor device according to claim 3, The first resistor element is annular in plan view.

6. 4. The semiconductor device according to claim 3, The first resistor element is a first resistor region located between the first contact member and the second contact member; a second resistance region located between the fifth contact member and the sixth contact member; Including, the first resistance region and the second resistance region are electrically connected in parallel between the gate pad and the gate wiring.

7. 4. The semiconductor device according to claim 3, moreover, a first wiring extending along the second direction in a plan view and connecting to the first contact member and the fifth contact member; a second wiring extending along the second direction in a plan view and connecting to the second contact member and the sixth contact member; a third wiring extending along the second direction in a plan view and connecting to the third contact member and the fourth contact member; having the first wiring is electrically connected to the gate pad; the second wiring is electrically connected to the gate wiring, the third wiring is electrically connected to the emitter electrode, A semiconductor device, wherein in the first direction in a plan view, the third wiring is arranged between the first wiring and the second wiring without overlapping with the first wiring or the second wiring.

8. 8. The semiconductor device according to claim 7, moreover, a fourth wiring arranged between the first wiring and the gate pad in the first direction in a plan view, extending in the second direction in a plan view, and electrically connected to the emitter electrode; a plurality of seventh contact members electrically connecting the fourth wiring to the well region; a fifth wiring arranged on an opposite side of the second wiring from the third wiring in the first direction in a plan view, extending in the second direction in a plan view, and electrically connected to the emitter electrode; a plurality of eighth contact members electrically connecting the fifth wiring to the well region; The semiconductor device has

9. 9. The semiconductor device according to claim 8, the seventh contact members are adjacent to the first folded portion, and are arranged in a region surrounded by the inner periphery of the first resistor element and in a region adjacent to the outer periphery; the eighth contact members are adjacent to the second folded portion, and are arranged in a region surrounded by the inner periphery of the first resistor element and in a region adjacent to the outer periphery.

10. 10. The semiconductor device according to claim 9, a first fold portion formed on the first gate pad and a second fold portion formed on the gate pad;

11. 10. The semiconductor device according to claim 9, A semiconductor device, wherein in the second direction when viewed in a plan view, the length of the third contact member is more than twice the length of the seventh contact member adjacent to the first folded region in a region surrounded by the inner periphery of the first resistor element.

12. 8. The semiconductor device according to claim 7, the first wiring extends continuously from the gate pad in the first direction in a plan view, in a plan view, the first folded portion, a portion of the first straight portion, and a portion of the second straight portion overlap with the first wiring; In a plan view, the first contact member and the fifth contact member overlap the first wiring.

13. 4. The semiconductor device according to claim 3, in a plan view, the first folded portion, a portion of the first linear portion, and a portion of the second linear portion overlap with the gate pad; In a plan view, the first contact member and the fifth contact member overlap the gate pad.

14. 4. The semiconductor device according to claim 3, moreover, a second trench and a third trench formed outside the well region in a plan view; a first gate electrode formed in the second trench with a second insulating film interposed therebetween; a second gate electrode formed in the third trench with a third insulating film interposed therebetween; an emitter region of the first conductivity type formed in the first major surface in a region between the second trench and the third trench; the second conductivity type base region formed below the first conductivity type emitter region in a region between the second trench and the third trench; a drift region of the first conductivity type formed below the base region; a collector region of the second conductivity type formed in a second main surface of the semiconductor substrate opposite to the first main surface; a ninth contact member electrically connecting the first gate electrode and the second gate electrode to the gate wiring; The semiconductor device has

15. 15. The semiconductor device according to claim 14, A semiconductor device, wherein a depth of the first trench from the first main surface is equal to a depth of the second trench or a depth of the third trench from the first main surface.

16. 16. The semiconductor device according to claim 15, a thickness of the first insulating film is equal to a thickness of the second insulating film and a thickness of the third insulating film.

17. 15. The semiconductor device according to claim 14, the first resistance element, the first gate electrode and the second gate electrode each include a polysilicon film.

18. 15. The semiconductor device according to claim 14, moreover, an interlayer insulating film formed on the first main surface so as to cover the well region, the first resistance element, the first gate electrode, and the second gate electrode; the first contact member, the second contact member, the fifth contact member, and the sixth contact member penetrate the interlayer insulating film and are connected to the first resistor element; the third contact member and the fourth contact member penetrate the interlayer insulating film and are connected to the well region; the ninth contact member penetrates the interlayer insulating film and is connected to the first gate electrode and the second gate electrode.

19. 4. The semiconductor device according to claim 3, moreover, a fourth trench formed in the well region so as to have no end in a plan view; a second resistor element formed endlessly and embedded in the fourth trench via a fourth insulating film; having the fourth trench is disposed adjacent to the first trench in the second direction in a plan view, the first resistance element and the second resistance element are electrically connected in parallel between the gate pad and the gate wiring.

20. a semiconductor substrate of a first conductivity type having a first main surface; a gate pad, a gate wiring, and an emitter electrode formed on the first main surface; a well region of a second conductivity type different from the first conductivity type formed in the first main surface; a first trench formed in the well region so as to have no end in a plan view; a first resistor element having an endless shape in a plan view, the first resistor element being embedded in the first trench via a first insulating film; a first contact member connected to the first resistor element; a second contact member that is disposed at a predetermined interval from the first contact member in a first direction that is a longitudinal direction of the first resistor element and that is connected to the first resistor element; a plurality of third contact members located between the first contact member and the second contact member in the first direction in a plan view, arranged in a region surrounded by an inner periphery of the first resistor element or in a region adjacent to an outer periphery of the first resistor element, and connected to the well region; having the gate pad is electrically connected to the first resistor element via the first contact member; the gate wiring is electrically connected to the first resistor element via the second contact member; the emitter electrode is electrically connected to the well region via the third contact members; The first resistor element has, in a plan view, a first linear portion and a second linear portion extending in the first direction and spaced apart from each other in a second direction that is a short-side direction of the first resistor element; a third straight line portion, a fourth straight line portion, a fifth straight line portion, and a sixth straight line portion, which extend in the first direction in a plan view and are spaced apart from each other in the second direction in a plan view in a region between the first straight line portion and the second straight line portion; a first fold-back portion connecting the first straight portion and the third straight portion, a second fold-back portion connecting the third straight portion and the fourth straight portion, a third fold-back portion connecting the fourth straight portion and the second straight portion, a fourth fold-back portion connecting the first straight portion and the fifth straight portion, a fifth fold-back portion connecting the fifth straight portion and the sixth straight portion, and a sixth fold-back portion connecting the sixth straight portion and the second straight portion, Including, In the first direction in a plan view, lengths of the third straight line portion, the fourth straight line portion, the fifth straight line portion, and the sixth straight line portion are shorter than lengths of the first straight line portion and the second straight line portion; the third linear portion and the fifth linear portion are linearly arranged in the first direction in a plan view, The fourth straight portion and the sixth straight portion are linearly arranged in the first direction in a plan view.

Images