Stacked wiring board, semiconductor device and method for manufacturing stacked wiring board

Abstract

To provide a stacked wiring board which can easily correspond to a narrow pitch of an electrode pad.SOLUTION: A stacked wiring board 10 has a first wiring board 20, and a second wiring board 60 mounted on the first wiring board 20. The first wiring board 20 has a wiring layer 40, an insulating layer 41 coating the wiring layer 40, a wiring layer 42 which is stacked on the upper surface of the insulating layer 41, and is electrically connected to the wiring layer 40, an insulating layer 43 which is stacked on the upper surface of the insulating layer 41 so as to coat the wiring layer 42, and a first electrode pad 44 which is stacked on the upper surface of the insulating layer 43, and is electrically connected to the wiring layer 42. The second wiring board 60 has a wiring structure 61 having higher wiring density than the first wiring board 20, and a second electrode pad 70 which is connected to the first electrode pad 44. The thickness of the insulating layer 43 is thinner than the thickness of the insulating layer 41.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board, a semiconductor device, and a method for manufacturing a multilayer wiring board. [Background technology]

[0002] Wiring boards for mounting electronic components such as semiconductor chips are available in various shapes and structures. For example, wiring boards with a fine wiring structure having a wiring layer with high wiring density are known. As one example, a laminated wiring board has been proposed in which a second wiring board having a fine wiring structure is mounted on a first wiring board, which is a base board (see, for example, Patent Document 1). In this type of laminated wiring board, the electrode pads of the first wiring board and the electrode pads of the second wiring board are bonded to each other by a solder layer, thereby mounting the second wiring board on the first wiring board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-47735 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in a multilayer wiring board, as the performance of semiconductor chips increases, there is a demand for narrower pitches of electrode pads. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device includes a first wiring board and a second wiring board mounted on the first wiring board, the first wiring board having a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer stacked on an upper surface of the first insulating layer and electrically connected to the first wiring layer, a second insulating layer stacked on the upper surface of the first insulating layer so as to cover the second wiring layer, and a first electrode pad stacked on the upper surface of the second insulating layer and electrically connected to the second wiring layer, the second wiring board having a wiring structure with a higher wiring density than the first wiring board and a second electrode pad connected to the first electrode pad, and a thickness of the second insulating layer is thinner than a thickness of the first insulating layer. Effect of the Invention

[0006] According to one aspect of the present invention, an effect is achieved in that it is possible to easily accommodate narrower pitches of electrode pads. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a multilayer wiring board according to the first embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view showing a part of the multilayer wiring board shown in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view showing the semiconductor device of the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 9]FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the first embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the multilayer wiring board of the second embodiment. [Figure 14] FIG. 14 is an enlarged cross-sectional view showing a part of the multilayer wiring board shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the second embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the second embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the second embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the second embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the second embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a method for manufacturing the multilayer wiring board of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, each embodiment will be described with reference to the accompanying drawings. For convenience, the accompanying drawings may show characteristic parts in an enlarged scale to make the characteristics easier to understand, and the dimensional ratios of each component may differ from one drawing to another. In addition, in the cross-sectional views, in order to make the cross-sectional structure of each component easier to understand, the hatching of some components is shown as a matte finish, and the hatching of some components is omitted.

[0009] (First embodiment) The first embodiment will be described below with reference to FIGS. (Overall Configuration of Multilayer Wiring Board 10) 1, the multilayer wiring board 10 has a first wiring board 20 and a second wiring board 60 mounted on the first wiring board 20. The multilayer wiring board 10 has, for example, an underfill resin 85 formed in the gap between the first wiring board 20 and the second wiring board 60.

[0010] (Specific Structure of First Wiring Board 20) The first wiring board 20 has a core layer 21. The core layer 21 is provided, for example, at the center of the first wiring board 20 in the thickness direction. For example, a so-called glass epoxy board can be used as the core layer 21, which is made by impregnating a non-photosensitive thermosetting resin mainly composed of an epoxy resin into a glass cloth (woven glass fabric) as a reinforcing material and hardening the resin. The reinforcing material is not limited to glass cloth, and for example, a glass nonwoven fabric, an aramid woven fabric, an aramid nonwoven fabric, a liquid crystal polymer (LCP: Liquid Crystal Polymer) woven fabric, or an LCP nonwoven fabric can be used. The thermosetting insulating resin is not limited to an epoxy resin, and for example, a resin material such as an imide resin, a phenol resin, or a cyanate resin can be used. The core layer 21 may contain a filler such as silica (SiO2) or alumina (Al2O3). The thickness of the core layer 21 can be, for example, about 60 μm to 400 μm.

[0011] The core layer 21 has through holes 21X at required locations (six locations in FIG. 1). The through holes 21X are formed so as to penetrate the core layer 21 in the thickness direction. A through electrode 22 is formed in the through hole 21X so as to penetrate the core layer 21 in the thickness direction. The through electrode 22 is formed, for example, so as to fill the through hole 21X. The material of the through electrode 22 can be, for example, copper (Cu) or a copper alloy.

[0012] On the lower surface of the core layer 21, a wiring layer 30, an insulating layer 31, a wiring layer 32, an insulating layer 33, a wiring layer 34, and a solder resist layer 35 are laminated in this order. On the upper surface of the core layer 21, a wiring layer 40, an insulating layer 41, a wiring layer 42, an insulating layer 43, a first electrode pad 44, and a solder resist layer 45 are laminated in this order. Here, the wiring layers 30, 32, 34, 40, 42 and the first electrode pad 44 of the first wiring board 20 have a lower wiring density, that is, a larger line and space (L / S), than the wiring layers of the second wiring board 60. The line and space (L / S) of the wiring layers 30, 32, 34, 40, 42 and the first electrode pad 44 can be, for example, about 20 μm / 20 μm. Here, the line in the line and space (L / S) represents the width of the wiring, and the space represents the distance between adjacent wirings. For example, if L / S is described as 20 μm / 20 μm, it means that the wiring width is 20 μm and the distance between adjacent wirings is 20 μm.

[0013] The wiring layers 30, 32, 34, 40, 42 and the first electrode pad 44 may be made of, for example, copper or a copper alloy. The insulating layers 31, 33, 41, 43 may be made of, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin such as an epoxy resin or a polyimide resin. The insulating layers 31, 33, 41, 43 may contain a filler such as silica or alumina. The solder resist layers 35, 45 may be made of, for example, an insulating resin mainly composed of a photosensitive resin such as a phenol resin or a polyimide resin. The solder resist layers 35, 45 may contain a filler such as silica or alumina.

[0014] The wiring layer 30 is laminated on the lower surface of the core layer 21. The wiring layer 30 is electrically connected to the wiring layer 40 via the through electrode 22. The insulating layer 31 is laminated on the lower surface of the core layer 21 so as to cover the wiring layer 30. The wiring layer 32 is laminated on the lower surface of the insulating layer 31. The wiring layer 32 is formed integrally with, for example, via wiring penetrating the insulating layer 31 in the thickness direction, and is electrically connected to the wiring layer 30 through the via wiring. The insulating layer 33 is laminated on the lower surface of the insulating layer 31 so as to cover the wiring layer 32. The wiring layer 34 is laminated on the lower surface of the insulating layer 33. The wiring layer 34 is a wiring layer formed in the lowest layer of the first wiring board 20. The wiring layer 34 is formed integrally with, for example, via wiring penetrating the insulating layer 33 in the thickness direction, and is electrically connected to the wiring layer 32 through the via wiring.

[0015] The wiring layers 30, 32, and 34 may have a thickness of, for example, about 15 μm to 35 μm. The insulating layers 31, 33 may have a thickness of, for example, about 20 μm to 45 μm. The solder resist layer 35 is the outermost insulating layer (here, the lowest layer) of the first wiring board 20. The solder resist layer 35 is formed on the lower surface of the insulating layer 33 so as to cover the lowest wiring layer 34. The solder resist layer 35 has openings 35X for exposing parts of the lowest wiring layer 34 as external connection pads 34P. External connection terminals used when mounting the stacked wiring board 10 on a mounting board such as a motherboard are connected to the external connection pads 34P.

[0016] A surface treatment layer is formed on the lower surface of the wiring layer 34 exposed at the bottom of the opening 35X, as necessary. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order). Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer in which a Ni layer and a Pd layer are laminated in this order), and a Pd layer / Au layer (a metal layer in which a Pd layer and an Au layer are laminated in this order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer) or a metal layer formed by electrolytic plating (electrolytic plated metal layer). The surface treatment layer may be an OSP film formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment on the lower surface of the wiring layer 34 exposed in the opening 35X. The OSP film may be an organic coating such as an azole compound or an imidazole compound. When a surface treatment layer is formed on the lower surface of the wiring layer 34, the surface treatment layer functions as the external connection pad 34P. The wiring layer 34 exposed from the opening 35X (or, when a surface treatment layer is formed on the wiring layer 34, the surface treatment layer) itself may be used as the external connection terminal.

[0017] The planar shape of the external connection pads 34P and the openings 35X may be any shape and any size. For example, the planar shape of the external connection pads 34P and the openings 35X may be a circle with a diameter of about 200 μm to 300 μm.

[0018] The wiring layer 40 is laminated on the upper surface of the core layer 21. The wiring layer 40 is electrically connected to the wiring layer 30 via the through electrode 22. The insulating layer 41 is laminated on the upper surface of the core layer 21 so as to cover the wiring layer 40. The insulating layer 41 has a through hole 41X formed therein, which penetrates the insulating layer 41 in the thickness direction and exposes a part of the upper surface of the wiring layer 40. The wiring layer 42 is laminated on the upper surface of the insulating layer 41. The wiring layer 42 is formed integrally with, for example, a via wiring 42V formed in the through hole 41X, and is electrically connected to the wiring layer 40 through the via wiring 42V. The via wiring 42V is formed so as to fill, for example, the through hole 41X.

[0019] 2, insulating layer 43 is laminated on the upper surface of insulating layer 41 so as to cover wiring layer 42. Insulating layer 43 is an interlayer insulating layer that is the outermost layer (here, the uppermost layer) of first wiring board 20. Insulating layer 43 is, for example, a build-up resin layer that is the outermost layer. Insulating layer 43 has a through hole 43X that penetrates insulating layer 43 in the thickness direction and exposes a part of the upper surface of wiring layer 42.

[0020] The thickness T1 of the insulating layer 43 is thinner than the thickness T2 of the insulating layer 41. The thickness T1 of the insulating layer 43 is formed to be, for example, 0.3 to 0.8 times the thickness T2 of the insulating layer 41. The thickness T1 of the insulating layer 43 may be, for example, about 20 μm to 30 μm. The thickness T2 of the insulating layer 41 may be, for example, about 40 μm to 50 μm.

[0021] The first electrode pad 44 is laminated on the upper surface of the insulating layer 43. The first electrode pad 44 is a wiring layer formed on the uppermost layer of the first wiring board 20. The first electrode pad 44 functions as an external connection terminal for electrically connecting to the second wiring board 60 (see FIG. 1). The first electrode pad 44 is formed integrally with, for example, a via wiring 44V penetrating the insulating layer 43 in the thickness direction, and is electrically connected to the wiring layer 42 through the via wiring 44V.

[0022] Here, the first electrode pad 44 and the via wiring 44V have, for example, a seed layer 46 that covers the upper surface of the insulating layer 43 and the inner surface of the through hole 43X. The seed layer 46 is formed so as to continuously cover, for example, the upper surface of the insulating layer 43, the entire inner wall surface of the through hole 43X, and the entire upper surface of the wiring layer 42 exposed at the bottom of the through hole 43X. For example, copper or a copper alloy can be used as the material of the seed layer 46. For example, an electroless plating layer formed by an electroless plating method or a sputtered film formed by a sputtering method can be used as the seed layer 46.

[0023] The via wiring 44V has a metal layer 47 filling the through hole 43X on the inner side of the seed layer 46. For example, copper or a copper alloy can be used as the material of the metal layer 47. For example, an electrolytic plating layer formed by an electrolytic plating method can be used as the metal layer 47.

[0024] The seed layer 46 and the metal layer 47 formed in the through hole 43X described above constitute the via wiring 44V. Here, the thickness T3 of the via wiring 44V is thinner than the thickness T4 of the via wiring 42V. Here, the thickness T3 of the via wiring 44V is equal to the thickness from the upper surface of the wiring layer 42 to the upper surface of the insulating layer 43. The thickness T4 of the via wiring 42V is equal to the thickness from the upper surface of the wiring layer 40 to the upper surface of the insulating layer 41. The thickness T3 of the via wiring 44V can be, for example, about 10 μm to 20 μm. The thickness T4 of the via wiring 42V can be, for example, about 25 μm to 35 μm.

[0025] The planar shape of the via wiring 44V can be set to any shape and any size. The planar shape of the via wiring 44V is, for example, circular. The via wiring 44V has a smaller size than the via wiring 42V in a planar view. The diameter of the via wiring 44V is, for example, smaller than the diameter of the via wiring 42V. The diameter of the upper surface of the via wiring 44V can be, for example, about 25 μm to 45 μm. The diameter of the upper surface of the via wiring 42V can be, for example, about 55 μm to 75 μm.

[0026] The first electrode pad 44 has a seed layer 46 formed on the upper surface of the insulating layer 43 and a metal layer 48 formed on the via wiring 44V (metal layer 47). The metal layer 48 is formed so as to protrude upward from the upper surface of the insulating layer 43. The metal layer 48 is formed integrally with the metal layer 47, for example. The material of the metal layer 48 may be, for example, copper or a copper alloy. The metal layer 48 may be, for example, an electrolytic plating layer formed by an electrolytic plating method.

[0027] The first electrode pad 44 is formed by the metal layer 48 and the seed layer 46 formed on the upper surface of the insulating layer 43 described above. Here, the thickness T11 of the first electrode pad 44 is, for example, thinner than the thickness T12 of the wiring layer 42. The thickness T11 of the first electrode pad 44 is, for example, thinner than the thickness T13 of the wiring layer 40. The thickness T11 of the first electrode pad 44 can be, for example, about 5 μm to 10 μm. The thicknesses T12, T13 of the wiring layers 40, 42 can be, for example, about 10 μm to 20 μm.

[0028] The planar shape of the first electrode pad 44 can be set to any shape and size. The planar shape of the first electrode pad 44 is formed, for example, in a circular shape. The diameter of the first electrode pad 44 can be, for example, about 70 μm to 85 μm.

[0029] As shown in FIG. 1, the solder resist layer 45 is an outermost insulating layer (here, the uppermost layer) of the first wiring board 20. The solder resist layer 45 is formed on the upper surface of the insulating layer 43. The solder resist layer 45 is laminated on the upper surface of the insulating layer 43 so as to expose the first electrode pads 44. The solder resist layer 45 has openings 45X formed therein, which penetrate the solder resist layer 45 in the thickness direction and expose the first electrode pads 44 and a part of the upper surface of the insulating layer 43. The openings 45X are formed, for example, so as to overlap with a mounting area in which the second wiring board 60 is mounted in a plan view. The openings 45X are formed so as to expose the upper surface of the insulating layer 43 and the first electrode pads 44 in the mounting area. In other words, the solder resist layer 45 is formed so as to surround the mounting area in a plan view.

[0030] The planar shape of the first wiring board 20 described above can be any shape and size. The first wiring board 20 has a size larger than the second wiring board 60 in a plan view. The planar shape of the first wiring board 20 can be, for example, a quadrangle of about 60 mm×60 mm to 80 mm×80 mm.

[0031] (Specific Structure of Second Wiring Board 60) The second wiring board 60 has a second electrode pad 70, an insulating layer 71, an insulating layer 72, a wiring layer 73, and a wiring structure 61. The wiring structure 61 is laminated on the insulating layer 72 and the wiring layer 73. The wiring structure 61 is a fine wiring structure in which a wiring layer having a higher wiring density than that of the first wiring board 20 is formed. The wiring structure 61 has a wiring layer 74, an insulating layer 75, a wiring layer 76, an insulating layer 77, a wiring layer 78, an insulating layer 79, and a wiring layer 80. The second electrode pad 70 and the wiring layers 73, 74, 76, 78, and 80 can be made of, for example, copper or a copper alloy.

[0032] The planar shape and size of the second wiring board 60 can be set to any shape and size. The planar shape of the second wiring board 60 can be, for example, a square shape of 30 mm×30 mm to 50 mm×50 mm.

[0033] The second electrode pad 70 is the bottom wiring layer of the second wiring board 60. The second electrode pad 70 is covered with an insulating layer 71. The lower surface of the second electrode pad 70 is exposed from the lower surface of the insulating layer 71. The lower surface of the second electrode pad 70 is formed, for example, flush with the lower surface of the insulating layer 71. The second electrode pad 70 functions as an external connection terminal for electrically connecting to another wiring board, here, the first wiring board 20. The thickness of the second electrode pad 70 can be, for example, about 10 μm to 20 μm.

[0034] The planar shape of the second electrode pad 70 can be set to any shape and any size. For example, the second electrode pad 70 has a size larger than the first electrode pad 44 in a plan view. The planar shape of the second electrode pad 70 is formed, for example, in a circular shape. The diameter of the second electrode pad 70 can be, for example, about 90 μm to 110 μm.

[0035] The insulating layer 71 is formed so as to cover the upper and side surfaces of the second electrode pad 70 and expose the lower surface of the second electrode pad 70. The insulating layer 71 is an insulating layer whose main component is a non-photosensitive thermosetting resin and does not have a reinforcing member. Examples of the thermosetting resin include epoxy resin, imide resin, phenol resin, and cyanate resin. The insulating layer 71 may contain a filler such as silica or alumina. The thickness of the insulating layer 71 may be, for example, about 15 μm to 30 μm.

[0036] The insulating layer 72 is an insulating layer mainly composed of a non-photosensitive thermosetting resin and has a reinforcing member 72G. The insulating layer 72 has a higher rigidity than the insulating layer 71. The insulating layer 72 may be configured by impregnating the reinforcing member 72G with a non-photosensitive thermosetting resin. Examples of the thermosetting resin include epoxy resin, imide resin, phenol resin, and cyanate resin. Examples of the reinforcing member 72G may include woven or non-woven fabrics such as glass fiber, carbon fiber, and aramid fiber. The thickness of the insulating layer 72 may be, for example, about 30 μm to 50 μm.

[0037] The wiring layer 73 is a via wiring embedded in the insulating layers 71 and 72. More specifically, the wiring layer 73 is a via wiring filled in a through hole 72X that penetrates the insulating layers 71 and 72 in the thickness direction and exposes a part of the upper surface of the second electrode pad 70. The wiring layer 73 is electrically connected to the second electrode pad 70. The wiring layer 73 is formed in a tapered shape that decreases in diameter from the upper side (the wiring layer 74 side) to the lower side (the second electrode pad 70 side) in FIG. 1. For example, the wiring layer 73 is formed in an inverted truncated cone shape with the upper end surface being larger in diameter than the lower end surface. The upper end surface of the wiring layer 73 is exposed from the insulating layer 72. The upper end surface of the wiring layer 73 is formed, for example, flush with the upper surface of the insulating layer 72. The upper end surface of the wiring layer 73 is directly bonded to the lower surface of the wiring layer 74. The lower end surface of the wiring layer 73 is directly bonded to the upper surface of the second electrode pad 70. The diameter of the upper end surface of the wiring layer 73 can be, for example, about 60 μm to 70 μm.

[0038] (Specific structure of wiring structure 61) The wiring layer 74 is laminated on the upper surface of the insulating layer 72 so as to be connected to the upper end surface of the wiring layer 73. That is, a part of the lower surface of the wiring layer 74 is in contact with the upper end surface of the wiring layer 73, and the wiring layer 74 and the wiring layer 73 are electrically connected. In other words, the wiring layer 74 and the wiring layer 73 are electrically connected but are not integrated. Specifically, the wiring layer 74 has, for example, a seed layer formed on the upper end surface of the wiring layer 73 and a metal layer formed on the seed layer.

[0039] The insulating layer 75 is formed on the upper surface of the insulating layer 72 so as to cover the wiring layer 74. The wiring layer 76 is laminated on the upper surface of the insulating layer 75. The wiring layer 76 is formed integrally with, for example, via wiring penetrating the insulating layer 75 in the thickness direction, and is electrically connected to the wiring layer 74 through the via wiring. The insulating layer 77 is formed on the upper surface of the insulating layer 75 so as to cover the wiring layer 76. The wiring layer 78 is laminated on the upper surface of the insulating layer 77. The wiring layer 78 is formed integrally with via wiring penetrating the insulating layer 77 in the thickness direction, and is electrically connected to the wiring layer 76 through the via wiring. The insulating layer 79 is formed on the upper surface of the insulating layer 77 so as to cover the wiring layer 78.

[0040] The wiring layer 80 is laminated on the upper surface of the insulating layer 79. The wiring layer 80 is a wiring layer formed on the uppermost layer of the second wiring board 60. The wiring layer 80 is formed integrally with via wiring penetrating the insulating layer 79 in the thickness direction, and is electrically connected to the wiring layer 78 through the via wiring. The wiring layer 80 has a pad P1. The pad P1 functions as a pad for mounting an electronic component for electrically connecting to an electronic component such as a semiconductor chip. The planar shape of the pad P1 can be any shape and any size. The planar shape of the pad P1 can be, for example, a circular shape with a diameter of about 20 μm to 30 μm. The pitch of the pads P1 can be, for example, about 40 μm to 60 μm. The thickness of the pad P1 can be, for example, about 10 μm to 15 μm.

[0041] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or only the top surface) of the pad P1. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, and a Pd layer / Au layer, and an OSP film.

[0042] Here, each of the wiring layers 74, 76, 78, 80 of the wiring structure 61 is thinner than the second electrode pad 70. Each of the wiring layers 74, 76, 78, 80 is thinner than each of the wiring layers 30, 32, 34, 40, 42 and the first electrode pad 44 of the first wiring board 20. The thickness of the wiring layers 74, 76, 78 can be, for example, about 1 μm to 3 μm. The thickness of the wiring layer 80 can be, for example, about 5 μm to 15 μm. Each of the wiring layers 74, 76, 78, 80 has a higher wiring density than the second electrode pad 70, that is, the line and space is smaller than that of the second electrode pad 70. The wiring layers 74, 76, 78, 80 have a higher wiring density than each of the wiring layers 30, 32, 34, 40, 42 and the first electrode pad 44 of the first wiring board 20. The line and space (L / S) of the wiring layers 74, 76, 78, and 80 can be set to about 1 μm / 1 μm to 3 μm / 3 μm.

[0043] The insulating layers 75, 77, and 79 of the wiring structure 61 may be made of a photosensitive insulating resin mainly composed of, for example, a phenolic resin or a polyimide resin. The insulating layers 75, 77, and 79 may contain a filler such as silica or alumina. Each of the insulating layers 75, 77, and 79 is thinner than each of the insulating layers 31, 33, 41, and 43 of the first wiring board 20. The thickness of the insulating layers 75, 77, and 79 may be, for example, about 5 μm to 10 μm.

[0044] The second wiring board 60 described above is mounted on the first wiring board 20. The second wiring board 60 is mounted on, for example, the first electrode pad 44 of the first wiring board 20. More specifically, the first electrode pad 44 of the first wiring board 20 and the second electrode pad 70 of the second wiring board 60 are joined to each other by a solder layer 81. The solder layer 81 is joined to, for example, the upper surface and side surface of the first electrode pad 44 and is also joined to the lower surface of the second electrode pad 70. Examples of materials that can be used for the solder layer 81 include an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and silver (Ag), and an alloy of Sn, Ag, and Cu.

[0045] Underfill resin 85 is provided so as to fill the gap between first wiring board 20 and second wiring board 60. Underfill resin 85 is provided so as to fill the gap between the upper surface of insulating layer 43 exposed in opening 45X and the lower surface of insulating layer 71 of second wiring board 60. As a material for underfill resin 85, for example, an insulating resin such as an epoxy resin can be used.

[0046] In this way, by mounting a second wiring board 60 having a wiring layer with high wiring density on a first wiring board 20 having a wiring layer with low wiring density, it is possible to easily manufacture a stacked wiring board 10 on which electronic components such as semiconductor chips can be mounted at a high density.

[0047] (Structure of semiconductor device 90) Next, the structure of the semiconductor device 90 will be described with reference to FIG. The semiconductor device 90 includes a multilayer wiring substrate 10, one or more semiconductor chips 91 (two in this embodiment), and an underfill resin 95.

[0048] Each semiconductor chip 91 has, for example, a plurality of electrode pads 92 formed on a circuit formation surface (here, the lower surface) of the semiconductor chip 91. The semiconductor chip 91 is flip-chip mounted on the second wiring substrate 60. More specifically, the electrode pads 92 of the semiconductor chip 91 are electrically connected to pads P1 of the second wiring substrate 60 via bumps 93. As a result, the semiconductor chip 91 is electrically connected to the wiring layer 80 via the electrode pads 92 and bumps 93.

[0049] The semiconductor chip 91 may be, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip. The semiconductor chip 91 may be, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or a flash memory chip. When a plurality of semiconductor chips 91 are mounted on the second wiring board 60, a logic chip and a memory chip may be combined and mounted on the second wiring board 60. The plurality of semiconductor chips 91 may be of the same size or may be of different sizes.

[0050] For example, a gold bump or a solder bump can be used as the bump 93. For example, an alloy containing Pb, an alloy of Sn and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used as the material of the solder bump.

[0051] The underfill resin 95 is provided so as to fill the gap between the second wiring board 60 and the semiconductor chip 91. As the material for the underfill resin 95, for example, an insulating resin such as an epoxy resin can be used.

[0052] In the semiconductor device 90, the semiconductor chip 91 is mounted on the second wiring board 60 having a wiring layer with high wiring density. Therefore, the multiple semiconductor chips 91 can be easily connected to each other by the wiring layer with high wiring density.

[0053] (Method of Manufacturing the Multilayer Wiring Board 10) Next, a description will be given of a method for manufacturing the multilayer wiring board 10. For ease of explanation, the parts that will ultimately become the components of the multilayer wiring board 10 will be described by using the reference numerals of the final components.

[0054] First, a method for manufacturing the first wiring board 20 will be described. 4, a structure is prepared in which a wiring layer 30, an insulating layer 31, and a wiring layer 32 are laminated in this order on the lower surface of the core layer 21, and a wiring layer 40, an insulating layer 41, and a wiring layer 42 are laminated in this order on the upper surface of the core layer 21. This structure can be manufactured by a known manufacturing method, for example, a build-up method, and therefore a detailed description thereof will be omitted here.

[0055] Next, in the process shown in FIG. 5, an insulating layer 43 is formed on the upper surface of the insulating layer 41 to cover the wiring layer 42. For example, the insulating layer 43 can be formed by laminating a multilayer film in which a plurality of insulating resin films in a semi-cured state are laminated on the upper surface of the insulating layer 41 so as to cover the wiring layer 42, and curing the multilayer film while applying heat and pressure. Here, the insulating layer 43 is formed so that the thickness T1 of the insulating layer 43 is thinner than the thickness T2 of the insulating layer 41. For example, the thickness T1 of the insulating layer 43 can be adjusted by adjusting the number of insulating resin films in the multilayer film. In this example, the number of insulating resin films is set to one, so that the thickness T1 of the insulating layer 43 is formed thinner than the thickness T2 of the insulating layer 41. Note that FIGS. 5 to 10 show structures corresponding to the portion shown in FIG. 2.

[0056] 6, a through hole 43X is formed in the insulating layer 43 to expose a part of the upper surface of the wiring layer 42. The through hole 43X can be formed by laser processing using, for example, a CO2 laser or a UV-YAG laser. At this time, since the thickness T1 of the insulating layer 43 is formed thin, the thickness from the upper surface of the wiring layer 42 to the upper surface of the insulating layer 43 is formed thin. This allows the depth of the through hole 43X to be shallow, and therefore the opening diameter (diameter in this example) of the through hole 43X can be made small.

[0057] Next, in the case where the through holes 43X are formed by laser processing, a desmear process is carried out to remove resin smears adhering to the exposed surface of the wiring layer 42 exposed at the bottom of the through holes 43X.

[0058] Next, in the process shown in FIG. 7, a seed layer 46 is formed so as to cover the entire upper surface of the insulating layer 43 and the entire inner surface of the through hole 43X. The seed layer 46 can be formed by, for example, a sputtering method or an electroless plating method. For example, when forming the seed layer 46 by a sputtering method, first, titanium (Ti) is deposited by sputtering on the upper surface of the insulating layer 43 and the inner surface of the through hole 43X to form a Ti layer so as to cover the upper surface of the insulating layer 43 and the inner surface of the through hole 43X. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This allows the seed layer 46 to have a two-layer structure (Ti layer / Cu layer). When forming the seed layer 46 by an electroless plating method, for example, the seed layer 46 made of a Cu layer (one-layer structure) can be formed by an electroless copper plating method.

[0059] 8, a resist layer 87 having an opening pattern 87X at a predetermined position is formed on the seed layer 46. The opening pattern 87X is formed so as to expose the seed layer 46 at a portion corresponding to the formation region of the first electrode pad 44 (see FIG. 2). The material of the resist layer 87 may be, for example, a material that is resistant to electrolytic plating in the next step. For example, the material of the resist layer 87 may be a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin). When a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the seed layer 46 by thermocompression bonding, and the dry film is patterned by a photolithography method to form the resist layer 87 having the opening pattern 87X. When a liquid photoresist is used, the resist layer 87 may be formed through the same steps.

[0060] 9, the seed layer 46 is subjected to electrolytic plating using the resist layer 87 as a plating mask, with the seed layer 46 serving as a plating power supply layer. That is, the upper surface of the seed layer 46 exposed from the opening pattern 87X of the resist layer 87 is subjected to electrolytic plating, here, electrolytic Cu plating. This process forms the metal layer 47 filling the through-holes 43X located inside the seed layer 46, and the metal layer 48 provided inside the opening pattern 87X.

[0061] Next, in a process shown in FIG. 10, the resist layer 87 shown in FIG. 9 is removed by an alkaline remover (for example, an organic amine-based remover, caustic soda, acetone, ethanol, or the like). Next, unnecessary seed layer 46 is removed by etching using metal layer 48 as an etching mask. Through this process, via wiring 44V composed of seed layer 46 and metal layer 47 formed inside through hole 43X is formed, and first electrode pad 44 composed of seed layer 46 and metal layer 48 is formed on the upper surface of insulating layer 43.

[0062] 11, an insulating layer 33 and a wiring layer 34 are laminated in this order on the lower surface of the insulating layer 31. The insulating layer 33 and the wiring layer 34 are formed, for example, at the same time as the insulating layer 43 and the first electrode pad 44.

[0063] 11, a solder resist layer 35 having openings 35X for exposing parts of the wiring layer 34 as external connection pads 34P is laminated on the lower surface of the lowermost insulating layer 33. Similarly, a solder resist layer 45 having openings 45X for exposing the mounting region of the second wiring board 60 (see FIG. 1) is laminated on the upper surface of the uppermost insulating layer 43. These solder resist layers 35, 45 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape.

[0064] Through the above manufacturing process, the first wiring board 20 of this embodiment can be manufactured. 12, the second wiring board 60 is manufactured. Note that the second wiring board 60 can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0065] Next, the second wiring board 60 is mounted on the first wiring board 20. More specifically, the solder layer 81 formed on the lower surface of the second electrode pad 70 of the second wiring board 60 is joined onto the first electrode pad 44 of the first wiring board 20.

[0066] Thereafter, the gap between the joined first wiring board 20 and second wiring board 60 is filled with underfill resin 85 (see FIG. 1), and the underfill resin 85 is cured. Through the above manufacturing steps, the multilayer wiring board 10 shown in FIG. 1 can be manufactured.

[0067] Next, the effects of this embodiment will be described. (1) In the first wiring board 20, the insulating layer 43, which is the uppermost interlayer insulating layer of the first wiring board 20, is formed thinner than the other insulating layers 41. As a result, the thickness T3 of the via wiring 44V penetrating the insulating layer 43 in the thickness direction can be made thinner than the thickness T4 of the via wiring 42V penetrating the insulating layer 41 in the thickness direction. Therefore, the diameter of the via wiring 44V can be made smaller than when the insulating layer 43 is formed to the same thickness as the insulating layer 41. Therefore, the diameter of the first electrode pad 44 connected to the via wiring 44V can be made smaller. In detail, even if there is a restriction on the accuracy of aligning the first electrode pad 44 on the via wiring 44V, the diameter of the via wiring 44V itself can be made smaller, so that the restriction on the accuracy of aligning the first electrode pad 44 on the via wiring 44V can be alleviated. As a result, the diameter of the first electrode pad 44 can be suitably made smaller in accordance with the reduction in the diameter of the via wiring 44V. As a result, it is possible to easily accommodate the narrowing of the pitch of the first electrode pad 44.

[0068] (2) By narrowing the pitch of the first electrode pads 44, for example, the number of vias in the power supply section can be increased, which contributes to improving the power supply performance. (3) Since the pitch of the first electrode pads 44 can be narrowed, for example, the number of signals that can be extracted from the second wiring board 60 to the first wiring board 20 can be increased, which contributes to a higher bandwidth for signal transmission.

[0069] (4) The first electrode pad 44 has a size smaller than the second electrode pad 70 of the second wiring board 60 in a plan view. As a result, when the first electrode pad 44 and the second electrode pad 70 are joined by the solder layer 81, the solder layer 81 formed on the lower surface of the second electrode pad 70 can be joined to the upper surface and side surfaces of the first electrode pad 44. Therefore, compared with the case where the solder layer 81 is joined only to the upper surface of the first electrode pad 44, the joining area between the first electrode pad 44 and the solder layer 81 can be increased, and the joining strength between the first electrode pad 44 and the solder layer 81 can be improved. As a result, the connection reliability between the first electrode pad 44 and the second electrode pad 70 can be improved.

[0070] Second embodiment The second embodiment will be described below with reference to Figures 13 to 20. A multilayer wiring board 10A of this embodiment differs from the first embodiment in the structure of a first wiring board 20A. The following description will focus on the differences from the first embodiment.

[0071] 13, the multilayer wiring board 10A has a first wiring board 20A and a second wiring board 60 mounted on the first wiring board 20A. The multilayer wiring board 10A has, for example, an underfill resin 85 formed in the gap between the first wiring board 20A and the second wiring board 60.

[0072] (Specific Structure of First Wiring Board 20A) The first wiring board 20A has a via wiring 50 that penetrates the insulating layer 43 in the thickness direction and has an upper end surface exposed from the insulating layer 43, and a first electrode pad 54 formed on the upper surface of the insulating layer 43 and the upper end surface of the via wiring 50.

[0073] As shown in FIG. 14, the via wiring 50 is embedded in the insulating layer 43. The via wiring 50 is filled in a through hole 43X that penetrates the insulating layer 43 in the thickness direction and exposes a part of the upper surface of the wiring layer 42. The via wiring 50 is electrically connected to the wiring layer 42 and is also electrically connected to the first electrode pad 54. The via wiring 50 is formed in a tapered shape that decreases in diameter from the upper side (the first electrode pad 54 side) to the lower side (the wiring layer 42 side) in FIG. 14. For example, the via wiring 50 is formed in an inverted truncated cone shape with a larger diameter at the upper end face than at the lower end face. The upper end face of the via wiring 50 is exposed from the insulating layer 43. The upper end face of the via wiring 50 is formed, for example, flush with the upper surface of the insulating layer 43. The upper end face of the via wiring 50 and the upper surface of the insulating layer 43 are, for example, polished surfaces. The upper end face of the via wiring 50 is directly bonded to the lower surface of the first electrode pad 54. The lower end surface of the via wiring 50 is directly joined to the upper surface of the wiring layer 42 .

[0074] The via wiring 50 has, for example, a seed layer 51 that covers the entire inner surface of the through hole 43X, and a metal layer 52 that fills the through hole 43X on the inner side of the seed layer 51. The seed layer 51 is formed so as to continuously cover, for example, the entire inner wall surface of the through hole 43X and the entire upper surface of the wiring layer 42 exposed at the bottom of the through hole 43X. For example, copper or a copper alloy can be used as the material of the seed layer 51. For example, an electroless plating layer formed by an electroless plating method or a sputtered film formed by a sputtering method can be used as the seed layer 51. The upper end surface of the metal layer 52 is formed flush with the upper surface of the insulating layer 43. For example, copper or a copper alloy can be used as the material of the metal layer 52. For example, an electrolytic plating layer formed by an electrolytic plating method can be used as the metal layer 52.

[0075] The thickness T5 of the via wiring 50 is thinner than the thickness T4 of the via wiring 42V. The thickness T5 of the via wiring 50 can be, for example, about 5 μm to 15 μm. The planar shape of the via wiring 50 can be set to any shape and any size. The planar shape of the via wiring 50 is, for example, circular. The via wiring 50 has a smaller size than the via wiring 42V in a planar view. The diameter of the via wiring 50 is, for example, smaller than the diameter of the via wiring 42V. The diameter of the upper surface of the via wiring 50 can be, for example, about 15 μm to 45 μm. The diameter of the upper surface of the via wiring 42V can be, for example, about 55 μm to 75 μm.

[0076] The first electrode pad 54 is laminated on the upper surface of the insulating layer 43 so as to be connected to the upper end surface of the via wiring 50. That is, a part of the lower surface of the first electrode pad 54 is in contact with the upper end surface of the via wiring 50, and the first electrode pad 54 and the via wiring 50 are electrically connected. In other words, the first electrode pad 54 and the via wiring 50 are electrically connected but are not integrated.

[0077] The first electrode pad 54 has a seed layer 55 that covers the upper surface of the insulating layer 43 and the upper end surface of the via wiring 50, and a metal layer 56 formed on the seed layer 55. That is, the metal layer 56 is connected to the via wiring 50 through the seed layer 55.

[0078] The seed layer 55 may be made of, for example, copper or a copper alloy. The seed layer 55 may be made of, for example, an electroless plating layer formed by an electroless plating method or a sputtered film formed by a sputtering method. The metal layer 56 is formed so as to cover the entire upper surface of the seed layer 55. The metal layer 56 may be made of, for example, copper or a copper alloy. The metal layer 56 may be made of, for example, an electrolytic plating layer formed by an electrolytic plating method.

[0079] Here, the thickness T21 of the first electrode pad 54 is, for example, thinner than the thickness T12 of the wiring layer 42. The thickness T21 of the first electrode pad 54 is, for example, thinner than the thickness T13 of the wiring layer 40. The thickness T21 of the first electrode pad 54 may be, for example, about 5 μm to 10 μm. The thicknesses T12, T13 of the wiring layers 40, 42 may be, for example, about 10 μm to 20 μm.

[0080] The planar shape of the first electrode pad 54 can be set to any shape and any size. The planar shape of the first electrode pad 54 is, for example, circular. The first electrode pad 54 has a smaller size than the second electrode pad 70 in a planar view. The diameter of the first electrode pad 54 can be, for example, about 60 μm to 85 μm. The diameter of the second electrode pad 70 can be, for example, about 90 μm to 110 μm.

[0081] 13, the second wiring board 60 is mounted on the first electrode pad 54 of the first wiring board 20A. More specifically, the first electrode pad 54 of the first wiring board 20A and the second electrode pad 70 of the second wiring board 60 are joined to each other by a solder layer 81.

[0082] (Method of Manufacturing the Multilayer Wiring Board 10A) Next, a method for manufacturing the multilayer wiring board 10A will be described. Here, a method for manufacturing the via wirings 50 and the first electrode pads 54 of the first wiring board 20A will be described in detail. Note that Fig. 15 to Fig. 20 show a structure corresponding to the portion shown in Fig. 14. Also, for ease of explanation, the portions that will ultimately become the respective components of the multilayer wiring board 10A will be described with the reference numerals of the final components.

[0083] 15, the same steps as those shown in FIGS. 4 to 10 are carried out to fill the through holes 43X of the insulating layer 43 and form a metal layer 52 that covers the upper surface of the insulating layer 43. The metal layer 52 may be formed, for example, so as to cover the entire upper surface of the insulating layer 43, or may be patterned and formed so as to cover only the upper surface of the insulating layer 43 in the vicinity of the through holes 43X. Note that the insulating layer 43 in this step may be formed, for example, to have a thickness approximately equal to that of the insulating layer 41, or may be formed thinner than the insulating layer 41.

[0084] 16, the upper surface of the insulating layer 43 and the metal layer 52 are polished by CMP (Chemical Mechanical Polishing) or the like. In this step, the upper surface of the insulating layer 43, the metal layer 52, and the seed layer 51 are polished until the thickness T1 of the insulating layer 43 becomes thinner than the thickness T2 of the insulating layer 41. As a result, as shown in FIG. 16, the via wiring 50 is formed, which is composed of the seed layer 51 covering the inner surface of the through hole 43X and the metal layer 52 filling the through hole 43X inside the seed layer 51, and the upper end surface of the via wiring 50 is formed flush with the upper surface of the insulating layer 43. In addition, this step makes the thickness T5 of the via wiring 50 thinner than before polishing, and the diameter of the upper end surface of the via wiring 50 smaller than before polishing. Furthermore, by polishing the upper surface of the insulating layer 43, the upper surface of the insulating layer 43 is smoothed. For example, while the roughness of the upper surface of insulating layer 43 before polishing is about 300 nm to 400 nm in terms of surface roughness Ra, the roughness of the upper surface of insulating layer 43 can be reduced to about 15 nm to 40 nm in terms of surface roughness Ra by polishing. Note that, by the polishing in this process, the upper surface of insulating layer 43 and the upper end surfaces of via wirings 50 become polished surfaces.

[0085] 17, a seed layer 55 is formed to cover the entire upper surface of the insulating layer 43 and the entire upper end surface of the via wiring 50. The seed layer 55 can be formed by, for example, a sputtering method or an electroless plating method. The seed layer 55 can be formed by, for example, a method similar to the step shown in FIG.

[0086] Next, in the step shown in FIG. 18, a resist layer 88 having an opening pattern 88X at a predetermined position is formed on the seed layer 55. The opening pattern 88X is formed so as to expose the seed layer 55 in a portion corresponding to the formation region of the first electrode pad 54 (see FIG. 14). The material of the resist layer 88 may be, for example, a material that is resistant to electrolytic plating in the next step. For example, the material of the resist layer 88 may be a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin). The resist layer 88 may be formed, for example, by a method similar to the step shown in FIG. 8.

[0087] 19, using the resist layer 88 as a plating mask, electrolytic plating is performed on the seed layer 55, utilizing the seed layer 55 as a plating power supply layer. That is, electrolytic plating, here Cu electrolytic plating, is performed on the upper surface of the seed layer 55 exposed from the opening pattern 88X of the resist layer 88. By this process, the metal layer 56 provided inside the opening pattern 88X is formed.

[0088] Next, in a process shown in FIG. 20, the resist layer 88 shown in FIG. 19 is removed by an alkaline remover (for example, an organic amine-based remover, caustic soda, acetone, ethanol, or the like).

[0089] Next, unnecessary seed layer 55 is removed by etching using metal layer 56 as an etching mask. By this process, first electrode pads 54 composed of seed layer 55 and metal layer 56 are formed on the upper surface of insulating layer 43 and the upper end surfaces of via wirings 50.

[0090] According to the embodiment described above, in addition to the effects (1) to (4) of the first embodiment, the following effects can be achieved. (5) In the first wiring board 20A, the insulating layer 43, which is the uppermost interlayer insulating layer of the first wiring board 20A, is polished by CMP or the like to be thinner than the other insulating layers 41. This allows the thickness T1 of the insulating layer 43 to be thinner than a single insulating resin film. Therefore, the thickness T5 of the via wiring 50 penetrating the insulating layer 43 in the thickness direction can be suitably thinner than the thickness T4 of the via wiring 42V penetrating the insulating layer 41 in the thickness direction. Therefore, the diameter of the via wiring 50 can be made smaller, and the diameter of the first electrode pad 54 connected to the via wiring 50 can be made smaller. As a result, it is possible to easily accommodate narrower pitches of the first electrode pads 54.

[0091] (Other embodiments) The above-described embodiments may be modified as follows: The above-described embodiments and the following modifications may be combined with each other to the extent that no technical contradiction occurs.

[0092] The number of wiring layers and insulating layers and the layout of the wiring in the first wiring boards 20 and 20A in each of the above embodiments can be modified and changed in various ways. In each of the above-described embodiments, the wiring layers 40, 30 above and below the core layer 21 are electrically connected to each other via the through electrodes 22 that fill the through holes 21X of the core layer 21. However, the present invention is not limited to this, and the wiring layers 40, 30 above and below the core layer 21 may be electrically connected to each other via a through-hole plating layer provided on the inner wall of the through hole 21X. In this case, the hole of the through hole 21X formed on the inside of the through-hole plating layer may be filled with resin.

[0093] In each of the above embodiments, the solder resist layer 35, 45 was given as an example of the protective insulating layer that is the outermost layer of the first wiring board 20, 20A, but the protective insulating layer can be formed from various types of insulating resins having photosensitivity.

[0094] The solder resist layers 35, 45 in the above embodiments may be omitted. In each of the above embodiments, one second wiring board 60 is mounted on the first wiring board 20, 20A, but this is not limited to the above. For example, multiple second wiring boards 60 may be mounted on the first wiring board 20, 20A.

[0095] The number of wiring layers and insulating layers in the second wiring board 60 of each of the above embodiments, the layout of the wiring, etc. can be modified and changed in various ways. For example, the insulating layer 71 may be omitted.

[0096] In each of the above embodiments, the semiconductor chip 91 is mounted on the multilayer wiring substrate 10. However, the present invention is not limited to this, and instead of the semiconductor chip 91, for example, electronic components other than semiconductor chips, such as chip components such as chip capacitors, chip resistors, and chip inductors, or crystal resonators, may be mounted on the multilayer wiring substrate 10.

[0097] Furthermore, the mounting form (for example, flip chip mounting, wire bonding mounting, solder mounting, or a combination of these) of electronic components such as the semiconductor chip 91, chip components, and crystal resonators can be modified or changed in various ways. [Explanation of symbols]

[0098] 10,10A multilayer wiring board 20,20A First wiring board 40 Wiring layer (1st wiring layer) 41 Insulating layer (first insulating layer) 41X through hole (2nd through hole) 42 Wiring layer (2nd wiring layer) 42V via wiring (second via wiring) 43 Insulating layer (second insulating layer) 43X through hole (1st through hole) 44 First electrode pad 44V via wiring (first via wiring) 50 Via wiring (third via wiring) 51 Seed layer (first seed layer) 52 Metal layer (first metal layer) 54 First electrode pad 55 Seed layer (second seed layer) 56 Metal layer (second metal layer) 60 Second wiring board 61 Wiring structure 70 Second electrode pad T1 Thickness T2 Thickness T3 Thickness T4 Thickness T5 Thickness

Claims

1. A first wiring board and a second wiring board mounted on the first wiring board, The first wiring substrate is A first wiring layer; a first insulating layer covering the first wiring layer; a second wiring layer laminated on an upper surface of the first insulating layer and electrically connected to the first wiring layer; a second insulating layer laminated on an upper surface of the first insulating layer so as to cover the second wiring layer; a first electrode pad that is laminated on an upper surface of the second insulating layer and is electrically connected to the second wiring layer; The second wiring board is a wiring structure having a higher wiring density than the first wiring substrate; a second electrode pad connected to the first electrode pad, The thickness of the second insulating layer is thinner than the thickness of the first insulating layer.

2. the second insulating layer has a first through hole penetrating the second insulating layer in a thickness direction and exposing a part of an upper surface of the second wiring layer; 2. The multilayer wiring board according to claim 1, wherein the first electrode pad is formed integrally with a first via wiring filling the first through hole.

3. the first insulating layer has a second through hole penetrating the first insulating layer in a thickness direction and exposing a part of an upper surface of the first wiring layer; the second wiring layer is formed integrally with a second via wiring filling the second through hole, The multilayer wiring board according to claim 2 , wherein the first via wiring has a size smaller than that of the second via wiring in a plan view.

4. the second insulating layer has a first through hole penetrating the second insulating layer in a thickness direction and exposing a part of an upper surface of the second wiring layer; the first wiring board has a third via wiring filling the first through hole and having an upper end surface exposed from the second insulating layer; an upper end surface of the third via wiring is formed flush with an upper surface of the second insulating layer; 2. The multilayer wiring board according to claim 1, wherein the first electrode pad is formed on an upper surface of the second insulating layer and an upper end surface of the third via wiring.

5. the third via wiring includes a first seed layer that covers an entire inner surface of the first through hole and an upper surface of the second wiring layer exposed from the first through hole, and a first metal layer that fills the first through hole on the inner side of the first seed layer; 5. The laminated wiring board according to claim 4, wherein the first electrode pad has a second seed layer covering an upper end surface of the third via wiring and an upper surface of the second insulating layer, and a second metal layer formed on the second seed layer.

6. an upper end surface of the third via wiring is a polished surface; 5. The multilayer wiring board according to claim 4, wherein an upper surface of the second insulating layer is a polished surface.

7. 2. The multilayer wiring board according to claim 1, wherein the first electrode pad has a size smaller than that of the second electrode pad in a plan view.

8. A laminated wiring board according to any one of claims 1 to 7, a semiconductor chip mounted on the second wiring substrate.

9. forming a first wiring substrate having a first electrode pad; forming a second wiring substrate having a wiring structure having a higher wiring density than the first wiring substrate and second electrode pads connected to the first electrode pads; and mounting the second wiring substrate on the first wiring substrate. The step of forming the first wiring substrate includes: forming a first insulating layer covering the first wiring layer; forming a second wiring layer on an upper surface of the first insulating layer, the second wiring layer being electrically connected to the first wiring layer; forming a second insulating layer on an upper surface of the first insulating layer so as to cover the second wiring layer; forming the first electrode pad electrically connected to the second wiring layer on an upper surface of the second insulating layer; The method for manufacturing a laminated wiring board, wherein the second insulating layer is formed to be thinner than the first insulating layer.

10. The step of forming the second insulating layer and the first electrode pad includes: forming the second insulating layer on an upper surface of the first insulating layer; forming a first through hole penetrating the second insulating layer in a thickness direction and exposing a portion of an upper surface of the second wiring layer; forming a metal layer that fills the first through hole and covers an upper surface of the second insulating layer; a step of polishing the metal layer and an upper surface of the second insulating layer to thin the second insulating layer and form a third via wiring having an upper end surface exposed from the second insulating layer and filling the first through hole; forming the first electrode pad so as to cover an upper surface of the second insulating layer after thinning and an upper end surface of the third via wiring; The method for manufacturing a multilayer wiring board according to claim 9 , further comprising:

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