Binarized neural network circuit using silicon gate diodes

Abstract

To provide a self-active binarized neural network circuit that self-performs an activation function.SOLUTION: A neural network circuit 400 includes a plurality of silicon gate diodes implementing unidirectional switching by potential barrier adjustment in a channel region based on mutually different voltages applied to an anode terminal and a gate terminal, and implementing memory characteristics by accumulating holes or electrons in a potential well by a positive feedback loop. The plurality of silicon gate diodes function as a synaptic element 401 in a memory array connected in parallel and output a result of a MAC operation based on an input signal applied from an input line processing unit connected to the memory array and a weighted value update signal applied from a synaptic line processing unit connected to the memory array.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a binarized neural network circuit using silicon gated diodes, and more particularly to a technology for implementing a self-activating binarized neural network that performs an activation function by itself using a silicon gated diode that performs memory and switching functions in a single element based on a positive feedback loop. [Background technology]

[0002] In the existing von Neumann-based computer system, the processor and memory are separated, and data signals are transmitted via a bus line.

[0003] However, as computing performance increases, a bottleneck phenomenon occurs due to the difference in data processing speed between the processor and memory, and a limit is being reached in processing large amounts of data.

[0004] In other words, a revolutionary development in the semiconductor industry, von Neumann-based systems have increased the integration density and performance of modern computers, but they have the drawback of consuming a lot of energy and increasing data transmission and latency due to the physical separation between the processor and memory hierarchy.

[0005] Since the Fourth Industrial Revolution, and considering the increase in data-intensive applications such as 5G communication standards, Internet of Things (IoT), Artificial Intelligence (AI), etc., a new computing paradigm is mandatory for large-scale data processing requirements.

[0006] In order to solve the above problems, research into logic in memory (LIM) technology, which combines computing and memory functions, is being intensively and accelerated.

[0007] Logic-in-memory technology performs the processor's calculation functions and memory's storage functions in the same space, reducing latency and power consumption that occurs during data transmission and greatly improving the system integration.

[0008] Conventional logic-in-memory technology has been actively researched based on volatile memory elements such as SRAM (static random access memory) and DRAM (dynamic RAM), and non-volatile memory elements such as ReRAM (resistive RAM), MRAM (magnetoresistive RAM), and PCRAM (phase-change RAM).

[0009] In order to overcome the limitations of large-volume data processing, POP (Package On Package) and TSV (Through Silicon Via) technologies that integrate logic memory into a single chip are being researched. However, since logic and memory functions are not performed simultaneously in transistors, problems related to bottlenecks, power consumption, calculation efficiency, and integration density still remain.

[0010] In addition, logic-in-memory technology based on non-volatile memory elements requires complex process steps because it uses non-silicon materials, and is difficult to put into practical use due to low element uniformity and stability.

[0011] In addition, logic-in-memory technologies that have been developed so far have low integration levels because they cannot implement all basic CMOS (complementary metal-oxide semiconductor) logic operations in a single cell and each logic operation requires separate circuits and wiring.

[0012] Therefore, there is a need to develop a binary neural network technology that can be applied to CMOS processes and uses silicon gated diodes that perform both switching and memory functions, and a self-activating neural network technology that performs the activation function of neuron circuits by itself within the neural network. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Korean Patent Publication No. 10-2023-0053195 (Stateful Logic-in-Memory Using Silicon Diodes) [Patent Document 2] Korean Patent Publication No. 10-2022-0110774 (Performance and area-efficient synapse memory cell structure) [Patent Document 3] Korean Patent Publication No. 10-2023-0020840 (Configurable logic-in-memory element using silicon transistors) [Patent Document 4] Korean Patent Publication No. 10-2022-0107808 (Mixed signal binarization neural network circuit device) Summary of the Invention [Problem to be solved by the invention]

[0014] The present invention aims to realize a self-activating binary neural network circuit that performs an activation function by itself using a silicon gated diode that performs memory and switching functions in a single element based on a positive feedback loop.

[0015] The present invention aims to realize a self-activating binary neural network circuit that can increase the area and calculation efficiency of an artificial neural network by having the excellent memory characteristics of a silicon gated diode, which has unidirectional switching characteristics through potential barrier control and memory characteristics due to the accumulation of holes or electrons in a potential well by a positive feedback loop, and a self-activating function through the linearity of an output signal according to an input signal.

[0016] The present invention is capable of utilizing a CMOS process, making it possible to fabricate a large-scale array, and aims to eliminate almost all deviations in characteristics between silicon gated diodes and synaptic devices, thereby increasing the accuracy of calculations in artificial neural networks.

[0017] The present invention aims to realize a binary neural network circuit with excellent uniformity and stability, in which a memory array composed of a silicon gated diode based on a positive feedback loop performs the activation function of a neuron circuit by itself.

[0018] The present invention aims to realize a binarized neural network circuit that can be used in next-generation artificial intelligence computing technology by reducing standby power using the excellent memory characteristics of a silicon gated diode and increasing computing efficiency with low power consumption through excellent switching characteristics. [Means for solving the problem]

[0019] In the binarized neural network circuit according to an embodiment of the present invention, a diode structure is located between an anode terminal and a cathode terminal as a channel region, a gate terminal is located on the diode structure, and unidirectional switching is implemented in the channel region through potential barrier adjustment based on different voltages applied to the anode terminal and the gate terminal, respectively. The binarized neural network circuit includes a plurality of silicon gated diodes that implement memory characteristics by accumulating holes or electrons in the potential well by a positive feedback loop. The plurality of silicon gated diodes operate as synapse elements in a memory array connected in parallel, and can output a result of a multiply-accumulate (MAC) operation based on an input signal applied from an input line processing unit connected to the memory array and a weight update signal applied from a synapse line processing unit connected to the memory array.

[0020] The silicon gated diode receives an anode voltage of the anode terminal as the input signal, and generates a latch-up phenomenon due to the positive feedback loop as the applied input signal increases in a positive direction. The channel region has one of two memory states, and receives a gate voltage of the gate terminal as the weight update signal, thereby adjusting the input signal at which the latch-up phenomenon occurs. A synapse state associated with one of the memory states is updated by application of the input signal and the weight update signal, and the MAC operation function can be performed according to the synapse weight.

[0021] The silicon gated diode performs a multiplication operation between the continuous input from “0” to “1” as the applied input signal increases in a positive direction and a synaptic weight value of either the “0” state or the “1” state corresponding to the two memory states, and outputs a current signal corresponding to either “0” or “1” as a result of the operation.

[0022] In the case of a potentiation operation in which the synaptic weight value is updated to the “1” state, the silicon gated diode outputs the operation result as a current signal proportional to the applied input signal, and in the case of a depression operation in which the synaptic weight value is updated to the “0” state, the silicon gated diode outputs a current signal of 0 mA regardless of the applied input signal.

[0023] When the synapse weight value is in a "1" state, the silicon gated diode may output a cathode current of the cathode terminal in a form similar to the outline of a graph of a rectified linear unit (ReLU) function, regardless of the gate voltage.

[0024] The memory array may form input lines, weighted value lines, and output lines by connecting the anode terminals, the gate terminals, and the cathode terminals of the plurality of silicon gated diodes in parallel, and the input lines may be arranged perpendicular to the weighted value lines and the output lines, and the weighted value lines and the output lines may be arranged in parallel.

[0025] The input line can receive the input signal, the weight line can receive the weight update signal, and the output line can output the result of the MAC operation based on the input signal and the weight update signal to a next artificial neural network terminal.

[0026] The memory array may include a plurality of silicon gated diodes connected in a form of N×M, and may perform a sum operation by adding up each current through the output line through a multiplication operation of synapse weights updated based on an input signal applied to the input line and a weight update signal applied to the weight line, and may output a result of the MAC operation as a synapse weight matrix.

[0027] When N and M are "2", the memory array may be configured such that the input signals are composed of a first input signal and a second input signal, the synaptic weight values ​​are composed of first to fourth synaptic weight values, the memory array is configured of a first current and a second current output to the output line, and the synaptic weight value matrix composed of the first current and the second current is calculated as a result of a vector matrix multiplication operation of the synaptic weight values ​​and the input signals.

[0028] When the first and second input signals are both applied with the weight update signal fixed at 1V, the first current has twice the value of the second current, and then when only the first input signal is applied, the first current and the second current may have the same value.

[0029] The memory array may be measured such that when only the second input signal is applied, only the first current has a value proportional to the second input signal, and when neither the first input signal nor the second input signal is applied, the first current and the second current approximate 0 mA.

[0030] The silicon gated diode may include any one of a single silicon gated diode, a double silicon gated diode, and a triple silicon gated diode. Effect of the Invention

[0031] The present invention can realize a self-activating binary neural network circuit that performs an activation function by itself using a silicon gated diode that performs memory and switching functions in a single element based on a positive feedback loop.

[0032] The present invention realizes a self-activating binary neural network circuit that can increase the area and calculation efficiency of an artificial neural network by having excellent memory characteristics of a silicon gated diode, which has unidirectional switching characteristics through potential barrier control and memory characteristics due to the accumulation of holes or electrons in a potential well by a positive feedback loop, and a self-activating function through the linearity of an output signal according to an input signal.

[0033] Since the present invention can utilize a CMOS process, it is possible to fabricate a large-scale array, and since there is almost no characteristic deviation between the silicon gated diode and the synaptic element, it is possible to increase the calculation accuracy of the artificial neural network.

[0034] In the present invention, a memory array composed of a silicon gated diode based on a positive feedback loop performs the activation function of a neuron circuit by itself, and a binary neural network circuit with excellent uniformity and stability can be realized.

[0035] The present invention reduces standby power by using the excellent memory characteristics of silicon gated diodes, and increases computing efficiency with low power consumption through excellent switching characteristics, thereby realizing a binarized neural network circuit that can be used in next-generation artificial intelligence computing technology. [Brief description of the drawings]

[0036] [Figure 1a] FIG. 2 is a diagram for explaining the structure and circuit symbol of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 1b]FIG. 2 is a diagram for explaining the structure and circuit symbol of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 2a] FIG. 2 is a diagram for explaining the structure and circuit symbol of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 2b] FIG. 2 is a diagram for explaining the structure and circuit symbol of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 3a] FIG. 1 is a diagram for explaining the electrical characteristics of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 3b] FIG. 1 is a diagram for explaining the electrical characteristics of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 3c] FIG. 1 is a diagram for explaining the electrical characteristics of a silicon gated diode that constitutes a binary neural network circuit according to an embodiment of the present invention. [Figure 4] FIG. 1 is a diagram illustrating a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 5a] FIG. 1 is a diagram for explaining a multiplication operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 5b] FIG. 1 is a diagram for explaining a multiplication operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 6a] FIG. 1 is a diagram for explaining a multiplication operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 6b] FIG. 1 is a diagram for explaining a multiplication operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 7a]FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 7b] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 8a] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 8b] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 9a] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 9b] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 9c] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 9d] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 9e] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 9f] FIG. 2 is a diagram for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 10] FIG. 2 is a diagram illustrating an optical image of a silicon gated diode according to an embodiment of the present invention. [Figure 11a] FIG. 1 is a diagram for explaining the calculation operation of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 11b] FIG. 1 is a diagram for explaining the calculation operation of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. [Figure 11c] FIG. 1 is a diagram for explaining the calculation operation of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] In the following, various embodiments of the present document will be described with reference to the accompanying drawings.

[0038] The examples and the terms used therein are not intended to limit the technology described in this document to a particular embodiment, but should be understood to include various modifications, equivalents, and / or alternatives of the relevant examples.

[0039] In the following description of various embodiments, if it is determined that a detailed description of related known functions or configurations may obscure the gist of the invention, the detailed description thereof will be omitted.

[0040] In addition, each term described below is defined in consideration of the functions in various embodiments, and may vary depending on the intentions or practices of users and operators, etc. Therefore, each term should be defined based on the overall content of this specification.

[0041] In connection with the description of the drawings, like reference numbers may be used for like components.

[0042] A singular expression can include a plural expression unless the context clearly indicates otherwise.

[0043] In this document, phrases such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0044] The expressions "first," "second," "initial," or "second" may modify the corresponding element without regard to order or importance, and are merely used to distinguish one element from other elements, and do not limit the corresponding element.

[0045] When a reference is made to a (e.g., first) component being "(functionally or communicatively) coupled" or "connected" to another (e.g., second) component, the component may be directly coupled to the other component or may be coupled through another component (e.g., a third component).

[0046] As used herein, "configured (or set)" may be used interchangeably with, for example, hardware or software "suitable for," "capable of," "modified to," "made to," "capable of," or "designed to," depending on the context.

[0047] In any context, the phrase "an apparatus configured to" may mean that the apparatus is "capable of" in conjunction with other apparatus or components.

[0048] For example, the phrase "a processor configured (or set) to perform A, B, and C" may refer to a dedicated processor for performing the corresponding operations (e.g., an embedded processor), or to a general-purpose processor (e.g., a CPU or application processor) that can perform the corresponding operations by executing one or more software programs stored in a memory device.

[0049] Additionally, the term "or" means an inclusive or rather than an exclusive or.

[0050] That is, unless otherwise stated or clear from the context, the phrase "x uses a or b" means any one of the natural inclusive permutations.

[0051] As used below, the terms "module", "machine", etc. refer to a unit that processes at least one function or operation, and may be embodied in hardware, software, or a combination of hardware and software.

[0052] 1a to 2b are diagrams for explaining the structure and circuit symbol of a silicon gated diode constituting a binarized neural network circuit according to an embodiment of the present invention.

[0053] 1a and 1b illustrate the structure and circuit symbol of a single silicon gated diode constituting a binarized neural network circuit according to one embodiment of the present invention.

[0054] Referring to FIG. 1a, a silicon gated diode 100 constituting a binary neural network circuit according to one embodiment of the present invention has a channel region between an anode terminal 101 and a cathode terminal 104, which is composed of a first channel region 102 and a second channel region 103.

[0055] A gate insulating film 105 is located on the second channel region 103 , and a gate terminal 106 is located on the gate insulating film 105 .

[0056] A circuit symbol 110 of a silicon gated diode constituting a binary neural network circuit according to one embodiment of the present invention has a channel region 112 located between an anode terminal 111 and a cathode terminal 113, to which a gate terminal 114 is connected.

[0057] Referring to FIG. 1b, a silicon gated diode 120 constituting a binary neural network circuit according to one embodiment of the present invention has a channel region between an anode terminal 121 and a cathode terminal 124, which is composed of a first channel region 122 and a second channel region 123.

[0058] A gate insulating film 125 is located on the first channel region 122 , and a gate terminal 126 is located on the gate insulating film 125 .

[0059] A circuit symbol 130 of a silicon gated diode constituting a binary neural network circuit according to one embodiment of the present invention has a channel region 132 located between an anode terminal 131 and a cathode terminal 133, to which a gate terminal 134 is connected.

[0060] According to one embodiment of the present invention, an input line is connected to the anode terminal 111 or the anode terminal 131, an output line is connected to the cathode terminal 113 or the cathode terminal 133, and the memory state of the channel region is determined by updating the synaptic weights.

[0061] FIG. 2a illustrates the structure and circuit symbol of a double silicon gated diode constituting a binarized neural network circuit according to one embodiment of the present invention.

[0062] Referring to FIG. 2a, a silicon gated diode 200 constituting a binary neural network circuit according to one embodiment of the present invention has an intrinsic region 202 located between an anode terminal 201 and a cathode terminal 203, a gate insulating film 204 located on the intrinsic region 202, and a first gate terminal 205 and a second gate terminal 206 located on the gate insulating film 204.

[0063] The intrinsic region 202 operates as a channel region based on a gate voltage input from either a first gate terminal 205 or a second gate terminal 206 .

[0064] A circuit symbol 210 of a silicon gated diode constituting a binary neural network circuit according to one embodiment of the present invention has an intrinsic region 212 located between an anode terminal 211 and a cathode terminal 213, to which a first gate terminal 214 and a second gate terminal 215 are connected.

[0065] FIG. 2b illustrates the structure and circuit symbol of a triple silicon gated diode constituting a binarized neural network circuit according to one embodiment of the present invention.

[0066] Referring to FIG. 2b, a silicon gated diode 220 constituting a binary neural network circuit according to one embodiment of the present invention has an intrinsic region 222 located between an anode terminal 221 and a cathode terminal 223, a gate insulating film 224 located on the intrinsic region 222, and a programming gate terminal 225 and a control gate terminal 226 located on the gate insulating film 224.

[0067] The intrinsic region 222 acts as a channel region based on a gate voltage input from a programming gate terminal 225 .

[0068] More specifically, when the level of the program voltage (VPG) input from the intrinsic region 222 to the programming gate terminal 225 is high, the intrinsic region 222 may operate as an n-channel corresponding to a first channel operation, and when the level of the program voltage (VPG) is low, the intrinsic region 222 may operate as a p-channel corresponding to a second channel operation.

[0069] When performing a first channel operation, the silicon gated diode 220 may be determined to be in an on state when the level of the control voltage (VCG) input through the control gate terminal 226 is a high level, and may be determined to be in an off state when the level of the control voltage (VCG) applied through the control gate terminal 226 is a low level.

[0070] A circuit symbol 230 of a silicon gated diode constituting a binary neural network circuit according to one embodiment of the present invention has an intrinsic region 232 located between an anode terminal 231 and a cathode terminal 233, to which a programming gate terminal 234 and a control gate terminal 235 are connected.

[0071] For example, the anode terminal, the gate terminal and the cathode terminal may be replaced with an anode electrode, a cathode electrode and a gate electrode, and each terminal may be referred to as an electrode.

[0072] That is, the silicon gated diode constituting the binary neural network circuit according to one embodiment of the present invention may have a structure in which a single gated electrode terminal is deposited on an n- or p-type doped channel region on a silicon channel, or a plurality of gated electrode terminals are deposited on an intrinsic doped region.

[0073] Silicon gated diodes also operate by inducing a positive feedback loop due to the potential barrier, and can be configured as synaptic elements in binarized neural networks because they have switching and memory properties.

[0074] In other words, since the silicon gated diode has switching and memory characteristics, it is possible to realize a self-activating binary neural network circuit that performs the activation function of a neuron circuit in a neural network by itself.

[0075] Therefore, the present invention can realize a self-activating binary neural network circuit that performs an activation function by itself using a silicon gated diode that performs memory and switching functions in a single element based on a positive feedback loop.

[0076] 3a to 3c are diagrams for explaining the electrical characteristics of a silicon gated diode constituting a binarized neural network circuit according to an embodiment of the present invention.

[0077] 3a to 3c illustrate the electrical characteristics of a silicon gated diode constituting a binarized neural network circuit according to one embodiment of the present invention.

[0078] Referring to FIG. 3a, a graph 300 relating to the electrical characteristics of a silicon gated diode constituting a binarized neural network circuit according to an embodiment of the present invention is shown as a graph of the anode voltage (V IN ) is the cathode current (I Diode ) changes.

[0079] Graph 300 shows the anode voltage (V IN ) in the positive direction, a latch-up phenomenon occurs due to a positive feedback loop, and it can have two states.

[0080] Also, the gate voltage of the silicon gated diode (V W ) changes the anode voltage at which latch-up occurs.

[0081] The binarized neural network circuit can apply anode voltages and gate voltages based on the characteristics of such single elements, and perform synaptic weight value updates and MAC (multiply-accumulate) calculation functions.

[0082] The cathode current (I Diode ) can be roughly similar to the graph of the ReLU (rectified linear unit) function.

[0083] The ReLU function can be the activation function of neuron circuits used in most artificial neural network architectures.

[0084] In other words, the silicon gated diode constituting the binary neural network of the present invention can embody a self-activating binary neural network circuit that self-activates a neuron circuit by having an approximate shape of a ReLU function in a synaptic weight value state where the output current is “1” regardless of the gate voltage.

[0085] Through the unidirectional switching or self-rectifying characteristics and high linearity of a single silicon gated diode, a self-activating binary neural network that performs an activation function by itself can be realized.

[0086] Referring to FIG. 3b, a graph 310 related to the electrical characteristics of a silicon gated diode constituting a binarized neural network circuit according to an embodiment of the present invention is a graph showing the electrical characteristics of a silicon gated diode when an anode voltage (V IN ) is the cathode current (I Diode ) in relation to the change in gate voltage (V W ) is 0V.

[0087] Referring to FIG. 3c, a graph 320 related to the electrical characteristics of a silicon gated diode constituting a binarized neural network circuit according to an embodiment of the present invention is a graph showing the electrical characteristics of a silicon gated diode when an anode voltage (V IN ) is the cathode current (I Diode ) in relation to the change in gate voltage (V W ) is 1V.

[0088] Anode voltage (V IN ) is 0V, it may correspond to a standby state.

[0089] Graph 320 shows the BNN (Bayesian Neural Network) operating conditions, and the anode voltage (V IN ) increases, the gate voltage (V W ) is about 2.5V and 1V, the cathode current (I Diode ) increases rapidly.

[0090] Graph 320 shows the anode voltage (V IN ) decreases, indicating that the positive feedback loop is eliminated at about 1 V.

[0091] The bistable characteristic is due to the cathode current (I Diode ) vs anode voltage (V IN ), and the high ratio of the magnitude of the current in states 1 and 0 is about 10 8 It could be.

[0092] Anode voltage of 2V (V IN ) vs. gate voltage (V W ) is 1V, it inherits the electrical characteristics of a pn diode with unipolar switching characteristics.

[0093] Gate voltage (V W ) the cathode current in state 1 (I Diode ) vs anode voltage (V IN) is similar to the shape of the rectified linear unit function used in the activation function of neural networks.

[0094] The cathode current (I Diode ) may be used for the MAC computation.

[0095] FIG. 4 is a diagram for explaining a binarized neural network circuit using silicon gated diodes according to an embodiment of the present invention.

[0096] FIG. 4 illustrates a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0097] Referring to FIG. 4, in a binarized neural network circuit 400 using silicon gated diodes according to an embodiment of the present invention, a diode structure between an anode terminal and a cathode terminal is positioned as a channel region, a gate terminal is positioned on the diode structure, and unidirectional switching is implemented through potential barrier adjustment in the channel region based on different voltages applied to the anode terminal and the gate terminal, respectively. A positive feedback loop is provided to accumulate holes or electrons in a potential well, thereby implementing memory characteristics.

[0098] For example, the binarized neural network circuit 400 using silicon gated diodes may be an artificial neural network that reduces calculation time and power consumption by binarizing synaptic weights.

[0099] Therefore, the present invention can realize a self-activating binary neural network circuit that can increase the area and calculation efficiency of an artificial neural network by having the excellent memory characteristics of a silicon gated diode, which has unidirectional switching characteristics through potential barrier adjustment and memory characteristics due to the accumulation of holes or electrons in a potential well by a positive feedback loop, and a self-activating function through the linearity of an output signal according to an input signal.

[0100] A plurality of silicon gated diodes are connected in parallel to operate as synapse elements 401 in a memory array, and can output the result of a multiply-accumulate (MAC) operation based on an input signal applied from an input line processing unit 402 connected to the memory array and a weighted value update signal applied from a synapse line processing unit 403 connected to the memory array.

[0101] In the memory array as the binarized neural network circuit 400, the anode terminal, the gate terminal and the cathode terminal of a plurality of silicon gated diodes are connected in parallel to form an input line (IL), a weight line (WL) and an output line (OL), respectively, and the input line (IL) is arranged perpendicular to the weight line (WL) and the output line (OL), and the weight line (WL) and the output line (OL) may be arranged in parallel.

[0102] The anode terminal is connected to an input line (IL), the gate terminal is connected to a weight line (WL), and the cathode terminal is connected to an output line (OL).

[0103] The gate terminal and the cathode terminal may form a weight line (WL) and an output line (OL), respectively.

[0104] For example, in a memory array, a first weight line (WL0) to an M-th weight line (WL m), and the first output line (OL0) to the Mth output line (OL m ).

[0105] The number of input lines (IL) corresponding to columns and the number of output lines (OL) corresponding to rows may be the same or different.

[0106] However, the weight lines (WL) and output lines (OL) must have the same number (M).

[0107] For example, since the number of elements constituting the rows and columns can be configured to be equal to the number of inputs and outputs, N and M can be the same or different numbers.

[0108] For example, in a memory array, the first input line (IL0) to the Nth input line (IL1) are numbered according to N, which is the number of columns of silicon gated diodes. n ).

[0109] The silicon gated diode receives the anode voltage of the anode terminal as an input signal, and generates a latch-up phenomenon due to a positive feedback loop as the applied input signal increases in the positive direction.

[0110] The silicon gated diode has one of two memory states for the channel region, and receives a gate voltage of the gate terminal as a weight update signal, so that an input signal at which the latch-up phenomenon occurs can be adjusted.

[0111] In addition, the silicon gated diode can update a synapse state associated with any one memory state by applying an input signal and a weight update signal, and perform a MAC operation function according to a synapse weight.

[0112] As an example, a silicon gated diode can perform a multiplication operation between successive inputs from “0” to “1” as the applied input signal increases in a positive direction and a synaptic weight value of one of two memory states, a “0” state and a “1” state, and output a current signal corresponding to one of “0” and “1” as the operation result.

[0113] 5a to 6b are diagrams for explaining a multiplication operation in the operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention.

[0114] FIG. 5a illustrates a multiplication operation in the operation mode of a binarized neural network circuit using a silicon gated diode according to one embodiment of the present invention.

[0115] Referring to FIG. 5a, the operation method of the binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention is divided into a first case 500 and a second case 501, and a MAC operation is performed between the input signal and the synaptic weight value.

[0116] Therefore, the binarized neural network circuit can implement artificial intelligence functions such as image recognition through successive layers of neural networks.

[0117] The synapse weights can be updated through the input voltages on the input lines and the weight lines.

[0118] The input signal (V IN ) can have continuous values, which may mean a continuous input (A) from 0 to 1 in a binarized neural network.

[0119] The corresponding current signal (I OUT ) can be read through OL, and at this time, the input (A) is converted to an input signal (VIN ) can have the form of a ReLU function for

[0120] The operations corresponding to the first case 500 and the second case 501 can be summarized as shown in Table 1 below.

[0121] [Table 1]

[0122] A silicon gated diode has two memory states, a "1" state and a "0" state, which may represent a binarized synaptic weight value (W(0, 1)).

[0123] In the first case 500, when the synaptic weight (W) is 0, this is the state in which the silicon gated diode is turned off (the “0” state), so that the applied input signal (V IN ), regardless of the output current (I OUT ) flows at a very low level.

[0124] With respect to the anode voltage (A) ranging from 0 to 1, a voltage less than the reference voltage corresponds to 0, and a voltage greater than the reference voltage corresponds to 1.

[0125] For example, if the reference voltage is 1V, a voltage equal to or greater than 1V may correspond to 1.

[0126] On the other hand, at the output, a current larger than a reference current of 0 to 1 is output as 1, and a current smaller than the reference current is output as 0.

[0127] This may mean that in the MAC operation of a binarized neural network, the result of the multiplication operation between the anode voltage and the synaptic weight value is always 0, regardless of the input signal.

[0128] In the second case 501, when the synapse weight (W) is 1, this is a state in which the silicon gated diode is turned on ("1" state), so the output current (IOUT ) is applied to the input signal (V IN ) can vary linearly in proportion to

[0129] This means that in the MAC operation of a binarized neural network, the result of the multiplication operation between the anode voltage and the synaptic weight value can be proportional to the input.

[0130] According to one embodiment of the present invention, a silicon gated diode performs a multiplication operation between successive inputs from “0” to “1” as an applied input signal increases in a positive direction and a synaptic weight value of one of two memory states, “0” and “1”, and outputs a current signal corresponding to either “0” or “1” as a result of the operation.

[0131] Here, in relation to the input going from "0" to "1" with an increase or decrease in a positive direction, a voltage below the reference voltage corresponds to "0" and a voltage above the reference voltage corresponds to "1".

[0132] For example, if the reference voltage is 1V, a voltage equal to or greater than 1V may correspond to "1".

[0133] FIG. 5b illustrates an energy band diagram according to the state change of a silicon gated diode in an operation mode of a binarized neural network circuit using the silicon gated diode according to an embodiment of the present invention.

[0134] Referring to FIG. 5b, a first energy band diagram 510 can show that the state of the silicon gated diode is "0", and a second energy band diagram 511 can show that the state of the silicon gated diode is "1".

[0135] In state “0” according to the first energy band diagram 510, the diode current (IDiode ) from flowing through the diode.

[0136] In contrast, in state "1" according to the second energy band diagram 511, excess charge carriers are stored in the potential wells of the n and p doped regions of the energy band diagram, causing diode current to flow through the diode.

[0137] Modulation of the potential barrier can cause the diode to exhibit bistable properties.

[0138] A weighted voltage of 0V is applied when performing rise and fall operations, and a weighted voltage of 1V is applied when performing standby and multiplication operations.

[0139] The conductance of the "0" and "1" states may be the conductance of the element that changes with the presence or absence of charge in a potential well by a lift or lower action.

[0140] FIG. 6a illustrates a timing diagram of a multiplication operation in the operation mode of a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0141] Referring to FIG. 6a, a timing diagram 600 can show a corresponding rising section 601 after updating the weight value to “1”, and a continuous input signal (V IN ) pulses, the output current (I OUT ) was measured, the corresponding falling section 602 can be shown after updating the weight value to "0", and the input signal (V IN ) regardless of the low output current (I OUT ) can be measured.

[0142] According to one embodiment of the present invention, in the case of an up-going operation in which the synaptic weight value is updated to a state of "1", the silicon gated diode outputs the result of the operation as a current signal proportional to the applied input signal, and in the case of a down-going operation in which the synaptic weight value is updated to a state of "0", the silicon gated diode outputs a current signal of 0 mA regardless of the applied input signal.

[0143] When the synaptic weight value of a silicon gated diode is in the "1" state, the cathode current of the cathode terminal can be output in a form similar to the outline of a graph of a ReLU (rectified linear unit) function, regardless of the gate voltage.

[0144] In the method of operation of the timing diagram 600, in order to update the synapse weight value (W) to 1, the input voltage (V IN )=2V, and the synapse weight voltage (V W ) = 0V voltage pulse is applied.

[0145] Then, a continuous V from 1.1V to 2.0V IN Proportional to a continuous I of 0mA to 7.4mA OUT can be measured.

[0146] To update the synaptic weight (W) to 0, V IN =2V and V W A voltage pulse of 0 V can be applied.

[0147] At this time, the same input voltage (V A ), very low levels of output current close to 0 mA can be measured.

[0148] Through this, it can be seen that a single synapse element performs a multiplication operation with excellent linearity.

[0149] Referring to FIG. 6b, in graph 610, a silicon gated diode can perform an integration operation while exhibiting an excellent linear relationship between input and output.

[0150] Graph 610 shows experimental results 611 and a linear fit 612 .

[0151] Therefore, since the present invention can utilize a CMOS process, it is possible to fabricate a large-scale array, and since there is almost no characteristic deviation between the silicon gated diode and the synaptic element, it is possible to increase the calculation accuracy of the artificial neural network.

[0152] Conventional technologies using next-generation memories such as ReRAM and MRAM have the disadvantages that CMOS processes cannot be applied, the uniformity and stability of elements are reduced, and the complicated process makes them difficult to put into practical use.

[0153] In conventional artificial neural network technology, many neural network layers are connected through activation functions, but implementing this requires complex additional neuron circuits, which can reduce the area and energy efficiency of the artificial neural network.

[0154] However, the present invention reduces standby power by using the excellent memory characteristics of silicon gated diodes, and increases computing efficiency with low power consumption through excellent switching characteristics, making it possible to realize a binary neural network circuit that can be used in next-generation artificial intelligence computer technology.

[0155] 7a to 8b are diagrams for explaining a MAC (multiply-accumulate) operation in an operation method of a binarized neural network circuit using a silicon gated diode according to an embodiment of the present invention.

[0156] 7a and 7b illustrate the use of a memory array made up of silicon gated diodes connected in a 4×1 configuration in connection with a MAC operation in an operating method of a binary neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0157] Referring to FIG. 7a, in a memory array 700 corresponding to a binarized neural network circuit according to an embodiment of the present invention, an output current (I OUT ) is subjected to current summation and an accumulate operation is performed.

[0158] Referring to FIG. 7b, in a timing diagram 710 corresponding to a binarized neural network circuit according to an embodiment of the present invention, the input voltage (V IN1 ~V IN4 ) is increased from 1.1V in steps of 0.1V up to 2V.

[0159] The timing diagram 710 shows the output current (I OUT ) is added with a current, and the result of the sum operation is shown.

[0160] 8a and 8b illustrate a matrix MAC operation associated with a MAC operation in an operating mode of a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0161] FIG. 8a shows a binarized neural network circuit 800 using silicon gated diodes according to one embodiment of the present invention, and a synapse weight matrix 801 calculated by the binarized neural network circuit.

[0162] FIG. 8b illustrates a binarized neural network circuit 800 using silicon gated diodes according to one embodiment of the present invention, and a timing diagram 810 associated with the operation of the binarized neural network circuit.

[0163] The binary neural network MAC operation uses a silicon gated diode array connected in a 2×2 configuration as the binary neural network circuit 800 .

[0164] The memory array associated with the binarized neural network circuit 800 has a plurality of silicon gated diodes connected in an N×N format, and performs a multiplication operation of synaptic weights updated based on an input signal applied to an input line and a weight update signal applied to a weight line, and performs a sum operation while adding up each current through an output line, and can output the result of the MAC operation as a synaptic weight matrix.

[0165] In addition, in the memory array, when N is “2”, the input signal is composed of a first input signal and a second input signal, the synaptic weight value is composed of a first synaptic weight value to a fourth synaptic weight value, and is composed of a first current and a second current output to an output line, and a synaptic weight value matrix composed of the first current and the second current can be calculated as a result of a vector matrix multiplication operation of the synaptic weight value and the input signal.

[0166] The silicon gated diode is connected to each input signal (V IN1 , V IN2 ) and synaptic weights (W 11 , W 12 , W 21 , W 22 ) and outputs each output current (I OUT1 , I OUT2 ) can be added together to perform an addition operation.

[0167] That is, mathematically, the 2×2 array is a vector-matrix multiplication operation.

number

number

[0168] In the binarized neural network circuit 800, after updating the synaptic weights of each element, V W is fixed at 1V and V IN1 and V IN2 When all of the above are applied, I OUT1 is exactly I OUT2 Then, V IN1 When only I is applied, OUT1 and I OUT2 may have the same value.

[0169] On the contrary, V IN2 When only I is applied, OUT1 Only can have a value proportional to the input signal.

[0170] Finally, when all input signals are removed, I OUT1 and I OUT2 can all be measured at low levels.

[0171] Such a result is consistent with a multiplication operation between the input vector and the synaptic weight matrix.

[0172] It is shown that a silicon gated diode array connected in a 2×2 configuration via a binary neural network circuit 800 can realize the MAC operation of a self-activating binary neural network.

[0173] The binarized neural network circuit 800 is illustrated in a 2×2 configuration, but is extendable to an N×M configuration.

[0174] The timing diagram 810 for the first area 811 is WWith V fixed at 1V IN1 and V IN2 When all of the above are applied, I OUT1 is exactly I OUT2 This indicates that the value is twice as high as that of the original value.

[0175] The second area 812 is V IN1 When only I is applied, OUT1 and I OUT2 may have the same value.

[0176] The third area 813 is V IN2 When only I is applied, OUT1 It shows that only θ can have a value proportional to the input signal.

[0177] The fourth area 814 is I OUT1 and I OUT2 can all be measured at low levels.

[0178] That is, in a memory array associated with the binarized neural network circuit 800, when the weight update signal is fixed at 1V and the first and second input signals are both applied, the first current has twice the value of the second current, and then, when only the first input signal is applied, the first current and the second current may have the same value.

[0179] Also, in the memory array, when only the second input signal is applied, only the first current has a value proportional to the second input signal, and when neither the first input signal nor the second input signal is applied, the first current and the second current can be measured to be close to 0 mA.

[0180] Therefore, the present invention is capable of realizing a binary neural network circuit having excellent uniformity and stability by having a memory array composed of a silicon gated diode based on a positive feedback loop perform the activation function of a neuron circuit by itself.

[0181] 9a to 9f are timing diagrams illustrating the results of performing a MAC matrix calculation with weight value update in a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0182] The matrix operations in the timing diagrams shown in Figures 9a to 9f refer to the matrix expressions on the respective timing diagrams.

[0183] During all matrix operations, the weight voltage is fixed at 1V, and the input voltage can have a value of 0V or between 1V and 2V.

[0184] For all determinants

number

[0185] In other words, by changing the weights of the 2x2 array elements while fixing all inputs "1" and "2" to "1", the calculation results in a result that matches the determinant.

[0186] Figure 9a shows the first output current (I OUT1 ) is measured as "0", and the second output current (I OUT2 9 shows a timing diagram 900 that corresponds to the case where 0 is measured as "0".

[0187] The matrix operations according to timing diagram 900 may be identical to the matrix operations on timing diagram 900.

[0188] During the matrix operation, the weight voltage is 1V, and the input voltage can have a value of 0V or between 1V and 2V.

[0189] Then, FIG. 11c illustrates a case where a matrix calculation operation is performed.

[0190] FIG. 9b shows the first output current (I OUT1 ) is measured as "1", and the second output current (I OUT2 ) is measured as "0."

[0191] The matrix operations according to timing diagram 910 may be identical to the matrix operations on timing diagram 910.

[0192] Figure 9c shows the first output current (I OUT1 ) is measured as "1", and the second output current (I OUT2 ) is measured as "1."

[0193] The matrix operations according to timing diagram 920 may be identical to the matrix operations on timing diagram 920.

[0194] Figure 9d shows the first output current (I OUT1 ) is measured as "2", and the second output current (I OUT2 ) is measured as "0."

[0195] The matrix operations according to timing diagram 930 may be identical to the matrix operations on timing diagram 930.

[0196] Figure 9e shows the first output current (I OUT1 ) is measured as "2", and the second output current (I OUT2 ) is measured as "1."

[0197] The matrix operations according to timing diagram 940 may be identical to the matrix operations on timing diagram 940.

[0198] Figure 9f shows the first output current (I OUT1 ) is measured as "2", and the second output current (IOUT2 ) is measured as "2."

[0199] The matrix operations according to timing diagram 950 may be identical to the matrix operations on timing diagram 950.

[0200] The above-mentioned matrix operations can be summarized as shown in Equation 1 below.

[0201]

number

[0202] In Equation 1, W may represent a binarized weighted value (conductance), IN may represent an input signal (voltage), and OUT may represent an output signal (current) obtained by a matrix operation.

[0203] According to timing diagrams 900 to 950, the first output current (I OUT1 ) and the second output current (I OUT2 ) is 7.5 mA, is "1", 15 mA, is "2", and less than 7.5 mA is "0".

[0204] However, the above example does not necessarily mean that 7.5 mA means an output of 1. When the output current is 0 mA, regardless of the input voltage, it means an output of 0, and alternatively, when the output current is measured at a constant level depending on the input voltage, it may mean an output of 1.

[0205] This proportionality can be seen in FIG. 6b, where an output “1” corresponds to one element, and in timing diagram 950, the output current is twice the current of one element compared to the input voltage, which may represent an output “2.”

[0206] The binarized neural network circuit using silicon gated diodes performs a matrix-MAC operation for each weighted value, and the output of the matrix-MAC operation has a high degree of consistency with a simplified VMM (vector-matrix multiplication) equation due to the high uniformity of the silicon gated diodes.

[0207] FIG. 10 is a diagram illustrating an optical image of a silicon gated diode according to an embodiment of the present invention.

[0208] FIG. 10 illustrates an optical image of a silicon gated diode according to one embodiment of the present invention.

[0209] Referring to FIG. 10, image 1010 displays an enlarged portion of image 1000.

[0210] For example, image 1000 and image 1010 may be optical images of silicon gated diodes for performing matrix-MAC operations between the binarized weights of a BNN and an analog input.

[0211] 11a to 11c are diagrams for explaining the calculation operation of a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0212] FIG. 11a illustrates weight update in the computational operation of a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0213] Referring to FIG. 11a, in the weight update operation 1100, the binarized weight (W) matrix is ​​V IN (2.0 or -2.0V) and V W A silicon gated diode selected from an array with V = 0.0V has a V of 2.0V (-2.0V). IN rose (or fell) at

[0214] FIG. 11b illustrates a standby state during a calculation operation of a binarized neural network circuit using silicon gated diodes according to one embodiment of the present invention.

[0215] Referring to FIG. 11b, in standby operation 1110, 1V is applied to all weight lines and 0V appears on all input lines.

[0216] Silicon gated diodes have a very low output current (I Diode ) to maintain memory state.

[0217] FIG. 11c illustrates an accumulation operation in the computational work of a binarized neural network circuit using a silicon gated diode according to one embodiment of the present invention.

[0218] Referring to FIG. 11c, in an accumulation operation 1120, a diode selected from the array is V W =1.0V and V IN = 0.0V or V IN =1.1V~2.0V.

[0219] The product of the input voltage and the binarized weighted value, I OUT is the output current (I Diode ) can be obtained by the sum of

[0220] In each of the above-mentioned specific embodiments, the elements included in the invention are expressed as singular or plural according to the specific embodiment presented.

[0221] However, the expressions singular or plural are chosen to suit the context presented for the convenience of explanation, and each of the above-described embodiments is not limited to singular or plural elements, and elements expressed in the plural may be composed of singular elements, and elements expressed in the singular may be composed of plural elements.

[0222] Meanwhile, in the description of the invention, specific embodiments have been described, but it is natural that various modifications are possible within the limits of the technical ideas contained within the various embodiments.

[0223] Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by not only the claims set forth below, but also equivalents thereto. [Explanation of symbols]

[0224] 100 Silicon Gated Diode 101 Anode terminal 102 First channel region 103 Second channel region 104 Cathode terminal 105 Gate insulating film 106 Gate terminal

Claims

1. a plurality of silicon gated diodes, each of which has a diode structure positioned as a channel region between an anode terminal and a cathode terminal, a gate terminal positioned on the diode structure, and which realizes unidirectional switching through potential barrier adjustment in the channel region based on different voltages applied to the anode terminal and the gate terminal, respectively, and realizes a memory characteristic by accumulating holes or electrons in the potential well by a positive feedback loop; The plurality of silicon gated diodes operate as synapse elements in a memory array connected in parallel, and output a result of a multiply-accumulate (MAC) operation based on an input signal applied from an input line processing unit connected to the memory array and a weight update signal applied from a synapse line processing unit connected to the memory array.

2. 2. The binarized neural network circuit of claim 1, wherein the silicon gated diode receives an anode voltage of the anode terminal as the input signal, generates a latch-up phenomenon due to the positive feedback loop as the applied input signal increases in a positive direction, has one of two memory states for the channel region, receives a gate voltage of the gate terminal as the weight update signal, and adjusts the input signal causing the latch-up phenomenon, updates a synapse state associated with the one memory state by applying the input signal and the weight update signal, and performs the MAC calculation function according to the synapse weight.

3. 3. The binarized neural network circuit of claim 2, wherein the silicon gated diode performs a multiplication operation between a continuous input from "0" to "1" as the applied input signal increases in a positive direction and a synaptic weight value of either a "0" state or a "1" state corresponding to the two memory states, and outputs a current signal corresponding to either "0" or "1" as a result of the operation.

4. 4. The binarized neural network circuit according to claim 3, wherein the silicon gated diode outputs a result of an operation as a current signal proportional to the applied input signal in the case of an up operation in which the synaptic weight value is updated to the "1" state, and outputs a current signal of 0 mA regardless of the applied input signal in the case of a down operation in which the synaptic weight value is updated to the "0" state.

5. 3. The binarized neural network circuit of claim 2, wherein the silicon gated diode outputs a cathode current of the cathode terminal in a form similar to a graph of a rectified linear unit (ReLU) function, regardless of the gate voltage, when the synapse weight value is "1".

6. the memory array forms an input line, a weight line and an output line by connecting the anode terminal, the gate terminal and the cathode terminal of the plurality of silicon gated diodes in parallel, respectively; the input lines are arranged perpendicular to the weight lines and the output lines; 2. The binarized neural network circuit according to claim 1, wherein the weight lines and the output lines are arranged in parallel.

7. the input line receives the input signal; the weight line receives the weight update signal; 7. The binarized neural network circuit of claim 6, wherein the output line outputs the result of the MAC operation based on the input signal and the weight update signal to a next artificial neural network terminal.

8. 8. The binarized neural network circuit of claim 7, wherein the memory array is configured such that the plurality of silicon gated diodes are connected in a form of N×M, and a sum operation is performed by adding currents through the output lines according to a multiplication operation of synapse weights updated based on an input signal applied to the input lines and a weight update signal applied to the weight lines, and a result of the MAC operation is output as a synapse weight matrix.

9. 9. The binarized neural network circuit of claim 8, wherein, when N and M are '2', the input signals are composed of a first input signal and a second input signal, the synaptic weight values ​​are composed of first to fourth synaptic weight values, the memory array is composed of a first current and a second current outputted to the output line, and the synaptic weight value matrix composed of the first current and the second current is calculated as a result of a vector matrix multiplication of the synaptic weight values ​​and the input signals.

10. 10. The binarized neural network circuit of claim 9, wherein when the first and second input signals are both applied with the weight update signal fixed at 1V, the first current has a value twice as large as the second current, and when only the first input signal is applied thereafter, the first current and the second current have the same value.

11. 11. The binarized neural network circuit of claim 10, wherein the memory array is measured such that when only the second input signal is applied, only the first current has a value proportional to the second input signal, and when neither the first input signal nor the second input signal is applied, the first current and the second current are approximately 0 mA.

12. 2. The binarized neural network circuit of claim 1, wherein the silicon gated diode comprises one of a single silicon gated diode, a double silicon gated diode, and a triple silicon gated diode.

Images