Randomizer subjected to self-seed processing for randomizing data in flash memory

Abstract

To provide a method for scrambling metadata that enables efficient internal copy back operation, a memory device, and machine-readable media.SOLUTION: A method includes the steps of: identifying data to be written to a set of memory cells of a memory device (host data from a host / metadata created by a controller of a memory device); generating, in response to receiving the data, a first seed value relative to the host data and a second seed value relative to the metadata; scrambling the host data by transforming the host data using a scrambling algorithm and the first seed value to generate scrambled host data; scrambling the metadata by transforming the metadata using a scrambling algorithm and the second seed value to generate scrambled metadata; and writing the scrambled host data and the metadata to a set of the memory cells of the memory device along with the first and second seed values.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. Application No. 16 / 837,315, filed April 1, 2020, which is incorporated by reference in its entirety.

[0002] Some embodiments relate to a memory device that enables an efficient internal copy-back operation to copy data between two different locations within the same memory die in a memory device while maintaining randomization of the data and updating metadata of the data that is subject to the copy-back operation. [Background technology]

[0003] Memory devices for computers or other electronic devices can be categorized into volatile and non-volatile memories. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when power is not applied and includes flash memory, read only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory, phase change memory, storage class memory, resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0004] Flash memory is used as a non-volatile memory for a wide range of electronic applications. Flash memory devices typically contain one or more groups of transistors, such as floating gate or charge trap memory cells, that enable high memory density, high reliability, and low power consumption.

[0005] In the drawings, which are not necessarily drawn to scale, like numerals may describe like components in different figures. Like numerals with different letter suffixes may represent different instances of the like components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. [Brief description of the drawings]

[0006] [Figure 1] 1 shows a diagram of a memory device, such as a storage device, according to some examples of the present disclosure. [Diagram 2] 1 illustrates an example schematic diagram of a portion of a NAND architecture semiconductor memory array according to some examples of the present disclosure. [Diagram 3] 1 illustrates an example schematic diagram of a 3D NAND architecture semiconductor memory according to some examples of the present disclosure. [Figure 4] FIG. 1 illustrates an example block diagram of a memory die according to some examples of the present disclosure. [Diagram 5] 1 illustrates a data flow for a write operation according to some examples of the present disclosure. [Figure 6] 4 illustrates a data flow for a read operation according to some examples of the present disclosure. [Figure 7] 1 illustrates a flowchart of a method for writing data to a memory device according to some examples of the present disclosure. [Figure 8] 1 shows a flowchart of a method for reading data from a memory device according to some examples of the present disclosure. [Figure 9] 1 illustrates the data flow of a write operation according to some examples of the present disclosure in which metadata and host data are encoded separately. [Figure 10] 1 illustrates a data flow for an internal copyback operation with metadata update according to some examples of the present disclosure, where the metadata and host data are encoded separately. [Figure 11] 1 illustrates a flowchart of a method for writing data to a memory device according to some examples of the present disclosure. [Figure 12]1 illustrates a flowchart of a method for writing data to a memory device during an internal copyback operation according to some examples of the present disclosure. [Figure 13] 1 illustrates a flowchart of a method for an internal copy-back operation on a memory device according to some examples of the present disclosure. [Figure 14] 1 illustrates a block diagram of an example machine upon which any one or more of the techniques (eg, methodologies) discussed herein may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Memory devices often consist of multiple physical memory dies connected to a controller via an internal communication interface such as a bus. Certain operations on memory devices require copying data from cells in one location on a die to cells in another location on the same die. One example is a copy operation from an SLC cache block to a TLC / QLC storage block. Many TLC / QLC memory systems use SLC blocks as a write cache for performance reasons. A copy operation is necessary when data in these SLC cache blocks needs to be moved to slower (but denser) TLC / QLC blocks. In traditional approaches, data is transferred from the die to the controller via an internal communication interface, processed, and then transferred back to the die via an internal I / O bus to be stored in a different location.

[0008] To reduce I / O bus traffic and lower controller utilization, an internal copyback operation may be performed to move data from one location to another within the same memory die of a memory device without transferring the data over a communications interface to the controller. Using an internal copyback operation saves controller resources (e.g., processing cycles and working memory), interface bandwidth, reduces energy consumption, and reduces latency in completing an operation. An internal copyback operation does not process data in any computationally intensive manner because the memory die does not have the resources to process the data in the same manner as the controller. Typically, an internal copyback copies data without any modification or processing.

[0009] Writing data without modification or processing can affect the reliability of the memory device and the data written. This lack of processing can cause problems with internal copy-back operations. Individual memory dies can be modified to perform these processing steps, but this would unacceptably increase the cost and complexity of these devices.

[0010] For example, randomizers are typically used in memory devices because the data patterns stored in memory cells must meet certain requirements to achieve reliability goals. As described below, NAND flash memory cells are arranged in a grid with word lines (WLs) connecting rows of memory cells and bit lines (BLs) connecting columns of cells. NAND memory devices typically ensure that the bits stored in each WL have an approximately equal number of values ​​0 and 1, and that the bits stored in each BL have an approximately equal number of values ​​0 and 1. Furthermore, when each memory cell stores more than one bit, such as MLC / TLC / QLC, each cell has more than two threshold voltage states. In these instances, the memory device ensures that the number of cells in each state is approximately equal within the same WL. Ensuring this data pattern distribution reduces storage errors.

[0011] These data pattern distribution requirements are typically met by using a scrambler. While the memory system has no control over the data patterns a user can choose to write, the scrambler "scrambles" the data being written so that a balanced number of value 0 / value 1 are more likely to be programmed into the media. The scrambler can be implemented in the controller or in the memory die itself.

[0012] Improved reliability is obtained by storing a balanced number of 1 and 0 values ​​across both wordlines and bitlines. Typically, the distribution requirements along a BL and across multiple pages within the same WL are met by ensuring proper scrambler seeding. Physical address based seeding is widely used for this purpose. For example, the input word to be written is XORed with a random number sequence seeded by the physical address of the page to which this word is written. When reading data, the data to be read is XORed again with the physical address to generate the descrambled data. Using the physical page address as part or as a whole of the scrambler seed ensures that the data programmed to the medium is randomized across the bitlines, even if the same data pattern is written to each page in a block.

[0013] Physical address based scrambler seeding is not compatible with internal copyback. As already explained, internal copyback does not usually change the data being copied. If the scrambler performs the scrambling using a physical page address (e.g., the scrambler is "seeded" with a physical page), the physical address of the page will change after the internal copyback operation is completed. If the data is descrambled using the current physical address of the data (e.g., the physical address after the internal copyback) instead of the original physical address, it cannot attempt to descramble the data during a read operation. Although memory devices can provide mechanisms to track the original physical page of the data for decoding purposes, this may be too costly in terms of the memory required to store such data.

[0014] Another issue with the internal copyback operation is updating the metadata that was created when the data was originally written. This metadata is written along with the data received from the host (host data). The metadata can be data specific to the state of the memory device at the time of the write operation. For example, the time the data was written, the temperature of the memory device during the initial write, the write voltage, an initial write verification indicator, etc. These fields allow the memory device to more reliably read the host data. The internal copyback operation cannot update this metadata because it does not decode and descramble the data. Failure to update the metadata can result in later reliability and / or performance issues (e.g., when attempting to read the data at a later time). The memory die can decode the metadata, update the value, and restore the data, but this requires additional processing and volatile memory resources on the memory die. This adds cost and complexity to each memory die.

[0015] Disclosed in some examples are methods, systems, devices, and machine-readable media that provide techniques for scrambling and / or updating metadata that enable efficient internal copy-back operations. In some examples, the improved data distribution techniques allow copy-back operations while maintaining data distribution requirements across the memory device by decoupling the scrambling key from the physical address. The controller can generate a seed value, which is used by an algorithm to scramble the host data and metadata before they are written. The seed value is then encoded and written to the page along with an encoded version of the scrambled user data and metadata. That is, the random number seed is written without scrambling the random number seed. When reading the data, the seed can be easily unscrambled since it is stored with the data. In some examples, the seed value is a random value generated by a random number generator.

[0016] In some examples, to update the metadata, the metadata and the host data are separated and only the metadata is sent to the controller and updated during the modified internal copyback operation. The host data is not sent to the controller. Sending the metadata utilizes resources of the communication link between the memory die and the controller, but uses much fewer resources than if the host data was also sent. To send the host data and metadata separately, the metadata and the host data are scrambled and encoded such that the metadata can be separately unscrambled and decoded even in the absence of the host data, e.g., by encoding and / or scrambling the host data and the metadata separately.

[0017] By using the above technique, various problems with internal copyback operations can be avoided. First, because the physical address is not used as a key to the scrambler, the host data and metadata can be copied unchanged from one memory location to another. Thus, the increased reliability of the data made possible by scrambling the data can be preserved while allowing the data that has undergone the internal copyback operation to be descrambled. Second, because the metadata and host data are scrambled and encoded such that they can be descrambled and decoded separately, the metadata may be sent back to the controller for updating before the internal copyback is completed. This allows the metadata to be updated while using negligible communication and processing resources of the controller and interface bandwidth between the memory die and the controller.

[0018] Memory Device Overview As mentioned above, flash memory is utilized as a non-volatile memory for a wide range of electronic applications. Flash memory typically includes one or more groups of transistors, such as floating gate or charge trap memory cells, that enable high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND architecture and NOR architecture, named for the logical format in which their respective basic memory cell configurations are arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled in series, source to drain, between a source line and a bit line.

[0019] Both NOR and NAND architecture semiconductor memory arrays are accessed through a decoder that activates particular memory cells by selecting the word lines coupled to their gates. In a NOR architecture semiconductor memory array, when activated, the selected memory cells place their data values ​​onto the bit lines, causing different currents to flow depending on the state to which the particular cell is programmed. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain side select gate (SGD) lines. The word lines coupled to the gates of the unselected memory cells of each group are driven with a designated pass voltage (e.g., Vpass) to cause the unselected memory cells of each group to act as pass transistors (e.g., to pass current in a manner not limited by the stored data value). A current then flows from the source line through each series-coupled group to the bit lines, limited only by the selected memory cells of each group, causing the currently encoded data values ​​of the selected memory cells to be placed onto the bit lines.

[0020] Flash memory cells in a semiconductor memory array of NOR or NAND architecture can be individually or collectively programmed to one or more programmed states. For example, a single level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), which represents one bit of data. However, flash memory cells can also represent one of more than two programmed states, and each cell can represent multiple binary digits (e.g., bits greater than 1), making it possible to manufacture high density memories without increasing the number of memory cells. Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLC). In a particular example, MLC can refer to memory cells that can store two bits of data per cell (e.g., one of four programmed states), triple level cells (TLC) can refer to memory cells that can store three bits of data per cell (e.g., one of eight programmed states), and quad level cells (QLC) can store four bits of data per cell. MLC is used in a broader context herein and may refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

[0021] Conventional memory arrays are two-dimensional (2D) structures located on the surface of a semiconductor substrate. To increase memory capacity for a given area and reduce cost, the size of individual memory cells is reduced. However, there are technological limits to the reduction in size of individual memory cells, and therefore the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as semiconductor memory devices with 3D NAND architecture, are being developed to further increase memory density and reduce memory costs.

[0022] Such 3D NAND devices often include strings of storage cells coupled in series (e.g., drain to source) between one or more source side select gates (SGS) proximate the source and one or more drain side select gates (SGD) proximate the bit lines. In embodiments, the SGS or SGD may include one or more field effect transistor (FET) structure devices or metal oxide semiconductor (MOS) structure devices, or the like. In some embodiments, the strings extend vertically through multiple vertically spaced layers including each word line. Semiconductor structures (e.g., polysilicon structures) may extend adjacent to the strings of storage cells to form channels for the storage cells of the strings. In vertical string embodiments, the polysilicon structures may be in the form of vertically extending pillars. In some embodiments, the strings may be "folded" and thus arranged with respect to U-shaped pillars. In other embodiments, multiple vertical structures may be stacked on top of each other to form a stacked array of strings of storage cells.

[0023] The memory arrays or devices may be coupled together to form a storage volume of a memory system, such as a solid-state drive (SSD), or one of various forms of managed memory devices. The managed memory devices may be configured and operated in accordance with recognized industry standards. For example, the managed NAND type devices may be (as non-limiting examples) Universal Flash Storage (UFS™) devices, or embedded MMC devices (eMMC™), or the like. For example, in the above example, the UFS devices may be configured in accordance with Joint Electron Device Engineering Council (JEDEC) standards, such as JEDEC standard JESD223D, entitled "JEDEC UFS Flash Storage 3.0", and / or updates or subsequent versions to such standards. Similarly, the identified eMMC devices may be configured in accordance with JEDEC standard JESD84-A51, entitled "JEDEC eMMC Standard 5.1", and / or updates or subsequent versions to such standards.

[0024] SSDs can be used, among other things, as the main storage device of a computer and are superior to traditional hard drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs can reduce seek times, latency, or other delays associated with magnetic disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells, such as flash memory cells, allowing drives to be more versatile and compact by eliminating the need for internal battery supply requirements.

[0025] An SSD may include multiple memory devices, including multiple dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logical functions necessary to operate the memory devices or interfaces with an external system. Such an SSD may include one or more flash memory dies, including multiple memory arrays and peripheral circuitry thereon. A flash memory array may include multiple blocks of memory cells organized into multiple physical pages. In many embodiments, the SSD also includes DRAM or SRAM (or other types of memory dies or other memory structures). The SSD may receive commands from the host related to memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory device and the host, or erase operations to erase data from the memory device.

[0026] A memory device includes individual memory dies, which may include a storage area having one or more arrays of memory cells, for example, implementing one (or more) selected storage techniques. Such memory dies often include support circuitry for operating the memory array(s). Other examples, sometimes known generally as "managed memory devices," include an assembly of one or more memory dies associated with a controller function configured to control the operation of the one or more memory dies. Such controller function can simplify interoperability with external devices, such as a "host," as described later herein. In such managed memory devices, the controller function can be implemented in one or more dies that also incorporate the memory arrays, or in a separate die. In other examples, one or more memory devices can be combined with the controller function to form a solid stage drive (SSD) storage volume. The term "memory system" is used herein to include one or more memory dies and any controller function, if present, of such memory dies, and thus includes individual memory devices, managed memory devices, and SSDs.

[0027] For purposes of this description, the exemplary embodiments include managed memory devices implementing NAND-type flash memory cells, referred to as "managed NAND" devices. Such managed NAND-type devices may generally be constructed and operated in accordance with the described JEDEC UFS Flash Storage 3.0 specification, and may be modified as appropriate to incorporate the structures and functions described herein. However, the described functions may be implemented in other types of memory devices, such as those mentioned above, that may incorporate other storage technologies, some non-limiting examples of which are described earlier herein and may be configured to operate in accordance with other industry standards or in accordance with non-industry standard protocols, as described above.

[0028] Electronic devices, such as mobile electronic devices (e.g., smartphones, tablets, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected appliances or devices (e.g., Internet of Things (IoT) devices, etc.), have various storage needs depending on the type of electronic device, the usage environment, performance expectations, etc., among others.

[0029] An electronic device can be broken down into several major components: a processor (e.g., a central processing unit (CPU) or other main processor), memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices, e.g., dynamic RAM (DRAM), mobile or low power double data rate synchronous DRAM (DDR SDRAM), etc.), and storage devices (e.g., non-volatile memory (NVM) devices, e.g., flash memory, read only memory (ROM), SSD, MMC, or other memory card structures or assemblies, etc.). In certain examples, an electronic device can include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor or one or more transceiver circuits, etc.

[0030] FIG. 1 illustrates a diagram of a memory device 100, such as a storage device, according to some examples of the present disclosure. The memory device 100 may include one or more host interfaces 123 that may utilize one or more protocols, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC™ interface, or one or more other connectors or interfaces, to communicate with a host device 135. The host 135 may send one or more commands, such as a read command, a write command, an erase command, etc., to the memory device 100 via the host interface 123. The host interface 123 may be part of the controller 105 or may be implemented by a separate circuit.

[0031] Memory device 100 may include one or more controllers 105. Controller 105 may include processing circuitry 110, which may include one or more processors 115. Processor 115 may be a general-purpose hardware processor that executes firmware or other software instructions to perform operations of the memory device, including implementing host interface 123 and memory die interface 125. In other examples, processor(s) 115 may be special-purpose hardware processors that are designed exclusively to perform operations of memory device 100 through hardware logic and / or through execution of software instructions. Processing circuitry 110 may also include logic and other circuit components configured to perform various control functions and memory management operations, or portions thereof, examples of which are described below.

[0032] In the depicted example, memory device 100 includes a host interface 123 that provides communication to an external host device 135 via a host bus 137. The configuration of host interface 123 may be of various forms depending on the dedicated configuration of memory device 100 (sometimes referred to as a "memory system"). For example, in an example where memory device 100 is a UFS device, the host interface complies with the applicable UFS standard.

[0033] Memory device 100 also incorporates one or more memory die interfaces 125 between processing circuitry 110 of controller 105 and at least some of memory dies 130-A through 130N+1 in memory device 100. Memory die interfaces 125 may be part of controller 105 or may be implemented by separate circuitry. For example, in the example UFS device, one or more of memory die interfaces 125 are a suitable memory interface, such as an Open NAND Flash Interface ("ONFI"), as defined by the ONFI 4.0 specification, or any later version or revision.

[0034] Components of memory device 100, such as controller 105, may include random access memory 120 for executing operations of memory device 100. Random access memory 120 may be separate from controller 105 or, as shown, integrated into controller 105. In some examples, random access memory 120 may be within controller 105 or separate from controller 105.

[0035] The controller 105 can handle one or more functions of the memory by interacting with memory cells of memory devices that are part of one or more memory dies 130-A through 130N+1. A schematic diagram of an exemplary implementation of the memory dies 130 is shown in FIG. 4. The controller 105 can communicate with these memory dies via an internal communication interface 127, such as an I / O bus, via a memory die interface 125. In some examples, the memory dies can have their own device controllers that include processing circuitry and processors to control operations on the respective memory dies. Such device controllers can be formed on a common die with the device storage array or on a separate die from the die that includes the device storage array. Either configuration is encompassed by the identified "memory die" (130A through N+1) described herein. The memory dies can be NAND dies, 3D NAND dies, phase change memory dies, etc.

[0036] The host device 135 may be a personal computer, a smartphone, a tablet, a portion of an integrated circuit, an Internet of Things (IoT) device (e.g., a refrigerator or other appliance, a sensor, a motor or actuator, a mobile communication device, an automobile, a drone, etc.), etc.

[0037] For purposes of describing the present invention, exemplary memory operation and management functions may be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions may include wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions.

[0038] The memory dies 130-A through 130-N+1 may include several memory cells arranged, for example, in multiple planes, sub-blocks, blocks, or pages. As an example, a 48 GB TLC NAND memory device may include 18,592 bytes (B) of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32 GB MLC memory device (storing 2 bits of data per cell (i.e., 4 programmable states)) may include 18,592 bytes (B) of data per page (16,384+2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but requires half the write time and twice the program / erase (P / E) cycles compared to a corresponding TLC memory device. Other examples may include other numbers or arrangements. In some embodiments, a memory device or a portion thereof may be selectively operated in an SLC mode or in a desired MLC mode (TLC, QLC, etc.).

[0039] In operation, data is typically written to or read from memory device 100 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells, as desired. The data transfer size of memory device 100 is typically referred to as a page, while the data transfer size of a host is typically referred to as a sector.

[0040] A page of data may include several bytes of user data (e.g., a data payload including several sectors of data) and corresponding metadata, but the size of a page often refers only to the number of bytes used to store user data. As an example, a page of data having a page size of 4KB may include 4KB of user data (e.g., 8 sectors assuming a sector size of 512B), as well as several bytes (e.g., 32B, 54B, etc.) of metadata corresponding to the user data, such as integrity data, address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0041] Different types of memory cells may provide different page sizes or require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may require different amounts of metadata to ensure the integrity of a data page (e.g., a memory device with a higher bit error rate may require error correction coding of more bytes of data than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Thus, an MLC device may require more metadata bytes of error data than a corresponding SLC device.

[0042] 2 illustrates an example schematic diagram of a portion of a NAND architecture semiconductor memory array 300 including a plurality of memory cells 202 arranged in a two-dimensional array of strings (e.g., strings 205-207) and tiers (e.g., illustrated as respective word lines (WL) WL0-WL7 210-217, drain side select gate (SGD) line 225, source side select gate (SGS) line 230, etc.) and sense amplifiers or devices 260, according to some examples of the present disclosure. For example, memory array 200 may represent an example schematic diagram of a portion of one physical page of memory cells of memory die 130 from FIG.

[0043] Each string of memory cells is coupled to a source line (SRC) 235 using a respective source side select gate (SGS) (e.g., SGS 231-233) and to a respective data line (e.g., bit lines (BL) BL0-BL2 220-222) using a respective drain side select gate (SGD) (e.g., SGD 226-228). While the example of Figure 2 is shown with eight tiers (e.g., using word lines (WL) WL0-WL7 210-217) and three data lines (BL0-BL2 226-228), other examples can include strings of memory cells having more or fewer tiers or data lines, as desired.

[0044] In a NAND architecture semiconductor memory array, such as the exemplary memory array 200, the state of a selected memory cell 202 can be accessed by sensing a change in current or voltage associated with a particular data line that contains the selected memory cell. The memory array 200 can be accessed (e.g., by control circuitry, one or more processors, digital logic, etc.) using one or more drivers. In one embodiment, the one or more drivers can activate a particular memory cell or set of memory cells by driving particular potentials to one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or select gates depending on the type of operation desired to be performed on the particular memory cell or set of memory cells.

[0045] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses) can be applied to a selected word line (e.g., WL4) and thus to the control gates of each memory cell coupled to the selected word line (e.g., control gates (CG) 241-243 of memory cells coupled to WL4). The programming pulses can begin, for example, at or near 15V and, in certain embodiments, can ramp up in magnitude during application of each programming pulse. While the programming voltage is applied to the selected word line, a potential such as ground potential (e.g., Vss) can be applied to the data line (e.g., bit line) and substrate (and thus the channel between the source and drain) of the memory cell targeted for programming, resulting in charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel of the targeted memory cell to a charge storage structure. Such charge storage structures can include, for example, a floating gate or a charge trapping region of the respective memory cell. In a floating gate memory cell, the charge is stored in an isolated polysilicon structure, whereas in a charge trapping memory cell, the charge is typically stored in a dielectric structure.

[0046] In contrast, a pass voltage (Vpass) can be applied to one or more word lines containing memory cells not targeted for programming, or a blocking voltage (such as Vcc) can be applied to data lines (such as bit lines) containing memory cells not targeted for programming, such as to prevent charge from moving from the channels of such memory cells to the charge storage structures. The pass voltage can be variable, for example, depending on the proximity of the applied pass voltage to a word line targeted for programming. The blocking voltage can include a power supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external power supply or source (e.g., a battery, an AC / DC converter, etc.).

[0047] As an example, if a programming voltage (e.g., 15V or more) is applied to a particular word line, such as WL4, a pass voltage of 10V can be applied to one or more other word lines, such as WL3, WL5, etc., to inhibit programming of non-target memory cells or to retain the value stored in such non-target memory cells. As the distance between the applied program voltage and the non-target memory cells increases, the pass voltage required to prevent programming of the non-target memory cells can be reduced. For example, if a programming voltage of 15V is applied to WL4, a pass voltage of 10V can be applied to WL3 and WL5, a pass voltage of 8V can be applied to WL2 and WL6, and a pass voltage of 7V can be applied to WL1 and WL7, for example. In other examples, the pass voltage or the number of word lines, etc. can be higher or lower, or more or less.

[0048] A sense amplifier 260 coupled to one or more data lines (e.g., first, second, or third bit lines (BL0-BL2) 220-222) can detect the state of each memory cell on the respective data line by sensing the voltage or current on the particular data line.

[0049] Between applications of one or more programming pulses (e.g., Vpgm), a verify operation can be performed to determine whether a selected memory cell has reached its intended program state. If the selected memory cell has reached the intended program state, the memory cell can be inhibited from further programming. If the selected memory cell has not reached the intended program state, additional programming pulses can be applied. If the selected memory cell has not reached the intended program state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell, or a string, block, or page associated with such selected memory cell, can be marked as defective.

[0050] For single-level cells (SLC), there are two possible voltage levels that may be programmed into the cell, one voltage level representing a binary "1" and another voltage level representing a binary "0". For multi-level cells (MLC), there are four possible voltage levels that may be programmed into the cell. The four possible voltage levels represent "00", "01", "10", and "11". To program an MLC cell, multiple programming pulses are applied. The first pulse programs a first "page" of data representing either the most significant or least significant bit of the cell. The second pulse programs a second "page" of data representing the other bit of the cell that was not programmed by the first pulse. Similarly, triple-level cells (TLC) store eight possible voltage levels and quad-level cells (QLC) store 16 possible voltage levels.

[0051] To read the value stored in one or more memory cells, a read voltage is applied to the word line of the selected cell. If the voltage stored in the cell on the word line is greater than the read voltage, the cell passes the voltage to a sense amplifier. For SLC cells, the read voltage is selected to be between the two voltages representing a "1" and a "0". For MLC, TLC, and QLC, multiple read operations are used to read each bit stored in the cell, with each read operation utilizing a different read voltage.

[0052] To erase a memory cell or group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) can be applied (e.g., using one or more bit lines, gate selecting, etc.) to the substrate (and thus the channel between the source and drain) of the memory cell to be erased while the word line of the memory cell to be erased is held at a potential such as ground potential (e.g., Vss), thereby transferring charge from the charge storage structure of the memory cell to the channel (e.g., by direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0053] FIG. 3 illustrates blocks (e.g., block A 301A, block B 301B, etc.) and sub-blocks (e.g., sub-block A 301A0, sub-block A n 301A n , subblock B0301B0, subblock B n 301B n A plurality of memory cell strings (e.g., A0 memory strings 305A0 to 307A0, A1, etc.) are organized into n Memory String 305A n ~307A n , B0 memory string 305B0 to 307B0, B n Memory String 305B n ~307B n 3 shows an example schematic diagram of a 3D NAND architecture semiconductor memory array 300 including multiple memory cells, such as a 3D NAND array, a 3D NAND memory cell ...

[0054] Each string of memory cells is connected to a source line (SRC) 335 or source side select gate (SGS) (e.g., A0SGS331A0 to 333A0, A n SGS331A n ~333A n , B0SGS331B0~333B0, B n SGS231B n ~233B n ) and the drain side select gate (SGD) (e.g., A0SGD326A0 to 328A0, A n SGD326A n ~328A n , B0SGD326B0~328B0, B n SGD326B n ~328B nA 3D memory array includes several layers of charge storage transistors (e.g., floating gate transistors, charge trapping structures, etc.) stacked in the Z direction from source to drain, with a data line (e.g., bit lines (BLs) BL0-BL2 320-322) along the X direction, and a physical page along the Y direction.

[0055] Within a physical page, each tier represents a row of memory cells and each string of memory cells represents a column. A subblock can include one or more physical pages. A block can include several subblocks (or physical pages) (e.g., 128, 256, 384, etc.). Although illustrated herein as having two blocks, each block having two subblocks, each subblock having a single physical page, each physical page having three strings of memory cells, each string having eight tiers of memory cells, in other embodiments, memory array 300 can include more or fewer blocks, subblocks, physical pages, strings of memory cells, memory cells, or tiers. For example, each string of memory cells can include more or fewer tiers (e.g., 16, 32, 64, 128, etc.), as well as one or more additional tiers of semiconductor material above or below the charge storage transistors (e.g., select gates, data lines, etc.), as desired. As an example, a 48 GB TLC NAND memory device can contain 18,592 bytes (B) (16,384+2208 bytes) of data per page, 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0056] Each memory cell in the memory array 300 includes a control gate (CG) coupled (e.g., electrically or otherwise operably connected) to an access line (e.g., word lines (WL) WL00-WL70, 310A-317A, WL01-WL71, 310B-317B, etc.), which collectively couples the control gates (CG) across a dedicated tier or portion of a tier, as appropriate. A particular tier in the 3D memory array, and accordingly, a particular memory cell in a string, can be accessed or controlled using a respective access line. Groups of select gates can be accessed using various select lines. For example, A0SGD326A0-328A0 can be accessed using A0SGD line SGDA0325A0, and A0SGD326A0-328A0 can be accessed using A0SGD line SGDA0325A0. n SGD326A n ~328A n SGD line SGDA n 325A n B0SGD326B0 to 328B0 can be accessed using the B0SGD line SGDB0325B0. n SGD326B n ~328B n To, B n SGD Line SGDB n 325B n It can be accessed using A0SGS331A0 to 333A0 and A n SGS331A n ~333A n can be accessed using gate select lines SGS0330A, B0, SGS331B0 to 333B0 and B n SGS331B n ~333B n can be accessed using gate select line SGS1330B.

[0057] In one example, memory array 300 may include several levels of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) (or a portion of the CG or select gate) of each memory cell or select gate of each tier of the array. A particular string of memory cells in the array may be accessed, selected, or controlled using a combination of bit lines (BL) and select gates, etc., and a particular memory cell in one or more tiers within a particular string may be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0058] 4 illustrates an example block diagram of a memory die 400 including a memory array 402 having a plurality of memory cells 404 and one or more circuits or components that provide communication with or perform one or more memory operations on the memory array 402, in accordance with some examples of the present disclosure. The memory die 400 can include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, input / output (I / O) circuitry 426, and a memory control unit 430.

[0059] The memory cells 404 of the memory array 402 may be arranged in blocks, such as first and second blocks 402A, 402B. Each block may include sub-blocks. For example, the first block 402A may include first and second sub-blocks 402A0, 402A1, and 402B2. n The second block 402B may include first and second sub-blocks 402B0, 402B1, nEach sub-block may include several physical pages, with each page including several memory cells 404. Although shown herein as having two blocks, each block having two sub-blocks, with each sub-block including several memory cells 404, in other examples, memory array 402 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, memory cells 404 may be arranged in several rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, access lines 406, first data lines 410, or one or more select gates, source lines, etc.

[0060] The memory control unit 430 may control memory operations of the memory die 400 according to one or more signals and / or instructions / commands received on control lines 432 at the memory interface by a memory controller (as described with respect to the controller 105 and host interface 123 of the memory device 100 of FIG. 1). Such signals and / or instructions may include, for example, one or more clock and / or control signals indicating a desired operation (e.g., write, read, erase, etc.), or address signals (A0-AX) received on one or more address lines 416. One or more devices external to the memory die 400 may control the values ​​of the control signals on the control lines 432 or the address signals on the address lines 416. Examples of devices external to the memory die 400 may include, but are not limited to, a host, a memory controller, a processor, or one or more circuits or components not shown in FIG. 4.

[0061] The memory die 400 can transfer data (e.g., write or erase) or transfer data (e.g., read) from one or more of the memory cells 404 using the access lines 406 and the first data lines 410. The row decoder 412 and the column decoder 414 can receive and decode address signals (A0-AX) from the address lines 416 to determine which memory cells 404 to access and provide signals to one or more of the access lines 406 (e.g., one or more of a plurality of word lines (WL0-WLm)) or the first data lines 410 (e.g., one or more of a plurality of bit lines (BL0-BLn)) as described above.

[0062] The memory die 400 may include sense circuitry, such as sense amplifiers 420, configured to identify (e.g., read) or determine the value of data to be written to the memory cells 404 using the first data lines 410. For example, at a selected string of memory cells 404, one or more of the sense amplifiers 420 may read the logic level of the selected memory cell 404 in response to a read current flowing to the data lines 410 through a selected string in the memory array 402.

[0063] One or more devices external to the memory die 400, such as the controller 105, can communicate with the memory die 400 using I / O lines (DQ0-DQN) 408, address lines 416 (A0-AX), or control lines 432. Input / output (I / O) circuitry 426 can transfer data values ​​into or out of the memory die 400, such as into or out of a page buffer 422 or memory array 402, using I / O lines 408 in accordance with, for example, the control lines 432 and the address lines 416. The page buffer 422 can store data received from one or more devices external to the memory die 400 before that data is programmed into an associated portion of the memory array 402, or store data read from the memory array 402 before that data is transmitted to one or more devices external to the memory die 400.

[0064] The column decoder 414 can receive and decode address signals (A0-AX) into one or more column select signals (CSEL1-CSELn). The selector 424 (e.g., a selection circuit) can receive the column select signals (CSEL1-CSELn) and select data in the page buffer 422 that represents the value of data to be read from or programmed into the memory cells 404. The selected data can be transferred between the page buffer 422 and the I / O circuitry 426 using second data lines 418. In some examples, a flash translation layer (not shown) can map addresses provided by the host to physical memory addresses used by the row decoder 412 and the column decoder 414 to read data in the memory array 402.

[0065] The memory control unit 430 can receive positive and negative power supply signals, such as a power supply voltage (Vcc) 434 and a negative power supply (Vss) 436 (e.g., ground potential) from an external power source or source (e.g., an internal or external battery, an AC / DC converter, etc.). In a particular example, the memory control unit 430 can include a regulator 428 for providing the positive or negative power supply signals internally.

[0066] Internal copyback capable scrambler As previously mentioned, utilizing the physical page address to scramble data to meet data pattern requirements when written to a memory device is not possible when the internal copyback operation does not modify the data, but instead directly copies data in one location on the die to another location. The physical address of the cell where the data is currently stored cannot be used to unscramble the data after the internal copyback operation, because the address changes from the address where the data was originally written.

[0067] As previously mentioned, this disclosure describes a method, system, and machine-readable medium that provides a seed generator for generating a seed value that is used by a scrambler to scramble one or both of the host data and metadata, either together or separately. The seed is then appended to the scrambled host data and metadata and written to the memory device. Any subsequent internal copy-back operation can copy the data, including the seed, exactly as it was written. A read operation then descrambles the data read from the memory device by first reading the seed (which is stored unscrambled), and then using it to reverse the scrambling operation to obtain the host data and metadata. This read operation still works after the internal copy-back operation because the scrambler's seed is stored in an unscrambled state along with the data written to the memory device.

[0068] As mentioned above, in some examples, the scrambler uses the same seed value to scramble and unscramble the data, while in other examples, the scrambler uses a different value to unscramble the data than was used to scramble the data. For example, a first encryption key of a key pair may be used to scramble (by encrypting) one or both of the host data and metadata, and a second encryption key of the key pair may be used to unscramble the data. In these examples, the value (e.g., the second key) used by the unscrambler to unscramble the data is stored with the data.

[0069] 5 illustrates the data flow of a write operation according to some examples of the present disclosure. Host data 615 is received from a host for writing to a memory device. Metadata 610 may be created by the controller 105, the memory device such as the memory die 130, or parts of the metadata 610 may be created by both the controller 105 and the memory die 130. The metadata may include information about the host data and the conditions under which the host data was stored, such as the write temperature and other details.

[0070] The host data 615 and metadata 610 are then input to a scrambler 620. The scrambler 620 can be any algorithm that can reversibly convert the host data 615 and metadata 610 to different values ​​using one or more seed values, such as an XOR operation, an encryption operation (e.g., RSA, Data Encryption Standard, Triple DES, RSA, Blowfish, Advanced Encryption Standard (AES), etc.), etc. Those skilled in the art will appreciate that multiple seed values ​​may be used for a scrambler algorithm that utilizes multiple keys or other values ​​that are used to unscramble the metadata and host data, for example, or in some examples the metadata and host data may be split and scrambled with different seeds. In examples where multiple seeds are used, each seed used to unscramble the data may be stored with the scrambled host data and metadata.

[0071] The seed 630 may be used by the scrambler to generate scrambled metadata and host data 635. The seed 630 may be generated by a seed generator 625. In some examples, the seed generator 625 may be a random number generator. The seed generator 625 may be a hardware random number generator, a software random number generator, etc. The seed generator 625 may be a true random number generator or a pseudo-random number generator. In other examples, the seed generator 625 may be a cryptographic key generator, etc. The seed generator 625 may select from a list of previously determined seed values ​​or may generate a new seed value (e.g., based on the execution of a formula or hardware logic). Each seed may be generated specifically in response to receiving the host data 615, so that a first seed for a first host data may be different from a second seed for a subsequently received host data.

[0072] In some examples, the seed generator 625 may need to be seeded. For example, if the seed generator 625 is a pseudo-random number generator, the seed generator may be seeded initially, at each startup of the memory device, periodically, and / or the like. The seed generator 625 may be seeded with the current time, the current temperature, a physical address corresponding to the last written word of the memory device or portion of the memory device (e.g., a die), the next written physical address, etc. As previously mentioned, the seed generator may have the seed refreshed periodically (e.g., after a predetermined period of time).

[0073] Each page written to the memory device may have a seed generated or selected for that page, which may be used by the scrambler to scramble the host data and / or metadata. In some examples, a single seed is generated for both the metadata and the host data, while in other examples, different seeds are generated for the metadata and the host data. In some examples, the seed 630 and scrambler 620 are operable to scramble the host data and metadata such that the host data and metadata may be descrambled independently of one another, thereby allowing the metadata to be descrambled without knowing the host data.

[0074] Once the seed is generated and used, it is appended to the scrambled metadata and host data (either before the scrambled metadata and host data as shown, or after the scrambled metadata and host data). The combined seed and scrambled metadata and host data are then encoded in error correction code encoder 640 to generate encoded data 645, which is programmed into memory cells of the memory device.

[0075] FIG. 6 illustrates the data flow of a read operation according to some examples of the present disclosure. The host sends a read request to the memory device, including a logical address, which the memory device translates into a physical address using a logical-to-physical (L2P) table. A command is then issued to the appropriate memory die corresponding to that physical address. The memory cell at that physical address is then read by applying an appropriate read voltage to the memory cell. The resulting encoded data 645 is decoded in the ECC decoder 650. If the ECC decoding is successful, the scrambled metadata and host data 635 and seed 630 are recovered. The seed is then used by the unscrambler 655 to unscramble the scrambled metadata and host data 635 back to the original metadata 610 and host data 615. The unscrambler 655 can apply the inverse operation to that performed by the scrambler 620. For example, if the scrambler 620 applies an XOR operation to XOR the metadata 610 and host data 615 with a random number sequence with the seed 630, the unscrambler 655 applies an XOR operation to XOR the random number sequence with the seed with the scrambled metadata and host data 635 to obtain descrambled metadata 610 and host data 615.

[0076] 7 illustrates a flowchart of a method 700 for writing data to a memory device according to some examples of the present disclosure. In operation 710, the memory device may receive data to write to memory cells. For example, a host may instruct the memory device to write host data to the memory device. This instruction may cause the host to provide host data to be written to the memory device.

[0077] In operation 715, a seed value may be generated. The seed value may be generated in response to receiving the data to be written (e.g., by being generated simultaneously as the data is received). The seed value may be an integer value. The seed value may be newly generated or selected each time the memory device writes new data to a memory cell. A particular seed value may differ from a previously generated seed value. In some examples, the seed value may be unique within a particular plane, a particular die, a particular memory device, etc. In other examples, the seed value may not be unique, but may eventually be repeated after a series of different seed values. The seed value may be random or pseudorandom. As previously discussed, the seed value may be a randomly generated value, a cryptographic key, etc.

[0078] In operation 720, the data to be written may be scrambled using a seed value. For example, the data received in operation 710 may be combined with the metadata generated by the memory device and transformed by a scrambling algorithm using the seed value. For example, the algorithm may be an XOR algorithm, and the data and metadata may be XORed with the seed to generate a scrambled value. In other examples, the data and metadata may be encrypted with the seed. The scrambling algorithm may be any algorithm that takes at least two inputs (data (e.g., the combined host data and metadata), and a seed value) and produces an output that is different from this data but is also reversible in that a function may be used to convert the scrambled data to the original data using the seed value. In some examples, the metadata and host data may be scrambled such that the metadata may be unscrambled without knowledge of the host data. In some examples, to accomplish this, the metadata and host data may be scrambled separately with the same seed or different seeds. If the host data and metadata are scrambled with different seeds, each seed may be stored with the encoded and scrambled metadata and host data (e.g., operation 730).

[0079] In operation 725, the seed value may be concatenated with the scrambled data (e.g., host data and metadata) and encoded, for example using an error correction coding (ECC) scheme. This encoded data may then be written to a first plurality of memory cells of a die (e.g., shown as a first die) of the memory device in operation 730. For example, the encoded data may be written to a series of memory cells that form a word of the memory device. As previously mentioned, if multiple seed values ​​are utilized, the multiple seed values ​​may be concatenated and stored with the host data and metadata.

[0080] In operation 735, the memory device may later identify that the data is to be copied to a second plurality of memory cells of the first die, where the first and second plurality may be different memory cells. For example, the first plurality of memory cells may include an SLC cache, from which the data may need to move out to MLC, TLC, or QLC storage. In operation 740, the data may be copied to the second plurality of memory cells. In some examples, no data is transferred over an internal communication interface of the memory device (e.g., to a controller). In some examples, as described below, a metadata portion may be transferred over an internal communication interface of the memory device to a location where the metadata is updated (e.g., to a controller) and transferred back to a location where the metadata is combined with the host data for storage during an internal copyback. In these examples, the host data portion is not transferred over an internal communication interface of the memory device (e.g., a controller), and only the metadata is transferred. In yet other examples, both the host data and the metadata may be transferred over an internal communication interface of the memory device (e.g., to a controller) and then transferred back and stored in the second plurality of cells. Operations 735 and 740 may occur independently of operations 710-730, i.e., the copyback operations described in operations 735-740 may occur at a later time or may not occur at all.

[0081] FIG. 8 illustrates a flowchart of a method 800 for reading data from a memory device according to some examples of the present disclosure. In operation 810, the memory device may receive a request to read data stored in the memory device. For example, a host may request data stored at a particular logical address in the memory device. In operation 815, the data is read from the memory device at the indicated location. The data to be read is encoded. In operation 820, the encoded data is decoded. The decoded data includes one or more seed values ​​and the scrambled data (host data and metadata). In operation 825, the seed value(s) are extracted from the decoded data. For example, the seed values ​​may be stored before, after, or adjacent to the scrambled data (e.g., host data and metadata). In operation 830, the scrambled data may be unscrambled with the seed values ​​by an unscrambler. The unscrambler may be any algorithm that applies an inverse transformation to the scrambler. The host data is then transmitted to the host in operation 835. In some examples, the host data may be further processed before being sent to the host in operation 835.

[0082] Update Metadata As mentioned above, conventional internal copyback operations do not update the appropriate metadata associated with the host data because they do not decode and descramble the data. This can cause reliability issues as these metadata values ​​may be used to properly read the host data. In some examples, to solve this problem, the metadata may be separated from the host data and only the metadata may be sent over the internal I / O interface and updated by the controller. The updated metadata is then sent back to the memory die and combined with the host data (which may be stored in a memory buffer while waiting for the updated metadata) and written to a new location on the die. Although sending the metadata does impact the internal I / O interface, the I / O usage is typically less than 1% of the amount of I / O required to send both the metadata and the host data back to the controller.

[0083] In conventional methods, the host data and metadata are scrambled and encoded together. If the host data is not transferred along with the metadata, the controller cannot properly update the ECC information (such as ECC parity bits) stored with the data. This results in inaccurate decoding because the ECC information is calculated based on both the host data and the metadata. In some examples, to solve this problem, the memory device can store separate ECC information (e.g., separate parity bits) for the metadata and the host data, and apply separate ECC processes to the metadata and the host data. When the metadata is updated and encoded, the parity bits associated with the metadata are updated. Because the host data was not affected, the ECC information for the host data is not affected and does not need to be updated. Thus, the host data can be properly decoded even if the metadata has been changed.

[0084] 9 illustrates the data flow of a write operation according to some examples of the present disclosure in which metadata and host data are encoded separately. Metadata 910 and host data 915 are input to a scrambler 920. A seed generator 925 generates a seed 930 that is used to scramble the metadata and host data to generate scrambled host data 937. The metadata and host data may need to be scrambled in a manner that allows for unscrambling of the metadata in the absence of the scrambled host data, thereby allowing for updating of the metadata without receiving the host data.

[0085] This can be accomplished by utilizing a scrambling algorithm that does not utilize the host data in computing the scrambled metadata. For example, an XOR operation that XORs a random number sequence with a seed with the data in a bit-wise manner can be reversed by applying the same XOR value to the scrambled data. In these examples, descrambling still works even if the metadata is separated from the host data. In these examples, the same seed value can be used to scramble the metadata and the host data.

[0086] In other examples, the metadata 910 and the host data 915 may be scrambled with different seed values. For example, if the scrambler 920 performs an operation (e.g., some cryptographic algorithm) that requires both the metadata and the host data to be present in order to unscramble (e.g., decrypt) the data (e.g., the unscrambled metadata value), then the metadata and the host data may be scrambled separately with separate seeds. In these examples, both seeds may be stored, or only one seed may be stored if one seed can be deduced from the other. In other examples, they may be the same seed value, but the scrambling operation is performed such that knowledge of the host data (either scrambled or unscrambled) is not required to unscramble the metadata.

[0087] The scrambled metadata 935 and the seed 930 can be input to an ECC encoder 940 to generate encoded metadata 945. Separately, the scrambled host data 937 can be fed to the ECC encoder 940 to generate encoded host data 947. The encoded metadata 950 and encoded host data 952 (along with ECC information such as parity bits) can then be written to memory cells of a memory device. As shown, the seed 930 is encoded along with the scrambled metadata 935, although in other examples the seed 930 may be encoded along with the scrambled host data 937 or along with both the scrambled metadata 935 and the scrambled host data 937.

[0088] 10 illustrates a data flow 1000 of an internal copyback operation with metadata update according to some examples of the present disclosure, where the metadata and host data are encoded separately. The encoded metadata 1010 and the encoded host data 1015 are read from the medium. The encoded host data 1015 is stored in a memory buffer, such as a page buffer 1020. In some examples, the encoded metadata 1010 is also stored in the buffer (unless the metadata needs to be updated).

[0089] The encoded metadata 1010 is transferred via a communications interface to the controller where it is decoded by a decoder 1025 and descrambled by an unscrambler 1030. ECC information and seeds, such as parity data for the scrambler (which may be encoded along with the metadata, the host data, or both), may also be transferred and used by the decoder 1025 and the unscrambler 1030. If the ECC check of the metadata fails, the memory device may abort the internal copyback operation and enter into a data recovery step.

[0090] Once the metadata can be read, at 1035, it can be determined whether the metadata needs to be updated. For example, updating the drive's write temperature, write time, etc. If the metadata does not need to be updated, an indication may or may not be sent back to the memory die. For example, a message indicating that no changes are required. In other examples, even if the metadata is not updated, it may be re-randomized, re-encoded, and sent back. This has the advantage of ensuring that the metadata is error-free. In some examples, the system may decide not to update the metadata if the written metadata is close enough (e.g., within a specified distance). Thus, if the drive temperature when the data was originally written is close to the current temperature, the metadata may not need to be updated. In some examples, this decision is optional, since the system may be configured to always update the metadata (e.g., update the write timestamp). In some examples, all metadata is updated, and in other examples, only some fields of the metadata are updated. In some examples, whether a particular field of the metadata is updated may depend on a particular rule. For example, one particular field may always be updated, but the remaining fields may only be updated if a rule evaluates to indicate that the metadata field needs to be updated. For example, a rule may be that if the difference between the temperature at which the data was originally written and the current temperature is above a threshold, then the write temperature may be updated, otherwise the write temperature may not be updated.

[0091] If 1035 determines that the metadata needs to be updated, the metadata is updated by the metadata updater 1040, for example by incorporating various measurements (e.g., temperature, time, etc.) from various sensors in the memory device. The scrambler 1045 then scrambles the updated metadata using the same key that was originally used to scramble the metadata. The encoder 1050 then encodes the scrambled and updated metadata to generate new ECC information. The encoded metadata with associated updated ECC information (e.g., parity bits) is then sent back to the memory die and combined with the encoded host data in the page buffer 1020. This combination of updated metadata and host data is then written to the medium.

[0092] FIG. 11 illustrates a flowchart of a method 1100 of writing data to a memory device according to some examples of the disclosure. FIG. 11 may be performed by a controller of a memory device, such as the controller 105 of FIG. 1. In operation 1110, the controller may receive a write request including host data. In operation 1115, the controller may determine metadata corresponding to the host data, such as the write temperature, the time the data was written, etc. In operation 1120, the controller scrambles the metadata and the host data such that the metadata may be descrambled without knowing the host data. In other words, the scrambling process does not utilize the host data, so knowledge of the host data is not required to descramble the metadata. For example, the metadata may be scrambled with a seed or key (either the same seed or key used to scramble the host data or a different seed or key) in a separate operation from the host data. In yet other examples, for certain scrambling algorithms, separate processing may not be required. That is, the nature of the scrambling algorithm allows for independent descrambling of bits given a seed. For example, the value of the descrambled bits of the metadata does not depend on the values ​​of any bits other than the metadata (eg, host data), except for the value of the key.

[0093] In operation 1125, the scrambled host data and metadata are separately encoded with separate encoding information. In operation 1130, the controller can cause the encoded metadata and the encoded host data to be stored in the memory device. For example, the controller can send a command over the internal communication interface to instruct the memory die to program the physical word line(s) of the memory cells to store the encoded metadata and the encoded host data.

[0094] FIG. 12 illustrates a flowchart of a method 1200 for writing data to a memory device during an internal copyback operation according to some examples of the disclosure. FIG. 12 may be performed by a controller of a memory device, such as controller 105 of FIG. 1. In operation 1210, in response to an internal copyback command (either issued by the controller or generated within the memory die), the memory die may send, and the controller may receive, encoded and scrambled metadata. This metadata is encoded and / or scrambled such that it can be decoded and / or unscrambled without the host data. That is, no host data is sent by the memory die to the controller.

[0095] In operation 1215, the metadata is decoded using the encoding information. As discussed above, if the decoding fails (e.g., the metadata has an uncorrectable ECC error), the memory device cancels the internal copyback operation and attempts to recover the data by a recovery operation. In operation 1220, the controller descrambles the decoded metadata from operation 1215. For example, by using a seed appended to the decoded metadata or a seed sent by the memory die. As discussed above, the seed may not be scrambled. Operation 1220 descrambles the decoded metadata without knowledge of the host data or data corresponding to the host data. That is, the descrambling of operation 1220 does not require knowledge of the host data, the encoded host data, the scrambled host data, the encoded and scrambled host data, etc.

[0096] Then, in operation 1225, the descrambled and decoded metadata is updated. For example, the write temperature is updated, the write time is updated, etc. As mentioned above, in some examples, the metadata or fields of the metadata may be selectively updated based on the evaluation of one or more rules, the current metadata, the current memory device state (e.g., temperature, time, etc.), etc. The metadata may be updated with the current memory device state. In operation 1230, the updated metadata is scrambled with a seed. In operation 1235, the scrambled and updated metadata is encoded. In operation 1240, the encoded scrambled and updated metadata is sent back to the memory die to be combined with the stored scrambled and encoded host data and written to the memory cells.

[0097] FIG. 13 illustrates a flowchart of a method 1300 of an internal copyback operation on a memory device according to some examples of the present disclosure. FIG. 13 may be performed by a memory die of a memory device, such as the memory die 130 of FIG. 1. The memory die 130 may have processing circuitry and working memory (e.g., volatile memory). The processing circuitry may be one or more processors that may be configured to perform the method 1300. In operation 1310, the memory die 130 may identify an internal copyback command for one or more memory locations in the memory die. For example, a command may be issued by a controller, various triggers may be identified for moving data stored in memory cells corresponding to the SLC cache to MLC, TLC, or QLC storage, etc. The various triggers may include idle time, utilization of the SLC cache, a controller command, etc. Both the SLC cache and the final target MLC, TLC, or QLC storage may be on the same memory die. In these instances (e.g., where the source and destination are identified as being on the same memory die), an internal copyback operation may be performed to copy data (host data and metadata) from a first location on the die to a second location on the same die without transferring the entire data over a communications interface with the controller.

[0098] In operation 1315, the source memory location of the internal copyback is read to obtain metadata and host data, which are both scrambled and encoded. In operation 1320, the encoded and scrambled host data read from the source memory location is copied to a buffer, such as a page buffer. In some examples, the encoded and scrambled metadata may also be copied to the same buffer, such as a page buffer, as the encoded and scrambled host data.

[0099] In operation 1325, the encoded and scrambled metadata may be sent to a controller for updating via an internal communication interface (e.g., a communication bus). In operation 1330, the memory die may receive the updated metadata or an indication that the metadata does not need to be updated. In operation 1335, the memory die may write the encoded and scrambled updated metadata (or the original metadata if the metadata does not need to be updated) along with the encoded and scrambled host data to the destination memory cells.

[0100] FIG. 14 illustrates a block diagram of an example machine 1400 in which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. For example, memory device 100 may include or be implemented by one or more components of FIG. 14. Host 135 may be or include one or more components of machine 1400. In these examples, memory device 100 may be mass storage 1421. One or more components of machine 1400 may implement one or more of the methods or structures of FIGS. 1-13. For example, by operation of instructions 1424.

[0101] In alternative embodiments, machine 1400 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 1400 may operate in a server-client network environment in the capacity of a server machine, a client machine, or both. In one example, machine 1400 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 1400 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, an IoT device, an automotive system, a host device, a memory device, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be performed by the machine. Components of machine 1400 may reside in a memory device (e.g., a processor, a main memory, a mass storage, etc.). Further, although only a single machine is shown, the term "machine" is also intended to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to implement any one or more of the methodologies described herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations, etc.

[0102] The embodiments described herein may include or operate with logic, components, devices, packages, or mechanisms. An electric circuit is a collection (e.g., set) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The components of an electric circuit may flexibly respond to the passage of time and variability of the underlying hardware. An electric circuit includes components that, alone or in combination, may perform a specific task when operated. In one embodiment, the hardware of an electric circuit may be invariably designed to perform a specific operation (e.g., hardwired). In one embodiment, the hardware of an electric circuit may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include a computer-readable medium that is physically modified (e.g., magnetic, electrical, movable arrangement of immutable mass particles, etc.) to encode instructions for a specific operation. In connecting the physical components, the underlying electrical properties of the hardware constructs are changed, for example, from an insulator to a conductor or vice versa. The instructions cause the associated hardware (e.g., an execution unit or a load mechanism) to create components of the circuitry within the hardware via variable connections to perform a portion of a particular task during operation. Thus, the computer-readable medium is communicatively coupled to other components of the circuitry when the device is operating. In one example, any of the physical components may be used in multiple elements of multiple circuitry. For example, during operation, an execution unit may be used in a first circuit of a first circuitry at one time and reused by a second circuit of the first circuitry or by a third circuit of the second circuitry at another time.

[0103] The machine (e.g., computer system) 1400 (e.g., host device 135, memory device 100, etc.) may include a hardware processor 1402 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as the processor 115 of the memory controller 105, etc.), a main memory 1404, and a static memory 1406, some or all of which may communicate with each other via an interlink (e.g., bus) 1408. The machine 1400 may further include a display unit 1410, an alphanumeric input device 1412 (e.g., a keyboard), and a user interface (UI) navigation device 1414 (e.g., a mouse). In one example, the display unit 1410, the input device 1412, and the UI navigation device 1414 may be touch screen displays. The machine 1400 may further include a sensor 1416, a signal generation device 1418 (e.g., a speaker), and a network interface device 1420. The sensors 1416 may include a Global Positioning System (GPS) sensor, a compass, an accelerometer, and / or other sensors. The machine 1400 may include an output controller 1428, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0104] The mass storage device 1421 may include a machine-readable medium 1422 on which is stored one or more sets of data structures or instructions 1424 (e.g., software) that incorporate or are utilized by any one or more of the techniques or functions described herein. The instructions 1424 may also reside, completely or at least partially, in the main memory 1404, in the static memory 1406, or in the hardware processor 1402 during their execution by the machine 1400. In one example, one or any combination of the hardware processor 1402, the main memory 1404, the static memory 1406, or the mass storage device 1416 may constitute the machine-readable medium 1422.

[0105] Although the machine-readable medium 1422 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 1424.

[0106] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by the machine 1400, causing the machine 1400 to perform any one or more of the techniques of this disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, as well as optical and magnetic media. In some examples, the machine-readable medium 1422 is a non-transitory machine-readable medium. In one embodiment, a massed machine-readable medium includes a machine-readable medium having a plurality of particles having a non-changing (e.g., stationary) mass. Thus, a massed machine-readable medium is not a transitory propagating signal. Specific examples of massed machine-readable media may include semiconductor memory devices (e.g., non-volatile memories such as electrically programmable read-only memories (EPROMs), electronically erasable programmable read-only memories (EEPROMs), and flash memory devices, magnetic disks such as internal hard disks and removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0107] Instructions 1424 (e.g., software, programs, operating system (OS), etc.) or other data can be stored in mass storage device 1421 and accessed by memory 1404 for use by processor 1402. Memory 1404 (e.g., DRAM) is a different type of storage than storage device 1421 (e.g., SSD), which is generally fast but volatile and thus suitable for long-term storage, including periods in an "off" state. Instructions 1424 or data used by a user or machine 1400 are typically loaded into memory 1404 for use by processor 1402. When memory 1404 becomes full, virtual space from storage device 1421 can be allocated to supplement memory 1404, but storage device 1421 is typically slower than memory 1404, with write speeds typically at least twice as slow as read speeds, so using virtual memory can significantly degrade the user experience due to the latency of storage devices (as opposed to memory 1404, e.g., DRAM). Furthermore, use of the storage device 1421 for virtual memory can significantly reduce the usable life of the storage device 1421.

[0108] In contrast to virtual memory, virtual memory compression (e.g., the Linux® kernel feature "ZRAM") uses a portion of memory as compressed block storage to avoid paging to storage device 1421. Paging is done in compressed blocks until it is necessary to write such data to storage device 1421. Virtual memory compression increases the available size of memory 1404 while reducing wear on storage device 1421.

[0109] Storage devices such as mass storage 1421 may be memory devices such as NAND memory devices. Storage devices such as mass storage 1421, including MMC solid state storage devices (e.g., micro Secure Digital (microSD™) cards, etc.), may be optimized for mobile electronic devices or mobile storage. MMC devices include multiple parallel interfaces with a host device (e.g., 8-bit parallel interfaces, etc.) and are often removable and separate components from the host device. In contrast, eMMC™ devices are mounted on a circuit board, considered a component of the host device, and have read speeds that rival Serial ATA™ (Serial AT (Advanced Technology) Attachment, or SATA)-based SSD devices. However, performance demands on mobile devices continue to increase, such as fully enabling virtual or augmented reality devices and taking advantage of increasing network speeds. In response to this demand, storage devices have transitioned from parallel to serial communication interfaces. A Universal Flash Storage (UFS) device, including the controller and firmware, communicates with a host device using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths to further increase read / write speeds.

[0110] The instructions 1424 may further be transmitted or received over a communications network 1426 using a transmission medium via a network interface device 1420 utilizing any one of a number of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Examples of communications networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile telephone networks (e.g., cellular networks), plain old telephone service (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, the IEEE 802.16 family of standards known as WiMax®), the IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. In one example, the network interface device 1420 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to the communications network 1426. In one example, the network interface device 1420 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" shall be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by the machine 1400, including digital or analog communications signals, or other intangible media to facilitate communication of such software.

[0111] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors also contemplate examples that use any combination or variation of those illustrated or described elements (or one or more aspects thereof) with respect to a particular example (or one or more aspects thereof) shown or described herein, or with respect to other examples (or one or more aspects thereof).

[0112] In this document, the terms "a" or "an" are used to include one or more, as is common in patent documents, regardless of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a non-exclusive or, unless otherwise indicated, "A or B" is used to include "A but not B," "B but not A," and "A and B." In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended. That is, a system, device, article, or process that includes elements in addition to the elements recited following such a term in a claim is also deemed to be within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0113] In various embodiments, a component, controller, processor, unit, engine, or table described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" refers to any type of computational circuitry, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuitry, including a group of processors or multi-core devices.

[0114] Various embodiments described herein according to the present disclosure include memories that utilize vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives are interpreted relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure is interpreted as extending away from the substrate surface, a bottom end of a vertical structure is interpreted as the end closest to the substrate surface, and a top end of a vertical structure is interpreted as the end furthest from the substrate surface).

[0115] As used herein, directional adjectives such as horizontal, vertical, perpendicular, parallel, perpendicular, etc., may refer to relative orientations and are not intended to require strict adherence to specific geometric characteristics unless otherwise specified. For example, a vertical structure as used herein need not be strictly perpendicular to the surface of the substrate, but may instead be generally perpendicular to the surface of the substrate and may form an acute angle (e.g., 60-120 degrees, etc.) with the surface of the substrate.

[0116] In some embodiments described herein, different doping configurations may be applied to the source side select gate (SGS), the control gate (CG), and the drain side select gate (SGD), each of which may be made of or at least include polysilicon in this example, so that these layers (such as polysilicon) may have different etching rates when exposed to an etchant. For example, in a process of forming a monolithic pillar in a 3D semiconductor device, the SGS and CG may form recesses, while the SGD may remain in a form with little or no recesses. Thus, these doping configurations may enable selective etching of separate layers (such as the SGS, CG, and SGD) of a 3D semiconductor device using an etchant (such as tetramethylammonium hydroxide (TMCH)).

[0117] As used herein, manipulating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. The act of placing a memory cell in an intended state is referred to herein as "programming" and can include both writing to or erasing from a memory cell (e.g., a memory cell can be programmed to an erased state).

[0118] In accordance with one or more embodiments of the present disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located within or external to a memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) the amount of wear cycles or wear state (e.g., recording wear cycles, counting memory device operations when wear cycles occur, tracking memory device operations that initiate the counting, evaluating memory device characteristics corresponding to the wear state, etc.).

[0119] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device for each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for changes in memory device performance corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0120] When an element is referred to as being "on," "connected to," or "coupled with" another element, it will be understood that the element may be directly on, connected to, or coupled with the other element, or that there may be intervening elements. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled with" another element, there are no intervening elements or layers present. When two elements are shown in a drawing with a line connecting them, the two elements are either coupled or directly coupled, unless otherwise indicated.

[0121] The embodiments of the methods described herein may be implemented, at least in part, in a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform a method as described in the above examples. Such method implementations may include code such as microcode, assembly language code, high-level language code, and the like. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSD), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, and the like.

[0122] The above description is intended to be illustrative and not limiting. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. This is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be construed as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may reside in less than all features of a particular disclosed embodiment. Accordingly, it is contemplated that the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and that such embodiments can be combined with each other in various combinations or variations. The scope of the invention should be determined with reference to the claims, along with the full scope of equivalents to which such claims are entitled.

[0123] Further notes and examples Example 1 is a method of storing data in a non-volatile memory device, the method including: receiving data and writing it to a plurality of memory cells of the memory device; in response to receiving the data, generating a scrambler seed value for the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of a first die of the memory device; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring a host data portion of the encoded data from the first die to a controller of the memory device.

[0124] In example 2, the subject matter of example 1 includes where generating the seed value includes obtaining a random number.

[0125] In example 3, the subject matter of example 2 includes where obtaining the random number includes using a hardware random number generator.

[0126] In example 4, the subject matter of examples 2-3 includes where the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0127] In example 5, the subject matter of examples 1-4 includes where the seed value is a cryptographic key.

[0128] In Example 6, the subject matter of Examples 1-5 includes the scrambling algorithm being an XOR algorithm, and scrambling the data includes XORing the data with a random number sequence generated by the seed value to generate the scrambled data.

[0129] In example 7, the subject matter of examples 1-6 includes where the scrambling algorithm is a cryptographic algorithm, and scrambling the data by transforming the data using the cryptographic algorithm and the seed value to generate the scrambled data includes encrypting the data with the seed value.

[0130] In Example 8, the subject matter of Examples 1-7 includes receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0131] Example 9 is a memory device, the memory device including a first memory die including a plurality of memory cells; and a controller, the controller configured to perform operations including receiving and writing data to the plurality of memory cells; in response to receiving the data, generating a scrambler seed value for the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of the first die; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring a host data portion of the encoded data from the first die to a controller of the memory device.

[0132] In example 10, the subject matter of example 9 includes where the operation of generating the seed value includes obtaining a random number.

[0133] In example 11, the subject matter of example 10 includes wherein the memory device includes a hardware random number generator, and wherein the operation of obtaining the random number includes obtaining the random number from the hardware random number generator.

[0134] In Example 12, the subject matter of Examples 10-11 includes where the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0135] In Example 13, the subject matter of Examples 9-12 includes where the seed value is a cryptographic key.

[0136] In Example 14, the subject matter of Examples 9-13 includes the scrambling algorithm being an XOR algorithm, and the operation of scrambling the data includes XORing the data with a random number sequence generated by the seed value to generate the scrambled data.

[0137] In Example 15, the subject matter of Examples 9-14 includes where the scrambling algorithm is a cryptographic algorithm, and where the operation of scrambling the data by transforming the data using the cryptographic algorithm and the seed value to generate the scrambled data includes encrypting the data with the seed value.

[0138] In Example 16, the subject matter of Examples 9-15 includes the operations further including receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0139] Example 17 is a non-transitory machine-readable medium storing instructions that, when executed, cause a memory device to perform operations including receiving data and writing it to a plurality of memory cells of the memory device; in response to receiving the data, generating a scrambler seed value for the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of the first die; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring a host data portion of the encoded data from the first die to a controller of the memory device.

[0140] In example 18, the subject matter of example 17 includes where the operation of generating the seed value includes obtaining a random number.

[0141] In Example 19, the subject matter of Example 18 includes wherein the memory device includes a hardware random number generator, and wherein the operation of obtaining the random number includes obtaining the random number from the hardware random number generator.

[0142] In Example 20, the subject matter of Examples 18-19 includes where the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0143] In Example 21, the subject matter of Examples 17-20 includes where the seed value is an encryption key.

[0144] In Example 22, the subject matter of Examples 17-21 includes where the scrambling algorithm is an XOR algorithm, and where the operation of scrambling the data includes XORing the data with a random number sequence generated by the seed value to generate the scrambled data.

[0145] In Example 23, the subject matter of Examples 17-22 includes where the scrambling algorithm is a cryptographic algorithm, and where the operation of scrambling the data by transforming the data using the cryptographic algorithm and the seed value to generate the scrambled data includes encrypting the data with the seed value.

[0146] In Example 24, the subject matter of Examples 17-23 includes the operations further including receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0147] Example 25 is at least one machine-readable medium containing instructions that, when executed by a processing circuit, cause the processing circuit to perform operations that implement any of Examples 1 to 24.

[0148] Example 26 is an apparatus including means for implementing any one of Examples 1 to 24.

[0149] The twenty-seventh embodiment is a system that implements any one of the first to twenty-fourth embodiments.

[0150] Example 28 is a method for implementing any one of Examples 1 to 24.

[0151] Example 29 is a method of storing data in a non-volatile memory device, the method including receiving data and writing it to a plurality of memory cells of the memory device, in response to receiving the data, generating a scrambler seed value for the data, scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data, encoding both the seed value and the scrambled data to create encoded data, causing the encoded data to be written to a first plurality of memory cells of a first die of the memory device, identifying that the encoded data is to be copied to a second plurality of memory cells in the first die, and in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring a host data portion of the encoded data from the first die to a controller of the memory device.

[0152] In Example 30, the subject matter of example 29 includes where generating the seed value includes obtaining a random number.

[0153] In example 31, the subject matter of example 30 includes where obtaining the random number includes using a hardware random number generator.

[0154] In Example 32, the subject matter of Examples 30-31 includes where the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0155] In Example 33, the subject matter of Examples 29-32 includes where the seed value is an encryption key.

[0156] In Example 34, the subject matter of Examples 29-33 includes the scrambling algorithm being an XOR algorithm, and scrambling the data includes XORing the data with a random number sequence generated by the seed value to generate the scrambled data.

[0157] In Example 35, the subject matter of Examples 29-34 includes where the scrambling algorithm is an encryption algorithm, and where scrambling the data by transforming the data using the encryption algorithm and the seed value to generate the scrambled data includes encrypting the data with the seed value.

[0158] In Example 36, the subject matter of Examples 29 to 35 includes receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0159] Example 37 is a memory device including a first memory die including a plurality of memory cells; and a controller configured to perform operations including receiving and writing data to the plurality of memory cells; in response to receiving the data, generating a scrambler seed value for the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of the first die; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring a host data portion of the encoded data from the first die to a controller of the memory device.

[0160] In example 38, the subject matter of example 37 includes where the operation of generating the seed value includes obtaining a random number.

[0161] In Example 39, the subject matter of Example 38 includes wherein the memory device includes a hardware random number generator, and wherein the operation of obtaining the random number includes obtaining the random number from the hardware random number generator.

[0162] In Example 40, the subject matter of Examples 38-39 includes where the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0163] In Example 41, the subject matter of Examples 37-40 includes where the seed value is an encryption key.

[0164] In Example 42, the subject matter of Examples 37-41 includes where the scrambling algorithm is an XOR algorithm, and where the operation of scrambling the data includes XORing the data with a random number sequence generated by the seed value to generate the scrambled data.

[0165] In Example 43, the subject matter of Examples 37-42 includes where the scrambling algorithm is an encryption algorithm, and where the operation of scrambling the data by transforming the data using the encryption algorithm and the seed value to generate the scrambled data includes encrypting the data with the seed value.

[0166] In example 44, the subject matter of examples 37-43 includes the operations further including receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0167] Example 45 is a non-transitory machine-readable medium storing instructions that, when executed, cause a memory device to perform operations including receiving data and writing it to a plurality of memory cells of the memory device; in response to receiving the data, generating a scrambler seed value for the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of the first die; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring a host data portion of the encoded data from the first die to a controller of the memory device.

[0168] In example 46, the subject matter of example 45 includes where the operation of generating the seed value includes obtaining a random number.

[0169] In example 47, the subject matter of example 46 includes wherein the memory device includes a hardware random number generator, and wherein the operation of obtaining the random number includes obtaining the random number from the hardware random number generator.

[0170] In example 48, the subject matter of examples 46-47 includes wherein the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0171] In Example 49, the subject matter of Examples 45-48 includes where the seed value is an encryption key.

[0172] In example 50, the subject matter of examples 45-49 includes where the scrambling algorithm is an XOR algorithm, and where the operation of scrambling the data includes XORing the data with a random number sequence generated by the seed value to generate the scrambled data.

[0173] In Example 51, the subject matter of Examples 45-50 includes where the scrambling algorithm is an encryption algorithm, and where the operation of scrambling the data by transforming the data using the encryption algorithm and the seed value to generate the scrambled data includes encrypting the data with the seed value.

[0174] In example 52, the subject matter of examples 45-51 includes the operations further including receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0175] Example 53 is at least one machine-readable medium containing instructions that, when executed by a processing circuit, cause the processing circuit to perform operations that implement any of Examples 29 to 52.

[0176] Example 54 is an apparatus including means for implementing any one of Examples 29 to 52.

[0177] Example 55 is a system that implements any one of Examples 29 to 52.

[0178] Example 56 is a method for implementing any one of Examples 29 to 52.

[0179] Example 57 is a method of performing a copyback operation for a memory device, the method including: receiving, at a memory controller of the memory device, encoded metadata from a memory die via an internal communication interface of the memory device in response to initiation of a copyback operation, wherein host data corresponding to the metadata is not transmitted by the memory die via the internal communication interface; decoding the encoded metadata to generate decoded metadata; descrambling the decoded metadata using a key value to generate descrambled metadata, wherein the key value is stored as part of the decoded metadata; updating the descrambled metadata to generate updated metadata; scrambling the updated metadata with the key value to generate scrambled updated metadata; encoding the scrambled updated metadata to generate encoded updated metadata; and transmitting the encoded updated metadata to the memory die, wherein the encoded updated metadata is combined with encoded host data and written to a new location on the memory die.

[0180] In Example 58, the subject matter of Example 57 includes where updating the descrambled metadata includes updating a write temperature.

[0181] In Example 59, the subject matter of Examples 57-58 includes where updating the descrambled metadata includes updating a write time.

[0182] In Example 60, the subject matter of Examples 57-59 includes identifying an internal copyback command for a first memory location in the memory die of the memory device, reading the first memory location to obtain the encoded metadata and the encoded host data, storing the encoded host data in a memory buffer on the memory die, transmitting the encoded metadata to the memory controller, receiving the encoded updated metadata from the memory controller, and writing the encoded updated metadata along with the encoded host data stored in the memory buffer to the new location on the memory die.

[0183] In Example 61, the subject matter of Examples 57-60 includes where descrambling the decoded metadata using the key value to generate unscrambled metadata includes applying an XOR operation to the decoded metadata and the key value.

[0184] In Example 62, the subject matter of Examples 57-61 includes where the encoded metadata includes encoding information used for the decoding.

[0185] In Example 63, the subject matter of Example 62 includes wherein the encoded information is at least one parity bit.

[0186] In Example 64, the subject matter of Examples 62-63 includes the encoding information of the encoded metadata being different from second encoding information included in encoded host data corresponding to the host data.

[0187] Example 65 is a memory device including a memory controller configured to perform operations including receiving encoded metadata from a memory die via an internal communication interface of the memory device in response to initiation of a copyback operation, wherein host data corresponding to the metadata is not transmitted by the memory die via the internal communication interface; decoding the encoded metadata to generate decoded metadata; descrambling the decoded metadata using a key value to generate descrambled metadata, wherein the key value is stored as part of the decoded metadata; updating the descrambled metadata to generate updated metadata; scrambling the updated metadata with the key value to generate scrambled updated metadata; encoding the scrambled updated metadata to generate encoded updated metadata; and transmitting the encoded updated metadata to the memory die, wherein the encoded updated metadata is combined with encoded host data and written to a new location on the memory die.

[0188] In Example 66, the subject matter of Example 65 includes where the operation of updating the descrambled metadata includes updating a write temperature.

[0189] In Example 67, the subject matter of Examples 65-66 includes where the operation of updating the descrambled metadata includes updating a write time.

[0190] In Example 68, the subject matter of Examples 65-67 includes the memory die, wherein the memory die includes a processor, the processor configured to perform operations including identifying an internal copyback command for a first memory location, reading the first memory location to obtain the encoded metadata and the encoded host data, storing the encoded host data in a memory buffer on the memory die, transmitting the encoded metadata to the memory controller, receiving the encoded updated metadata from the memory controller, and writing the encoded updated metadata, along with the encoded host data stored in the memory buffer, to the new location on the memory die.

[0191] In Example 69, the subject matter of Examples 65-68 includes where the operation of descrambling the decoded metadata using the key value to generate unscrambled metadata includes applying an XOR operation to the decoded metadata and the key value.

[0192] In Example 70, the subject matter of Examples 65-69 includes where the encoded metadata includes encoding information used for the decoding.

[0193] In Example 71, the subject matter of Example 70 includes wherein the encoded information is at least one parity bit.

[0194] In Example 72, the subject matter of Examples 70-71 includes the encoding information of the encoded metadata being different from second encoding information included in encoded host data corresponding to the host data.

[0195] Example 73 is a non-transitory machine-readable medium storing instructions that, when executed by a memory device, include receiving encoded metadata from a memory die via an internal communications interface of the memory device in response to initiating a copyback operation, wherein no host data corresponding to the metadata is transmitted by the memory die via the internal communications interface; decoding the encoded metadata to generate decoded metadata; and descrambling the decoded metadata using a key value to generate the descrambled metadata, wherein the key value is used to decode the descrambled metadata. causing the memory device to perform operations including: generating, storing the descrambled metadata as part of the metadata; updating the descrambled metadata to generate updated metadata; scrambling the updated metadata with the key value to generate scrambled updated metadata; encoding the scrambled updated metadata to generate encoded updated metadata; and transmitting the encoded updated metadata to the memory die, where the encoded updated metadata is combined with encoded host data and written to a new location on the memory die.

[0196] In Example 74, the subject matter of Example 73 includes where the operation of updating the descrambled metadata includes updating a write temperature.

[0197] In Example 75, the subject matter of Examples 73-74 includes where the operation of updating the descrambled metadata includes updating a write time.

[0198] In Example 76, the subject matter of Examples 73-75 includes the operations further including identifying an internal copyback command for a first memory location in the memory die, reading the first memory location to obtain the encoded metadata and the encoded host data, storing the encoded host data in a memory buffer on the memory die, sending the encoded metadata to the memory controller, receiving the encoded updated metadata from the memory controller, and writing the encoded updated metadata along with the encoded host data stored in the memory buffer to the new location on the memory die.

[0199] Example 77 is at least one machine-readable medium containing instructions that, when executed by a processing circuit, cause the processing circuit to perform operations that implement any of Examples 57 to 76.

[0200] Example 78 is an apparatus including means for implementing any of Examples 57 to 76.

[0201] Example 79 is a system that implements any one of Examples 57 to 76.

[0202] Example 80 is a method for implementing any one of Examples 57 to 76.

Claims

1. 1. A method for memory device storage, comprising: identifying data to be written to a first set of one or more memory cells of a memory device, the data including host data from a host and metadata created by a controller of the memory device; generating a first seed value for the host data and a second seed value for the metadata in response to receiving the data, the first and second seed values ​​not being generated based on a physical address at which the data is located; scrambling the host data by transforming the host data with a scrambling algorithm and the first seed value to generate scrambled host data; scrambling the metadata by transforming the metadata with the scrambling algorithm and the second seed value to generate scrambled metadata; writing the scrambled host data and metadata, along with the first and second seed values, to the first set of memory cells of a first die of the memory device; The method includes:

2. The method of claim 1 , further comprising receiving the host data from the host.

3. The method of claim 1 , wherein generating the first seed value comprises generating a random seed value.

4. The method of claim 3 , wherein generating the random seed value comprises seeding a random number generator with one or more of a current time or a current temperature.

5. The method of claim 1 , wherein the scrambling algorithm includes using an XOR operation.

6. 2. The method of claim 1, wherein a third seed value generated for second data written to a second set of memory cells is different from the first seed value and the second seed value.

7. 2. The method of claim 1, wherein the scrambling algorithm comprises one of Rivest Shamir Adleman (RSA) encryption, Blowfish ciphertext, an Advanced Encryption Standard (AES) algorithm, or a Triple Data Encryption Algorithm (Triple DES).

8. 1. A memory device including a hardware processor, the hardware processor comprising: identifying data to be written to a first set of one or more memory cells of the memory device, the data including host data from a host and metadata created by a controller of the memory device; generating a first seed value for the host data and a second seed value for the metadata in response to receiving the data, the first and second seed values ​​not being generated based on a physical address at which the data is located; scrambling the host data by transforming the host data with a scrambling algorithm and the first seed value to generate scrambled host data; scrambling the metadata by transforming the metadata with the scrambling algorithm and the second seed value to generate scrambled metadata; writing the scrambled host data and metadata, along with the first and second seed values, to the first set of memory cells of a first die of the memory device; 16. A memory device configured to perform operations including:

9. The memory device of claim 8 , further comprising receiving the host data from the host.

10. The memory device of claim 8 , wherein generating the first seed value comprises generating a random seed value.

11. 11. The memory device of claim 10, wherein generating the random seed value comprises seeding a random number generator with one or more of a current time or a current temperature.

12. The memory device of claim 8 , wherein the scrambling algorithm includes using an XOR operation.

13. 9. The memory device of claim 8, wherein a third seed value generated for second data written to a second set of memory cells is different from the first seed value and the second seed value.

14. 9. The memory device of claim 8, wherein the scrambling algorithm comprises one of Rivest Shamir Adleman (RSA) encryption, Blowfish ciphertext, an Advanced Encryption Standard (AES) algorithm, or a Triple Data Encryption Algorithm (Triple DES).

15. A non-transitory machine-readable medium having stored thereon instructions that, when executed by a processor, cause a memory device to perform an operation, the operation comprising: identifying data to be written to a first set of one or more memory cells of a memory device, the data including host data from a host and metadata created by a controller of the memory device; generating a first seed value for the host data and a second seed value for the metadata in response to receiving the data, the first and second seed values ​​not being generated based on a physical address at which the data is located; scrambling the host data by transforming the host data with a scrambling algorithm and the first seed value to generate scrambled host data; scrambling the metadata by transforming the metadata with the scrambling algorithm and the second seed value to generate scrambled metadata; writing the scrambled host data and metadata, along with the first and second seed values, to the first set of memory cells of a first die of the memory device; A non-transitory machine-readable medium, including

16. 20. The non-transitory machine-readable medium of claim 15, further comprising receiving the host data from the host.

17. 20. The non-transitory machine-readable medium of claim 15, wherein generating the first seed value comprises generating a random seed value.

18. 20. The non-transitory machine-readable medium of claim 17, wherein generating the random seed value comprises seeding a random number generator with one or more of a current time or a current temperature.

19. 20. The non-transitory machine-readable medium of claim 15, wherein the scrambling algorithm includes using an XOR operation.

20. 16. The non-transitory machine-readable medium of claim 15, wherein a third seed value generated for second data written to a second set of memory cells is different from the first seed value and the second seed value.

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