Low resistance and high reliability metallization module

Abstract

To provide a method and a processing tool for fabricating an electronic device with low resistance and high reliability in narrow features.SOLUTION: In a device 200, a via 214 with reduced resistance is formed by selectively depositing a barrier layer 218 on an insulating layer 208 not on a first metallization layer 204a. A planar hydrocarbon is utilized to form a blocking layer on a metal layer 214. Deposition is performed to selectively deposit on an unblocked insulating layer 208.SELECTED DRAWING: Figure 2F

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular to integrated circuit (IC) manufacturing. More particularly, embodiments of the present disclosure are directed to methods for manufacturing electronic devices having low resistance and high reliability in narrow features. [Background technology]

[0002]

[0002] Generally, an integrated circuit (IC) refers to a set of electronic devices (e.g., transistors) formed on a small chip of semiconductor material (typically silicon). An IC usually includes one or more layers of metallization with metal lines to connect the electronic devices of the IC to each other and to external connections. Layers of interlayer dielectric material are usually disposed between the metallization layers of the IC for insulation.

[0003]

[0003] As IC sizes decrease, metal lines become closer together, and planar processes are typically used to fabricate interconnect structures, which involve aligning and connecting metallization on one layer with metallization on another layer.

[0004]

[0004] Reducing via resistance is important for improving the performance of electronic devices. Reducing via resistance is usually controlled by minimizing cladding and reducing the resistance of the via material. Therefore, a method for reducing via resistance is needed. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a method of forming an electronic device, the method including providing a substrate including an insulating layer on a first metallization layer, the insulating layer including an opening extending from a top surface of the insulating layer to the first metallization layer, the opening having at least one sidewall, a top, and a bottom, depositing a metal layer in the bottom of the opening, the metal layer extending to the first metallization layer, selectively depositing a barrier layer on at least one sidewall of the opening but not on the metal layer, and forming a second metallization layer in the top of the opening over the metal layer and the barrier layer.

[0006] A further embodiment of the present disclosure relates to a method of forming an electronic device, the method including providing a substrate including an insulating layer on a first metallization layer, the insulating layer including an opening extending from a top surface of the insulating layer to the first metallization layer, depositing a metal layer in the opening, the metal layer extending to the first metallization layer, selectively depositing a barrier layer on the top surface of the insulating layer but not the metal layer, forming a second metallization layer on the metal layer and the barrier layer, and etching the second metallization layer to form a trench.

[0007] Another embodiment of the present disclosure relates to a method of forming an electronic device, the method including providing a substrate including a first insulating layer on a metal layer, the metal layer being on a first metallization layer, depositing an etch stop layer on an upper surface of the first insulating layer and on an upper surface of the metal layer, depositing a second insulating layer on the upper surface of the etch stop layer, performing a single damascene process to form an opening extending from an upper surface of the second insulating layer to an upper surface of the metal layer, selectively depositing a barrier layer in the opening but not on the metal layer, and forming a second metallization layer on the metal layer and the barrier layer.

[0008]

[0008] Further embodiments of the present disclosure relate to a processing tool. In one or more embodiments, the processing tool includes a pre-clean chamber having a substrate support therein, a selective metal deposition chamber, a barrier metal deposition chamber, a metal deposition chamber, a PVD metal deposition chamber, a CVD metal deposition chamber, optionally a blocking layer deposition chamber with optional pre-clean functionality, optionally a liner metal deposition chamber, optionally a plasma chamber, and optionally an etch chamber, and a robot for accessing the pre-clean chamber, the selective deposition chamber, the optional blocking layer deposition chamber, the barrier metal deposition chamber, the PVD metal deposition chamber, the optional plasma chamber, and the optional etch chamber, the optional liner metal deposition chamber, the CVD metal deposition chamber, and the PVD metal deposition chamber. The present invention also includes a robot configured with a pre-clean chamber, a selective deposition chamber, an optional blocking layer deposition chamber, a barrier metal deposition chamber, a PVD metal deposition chamber, an optional plasma chamber, and an optional etch chamber, an optional liner metal deposition chamber, a CVD metal deposition chamber, and a PVD metal deposition chamber, and a controller connected to the robot, the controller having one or more configurations selected from cleaning the substrate, selectively forming a blocking layer, selectively depositing a liner, optionally forming a metal liner, forming a metallization layer, optionally etching the substrate, and optionally removing the blocking layer.

[0009]

[0009] In order that the above features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure, and the present disclosure may admit of other equally effective embodiments, and therefore the accompanying drawings should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]

[0010] [Figure 1]

[0010] A process flow diagram of a method according to one or more embodiments of the present disclosure is shown. [Figure 2A]

[0011] 2A-2F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 2B] 2A-2F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 2C] 2A-2F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 2D] 2A-2F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 2E] 2A-2F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 2F] 2A-2F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 3A]

[0012] 3A-3E illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 3B] 3A-3E illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 3C] 3A-3E illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 3D] 3A-3E illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 3E] 3A-3E illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 4]

[0013] 1 shows a process flow diagram of a method according to one or more embodiments of the present disclosure. [Figure 5A]

[0014] 5A-5F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 5B] 5A-5F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 5C] 5A-5F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 5D] 5A-5F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 5E] 5A-5F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 5F] 5A-5F illustrate cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 6]

[0015] 1 shows a process flow diagram of a method according to one or more embodiments of the present disclosure. [Figure 7A]

[0016] 7A-7E show cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 7B] 7A-7E show cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 7C] 7A-7E show cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 7D] 7A-7E show cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 7E] 7A-7E show cross-sectional views of an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 8]

[0017] 1 illustrates an exemplary cluster tool in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0018] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as being capable of other embodiments and of being practiced or carried out in various ways.

[0012]

[0019] The term "substrate" as used herein and in the appended claims refers to a surface or a portion of a surface on which a process acts. It will also be appreciated by those skilled in the art that when reference is made to a substrate, it may refer to only a portion of the substrate unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate on which one or more films or features have been deposited or formed.

[0013]

[0020] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may undergo pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam (e-beam) cure, and / or bake the substrate surface. In addition to performing film processing directly on the substrate surface itself, the present disclosure also includes that any of the disclosed film processing steps are performed on an underlayer formed on the substrate, as described in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0014]

[0021] As used in this specification and the appended claims, the term "selectively deposit on a first surface over a second surface" and the like means that a first amount or thickness is deposited on the first surface and a second amount or thickness is deposited on the second surface, the second amount or thickness being less than the first amount or thickness, or in some embodiments not deposited on the second surface.

[0015]

[0022] As used in this context, the term "over" does not refer to the physical orientation of one surface over the other, but rather the relationship of thermodynamic or kinetic properties of the chemical reaction of one surface relative to the other. For example, selectively depositing cobalt on a copper surface over a dielectric surface means that a cobalt film deposits on the copper surface and less or no cobalt film deposits on the dielectric surface, or that the formation of a cobalt film on the copper surface is thermodynamically or kinetically favored relative to the formation of a cobalt film on the dielectric surface.

[0016]

[0023] In some embodiments, "selectively" means that the target material is formed on the selected surface at a rate that is about 2, 3, 4, 5, 7, 10, 15, 20, 25, 30, 35, 40, 45, or 50 times or more faster than the rate of formation on the non-selected surfaces. In other words, the selectivity of the described process of the selected surface over the non-selected surfaces is 2:1, 3:1, 4:1, 5:1, 7:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, or 50:1 or more.

[0017]

[0024] According to one or more embodiments, the method utilizes an atomic layer deposition (ALD) process. In such embodiments, the substrate surface is continuously or substantially continuously exposed to the precursor (or reactive gas). As used throughout this specification, "substantially continuously" means that the majority of the period of exposure to the precursor does not overlap with exposure to a co-reagent. However, some overlap may exist. As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0018]

[0025] Metals can be grown by atomic layer deposition for many applications. One or more embodiments of the present disclosure advantageously provide a process for atomic layer deposition to form metal-containing films. As used herein and in the appended claims, the term "metal-containing film" refers to a film that includes metal atoms and has about 1 atomic % or more of metal, 2 atomic % or more of metal, 3 atomic % or more of metal, 4 atomic % or more of metal, 5 atomic % or more of metal, 10 atomic % or more of metal, 15 atomic % or more of metal, 20 atomic % or more of metal, 25 atomic % or more of metal, 30 atomic % or more of metal, 35 atomic % or more of metal, 40 atomic % or more of metal, 45 atomic % or more of metal, or 50 atomic % or more of metal. In some embodiments, the metal-containing film includes one or more of a metal, a metal nitride, a metal carbide, or a metal oxide. Those skilled in the art will recognize that the use of a molecular formula such as MO (where M is a metal) does not imply a particular stoichiometric relationship between elements, but simply the identity of the major components of the film. For example, MO refers to a film whose major composition includes metal and oxygen atoms. In some embodiments, the major composition of a particular film (ie, the sum of the atomic percentages of a particular atom) is greater than or equal to about 95%, 98%, 99%, or 99.5% of the film on an atomic basis.

[0019]

[0026] In some embodiments, the selective deposition includes a combination of a deposition process and an etching process. For example, a barrier layer may be selectively deposited on a dielectric material forming a thinner layer on the metal than on the metal. In some embodiments, to complete the selective deposition, a subsequent etching process, also referred to as a selective etching process, is used to remove the barrier layer from the conductive material at a faster rate than it is removed from the dielectric material.

[0020]

[0027] As used herein, the term "barrier layer" refers to a film that prevents diffusion of materials across it. As used herein, the term "liner" refers to a film that is typically used over a barrier layer that aids in the integrity and reliability of the underlying film over which it is deposited. In some embodiments, both a barrier layer and a liner are formed. In some other embodiments, a liner is not formed.

[0021]

[0028] One or more embodiments of the present disclosure are directed to a method for selectively forming a blocking layer on a metal layer (i.e., not on an insulating layer) over an insulating layer. One or more embodiments of the present disclosure provide a method for selectively forming a barrier layer on an insulating layer (i.e., not on a metal surface or layer) over a metal surface or layer. The method of one or more embodiments is an integrated process that is performed in a processing tool without breaking reduced pressure.

[0022]

[0029] The metal layer or metal material of one or more embodiments may be any suitable metal material. In some embodiments, the metal material of the present disclosure is a conductive material. Suitable metal materials include, but are not limited to, metals, conductive metal nitrides, conductive metal oxides, metal alloys, silicon, combinations thereof, and other conductive materials.

[0023]

[0030] In one or more embodiments, the metal or metallic material may comprise any suitable metal known to one of skill in the art. In some embodiments, the metal or metallic material is selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In some embodiments, the metal or metallic material consists essentially of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), or platinum (Pt). In some embodiments, the metal or metallic material consists essentially of copper, cobalt, ruthenium, tungsten, or molybdenum. In some embodiments, the metallic material includes or consists essentially of copper. As used in this specification and the appended claims, the term "consists essentially of" means that a material is about 95%, 98%, or 99% or more of the stated material on an atomic basis.

[0024]

[0031] As used herein and in the appended claims, the term "oxide" or the like means that a material contains a particular element(s). The term should not be interpreted to mean a particular ratio of elements. Thus, an "oxide" or the like may be composed of elements in stoichiometric or non-stoichiometric ratios.

[0025]

[0032] A method for forming an electronic device having self-aligned vias and processing tools for performing the method are described. Referring to FIG. 1, which is a process flow diagram, one or more embodiments of the present disclosure are directed to a method 100 for forming an electronic device. The method illustrated in FIG. 1 represents an integrated process. In some embodiments, the method 100 includes a pre-clean operation 102. The pre-clean operation can be any suitable pre-clean operation known to those skilled in the art. Suitable pre-clean operations include, but are not limited to, soaking, native oxide removal, and the like.

[0026]

[0033] 2A-2F show cross-sectional views of an exemplary device 200 during a processing method 100 according to one or more embodiments of the present disclosure. A substrate 202 having an insulating layer 208 thereon is provided. As used herein and in the appended claims, the term "provided" means that the device 200 having the substrate 202 is made available for processing (e.g., placed in a processing chamber). In some embodiments, an etch stop layer 206 is on the top surface of the substrate 202 between the substrate 202 and the insulating layer 208. In one or more embodiments, the etch stop layer 206 may comprise any suitable material known to one of ordinary skill in the art. In one or more embodiments, the etch stop layer 206 is selected from the group consisting of silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO x ), and aluminum nitride (AlN). In some embodiments, the etch stop layer 206 may be deposited using a technique selected from CVD, PVD, and ALD.

[0027]

[0034] In one or more embodiments, the insulating layer 208 has an opening 211 that extends from a top surface 209 of the insulating layer 208 to the first metallization layer 204. In one or more embodiments, the opening 211 has at least one sidewall 213, an upper portion 212, and a lower portion 210. In some embodiments, the lower portion 210 may be referred to as a via opening and the upper portion 212 may be referred to as a trench. As used herein, the term "aspect ratio" of an opening, trench, via, etc., refers to the ratio of the depth of the opening to the width of the opening. In one or more embodiments, the aspect ratio of each lower portion 210 or via opening is approximately in the range of about 1:1 to about 200:1. In some embodiments, the aspect ratio of the lower portion 210 or via opening is at least 2:1. In other embodiments, the aspect ratio of the lower portion 210 or via portion is at least 5:1, or at least 10:1.

[0028]

[0035] As used herein, the terms "insulating layer" or "insulating material" or the like refer to any material suitable for insulating adjacent devices and preventing electrical leakage. In one or more embodiments, the insulating layer 208 is an oxide layer (e.g., silicon dioxide) or any other electrically insulating layer as determined by the electronic device design. In one or more embodiments, the insulating layer 208 comprises an interlayer dielectric (ILD). In one or more embodiments, the insulating layer 208 is a low-k dielectric, including, but not limited to, materials such as silicon dioxide, silicon oxide, carbon-doped oxides ("CDO"), e.g., carbon-doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), or any combination thereof.

[0029]

[0036] In one or more embodiments, the insulating layer 208 comprises a dielectric material having a k value less than 5. In one or more embodiments, the insulating layer 208 comprises a dielectric material having a k value less than 3. In at least some embodiments, the insulating layer 208 comprises an oxide, a carbon doped oxide, a porous silicon dioxide, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphate glass, a fluorosilicate (SiOF) glass, an organosilicate glass (SiOCH), or any combination thereof, other electrically insulating materials as dictated by the electronic device design, or any combination thereof. In at least some embodiments, the insulating layer 208 may comprise a polyimide, an epoxy, a photosensitive material such as benzocyclobutene (BCB), and a WPR based material, or a spin-on-glass.

[0030]

[0037] In one or more embodiments, the insulating layer 208 is a low-k interlevel dielectric to insulate one metallization layer or metal line 204 from another metal line on the substrate 202. In one or more embodiments, the insulating layer 208 has a thickness in the approximate range of about 10 nanometers (nm) to about 2 microns (μm).

[0031]

[0038] In one embodiment, the insulating layer 208 is deposited using one of a number of deposition techniques, such as, but not limited to, chemical vapor deposition ("CVD"), physical vapor deposition ("PVD"), molecular beam epitaxy ("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), spin-on, or other insulating deposition techniques known to those skilled in the art of microelectronic device manufacturing.

[0032]

[0039] In some embodiments, an etch stop layer 206 is deposited on the top surface of the substrate 202 and the first metallization layer 204. In some embodiments not shown, a mask layer is formed on the insulating layer 208. The insulating layer 208 may be etched to form an opening 211. At least one via opening 210 has a bottom surface that includes an exposed portion of the etch stop layer 206. In one or more embodiments, the etch stop layer 206 exposed through the via opening 210 is selectively removed. The bottom surface of the via opening 210 thereby includes the first metallization layer 204.

[0033]

[0040] 1 and 2B, in operation 104, a metal layer 214 is formed or deposited in the opening 211. In some embodiments, the metal layer 214 is deposited in the lower portion 210 of the insulating layer (or in the via opening). In one or more embodiments, the metal layer 214 extends to the first metallization layer 204. In some embodiments, the metal layer 214 is not formed in the trench or upper portion 212 of the opening 211.

[0034]

[0041] In one or more embodiments, the first metallization layer 204 includes a metal selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In some specific embodiments, the first metallization layer 204 includes copper (Cu) or cobalt (Co).

[0035]

[0042] In one or more embodiments, the metal layer 214 comprises a metal selected from one or more of cobalt (Co), ruthenium (Ru), molybdenum (Mo), and tungsten (W). In some embodiments, the metal layer 214 comprises a different metal than the first metallization layer 204. In one or more embodiments, the metal layer 214 comprises tungsten (W).

[0036]

[0043] In operation 106, device 200 may be optionally pre-cleaned. The pre-cleaning operation may be any suitable pre-cleaning process. Suitable pre-cleaning operations include, but are not limited to, plasma cleaning, remote plasma cleaning, soaking, soaking in reducing vapors, native oxide removal, etc. For example, in one or more embodiments, device 200 is pre-cleaned to remove native oxide from the top surface of metal layer 214.

[0037]

[0044] 1 and 2C, in operation 108, a blocking layer 216 is selectively formed on the top surface of metal layer 214 but not on the exposed surface of insulating layer 208. Thus, in some embodiments, blocking layer 216 is selectively formed on the top surface of metal layer 214 but not in the trench or top portion 212 of opening 211.

[0038]

[0045] In one or more embodiments, the device 200 is exposed to a planar non-polar organic molecule to selectively form the blocking layer 216 on the metal layer 214 over the insulating layer 208. In one or more embodiments, the device 200 is exposed to a planar hydrocarbon to selectively form the blocking layer 216 on the metal layer 214 over the insulating layer 208. When used in this manner, the phrase "substrate is exposed" means that the entire substrate, including the individual materials and layers thereon, is exposed to the stated process or conditions. In some embodiments, the planar hydrocarbon comprises one or more of anthracene, benzene, naphthalene, toluene, ethylbenzene, phenanthrene, mesitylene, and the like. In some embodiments, the planar hydrocarbon consists essentially of anthracene. In some embodiments, the planar hydrocarbon consists essentially of naphthalene. In some embodiments, the planar hydrocarbon consists essentially of toluene. When used in this manner, the term "consisting essentially of" means that, on a molar basis, about 95%, 98%, 99%, or 99.5% or more of the planar hydrocarbons are the described compounds.

[0039]

[0046] Although blocking layer 216 is shown in the drawings as a series of parallel wavy lines, one of ordinary skill in the art will appreciate that this is used merely as a general depiction and does not imply any particular morphology, density, or structure of blocking layer 216. Formation of a thin film of blocking layer 216 may be considered a treatment process, while formation of a thicker film is generally considered a selective deposition.

[0040]

[0047] Without intending to be bound by theory, it is believed that the d orbitals of the metal layer 214 are aligned with the sp 2 It is believed that the planar hydrocarbon begins to share electrons with the orbitals. Thus, in some embodiments, the planar hydrocarbon comprises at least one compound having at least one double bond between two carbon atoms. In some embodiments, the planar hydrocarbon comprises at least one compound having at least one triple bond between two carbon atoms.

[0041]

[0048] Furthermore, without being bound by theory, it is believed that the planar hydrocarbon (blocking layer 216 ) inhibits one or more of the nucleation or growth rates of subsequent films on the metal layer 214 .

[0042]

[0049] In some embodiments, the substrate is immersed in a vapor of a planar hydrocarbon. In some embodiments, the process conditions for exposing the substrate to the planar hydrocarbon may be controlled.

[0043]

[0050] In some embodiments, the pressure of the processing chamber is controlled. The pressure of the processing chamber may be any suitable pressure for forming the blocking layer 216. In some embodiments, the pressure of the processing chamber is maintained at about 80 Torr or less, about 70 Torr or less, about 60 Torr or less, about 50 Torr or less, about 40 Torr or less, about 30 Torr or less, about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, or about 5 Torr or less. In some embodiments, the pressure of the processing chamber is maintained at about 10 Torr, about 20 Torr, about 30 Torr, about 40 Torr, or about 50 Torr.

[0044]

[0051] In some embodiments, the flow rate of the planar hydrocarbon into the processing chamber is controlled. The flow rate of the planar hydrocarbon may be any suitable flow rate for forming the blocking layer 216. In some embodiments, the flow rate of the planar hydrocarbon is in a range of about 50 sccm to about 100 sccm, or about 75 sccm to about 100 sccm. In some embodiments, the flow rate of the planar hydrocarbon is about 600 sccm or less, about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, about 150 sccm, about 100 sccm or less, about 75 sccm or less, or about 50 sccm or less. In some embodiments, the flow rate of the planar hydrocarbon is about 50 sccm or about 100 sccm.

[0045]

[0052] In some embodiments, the soaking duration during which the planar hydrocarbon is exposed to the substrate is controlled. The soaking duration may be any suitable duration for forming the blocking layer 216. In some embodiments, the soaking duration is about 1 second or more, about 10 seconds or more, about 20 seconds or more, about 30 seconds or more, about 45 seconds or more, about 60 seconds or more, about 80 seconds or more, about 120 seconds or more, about 150 seconds or more, or about 200 seconds or more. In some embodiments, the soaking duration is about 60 seconds. In some embodiments, the soaking duration is about 200 seconds.

[0046]

[0053] In some embodiments, the temperature of the substrate is controlled during exposure to the planar hydrocarbon. The temperature of the substrate may also be referred to as the operating temperature. In some embodiments, the temperature of the substrate is about 300° C. or less, about 275° C. or less, about 250° C. or less, about 225° C. or less, or about 200° C. or less.

[0047]

[0054] In some embodiments, the planar hydrocarbon compound is liquid at the operating temperature, hi some embodiments, the planar hydrocarbon compound has a vapor pressure of about 0.1 Torr or greater at the operating temperature.

[0048]

[0055] 1 and 2D, in some embodiments, the method 100 continues with operation 110 of depositing a conformal barrier layer 218 on the insulating layer 208 over the blocked metal layer 214. The barrier layer 218 may be deposited by any technique known to one of ordinary skill in the art. The deposition of the barrier layer 218 on the insulating layer 208 may be referred to as "reverse selective deposition" or "reversely selective deposition." One of ordinary skill in the art will appreciate that the term "selective deposition" typically applies to the formation of a film on a metallic surface, but not on a non-metallic surface. The reverse selective deposition process forms a film or barrier layer 218 on the insulating layer 208, which is a non-metallic surface.

[0049]

[0056] In one or more embodiments, the barrier layer 218 is deposited by atomic layer deposition. In some embodiments, the barrier layer 218 is deposited by sequential exposure of the substrate 202 to a metal precursor and a reactant. In some embodiments, the barrier layer 218 comprises a metal nitride. In some embodiments, the barrier layer 218 functions as a barrier film. In some embodiments, the barrier layer 218 comprises or consists essentially of titanium nitride (TiN). In some embodiments, the barrier layer 218 comprises or consists essentially of tantalum nitride (TaN). In some embodiments, the metal precursor comprises pentakis(dimethylamino)tantalum. In some embodiments, the reactant comprises ammonia. In some embodiments, the barrier layer 218 is formed without the use of a plasma.

[0050]

[0057] Referring to FIG. 1, in some embodiments, in operation 112, the method 100 continues by removing the blocking layer 216 from the metal layer 214. The blocking layer 216 may be removed by any suitable means, including but not limited to a plasma cleaning process. In some embodiments, the substrate 202 is exposed to a plasma to remove the blocking layer 216 from the metal layer 214. In some embodiments, the plasma comprises or consists essentially of one or more of argon (Ar), nitrogen (N2), or hydrogen (H2). As used herein, a plasma comprising nitrogen, hydrogen, oxygen, etc. refers to a plasma generated from the molecular forms of these nuclear species. For example, nitrogen plasma refers to a plasma ignited from nitrogen (N2) molecules. As used herein and in the appended claims, an element-containing plasma (e.g., nitrogen-containing plasma) refers to a compound that includes an element. For example, a nitrogen-containing plasma comprises or consists essentially of one or more compounds having nitrogen as an element (e.g., ammonia (NH3)). In some embodiments, the plasma consists essentially of argon. In some embodiments, the plasma comprises or consists essentially of a mixture of H2 and Ar.

[0051]

[0058] In some embodiments, the apparatus or process tool is configured to maintain the substrate under reduced pressure to prevent formation of an oxide layer after removal of the blocking layer, In some such embodiments, the process tool is configured to move the substrate from the plasma processing chamber to the deposition process chamber without exposing the substrate to atmospheric conditions.

[0052]

[0059] In one or more embodiments, the mixture of H2 and Ar has a ratio of H2 to Ar in the range of about 10:1 to about 1:10, in the range of about 10:1 to about 1:1, in the range of about 1:1 to about 1:10, in the range of about 5:1 to about 1:5, in the range of about 5:1 to about 1:1, in the range of about 1:1 to about 1:5, in the range of about 2:1 to about 1:2, in the range of about 2:1 to about 1:1, or in the range of about 1:1 to about 1:2. In some embodiments, the mixture of H2 / Ar is about 1:1.

[0053]

[0060] In one or more embodiments, the power of the plasma may vary depending on the composition, packing, and / or thickness of the blocking layer and the composition and / or thickness of the surrounding material. In some embodiments, the plasma power is in the range of about 20 W to about 500 W, about 20 W to about 400 W, about 20 W to about 250 W, about 50 W to about 500 W, about 100 W to about 500 W, about 100 W to about 450 W, about 100 W to about 500 W, or about 200 W to about 400 W. In some embodiments, the plasma power is about 50 W, about 200 W, or about 400 W.

[0054]

[0061] In one or more embodiments, the duration of the plasma exposure may vary depending on the composition, packing, and / or thickness of the blocking layer 216 and the composition and / or thickness of the surrounding materials. In some embodiments, the substrate is exposed to the plasma for a period ranging from about 2 seconds (s) to about 60 seconds (s), from about 3 seconds to about 30 seconds, or from about 5 seconds to about 10 seconds. In some embodiments, the substrate is exposed to the plasma for a period of about 3 seconds, about 5 seconds, about 10 seconds, or about 30 seconds.

[0055]

[0062] In some embodiments, such as those shown in FIGS. 2E and 2F, where the conductive via fill material 214 is grown in a bottom-up manner to fill the via portion 210 that constitutes the lower portion of the feature 211, a second conductive material 220 is deposited in the upper portion 212. For example, in operation 114 shown in FIG. 2E, the upper portion 212 of the feature 211 is x+1 It is filled with a conductive material 220 to form a conductive line.

[0056]

[0063] 1 and 2E-2F, in operation 114, after blocking layer 216 is removed from the top surface of metal layer 214, a second metallization layer 220 or second metal line is formed or deposited. In one or more embodiments, second metallization layer 220 may include any suitable material known to one of ordinary skill in the art. In some embodiments, second metallization layer 220 is selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In some embodiments, the second metallization layer 220 consists essentially of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), or platinum (Pt). In some embodiments, the second metallization layer 220 consists essentially of copper, cobalt, ruthenium, tungsten, or molybdenum. In some embodiments, the second metallization layer 220 includes copper or consists essentially of copper. As used herein and in the appended claims, the term "consists essentially of" means that a material is about 95%, 98%, or 99% or more of the stated material on an atomic basis. Referring to FIG. 2F, in one or more embodiments, the first metallization layer 204a and the second metallization layer 204b include the same metallic material.

[0057]

[0064] Figures 3A-3E show another embodiment of the present disclosure similar to that shown in both Figures 1-2F. The method is carried out with the same materials and overall process as previously described. The embodiment shown in Figures 3A-3E includes, as will be appreciated by those skilled in the art, M x and M x+1 1 illustrates a method for the formation of vias connecting metal lines.

[0058]

[0065] 3A-3E, the exemplary selective reverse deposition method used begins by providing a substrate 200 having an insulating layer 208 with at least one feature 211 formed therein. Those skilled in the art will recognize that the various films and layers described are similar to those of FIGS. 2A-2F, and that these are merely different structural forms of a similar method. The at least one feature 211 has a lower or via portion 210 and an upper or trench portion 212. In one embodiment shown, the sidewalls include and are formed by the insulating layer 208. The lower surface of the via opening 210 includes and is formed by the first metallization layer 204 or first metallization line. The at least one feature 211 may have one sidewall (e.g., a circular via), two sidewalls (e.g., a trench), or more sidewalls (e.g., a square or polygonal via).

[0059]

[0066] 3B, a metal layer 214 is formed or deposited in the lower portion 210 of at least one feature 211. The metal layer 214 has a height. In some embodiments, the height of the metal layer 214 is less than the depth of the lower portion 210 or the via opening. In one or more embodiments, the metal layer 214 has a height in a range from about 25% to about 90% of the depth of the lower portion or via portion 210.

[0060]

[0067] 3C, the substrate 200 is exposed to a planar hydrocarbon to selectively form a blocking layer 216 on the top surface of the metal layer 214 that forms the bottom of the feature 211 relative to the top of the insulating layer 208. In other words, the substrate 200 is treated with a planar hydrocarbon to passivate or block future deposition on the metal layer 214.

[0061]

[0068] 3D, selective reverse deposition of the barrier layer 218 is performed on the insulating layer 208 over the blocking layer 216. Again, one skilled in the art will appreciate that the term "selective reverse deposition" refers to a selective deposition process in which a film is formed on the insulating layer 208. In some embodiments, the barrier layer 218 is deposited by sequential exposure of the substrate 200 to metal precursors and reactants. In some embodiments, the barrier layer 218 includes a material that acts as a barrier layer. In some embodiments, depending on the thickness of the metal layer 214, the barrier layer 218 may be formed in both the upper portion 212 or trench portion and the lower portion 210 or via opening of the at least one opening 211. In other embodiments, the conformal barrier layer 218 is not formed in the lower portion 210 of the at least one opening.

[0062]

[0069] In one or more embodiments, the blocking layer 216 is optionally removed from the surface of the metal layer 214 underneath the feature 211. Without intending to be bound by theory, it is believed that the blocking layer 216 only slightly increases the resistance of the conductive fill material 220 compared to the increase in resistance typically seen with most barrier layers (e.g., barrier layer 218). Thus, removal of the blocking layer 216 is an optional process that may further reduce the resistance of the conductive fill material 220.

[0063]

[0070] Regardless of whether the blocking layer 216 is removed in operation 112, a conductive fill material 220 (or a second metallization layer or line) is deposited in the at least one feature 211 to form a low-k metal via. In some embodiments, the low-k metal via has a resistance of about 80% or less than a metal via formed without the blocking layer. In other words, the low-k metal via formed by the processes of the present disclosure including the blocking layer 216 provides a reduction in via resistance of about 20% or more.

[0064]

[0071] In some embodiments, such as that shown in FIG. 3E, where the conductive via fill material 214 is grown in a bottom-up manner to fill the via portion 210 that constitutes the lower portion of the feature 211, a second conductive material 220 is deposited within the upper portion 212. For example, as shown in FIG. 3E, the upper portion 212 of the feature 211 is x+1 It is filled with a conductive material 220 to form a conductive line.

[0065]

[0072] In some embodiments, a second metallization layer 220 is deposited to overfill the features 211 and form burdens on the surface of the substrate 200. The burdens are then removed by any suitable technique (e.g., etching, chemical mechanical planarization (CMP)).

[0066]

[0073] Figures 4 and 5A-5F show another embodiment of the present disclosure similar to that shown in both Figures 1-3E. The method 120 begins at operation 122, when a substrate is optionally pre-cleaned.

[0067]

[0074] 4 and 5A, a substrate 222 has an insulating layer 228 and a conductive material 224 or first metallization layer thereon. A feature 221 is formed in the insulating layer 228. The feature 221 has sidewalls 223a, 223b and a bottom portion 223c. The sidewalls 223a, 223b are formed by the insulating layer 228. In some embodiments, an etch stop layer 226 is disposed on the top surface of the substrate 222 and the first metallization layer 224. The bottom portion 223c of at least one feature 221 is formed by the top surface of the conductive material 224 (or first metallization layer). In some embodiments, the conductive material 224 of the first metallization line is M x Also called a line.

[0068]

[0075] 4 and 5B, in operation 124, via metal 230 is formed or deposited in at least one opening 221 and in contact with first metallization layer 224. In operation 126, the substrate may optionally be pre-cleaned. For example, in some embodiments, via metal 230 may be cleaned to remove any native oxide that may have formed.

[0069]

[0076] As shown in FIG. 5C, in operation 128, the substrate is exposed to a planar hydrocarbon to selectively form a blocking layer 232 on the top surface of the via metal 230 relative to the top surface of the insulating layer 228.

[0070]

[0077] 4 and 5D, in operation 132, a barrier layer 234 is selectively deposited on the insulating layer 228 over the blocking layer 232. As shown in FIG. 5D, the barrier layer 234 is selectively deposited on the top surface of the insulating layer 228. The barrier layer 234 is deposited on the exposed insulating layer 228 but not on the via metal 230. The barrier layer 234 may be deposited by any suitable technique known to those of skill in the art. In some embodiments, the barrier layer 234 is deposited by sequentially exposing the substrate to a metal precursor and a reactant.

[0071]

[0078] 4 and 5E , whether or not the blocking layer 232 is removed in operation 132, the method 120 continues in operation 134 with selective deposition of a second metallization layer 236. A conductive via fill material 236 is selectively deposited on the barrier layer 234.

[0072]

[0079] The second metallization layer 236 may be any suitable material known to one of ordinary skill in the art. In one illustrated embodiment, the first metallization layer 224, the via metal 230, and the second metallization layer 236 are different materials. In other embodiments, the first metallization layer 224 and the second metallization layer 236 may be the same material. For example, in some embodiments, the first metallization layer 224 and the second metallization layer 236 include copper and the via metal 230 includes cobalt.

[0073]

[0080] The second metallization layer 236 may be deposited by any suitable technique known to one of skill in the art. In some embodiments, the second metallization layer 236 is deposited by one or more of a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process.

[0074]

[0081] Referring to FIG. 5F, the substrate 220 is etched (ie, subtractively etched) to form an opening 238 (or trench) in the second metallization layer 236 .

[0075]

[0082] Figures 6 and 7A-7E show another embodiment of the present disclosure similar to that shown in Figures 1-5F. The method is carried out with the same materials and overall process as previously described. The embodiment shown in Figures 7A-7E includes, as will be appreciated by those skilled in the art, M x and M x+1 7A through 7E depict a method for the formation of vias connecting metal lines. The method illustrated in Figures 7A through 7E is an integrated process that is carried out in a processing tool without breaking reduced pressure.

[0076]

[0083] 6 and 7A-7E, an exemplary selective reverse deposition method 140 begins by providing a substrate 250 having an insulating layer 252, a first metallization layer 254, and a first feature (not shown) thereon. In operation 142, the substrate is optionally pre-cleaned. In operation 144, a via / contact 256 is selectively deposited or formed on the top surface of the first metallization layer 254 beneath the first feature. Those skilled in the art will recognize that the various films and layers described are similar to those of FIGS. 2A-2F, and that these are merely different structural forms of a similar method.

[0077]

[0084] An etch stop layer 258 is deposited on the top surface of the insulating layer 252 and the via / contact 256. The etch stop layer 258 may include any suitable material known to one of skill in the art. In one or more embodiments, the etch stop layer 258 includes one or more of aluminum oxide (AlO), silicon carbonitride (SiCN), and silicon nitride (SiN). A second insulating layer 260 is deposited on the etch stop layer 258. With reference to FIGS. 6 and 7B, a single damascene process is performed to form a trench 262 in the insulating layer 260. The single damascene process opens the etch stop layer 258 and exposes the top surface of the via / contact 256. The top surface of the via / contact 256 thereby becomes the bottom surface of the trench 262. In some embodiments, the single damascene process to open the etch stop layer 258 includes a plasma / radical-based etch. This is followed by a pre-clean. The pre-clean operation may be any suitable pre-clean operation known to one of skill in the art. Suitable pre-cleaning operations include, but are not limited to, soaking, native oxide removal, and the like. In one or more embodiments, a single damascene process is performed in an integrated system without breaking reduced pressure. A damascene trench 262 has sidewalls 263a, 263b, and a bottom 263c. In one illustrated embodiment, the sidewalls include and are formed by an insulating layer 260. A bottom surface of the damascene trench 262 includes and is formed by the via / contact 256 and a portion of the insulating layer 252. The damascene trench 262 may have one sidewall (e.g., a circular via), two sidewalls (e.g., a trench), or more sidewalls (e.g., a square or polygonal via).

[0078]

[0085] 7C, the substrate 250 is exposed to a planar hydrocarbon to selectively form a blocking layer 264 on the top surface of the via / contact 256 relative to the insulating layer 260. In other words, the substrate 250 is treated with a planar hydrocarbon to passivate or block future deposition on the via / contact 256.

[0079]

[0086] 7D, selective reverse deposition of a barrier layer 266 is performed on the insulating layer 260 rather than on the blocking layer 264. Again, one of ordinary skill in the art will appreciate that the term "selective reverse deposition" refers to a selective deposition process in which a film is formed on the insulating layer 264 rather than on the via / contact 256. In some embodiments, the barrier layer 266 is deposited by sequential exposure of the substrate 250 to metal precursors and reactants. In some embodiments, the barrier layer 266 includes a material that acts as a barrier layer.

[0080]

[0087] In one or more embodiments, the blocking layer 264 is optionally removed from the surfaces of the via / contact 256. Without intending to be bound by theory, it is believed that the blocking layer 264 only slightly increases the resistance of the conductive fill material 268 compared to the increase in resistance typically seen with most barrier layers (e.g., barrier layer 266). Thus, removal of the blocking layer 264 is an optional process that may further reduce the resistance of the conductive fill material 268.

[0081]

[0088] Regardless of whether blocking layer 266 is removed in operation 152, a conductive fill material 268 (or a second metallization layer or line) is deposited in at least one feature 262 to form a low-k metal via. In some embodiments, the low-k metal via has a resistance of about 80% or less than a metal via formed without the blocking layer. In other words, the low-k metal via formed by the processes of the present disclosure including blocking layer 264 provides a reduction in via resistance of about 20% or more.

[0082]

[0089] In some embodiments, a second metallization layer 268 is deposited to overfill the features 262 and form overburdens on the surface of the substrate 250. The overburdens are then removed by any suitable technique (e.g., etching, chemical mechanical planarization (CMP)).

[0083]

[0090] Further embodiments of the present disclosure are directed to a processing tool 900 for forming the described devices and methods, as shown in FIG. 8. A variety of multi-processing platforms, including Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®, as well as other processing systems, may be utilized. In one or more embodiments, the cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are disposed within the central transfer station 921, 931 and configured to move the robot blade and wafer to each of the multiple sides.

[0084]

[0091] The cluster tool 900 comprises multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chambers may be any suitable chamber, including, but not limited to, selective metal deposition chambers, barrier metal deposition chambers, metal deposition chambers, PVD metal deposition chambers, CVD metal deposition chambers, blocking layer deposition chambers, liner metal deposition chambers, plasma chambers, pre-clean chambers, etch chambers, transfer space(s), wafer orientation / degassing chambers, cryogenic cooling chambers, and the like. The particular arrangement of process chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0085]

[0092] In one or more embodiments, the cluster tool 900 includes a blocking layer deposition chamber for exposing the substrate to a planar hydrocarbon to form a blocking layer, In one or more embodiments, the cluster tool 900 includes a pre-clean chamber connected to a central transfer station.

[0086]

[0093] 8, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front side 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one of ordinary skill in the art will appreciate that this is merely representative of one possible configuration.

[0087]

[0094] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary depending on, for example, the substrate being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with multiple wafers disposed within the cassette.

[0088]

[0095] A robot 952 resides in the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can include multiple robots 952. For example, the factory interface 950 can include a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0089]

[0096] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally positioned with respect to the load lock chambers 960, 962, the processing chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 in some embodiments is a multi-arm robot capable of independently moving multiple wafers at a time. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are supported on a wafer transport blade located at the distal end of the first robotic mechanism.

[0090]

[0097] After processing the wafer in the first section 920, the wafer may move through a pass-through chamber to the second section 930. For example, the chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryo-cool the wafer before processing in the second section 930 or to allow wafer cooling or post-processing before returning to the first section 920.

[0091]

[0098] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0092]

[0099] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the chamber operation so that the processes are performed.

[0093]

[0100] In one or more embodiments, the processing tool 900 includes a central transfer station 921, 931 including at least one robot 925, 935 configured to move the wafer, one or more of a selective via fill station, a selective reverse deposition station, a blocking layer formation station, a CVD station, a PVD station connected to the central transfer station, an optional pre-clean station connected to the central transfer station, and at least one controller connected to one or more of the central transfer station, the selective via fill station, the selective reverse deposition station, the blocking layer formation station, the CVD station, the PVD station, or the optional pre-clean station. In one or more embodiments, the at least one controller has at least one configuration selected from a configuration for moving the wafer between the stations using a robot, a configuration for selectively filling the vias, a configuration for exposing the substrate to a planar hydrocarbon and forming a blocking layer, a configuration for selective reverse deposition of a barrier layer, a configuration for depositing a metal, and a configuration for pre-cleaning the wafer.

[0094]

[0101] In one or more embodiments, the processing tool includes a pre-clean chamber having a substrate support therein, a selective metal deposition chamber, a barrier metal deposition chamber, a metal deposition chamber, a PVD metal deposition chamber, a CVD metal deposition chamber, optionally a blocking layer deposition chamber with optional pre-clean functionality, optionally a liner metal deposition chamber, optionally a plasma chamber, and optionally an etch chamber, and a robot for accessing the pre-clean chamber, the selective deposition chamber, the optional blocking layer deposition chamber, the barrier metal deposition chamber, the PVD metal deposition chamber, the optional plasma chamber, and the optional etch chamber, the optional liner metal deposition chamber, the CVD metal deposition chamber, and the PVD metal deposition chamber. The present invention also includes a robot configured with a pre-clean chamber, a selective deposition chamber, an optional blocking layer deposition chamber, a barrier metal deposition chamber, a PVD metal deposition chamber, an optional plasma chamber, and an optional etch chamber, an optional liner metal deposition chamber, a CVD metal deposition chamber, and a PVD metal deposition chamber, and a controller connected to the robot, the controller having one or more configurations selected from cleaning the substrate, selectively forming a blocking layer, selectively depositing a liner, optionally forming a metal liner, forming a metallization layer, optionally etching the substrate, and optionally removing the blocking layer.

[0095]

[0102] Spatially relative terms, such as "below," "lower," "lower side," "up," "above," "upper," and the like, may be used herein to facilitate describing the relationship of one element or feature to another element(s) or feature(s) as depicted in the drawings. It should be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if a device in the drawings were turned over, an element described as "below" or "below" the other element or feature would be oriented "above" the other element or feature. Thus, the exemplary term "below" may include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or to other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0096]

[0103] In the context of describing the materials and methods described herein (particularly in the context of the claims below), the use of the terms "a" and "an" as well as "the" and similar referents are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods and does not limit the scope, unless otherwise claimed. No language in the specification should be construed as indicating any element not claimed as essential to the practice of the disclosed materials and methods.

[0097]

[0104] References throughout this specification to "one embodiment," "certain embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0098]

[0105] Although the disclosure herein has been described with reference to particular embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations that are within the scope of the disclosure.

Claims

1. 1. A method of forming an electronic device, comprising: selectively depositing a metal layer in a lower portion of an opening on a substrate, the substrate including an insulating layer over a first metallization layer, the insulating layer including the opening extending from a top surface of the insulating layer to the first metallization layer, the opening having at least one sidewall, a top, and the bottom, the metal layer extending to the first metallization layer; selectively depositing a barrier layer on the at least one sidewall of the opening rather than on the metal layer; and forming a second metallization layer over the metal layer and the barrier layer within the upper portion of the opening.

2. The method of claim 1 , wherein selectively depositing the barrier layer comprises forming a blocking layer on the metal layer but not on the insulating layer.

3. The method of claim 2 , wherein forming the blocking layer comprises exposing the metal layer to a planar hydrocarbon.

4. 4. The method of claim 3, wherein the planar hydrocarbons include one or more of anthracene, benzene, naphthalene, toluene, ethylbenzene, phenanthrene, mesitylene, and the like.

5. The method of claim 2 , further comprising exposing the substrate to a plasma to remove the blocking layer.

6. 10. The method of claim 1, wherein the first metallization layer, the second metallization layer, and the metal layer independently comprise a metal selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt).

7. The method of claim 6 , wherein the first metallization layer and the second metallization layer comprise the same metal.

8. The method of claim 1 , wherein the openings include trenches and vias.

9. The method of claim 8 , wherein the barrier layer is not formed in the via.

10. The method of claim 8 , wherein the barrier layer is formed in the via.

11. The method of claim 1 , wherein the insulating layer comprises one or more of silicon dioxide, silicon oxide, carbon doped oxide, silicon carbide, and silicon nitride (SiN).

12. The method of claim 1 , wherein the method is performed in a cluster tool without breaking reduced pressure.

13. The method of claim 1 , further comprising pre-cleaning the substrate prior to depositing the metal layer.

14. 1. A method of forming an electronic device, comprising: selectively depositing a metal layer in an opening on a substrate, the substrate including an insulating layer on a first metallization layer, the insulating layer including the opening extending from a top surface of the insulating layer to the first metallization layer, the metal layer extending to the first metallization layer; selectively depositing a barrier layer on the top surface of the insulating layer but not on the metal layer; forming a second metallization layer over the metal layer and the barrier layer; and etching the second metallization layer to form a trench.

15. 15. The method of claim 14, wherein selectively depositing the barrier layer comprises forming a blocking layer on the metal layer but not on the insulating layer.

16. The method of claim 15 , wherein forming the blocking layer comprises exposing the metal layer to a planar hydrocarbon.

17. 17. The method of claim 16, wherein the planar hydrocarbons include one or more of anthracene, benzene, naphthalene, toluene, ethylbenzene, phenanthrene, mesitylene, and the like.

18. 15. The method of claim 14, wherein the metal layer, the first metallization layer, and the second metallization layer independently comprise a metal selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt).

19. 1. A method of forming an electronic device, comprising: selectively depositing a metal layer in at least one feature on a substrate, the substrate including a first insulating layer, a first metallization layer, and the at least one feature thereon; depositing an etch stop layer on an upper surface of the first insulating layer and on an upper surface of the metal layer; depositing a second insulating layer on top of the etch stop layer; performing a single damascene process to form an opening extending from an upper surface of the second insulating layer to an upper surface of the metal layer; selectively depositing a barrier layer in the opening but not on the metal layer; and forming a second metallization layer over the metal layer and the barrier layer.

20. 20. The method of claim 19, wherein selectively depositing the barrier layer comprises forming a blocking layer on the metal layer but not on the first insulating layer but not on the second insulating layer.

21. 21. The method of claim 20, wherein forming the blocking layer comprises exposing the metal layer to a planar hydrocarbon.

22. 22. The method of claim 21, wherein the planar hydrocarbons include one or more of anthracene, benzene, naphthalene, toluene, ethylbenzene, phenanthrene, mesitylene, and the like.

23. 20. The method of claim 19, wherein the metal layer, the first metallization layer, and the second metallization layer independently comprise a metal selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt).

24. 1. A processing tool, comprising: a pre-clean chamber having a substrate support therein; A selective metal deposition chamber; a barrier metal deposition chamber; Metal deposition chamber, PVD metal deposition chambers, CVD metal deposition chamber, Optionally, a blocking layer deposition chamber with optional pre-cleaning capabilities; Optionally, a liner metal deposition chamber; Optionally, a plasma chamber; Optionally, an etching chamber; a robot configured to access the pre-clean chamber, the selective deposition chamber, the optional blocking layer deposition chamber, the barrier metal deposition chamber, the PVD metal deposition chamber, the optional plasma chamber, the optional etch chamber, the optional liner metal deposition chamber, the CVD metal deposition chamber, and the PVD metal deposition chamber; and 11. A processing tool comprising: a controller connected to the pre-clean chamber, the selective deposition chamber, the optional blocking layer deposition chamber, the barrier metal deposition chamber, the PVD metal deposition chamber, the optional plasma chamber, the optional etch chamber, the optional liner metal deposition chamber, the CVD metal deposition chamber, the PVD metal deposition chamber, and the robot, the controller having one or more configurations selected from cleaning a substrate, selectively forming a blocking layer, selectively depositing a liner, optionally forming a metal liner, forming a metallization layer, optionally etching a substrate, and optionally removing a blocking layer.

Images