Display with thin film transistor and method for manufacturing the same

Abstract

SOLUTION: A display 110 includes: a substrate 120 including a display area DA and a non-display area NDA surrounding the display area; a first semiconductor layer 124 containing a polycrystalline semiconductor material and a second semiconductor layer 126 containing an oxide semiconductor material, which are disposed in a non-display area on the substrate; a first gate insulating layer 128 placed on the first and second semiconductor layers; a first gate electrode 130 and a second gate electrode 132, corresponding to the first and second semiconductor layers, respectively, and located on the first gate insulating layer; a first interlayer dielectric layer 136 placed over the first and second gate electrodes; a first source electrode 146 disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer; and a second source electrode 152 and a second drain electrode 154 disposed on the first drain electrode 148 and the first interlayer insulating layer and connected to both ends of the second semiconductor layer respectively.EFFECT: By forming thin film transistors of polycrystalline semiconductor materials and thin-film transistors of oxide semiconductor materials on a same substrate, power consumption and manufacturing costs can be reduced.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a display device, and in particular to an organic light-emitting diode including a polycrystalline thin film transistor and an oxide thin film transistor, and a method for manufacturing the same. [Background technology]

[0002] In recent years, with the advent of the information society, interest in information displays that process and display huge amounts of information has increased. In response to the growing demand for portable information media, various lightweight and thin flat display devices have been developed and are attracting attention.

[0003] Among such flat display devices, organic light emitting diode display devices are self-emitting elements that do not require a separate light source such as a backlight, and therefore have advantages in terms of viewing angle, contrast ratio, power consumption, etc., and are therefore widely adopted in various fields.

[0004] The driving section and the pixels of the organic light emitting diode display device each include a thin film transistor. The thin film transistor of the driving section preferably has a relatively high mobility, and the thin film transistor of the pixel preferably has a relatively low off-current.

[0005] However, when the thin film transistors of the driving section and the thin film transistors of the pixels are formed from the same semiconductor material through the same process, it is difficult to achieve high mobility in the thin film transistors of the driving section and low off-current in the thin film transistors of the pixels.

[0006] In addition, since it is difficult to adopt a driving method such as a variable refresh rate (VRR), there is a problem in that reduction in power consumption is limited. Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been proposed to solve such problems, and aims to provide a display device and a manufacturing method thereof that reduce power consumption by forming a thin film transistor made of a polycrystalline semiconductor material and a thin film transistor made of an oxide semiconductor material on the same substrate.

[0008] Another object of the present invention is to provide a display device and a manufacturing method thereof, in which a manufacturing process is simplified and manufacturing costs are reduced by forming a thin film transistor made of a polycrystalline semiconductor material and a thin film transistor made of an oxide semiconductor material using a gate insulating layer and a gate electrode of the same layer. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, the present invention provides a display device including a substrate including a display region and a non-display region surrounding the display region, a first semiconductor layer disposed in the non-display region on the substrate and including a polycrystalline semiconductor material, a second semiconductor layer disposed in the display region on the substrate and including an oxide semiconductor material, a first gate insulating layer disposed on the first semiconductor layer and on the second semiconductor layer, first gate electrodes and second gate electrodes disposed on the first gate insulating layer corresponding to the first semiconductor layer and the second semiconductor layer, respectively, a first interlayer insulating layer disposed on the first gate electrode and on the second gate electrode, a first source electrode and a first drain electrode disposed on the first interlayer insulating layer and connected to both ends of the first semiconductor layer, respectively, and a second source electrode and a second drain electrode disposed on the first interlayer insulating layer and connected to both ends of the second semiconductor layer, respectively.

[0010] The first semiconductor layer and the second semiconductor layer may be in the same layer.

[0011] The display device may further include a first buffer layer disposed between the substrate and the first semiconductor layer and the second semiconductor layer, a second buffer layer, a second interlayer insulating layer, a first planarization layer, and a second planarization layer sequentially disposed on the first interlayer insulating layer, a storage capacitor disposed between the first gate insulating layer and the second buffer layer, a light emitting diode disposed on the second planarization layer, and a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed on the light emitting diode.

[0012] The display device further includes a first gate extension electrode and a second gate extension electrode connected to the first gate electrode and the second gate electrode, respectively, and a capacitor extension electrode connected to the storage capacitor, and the first gate extension electrode, the first source electrode, the first drain electrode, the second gate extension electrode, the second source electrode, and the second drain electrode may be formed in a same layer and made of a same material on the second interlayer insulating layer.

[0013] The display device may further include a second gate insulating layer disposed on an entire surface of the first semiconductor layer, and the second semiconductor layer may be disposed on the second gate insulating layer.

[0014] The display device may further include a second gate insulating layer disposed on the first semiconductor layer and below the second semiconductor layer.

[0015] In addition, the first semiconductor layer and the second gate insulating layer on the first semiconductor layer may have the same shape, and the second semiconductor layer and the second gate insulating layer below the second semiconductor layer may have the same shape.

[0016] The display device further includes a first gate extension electrode arranged on the first interlayer insulating layer and connected to a first gate electrode, and a second gate extension electrode arranged on the first interlayer insulating layer and connected to a second gate electrode, and the first gate extension electrode, the first source electrode, the first drain electrode, the second gate extension electrode, the second source electrode, and the second drain electrode can be formed in the same layer and from the same material on the first interlayer insulating layer.

[0017] The display device may further include a first buffer layer disposed between the substrate and the first semiconductor layer and the second semiconductor layer, a second buffer layer, a first planarization layer, and a second planarization layer sequentially disposed on the first interlayer insulating layer, a storage capacitor disposed between the first gate insulating layer and the second buffer layer, a light emitting diode disposed on the second planarization layer, and a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed on the light emitting diode.

[0018] In addition, the display device further includes a first source extension electrode, a first drain extension electrode, a second source extension electrode, and a second drain extension electrode connected to the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, respectively, and the first source extension electrode, the first drain extension electrode, the second source extension electrode, and the second drain extension electrode may be formed in the same layer and from the same material on the first planarization layer.

[0019] Additionally, the second source electrode may be connected to the storage capacitor. Effect of the Invention

[0020] The present invention has the advantage of reducing power consumption by forming a thin film transistor made of a polycrystalline semiconductor material and a thin film transistor made of an oxide semiconductor material on the same substrate.

[0021] In addition, the present invention provides a method for forming a thin film transistor made of a polycrystalline semiconductor material and a thin film transistor made of an oxide semiconductor material by using a gate insulating layer and a gate electrode of the same layer, thereby simplifying the manufacturing process and reducing manufacturing costs. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram showing a display device according to a first embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view showing a non-display area and a display area in a display device according to a first embodiment of the present invention. [Figure 3A] 2A to 2C are cross-sectional views illustrating a method for manufacturing the display device according to the first embodiment of the present invention. [Figure 3B] 2A to 2C are cross-sectional views illustrating a method for manufacturing the display device according to the first embodiment of the present invention. [Figure 3C] 2A to 2C are cross-sectional views illustrating a method for manufacturing the display device according to the first embodiment of the present invention. [Figure 3D] 2A to 2C are cross-sectional views illustrating a method for manufacturing the display device according to the first embodiment of the present invention. [Figure 3E] 2A to 2C are cross-sectional views illustrating a method for manufacturing the display device according to the first embodiment of the present invention. [Figure 3F] 2A to 2C are cross-sectional views illustrating a method for manufacturing the display device according to the first embodiment of the present invention. [Figure 4] FIG. 11 is a cross-sectional view showing a non-display area and a display area in a display device according to a second embodiment of the present invention. [Figure 5A] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5B] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5C] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5D] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5E]10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 5F] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention. [Figure 6] FIG. 11 is a cross-sectional view showing a non-display area and a display area in a display device according to a third embodiment of the present invention. [Figure 7A] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7B] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7C] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7D] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7E] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 7F] 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention. [Figure 8] FIG. 11 is a cross-sectional view showing a non-display area and a display area in a display device according to a fourth embodiment of the present invention. [Figure 9A] 13A to 13C are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9B] 13A to 13C are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9C] 13A to 13C are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9D] 13A to 13C are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. [Figure 9E] 13A to 13C are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, a display device including a thin film transistor according to the present invention will be described with reference to the drawings.

[0024] FIG. 1 is a diagram showing a display device according to a first embodiment of the present invention. The display device may be an organic light emitting diode (OLED) display device.

[0025] As shown in FIG. 1, a display device 110 according to a first embodiment of the present invention may include a timing controller TC, a data driver DD, a first gate driver GD1, a second gate driver GD2, and a display panel DP.

[0026] The timing controller TC can generate video data, data control signals, and gate control signals using a number of timing signals, such as a video signal, a data enable signal, a horizontal sync signal, a vertical sync signal, and a clock, transmitted from an external system (not shown), such as a graphic card or a television system. In addition, the timing controller TC transmits the generated video data and data control signals to the data driver DD, and transmits the generated gate control signals to the first gate driver GD1 and the second gate driver GD2.

[0027] The data driver DD generates a data signal (data voltage) using the data control signal and image data transmitted from the timing controller TC, and applies the generated data signal to the data lines DL of the display panel DP.

[0028] The first gate driver GD1 and the second gate driver GD2 generate gate signals (gate voltages) using gate control signals transmitted from the timing controller TC, and apply the generated gate signals to the gate lines GL of the display panel DP.

[0029] For example, the gate signal may include a scanning signal, a sensing signal, and a light emitting signal.

[0030] The first gate driver GD1 and the second gate driver GD2 each include a shift register including a plurality of stages connected in a cascade manner, and each stage in the shift register includes a plurality of circuit thin film transistors (T1 in FIG. 2), at least one of which may include a semiconductor layer (active layer) made of a polycrystalline semiconductor material such as polycrystalline silicon.

[0031] Here, the first gate driver GD1 and the second gate driver GD2 may be of a gate driver in panel (GIP) type that is formed together on a substrate of a display panel DP on which the gate lines GL, data lines DL, and pixels P are formed, and is disposed in a non-display area NDA.

[0032] In the embodiment of FIG. 1, the first gate driver GD1 and the second gate driver GD2 are arranged on both sides of the display panel DP, but in another embodiment, one gate driver may be arranged on one side of the display panel DP.

[0033] The display panel DP includes a display area DA at the center and a non-display area NDA surrounding the display area DA, and displays images using gate signals and data signals. To display images, the display panel DP includes a plurality of pixels P, a plurality of gate lines GL, and a plurality of data lines DL, which are arranged in the display area DA.

[0034] Each of the pixels P includes a first subpixel SP1 to a fourth subpixel SP4, and the gate line GL and the data line DL cross each other to define the first subpixel SP1 to the fourth subpixel SP4. The first subpixel SP1 to the fourth subpixel SP4 are connected to the gate line GL and the data line DL, respectively. For example, the first subpixel SP1 to the fourth subpixel SP4 may correspond to red, green, blue, and white, respectively.

[0035] The first to fourth subpixels SP1 to SP4 each include a plurality of pixel thin film transistors (T2 in FIG. 2) such as a switching thin film transistor, a driving thin film transistor, and a reference thin film transistor, a storage capacitor (Cs in FIG. 2), and a light emitting diode (De in FIG. 2). At least one of the pixel thin film transistors T2 may include a semiconductor layer (active layer) made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO).

[0036] The cross-sectional structure of the display device 110 will be described with reference to the drawings.

[0037] 2 is a cross-sectional view showing a non-display area and a display area in the display device according to the first embodiment of the present invention, and will be described with reference to FIG.

[0038] As shown in FIG. 2, a first thin film transistor T1, which is a circuit thin film transistor, is arranged in the first gate driver GD1 and the second gate driver GD2 of the non-display area NDA in the display device 110 of the first embodiment of the present invention, and a second thin film transistor T2, which is a pixel thin film transistor, a storage capacitor Cs, and a light-emitting diode De are arranged in each of the sub-pixels SP1 to SP4 of the display area DA.

[0039] Specifically, a first buffer layer 122 is disposed on the entire surface of the substrate 120, and a first semiconductor layer 124 and a second semiconductor layer 126 are disposed on the first buffer layer 122 in the first gate driver GD1 and the second gate driver GD2 of the non-display area NDA, and in each of the sub-pixels SP1 to SP4 of the display area DA, respectively.

[0040] For example, the first buffer layer 122 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0041] The first semiconductor layer 124 includes an undoped channel region 124a, and a source region 124b and a drain region 124c on either side of the channel region 124a that are doped with impurities. The second semiconductor layer 126 includes an undoped channel region 126a, and a source region 126b and a drain region 126c on either side of the channel region 126a that are doped with impurities (or made conductive).

[0042] For example, the first semiconductor layer 124 may be made of a polycrystalline semiconductor material such as polycrystalline silicon, and the second semiconductor layer 126 may be made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO).

[0043] A first gate insulating layer 128 is disposed on the entire surface of the first semiconductor layer 124 and the second semiconductor layer 126, a first gate electrode 130 and a second gate electrode 132 are disposed on the first gate insulating layer 128 corresponding to the first semiconductor layer 124 and the second semiconductor layer 126, respectively, and a first capacitor electrode 134 is disposed in each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 128.

[0044] For example, the first gate insulating layer 128 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0045] The first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134 may be formed in the same layer and from the same material.

[0046] For example, the first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0047] The first gate electrode 130, the first gate insulating layer 128, and the first semiconductor layer 124 constitute a first thin film transistor T1, and the second gate electrode 132, the first gate insulating layer 128, and the second semiconductor layer 126 constitute a second thin film transistor T2.

[0048] A first interlayer insulating layer 136 is disposed over the entire surfaces of the first gate electrode 130, the second gate electrode 132, and the first capacitor electrode 134, and a second capacitor electrode 138 is disposed on the first interlayer insulating layer 136 corresponding to the first capacitor electrode 134.

[0049] For example, the first interlayer insulating layer 136 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0050] For example, the second capacitor electrode 138 may be a single layer or multiple layers of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0051] The first capacitor electrode 134, the first interlayer insulating layer 136, and the second capacitor electrode 138 constitute a storage capacitor Cs.

[0052] A second buffer layer 140 may be disposed on the entire surface of the second capacitor electrode 138 , and a second interlayer insulating layer 142 may be disposed on the entire surface of the second buffer layer 140 .

[0053] For example, the second buffer layer 140 may be made of silicon oxide (SiO2), silicon nitride (SiN x The second interlayer insulating layer 142 may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0054] A first gate extension electrode 144, a first source electrode 146, and a first drain electrode 148 are disposed on the second interlayer insulating layer 142 corresponding to the first thin film transistor T1, and a second gate extension electrode 150, a second source electrode 152, and a second drain electrode 154 are disposed on the second interlayer insulating layer 142 corresponding to the second thin film transistor T2. In addition, a capacitor extension electrode 156 is disposed on the second interlayer insulating layer 142 corresponding to the storage capacitor Cs, and a first planarization layer 158 is disposed on the entire surface of the first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156.

[0055] The first gate extension electrode 144 is connected to the first gate electrode 130 via a contact hole in the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136, the first source electrode 146 is connected to the source region 124b of the first semiconductor layer 124 via a contact hole in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128, and the first drain electrode 148 is connected to the drain region 124c of the first semiconductor layer 124 via a contact hole in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128.

[0056] The second gate extension electrode 150 is connected to the second gate electrode 132 via contact holes in the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136, the second source electrode 152 is connected to the source region 126b of the second semiconductor layer 126 via contact holes in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128, and the second drain electrode 154 is connected to the drain region 126c of the second semiconductor layer 126 via contact holes in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128.

[0057] The capacitor extension electrode 156 is connected to the second capacitor electrode 138 via contact holes in the second interlayer insulating layer 142 and the second buffer layer 140 .

[0058] The first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156 may be formed in the same layer and from the same material.

[0059] For example, the first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0060] For example, the first planarization layer 158 can be a single layer or multiple layers made of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0061] A first connection electrode 160 and a second connection electrode 162 are arranged in each of the subpixels SP1 to SP4 of the display area DA on the first planarization layer 158, and a second planarization layer 164 is arranged over the entire surfaces of the first connection electrode 160 and the second connection electrode 162.

[0062] The first connection electrode 160 is connected to the second drain electrode 154 through a contact hole in the first planarization layer 158 .

[0063] Although not shown in the figure, the second connection electrode 162 can be connected to the second source electrode 152 and the capacitor extension electrode 156 .

[0064] The first connection electrode 160 and the second connection electrode 162 can be formed in the same layer and from the same material.

[0065] For example, the first connection electrode 160 and the second connection electrode 162 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0066] For example, the second planarization layer 164 can be a single layer or multiple layers made of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0067] A first electrode 166 is disposed on the second planarization layer 164 in each of the sub-pixels SP1 to SP4 in the display area DA, and a bank layer 168 is disposed over the entire surface of the first electrode 166.

[0068] The first electrode 166 is connected to the first connection electrode 160 through a contact hole in the second planarization layer 164 .

[0069] For example, the first electrode 166 can be an anode, a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0070] The bank layer 168 has an opening that exposes the center of the first electrode 166 while covering the ends of the first electrode 166 .

[0071] For example, the bank layer 168 can be a single layer or multiple layers of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0072] Trenches TR may be formed on the bank layer 168 corresponding to boundaries between the sub-pixels SP1 to SP4, and spacers 170 may be disposed on the bank layer 168. A plurality of trenches TR may be present between adjacent sub-pixels, and the bottom surface of the trenches TR may abut against the second planarization layer 164, exposing the second planarization layer 164.

[0073] A light-emitting layer 172 is disposed on the entire surface of the first electrode 166 , and a second electrode 174 is disposed on the entire surface of the light-emitting layer 172 .

[0074] The light-emitting layer 172 is in contact with the first electrode 166 exposed through the opening in the bank layer 168, the sidewall of the opening in the bank layer 168, the top surface of the bank layer 168, and the sidewall and top surface of the spacer 170, but can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0075] Light-emitting layer 172 can include a hole-related layer, such as a hole-injection layer or a hole-transport layer, a light-emitting material layer, and an electron-related layer, such as an electron-transport layer or an electron-injection layer.

[0076] The second electrode 174 is not separated by the trenches TR, but may be continuous and extend over the trenches TR.

[0077] For example, the second electrode 174 can be a cathode and can be a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0078] The first electrode 166, the light-emitting layer 172 and the second electrode 174 constitute a light-emitting diode De.

[0079] A first sealing layer 176, a second sealing layer 178, and a third sealing layer 180 that suppress moisture penetration are disposed in this order on the entire surface of second electrode 174.

[0080] For example, the first sealing layer 176 and the third sealing layer 180 may be made of silicon oxide (SiO2), silicon nitride (SiN x The second sealing layer 178 may be a single layer or multiple layers made of an inorganic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0081] A method for manufacturing the display device 110 will be described with reference to the drawings.

[0082] 3A to 3F are cross-sectional views illustrating a method for manufacturing a display device according to a first embodiment of the present invention, which will be described with reference to both FIG.

[0083] As shown in FIG. 3A, a first buffer layer 122 is formed on the entire surface of a substrate 120.

[0084] Thereafter, a polycrystalline semiconductor material layer (not shown) is formed on the first buffer layer 122 and then patterned to form a first semiconductor layer 124 in the first and second gate drivers GD1 and GD2 in the non-display area NDA.

[0085] Thereafter, an oxide semiconductor material layer (not shown) is formed on the first semiconductor layer 124 and the first buffer layer 122, and then patterned to form the second semiconductor layer 126 in each of the subpixels SP1 to SP4 of the display area DA.

[0086] As shown in FIG. 3B, a first gate insulating layer 128 is formed on the entire surface of the first semiconductor layer 124 and the second semiconductor layer 126.

[0087] As shown in FIG. 3C, a first metal material layer (not shown) is formed on the first gate insulating layer 128 and then patterned to form a first gate electrode 130 corresponding to the first semiconductor layer 124, a second gate electrode 132 corresponding to the second semiconductor layer 126, and a first capacitor electrode 134 in each of the sub-pixels SP1 to SP4 of the display area DA.

[0088] Then, using the first gate electrode 130 and the second gate electrode 132 as a doping mask, N-type or P-type impurities are injected into the first semiconductor layer 124 and the second semiconductor layer 126 to divide the first semiconductor layer 124 into an undoped channel region 124a and a source region 124b and a drain region 124c which are doped with impurities on both sides of the channel region 124a, and the second semiconductor layer 126 into an undoped channel region 126a and a source region 126b and a drain region 126c which are doped with impurities (or made conductive) on both sides of the channel region 126a.

[0089] The first gate electrode 130, the first gate insulating layer 128 and the first semiconductor layer 124 constitute a first thin film transistor T1, and the second gate electrode 132, the first gate insulating layer 128 and the second semiconductor layer 126 constitute a second thin film transistor T2.

[0090] Thereafter, a first interlayer insulating layer 136 is formed over the entire surfaces of the first gate electrode 130, the second gate electrode 132 and the first capacitor electrode .

[0091] As shown in FIG. 3D, a second metal material layer (not shown) is formed on the first interlayer insulating layer 136 and then patterned to form a second capacitor electrode 138 corresponding to the first capacitor electrode 134.

[0092] The first capacitor electrode 134, the first interlayer insulating layer 136, and the second capacitor electrode 138 constitute a storage capacitor Cs.

[0093] Thereafter, a second buffer layer 140 is formed on the entire surface on the second capacitor electrode 138, a second interlayer insulating layer 142 is formed on the entire surface on the second buffer layer 140, and then patterning is performed to form a contact hole exposing the first gate electrode 130 in the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136, a contact hole exposing the source region 124b of the first semiconductor layer 124 is formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128, and a contact hole exposing the drain region 124c of the first semiconductor layer 124 is formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128. In addition, a contact hole exposing the second gate electrode 132 is formed in the second interlayer insulating layer 142, the second buffer layer 140, and the first interlayer insulating layer 136, a contact hole exposing the source region 126b of the second semiconductor layer 126 is formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128, a contact hole exposing the drain region 126c of the second semiconductor layer 126 is formed in the second interlayer insulating layer 142, the second buffer layer 140, the first interlayer insulating layer 136, and the first gate insulating layer 128, and a contact hole exposing the second capacitor electrode 138 is formed in the second interlayer insulating layer 142 and the second buffer layer 140.

[0094] Then, a third metal material layer (not shown) is formed on the entire surface of the second interlayer insulating layer 142, and then patterned to form a first gate extension electrode 144, a first source electrode 146, and a first drain electrode 148 corresponding to the first thin film transistor T1, a second gate extension electrode 150, a second source electrode 152, and a second drain electrode 154 corresponding to the second thin film transistor T2, and a capacitor extension electrode 156 corresponding to the storage capacitor Cs.

[0095] As shown in FIG. 3E, a first planarization layer 158 is formed on the entire surface of the first gate extension electrode 144, the first source electrode 146, the first drain electrode 148, the second gate extension electrode 150, the second source electrode 152, the second drain electrode 154, and the capacitor extension electrode 156, and then patterning is performed to form a contact hole in the first planarization layer 158 to expose the second drain electrode 154.

[0096] Thereafter, a fourth metal material layer (not shown) is formed on the entire surface of the first planarization layer 158 and then patterned to form the first connection electrodes 160 and the second connection electrodes 162 in the sub-pixels SP1 to SP4 of the display area DA.

[0097] As shown in FIG. 3F, a second planarization layer 164 is formed over the entire surfaces of the first connection electrode 160 and the second connection electrode 162, and then patterning is performed to form a contact hole in the second planarization layer 164 that exposes the first connection electrode 160.

[0098] Thereafter, a first electrode material layer (not shown) is formed on the entire surface of the second planarization layer 164 and then patterned to form the first electrodes 166 in the sub-pixels SP1 to SP4 of the display area DA.

[0099] Then, a bank layer 168 having an opening that exposes the central portion of the first electrode 166 while covering the ends of the first electrode 166 is formed on the first electrode 166, and a spacer 170 is formed on the bank layer 168, while a trench TR is formed on the bank layer 168 corresponding to the boundary portion between the sub-pixels SP1 to SP4.

[0100] Thereafter, the light-emitting layer 172 is formed on the entire surface of the first electrode 166, and the light-emitting layer 172 can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0101] Thereafter, the second electrode 174 is formed on the entire surface of the light emitting layer 172. The second electrode 174 is not separated by the trenches TR, but can be connected and extended over the trenches TR.

[0102] The first electrode 166, the light-emitting layer 172, and the second electrode 174 constitute a light-emitting diode De.

[0103] Thereafter, first sealing layer 176, second sealing layer 178, and third sealing layer 180 are formed in this order over the entire surface of second electrode 174, and display device 110 is completed.

[0104] As described above, in the display device 110 according to the first embodiment of the present invention, the first thin film transistor T1 using a polycrystalline semiconductor material for the semiconductor layer (active layer) and the second thin film transistor T2 using an oxide semiconductor material for the semiconductor layer (active layer) are formed on one substrate 120, so that the first thin film transistor T1 in the first gate driver GD1 and the second gate driver GD2 has a relatively high mobility, and the second thin film transistor T2 in each of the sub-pixels SP1 to SP4 has a relatively low off-current. As a result, a driving method such as a variable refresh rate (VRR) that drives a still image at a relatively low refresh rate and drives a moving image at a relatively high refresh rate is adopted, thereby reducing power consumption.

[0105] In addition, by forming the first semiconductor layer 124 containing a polycrystalline semiconductor material and the second semiconductor layer 126 containing an oxide semiconductor material in the same layer, forming the first gate insulating layer 128 in common on the first semiconductor layer 124 and the second semiconductor layer 126, and forming the first gate electrode 130 and the second gate electrode 132 in the same layer and from the same material, the manufacturing process is simplified and manufacturing costs are reduced.

[0106] In another embodiment, a second gate insulating layer can be formed between the first semiconductor layer and the second semiconductor layer to improve the reliability of the first semiconductor layer, which will be described with reference to the drawings.

[0107] 4 is a cross-sectional view showing a non-display area and a display area in a display device according to a second embodiment of the present invention, in which the description of the same parts as those in the first embodiment will be omitted.

[0108] As shown in FIG. 4, in the display device 210 according to the second embodiment of the present invention, a first thin film transistor T1 which is a circuit thin film transistor is arranged in the first gate driver GD1 and the second gate driver GD2 of the non-display area NDA, and a second thin film transistor T2 which is a pixel thin film transistor, a storage capacitor Cs, and a light emitting diode De are arranged in each of the sub-pixels SP1 to SP4 of the display area DA.

[0109] Specifically, a first buffer layer 222 is disposed on the entire surface of the substrate 220, and a first semiconductor layer 224 is disposed on the first buffer layer 222 in the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA.

[0110] For example, the first buffer layer 222 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0111] The first semiconductor layer 224 includes an undoped channel region 224a and doped source and drain regions 224b and 224c on either side of the channel region 224a.

[0112] For example, the first semiconductor layer 224 can be made of a polycrystalline semiconductor material, such as polycrystalline silicon.

[0113] A second gate insulating layer 225 is disposed on the entire surface of the first semiconductor layer 224, and a second semiconductor layer 226 is disposed on the second gate insulating layer 225 in each of the sub-pixels SP1 to SP4 of the display area DA.

[0114] For example, the second gate insulating layer 225 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0115] The second semiconductor layer 226 includes an undoped channel region 226a, and a source region 226b and a drain region 226c that are doped with impurities (or made conductive) on either side of the channel region 226a.

[0116] For example, the second semiconductor layer 226 may be made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO).

[0117] A first gate insulating layer 228 is disposed on the entire surface of the second semiconductor layer 226, a first gate electrode 230 and a second gate electrode 232 are disposed on the first gate insulating layer 228 corresponding to the first semiconductor layer 224 and the second semiconductor layer 226, respectively, and a first capacitor electrode 234 is disposed in each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 228.

[0118] By disposing the second gate insulating layer 225 on the first semiconductor layer 224, disposing the second semiconductor layer 226 on the second gate insulating layer 225, and disposing the first gate insulating layer 228 commonly on the first semiconductor layer 224 and the second semiconductor layer 226, the second gate insulating layer 225 can be formed so as to satisfy conditions suitable for the first semiconductor layer 224 of a polycrystalline semiconductor material, and the first gate insulating layer 228 can be formed so as to satisfy conditions suitable for the second semiconductor layer 226 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 224 and the second semiconductor layer 226 can be improved.

[0119] For example, the thickness of the second gate insulating layer 225 may be thinner than the thickness of the first gate insulating layer 228, and the first gate insulating layer 228 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0120] The first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234 may be formed in the same layer and from the same material.

[0121] For example, the first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0122] The first gate electrode 230, the second gate insulating layer 225, the first gate insulating layer 228, and the first semiconductor layer 224 constitute a first thin film transistor T1, and the second gate electrode 232, the first gate insulating layer 228, and the second semiconductor layer 226 constitute a second thin film transistor T2.

[0123] A first interlayer insulating layer 236 is disposed over the entire surfaces of the first gate electrode 230, the second gate electrode 232, and the first capacitor electrode 234, and a second capacitor electrode 238 is disposed on the first interlayer insulating layer 236 corresponding to the first capacitor electrode 234.

[0124] For example, the first interlayer insulating layer 236 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0125] For example, the second capacitor electrode 238 may be a single layer or multiple layers of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0126] The first capacitor electrode 234, the first interlayer insulating layer 236, and the second capacitor electrode 238 constitute a storage capacitor Cs.

[0127] A second buffer layer 240 is disposed on the entire surface of the second capacitor electrode 238 , and a second interlayer insulating layer 242 is disposed on the entire surface of the second buffer layer 240 .

[0128] For example, the second buffer layer 240 may be made of silicon oxide (SiO2), silicon nitride (SiN x The second interlayer insulating layer 242 may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0129] A first gate extension electrode 244, a first source electrode 246, and a first drain electrode 248 are disposed on the second interlayer insulating layer 242 corresponding to the first thin film transistor T1, and a second gate extension electrode 250, a second source electrode 252, and a second drain electrode 254 are disposed on the second interlayer insulating layer 242 corresponding to the second thin film transistor T2. In addition, a capacitor extension electrode 256 is disposed on the second interlayer insulating layer 242 corresponding to the storage capacitor Cs, and a first planarization layer 258 is disposed on the entire surface of the first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256.

[0130] The first gate extension electrode 244 is connected to the first gate electrode 230 via a contact hole in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236, the first source electrode 246 is connected to the source region 224b of the first semiconductor layer 224 via a contact hole in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225, and the first drain electrode 248 is connected to the drain region 224c of the first semiconductor layer 224 via a contact hole in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225.

[0131] The second gate extension electrode 250 is connected to the second gate electrode 232 via contact holes in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236, the second source electrode 252 is connected to the source region 226b of the second semiconductor layer 226 via contact holes in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, and the first gate insulating layer 228, and the second drain electrode 254 is connected to the drain region 226c of the second semiconductor layer 226 via contact holes in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, and the first gate insulating layer 228.

[0132] The capacitor extension electrode 256 is connected to the second capacitor electrode 238 via contact holes in the second interlayer insulating layer 242 and the second buffer layer 240 .

[0133] The first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256 may be formed in the same layer and from the same material.

[0134] For example, the first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0135] For example, the first planarization layer 258 can be a single layer or multiple layers of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0136] A first connection electrode 260 and a second connection electrode 262 are arranged in each of the subpixels SP1 to SP4 of the display area DA on the first planarization layer 258, and a second planarization layer 264 is arranged over the entire surfaces of the first connection electrode 260 and the second connection electrode 262.

[0137] The first connection electrode 260 is connected to the second drain electrode 254 through a contact hole in the first planarization layer 258 .

[0138] Although not shown in the figure, the second connection electrode 262 can be connected to the second source electrode 252 and the capacitor extension electrode 256 .

[0139] The first connection electrode 260 and the second connection electrode 262 can be formed in the same layer and from the same material.

[0140] For example, the first connecting electrode 260 and the second connecting electrode 262 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0141] For example, the second planarization layer 264 can be a single layer or multiple layers made of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0142] A first electrode 266 is disposed on the second planarization layer 264 in each of the sub-pixels SP1 to SP4 in the display area DA, and a bank layer 268 is disposed over the entire surface of the first electrode 266.

[0143] The first electrode 266 is connected to the first connection electrode 260 through a contact hole in the second planarization layer 264 .

[0144] For example, the first electrode 266 can be an anode, a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0145] The bank layer 268 has an opening that exposes the center of the first electrode 266 while covering the ends of the first electrode 266 .

[0146] For example, the bank layer 268 can be a single layer or multiple layers of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0147] Trenches TR are formed on the bank layer 268 corresponding to the boundaries between the sub-pixels SP1 to SP4, and spacers 270 are disposed on the bank layer 268.

[0148] A light emitting layer 272 is disposed on the entire surface of the first electrode 266 , and a second electrode 274 is disposed on the entire surface of the light emitting layer 272 .

[0149] The light-emitting layer 272 is in contact with the first electrode 266 exposed through the opening in the bank layer 268, the sidewall of the opening in the bank layer 268, the top surface of the bank layer 268, and the sidewall and top surface of the spacer 270, but can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0150] Light-emitting layer 272 can include a hole-related layer, such as a hole-injection layer or a hole-transport layer, a light-emitting material layer, and an electron-related layer, such as an electron-transport layer or an electron-injection layer.

[0151] The second electrode 274 is not separated by the trench TR, but may be continuous and extend over the trench TR.

[0152] For example, the second electrode 274 can be a cathode and can be a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0153] The first electrode 266, the light emitting layer 272 and the second electrode 274 constitute a light emitting diode De.

[0154] A first sealing layer 276, a second sealing layer 278, and a third sealing layer 280 that suppress moisture penetration are disposed in this order on the entire surface of second electrode 274.

[0155] For example, the first sealing layer 276 and the third sealing layer 280 may be made of silicon oxide (SiO2), silicon nitride (SiN xThe second sealing layer 278 may be a single layer or multiple layers made of an inorganic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0156] A method for manufacturing the display device 210 will be described with reference to the drawings.

[0157] 5A to 5F are cross-sectional views illustrating a method for manufacturing a display device according to a second embodiment of the present invention, which will be described with reference to FIG.

[0158] As shown in FIG. 5A, a first buffer layer 222 is formed on the entire surface of a substrate 220.

[0159] Thereafter, a polycrystalline semiconductor material layer (not shown) is formed on the first buffer layer 222 and then patterned to form a first semiconductor layer 224 in the first and second gate drivers GD1 and GD2 in the non-display area NDA.

[0160] Thereafter, the second gate insulating layer 225 is formed on the entire surface of the first semiconductor layer 224 and the first buffer layer 222 .

[0161] As shown in FIG. 5B, an oxide semiconductor material layer (not shown) is formed on the entire surface of the second gate insulating layer 225 and then patterned to form the second semiconductor layer 126 in each of the subpixels SP1 to SP4 of the display area DA.

[0162] Thereafter, the first gate insulating layer 228 is formed on the entire surface of the second semiconductor layer 226 .

[0163] In this way, by disposing the second gate insulating layer 225 on the first semiconductor layer 224, disposing the second semiconductor layer 226 on the second gate insulating layer 225, and disposing the first gate insulating layer 228 commonly on the first semiconductor layer 224 and the second semiconductor layer 226, the second gate insulating layer 225 can be formed so as to satisfy conditions suitable for the first semiconductor layer 224 of a polycrystalline semiconductor material (for example, changes in the characteristics of the first semiconductor layer 224 due to an etching solution, changes in the characteristics due to the deposition temperature of the first semiconductor layer 224 and the second gate insulating layer 225, changes in the characteristics due to surface treatment of the first semiconductor layer 224), and the first gate insulating layer 228 can be formed so as to satisfy conditions suitable for the second semiconductor layer 226 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 224 and the second semiconductor layer 226 can be improved.

[0164] As shown in FIG. 5C, a first metal material layer (not shown) is formed on the first gate insulating layer 228 and then patterned to form a first gate electrode 230 corresponding to the first semiconductor layer 224, a second gate electrode 232 corresponding to the second semiconductor layer 226, and a first capacitor electrode 234 in each of the sub-pixels SP1 to SP4 of the display area DA.

[0165] Then, using the first gate electrode 230 and the second gate electrode 232 as a doping mask, N-type or P-type impurities are injected into the first semiconductor layer 224 and the second semiconductor layer 226 to divide the first semiconductor layer 224 into an undoped channel region 224a and a source region 224b and a drain region 224c on both sides of the channel region 224a which are doped with impurities, and the second semiconductor layer 226 into an undoped channel region 226a and a source region 226b and a drain region 226c on both sides of the channel region 226a which are doped with impurities (or made conductive).

[0166] The first gate electrode 230, the first gate insulating layer 228, the second gate insulating layer 225, and the first semiconductor layer 224 constitute a first thin film transistor T1, and the second gate electrode 232, the first gate insulating layer 228, and the second semiconductor layer 226 constitute a second thin film transistor T2.

[0167] Thereafter, a first interlayer insulating layer 236 is formed over the entire surfaces of the first gate electrode 230, the second gate electrode 232 and the first capacitor electrode 234.

[0168] As shown in FIG. 5D, a second metal material layer (not shown) is formed on the first interlayer insulating layer 236 and then patterned to form a second capacitor electrode 238 corresponding to the first capacitor electrode 234.

[0169] The first capacitor electrode 234, the first interlayer insulating layer 236, and the second capacitor electrode 238 constitute a storage capacitor Cs.

[0170] Thereafter, a second buffer layer 240 is formed on the entire surface on the second capacitor electrode 238, a second interlayer insulating layer 242 is formed on the entire surface on the second buffer layer 240, and then patterning is performed. A contact hole exposing the first gate electrode 230 is formed in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236. A contact hole exposing the source region 224b of the first semiconductor layer 224 is formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225. A contact hole exposing the drain region 224c of the first semiconductor layer 224 is formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225. In addition, a contact hole exposing the second gate electrode 232 is formed in the second interlayer insulating layer 242, the second buffer layer 240, and the first interlayer insulating layer 236, a contact hole exposing the source region 226b of the second semiconductor layer 226 is formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225, a contact hole exposing the drain region 226c of the second semiconductor layer 226 is formed in the second interlayer insulating layer 242, the second buffer layer 240, the first interlayer insulating layer 236, the first gate insulating layer 228, and the second gate insulating layer 225, and a contact hole exposing the second capacitor electrode 238 is formed in the second interlayer insulating layer 242 and the second buffer layer 240.

[0171] Then, a third metal material layer (not shown) is formed on the entire surface of the second interlayer insulating layer 242, and then patterned to form a first gate extension electrode 244, a first source electrode 246, and a first drain electrode 248 corresponding to the first thin film transistor T1, a second gate extension electrode 250, a second source electrode 252, and a second drain electrode 254 corresponding to the second thin film transistor T2, and a capacitor extension electrode 256 corresponding to the storage capacitor Cs.

[0172] As shown in FIG. 5E, a first planarization layer 258 is formed on the entire surface of the first gate extension electrode 244, the first source electrode 246, the first drain electrode 248, the second gate extension electrode 250, the second source electrode 252, the second drain electrode 254, and the capacitor extension electrode 256, and then patterned to form a contact hole in the first planarization layer 258 to expose the second drain electrode 254.

[0173] Thereafter, a fourth metal material layer (not shown) is formed on the entire surface of the first planarization layer 258 and then patterned to form the first connection electrodes 260 and the second connection electrodes 262 in the sub-pixels SP1 to SP4 of the display area DA.

[0174] As shown in FIG. 5F, a second planarization layer 264 is formed over the entire surfaces of the first connection electrode 260 and the second connection electrode 262, and then patterning is performed to form a contact hole in the second planarization layer 264 that exposes the first connection electrode 260.

[0175] Thereafter, a first electrode material layer (not shown) is formed on the entire surface of the second planarization layer 264 and then patterned to form the first electrodes 266 in the sub-pixels SP1 to SP4 of the display area DA.

[0176] Then, a bank layer 268 having an opening that exposes the central portion of the first electrode 266 while covering the ends of the first electrode 266 is formed on the first electrode 266, and a spacer 270 is formed on the bank layer 268, while a trench TR is formed on the bank layer 268 corresponding to the boundary portion between the sub-pixels SP1 to SP4.

[0177] Thereafter, the light-emitting layer 272 is formed on the entire surface of the first electrode 266, and the light-emitting layer 272 can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0178] Thereafter, the second electrode 274 is formed on the entire surface of the light emitting layer 272. The second electrode 274 is not separated by the trenches TR, but can be connected and extended over the trenches TR.

[0179] The first electrode 266, the light-emitting layer 272, and the second electrode 274 constitute a light-emitting diode De.

[0180] Thereafter, a first sealing layer 276, a second sealing layer 278, and a third sealing layer 280 are formed in this order over the entire surface of the second electrode 274, and the display device 210 is completed.

[0181] As described above, in the display device 210 according to the second embodiment of the present invention, the first thin film transistor T1 using a polycrystalline semiconductor material for the semiconductor layer (active layer) and the second thin film transistor T2 using an oxide semiconductor material for the semiconductor layer (active layer) are formed on one substrate 220, so that the first thin film transistor T1 in the first gate driver GD1 and the second gate driver GD2 has a relatively high mobility, and the second thin film transistor T2 in each of the sub-pixels SP1 to SP4 has a relatively low off-current. As a result, a driving method such as a variable refresh rate (VRR) that drives a still image at a relatively low refresh rate and drives a moving image at a relatively high refresh rate is adopted, thereby reducing power consumption.

[0182] In addition, the first gate insulating layer 228 is commonly formed on the first semiconductor layer 224 including a polycrystalline semiconductor material and the second semiconductor layer 226 including an oxide semiconductor material, and the first gate electrode 230 and the second gate electrode 232 are formed in the same layer from the same material, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0183] In addition, by arranging the second gate insulating layer 225 on the first semiconductor layer 224, by arranging the second semiconductor layer 226 on the second gate insulating layer 225, and by arranging the first gate insulating layer 228 in common on the first semiconductor layer 224 and the second semiconductor layer 226, the reliability of the first semiconductor layer 224 and the second semiconductor layer 226 is improved.

[0184] In another embodiment, the first semiconductor layer and the second semiconductor layer can be formed using one mask to simplify the manufacturing process, which will be described with reference to the drawings.

[0185] 6 is a cross-sectional view showing a non-display area and a display area in a display device according to a third embodiment of the present invention, in which the description of the same parts as those in the first and second embodiments will be omitted.

[0186] As shown in FIG. 6, in the display device 310 according to the third embodiment of the present invention, a first thin film transistor T1 which is a circuit thin film transistor is arranged in the first gate driver GD1 and the second gate driver GD2 of the non-display area NDA, and a second thin film transistor T2 which is a pixel thin film transistor, a storage capacitor Cs, and a light emitting diode De are arranged in each of the sub-pixels SP1 to SP4 of the display area DA.

[0187] Specifically, a first buffer layer 322 is disposed on the entire surface of the substrate 320, and a first semiconductor layer 324 is disposed on the first buffer layer 322 in the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA.

[0188] For example, the first buffer layer 322 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0189] The first semiconductor layer 324 includes an undoped channel region 324a and doped source and drain regions 324b and 324c on either side of the channel region 324a.

[0190] For example, the first semiconductor layer 324 can be made of a polycrystalline semiconductor material, such as polycrystalline silicon.

[0191] A second gate insulating layer 325 is arranged on the first semiconductor layer 324 and on the first buffer layer 322 in each of the subpixels SP1 to SP4 of the display area DA, and a second semiconductor layer 326 is arranged on the second gate insulating layer 325 in each of the subpixels SP1 to SP4 of the display area DA.

[0192] The first semiconductor layer 324 and the second gate insulating layer 325 thereon may have the same shape in a planar view. Also, the second semiconductor layer 326 and the second gate insulating layer 325 thereunder may have the same shape in a planar view.

[0193] For example, the second gate insulating layer 325 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0194] The second semiconductor layer 326 includes an undoped channel region 326a, and a source region 326b and a drain region 326c that are doped with impurities (or made conductive) on either side of the channel region 326a.

[0195] For example, the second semiconductor layer 326 may be made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO).

[0196] A first gate insulating layer 328 is arranged on the second gate insulating layer 325 on the first semiconductor layer 324 and on the entire surface of the second semiconductor layer 326, a first gate electrode 330 and a second gate electrode 332 are arranged on the first gate insulating layer 328 corresponding to the first semiconductor layer 324 and the second semiconductor layer 326, respectively, and a first capacitor electrode 334 is arranged in each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 328.

[0197] By disposing the second gate insulating layer 325 on the first semiconductor layer 324, disposing the second semiconductor layer 326 on the second gate insulating layer 325, and disposing the first gate insulating layer 328 commonly on the first semiconductor layer 324 and the second semiconductor layer 326, the second gate insulating layer 325 can be formed so as to satisfy conditions suitable for the first semiconductor layer 324 of a polycrystalline semiconductor material, and the first gate insulating layer 328 can be formed so as to satisfy conditions suitable for the second semiconductor layer 326 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 324 and the second semiconductor layer 326 can be improved.

[0198] For example, the thickness of the second gate insulating layer 325 may be thinner than the thickness of the first gate insulating layer 328, and the first gate insulating layer 328 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0199] The first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334 may be formed in the same layer and from the same material.

[0200] For example, the first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0201] The first gate electrode 330, the second gate insulating layer 325, the first gate insulating layer 328, and the first semiconductor layer 324 constitute a first thin film transistor T1, and the second gate electrode 332, the first gate insulating layer 328, and the second semiconductor layer 326 constitute a second thin film transistor T2.

[0202] A first interlayer insulating layer 336 is disposed over the entire surfaces of the first gate electrode 330, the second gate electrode 332, and the first capacitor electrode 334, and a second capacitor electrode 338 is disposed on the first interlayer insulating layer 336 corresponding to the first capacitor electrode 334.

[0203] For example, the first interlayer insulating layer 336 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0204] For example, the second capacitor electrode 338 may be a single layer or multiple layers of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0205] The first capacitor electrode 334, the first interlayer insulating layer 336, and the second capacitor electrode 338 constitute a storage capacitor Cs.

[0206] A second buffer layer 340 is disposed over the entire surface of the second capacitor electrode 338 , and a second interlayer insulating layer 342 is disposed over the entire surface of the second buffer layer 340 .

[0207] For example, the second buffer layer 340 may be made of silicon oxide (SiO2), silicon nitride (SiN x The second interlayer insulating layer 342 may be a single layer or a multilayer made of an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0208] A first gate extension electrode 344, a first source electrode 346, and a first drain electrode 348 are disposed on the second interlayer insulating layer 342 corresponding to the first thin film transistor T1, and a second gate extension electrode 350, a second source electrode 352, and a second drain electrode 354 are disposed on the second interlayer insulating layer 342 corresponding to the second thin film transistor T2. In addition, a capacitor extension electrode 356 is disposed on the second interlayer insulating layer 342 corresponding to the storage capacitor Cs, and a first planarization layer 358 is disposed on the entire surface of the first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356.

[0209] The first gate extension electrode 344 is connected to the first gate electrode 330 via a contact hole in the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336, the first source electrode 346 is connected to the source region 324b of the first semiconductor layer 324 via a contact hole in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325, and the first drain electrode 348 is connected to the drain region 324c of the first semiconductor layer 324 via a contact hole in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325.

[0210] The second gate extension electrode 350 is connected to the second gate electrode 332 via contact holes in the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336, the second source electrode 352 is connected to the source region 326b of the second semiconductor layer 326 via contact holes in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325, and the second drain electrode 354 is connected to the drain region 326c of the second semiconductor layer 326 via contact holes in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325.

[0211] The capacitor extension electrode 356 is connected to the second capacitor electrode 338 via a contact hole in the second interlayer insulating layer 342 and the second buffer layer 340 .

[0212] The first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356 may be formed in the same layer and from the same material.

[0213] For example, the first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0214] For example, the first planarization layer 358 can be a single layer or multiple layers of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0215] A first connection electrode 360 ​​and a second connection electrode 362 are arranged in each of the subpixels SP1 to SP4 of the display area DA on the first planarization layer 358, and a second planarization layer 364 is arranged over the entire surfaces of the first connection electrode 360 ​​and the second connection electrode 362.

[0216] The first connection electrode 360 ​​is connected to the second drain electrode 354 through a contact hole in the first planarization layer 358 .

[0217] Although not shown, the second connection electrode 362 can be connected to the second source electrode 352 and the capacitor extension electrode 356 .

[0218] The first connection electrode 360 ​​and the second connection electrode 362 can be formed in the same layer and from the same material.

[0219] For example, the first connection electrode 360 ​​and the second connection electrode 362 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0220] For example, the second planarization layer 364 can be a single layer or multiple layers made of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0221] A first electrode 366 is disposed on the second planarization layer 364 in each of the sub-pixels SP1 to SP4 in the display area DA, and a bank layer 368 is disposed over the entire surface of the first electrode 366.

[0222] The first electrode 366 is connected to the first connection electrode 360 ​​through a contact hole in the second planarization layer 364 .

[0223] For example, the first electrode 366 can be an anode, a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0224] The bank layer 368 has an opening that exposes the center of the first electrode 366 while covering the ends of the first electrode 366 .

[0225] For example, the bank layer 368 can be a single layer or multiple layers of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0226] Trenches TR are formed on the bank layer 368 corresponding to the boundaries between the sub-pixels SP1 to SP4, and spacers 370 are disposed on the bank layer 368.

[0227] A light emitting layer 372 is disposed on the entire surface of the first electrode 366 , and a second electrode 374 is disposed on the entire surface of the light emitting layer 372 .

[0228] The light-emitting layer 372 is in contact with the first electrode 366 exposed through the opening in the bank layer 368, the sidewall of the opening in the bank layer 368, the top surface of the bank layer 368, and the sidewall and top surface of the spacer 370, but can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0229] Light-emitting layer 372 can include a hole-related layer, such as a hole-injection layer or a hole-transport layer, a light-emitting material layer, and an electron-related layer, such as an electron-transport layer or an electron-injection layer.

[0230] The second electrode 374 is not separated by the trench TR, but may be continuous and extend over the trench TR.

[0231] For example, the second electrode 374 can be a cathode and can be a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0232] The first electrode 366, the light-emitting layer 372, and the second electrode 374 constitute a light-emitting diode De.

[0233] A first sealing layer 376, a second sealing layer 378, and a third sealing layer 380 that suppress moisture penetration are disposed in this order on the entire surface of second electrode 374.

[0234] For example, the first sealing layer 376 and the third sealing layer 380 may be made of silicon oxide (SiO2), silicon nitride (SiN x The first sealing layer 376 may be made of an inorganic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin, and the second sealing layer 378 may be made of an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0235] A method for manufacturing such a display device 310 will be described with reference to the drawings.

[0236] 7A to 7F are cross-sectional views illustrating a method for manufacturing a display device according to a third embodiment of the present invention, which will be described with reference to FIG.

[0237] As shown in FIG. 7A, a first buffer layer 322 is formed on the entire surface of a substrate 320.

[0238] Thereafter, an amorphous semiconductor material layer (not shown) is formed on the first buffer layer 322, and then the amorphous semiconductor material layer of the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA is selectively crystallized, and the uncrystallized amorphous semiconductor material layer is selectively removed to form a polycrystalline semiconductor pattern 323 in the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA.

[0239] Thereafter, a second gate insulating layer 325 is formed on the entire surface of the polycrystalline semiconductor pattern 323 and the first buffer layer 322 , and an oxide semiconductor material layer 327 is formed on the entire surface of the second gate insulating layer 325 .

[0240] As shown in FIG. 7B , a semi-transparent mask is used to etch the oxide semiconductor material layer 327, the second gate insulating layer 325, and the polycrystalline semiconductor pattern 323 in the non-display area NDA, and the oxide semiconductor material layer 327 and the second gate insulating layer 325 in the display area DA, and then the photoresist is ashed to expose the oxide semiconductor material layer 327 in the non-display area NDA. The exposed oxide semiconductor material layer 327 in the non-display area NDA is removed, and a first semiconductor layer 324 and a second gate insulating layer 325 are formed in the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA on the first buffer layer 322, and a second gate insulating layer 325 and a second semiconductor layer 326 are formed in each of the sub-pixels SP1 to SP4 of the display area DA on the first buffer layer 322.

[0241] By using one mask to pattern the first semiconductor layer 324, the second gate insulating layer 325 and the second semiconductor layer 326, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0242] Thereafter, the first gate insulating layer 328 is formed on the entire surface of the second gate insulating layer 325 and the second semiconductor layer 326 .

[0243] As shown in FIG. 7C, a first metal material layer (not shown) is formed on the first gate insulating layer 328 and then patterned to form a first gate electrode 330 corresponding to the first semiconductor layer 324, a second gate electrode 332 corresponding to the second semiconductor layer 326, and a first capacitor electrode 334 in each of the sub-pixels SP1 to SP4 of the display area DA.

[0244] Then, using the first gate electrode 330 and the second gate electrode 332 as a doping mask, N-type or P-type impurities are injected into the first semiconductor layer 324 and the second semiconductor layer 326 to divide the first semiconductor layer 324 into an undoped channel region 324a and a source region 324b and a drain region 324c which are doped with impurities on both sides of the channel region 324a, and the second semiconductor layer 326 into an undoped channel region 326a and a source region 326b and a drain region 326c which are doped with impurities (or made conductive) on both sides of the channel region 326a.

[0245] The first gate electrode 330, the first gate insulating layer 328, the second gate insulating layer 325, and the first semiconductor layer 324 constitute a first thin film transistor T1, and the second gate electrode 332, the first gate insulating layer 328, and the second semiconductor layer 326 constitute a second thin film transistor T2.

[0246] Thereafter, a first interlayer insulating layer 336 is formed over the entire surfaces of the first gate electrode 330 , the second gate electrode 332 and the first capacitor electrode 334 .

[0247] As shown in FIG. 7D, a second metal material layer (not shown) is formed on the first interlayer insulating layer 336 and then patterned to form a second capacitor electrode 338 corresponding to the first capacitor electrode 334.

[0248] The first capacitor electrode 334, the first interlayer insulating layer 336, and the second capacitor electrode 338 constitute a storage capacitor Cs.

[0249] Thereafter, a second buffer layer 340 is formed on the entire surface on the second capacitor electrode 338, a second interlayer insulating layer 342 is formed on the entire surface on the second buffer layer 340, and then patterning is performed. A contact hole exposing the first gate electrode 330 is formed in the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336. A contact hole exposing the source region 324b of the first semiconductor layer 324 is formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325. A contact hole exposing the drain region 324c of the first semiconductor layer 324 is formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, the first gate insulating layer 328, and the second gate insulating layer 325. In addition, a contact hole exposing the second gate electrode 332 is formed in the second interlayer insulating layer 342, the second buffer layer 340, and the first interlayer insulating layer 336, a contact hole exposing the source region 326b of the second semiconductor layer 326 is formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, and the first gate insulating layer 328, a contact hole exposing the drain region 326c of the second semiconductor layer 326 is formed in the second interlayer insulating layer 342, the second buffer layer 340, the first interlayer insulating layer 336, and the first gate insulating layer 328, and a contact hole exposing the second capacitor electrode 338 is formed in the second interlayer insulating layer 342 and the second buffer layer 340.

[0250] Then, a third metal material layer (not shown) is formed on the entire surface of the second interlayer insulating layer 342, and then patterned to form a first gate extension electrode 344, a first source electrode 346, and a first drain electrode 348 corresponding to the first thin film transistor T1, a second gate extension electrode 350, a second source electrode 352, and a second drain electrode 354 corresponding to the second thin film transistor T2, and a capacitor extension electrode 356 corresponding to the storage capacitor Cs.

[0251] As shown in FIG. 7E, a first planarization layer 358 is formed on the entire surface of the first gate extension electrode 344, the first source electrode 346, the first drain electrode 348, the second gate extension electrode 350, the second source electrode 352, the second drain electrode 354, and the capacitor extension electrode 356, and then patterned to form a contact hole in the first planarization layer 358 to expose the second drain electrode 354.

[0252] Thereafter, a fourth metal material layer (not shown) is formed on the entire surface of the first planarization layer 358 and then patterned to form the first connection electrodes 360 and the second connection electrodes 362 in the sub-pixels SP1 to SP4 of the display area DA.

[0253] As shown in FIG. 7F, a second planarization layer 364 is formed over the entire surfaces of the first connection electrode 360 ​​and the second connection electrode 362, and then patterning is performed to form a contact hole in the second planarization layer 364 that exposes the first connection electrode 360.

[0254] Thereafter, a first electrode material layer (not shown) is formed on the entire surface of the second planarization layer 364 and then patterned to form the first electrodes 366 in the sub-pixels SP1 to SP4 of the display area DA.

[0255] Then, a bank layer 368 having an opening that exposes the central portion of the first electrode 366 while covering the ends of the first electrode 366 is formed on the first electrode 366, and a spacer 370 is formed on the bank layer 368, while a trench TR is formed on the bank layer 368 corresponding to the boundary portion between the sub-pixels SP1 to SP4.

[0256] Thereafter, the light-emitting layer 372 is formed on the entire surface of the first electrode 366, and the light-emitting layer 372 can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0257] Thereafter, the second electrode 374 is formed on the entire surface of the light emitting layer 372. The second electrode 374 is not separated by the trenches TR, but can be connected and extended over the trenches TR.

[0258] Thereafter, a first sealing layer 376, a second sealing layer 378, and a third sealing layer 380 are formed in this order over the entire surface of the second electrode 374, and the display device 310 is completed.

[0259] As described above, in the display device 310 according to the third embodiment of the present invention, the first thin film transistor T1 using a polycrystalline semiconductor material for the semiconductor layer (active layer) and the second thin film transistor T2 using an oxide semiconductor material for the semiconductor layer (active layer) are formed on one substrate 320, so that the first thin film transistor T1 in the first gate driver GD1 and the second gate driver GD2 has a relatively high mobility, and the second thin film transistor T2 in each of the sub-pixels SP1 to SP4 has a relatively low off-current. As a result, a driving method such as a variable refresh rate (VRR) that drives a still image at a relatively low refresh rate and drives a moving image at a relatively high refresh rate is adopted, thereby reducing power consumption.

[0260] In addition, the first gate insulating layer 328 is commonly formed on the first semiconductor layer 324 including a polycrystalline semiconductor material and the second semiconductor layer 326 including an oxide semiconductor material, and the first gate electrode 330 and the second gate electrode 332 are formed in the same layer from the same material, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0261] In addition, by arranging the second gate insulating layer 325 on the first semiconductor layer 324, by arranging the second semiconductor layer 326 on the second gate insulating layer 325, and by arranging the first gate insulating layer 328 in common on the first semiconductor layer 324 and the second semiconductor layer 326, the reliability of the first semiconductor layer 324 and the second semiconductor layer 326 is improved.

[0262] In addition, the first semiconductor layer 324, the second gate insulating layer 325, and the second semiconductor layer 326 are patterned using one mask, which further simplifies the manufacturing process and further reduces manufacturing costs.

[0263] In another embodiment, the manufacturing process can be simplified by forming the source electrode and the drain electrode in the same layer and from the same material as the gate extension electrode, and this will be described with reference to the drawings.

[0264] 8 is a cross-sectional view showing a non-display area and a display area in a display device according to a fourth embodiment of the present invention, in which the description of the same parts as those in the first to third embodiments will be omitted.

[0265] As shown in FIG. 8, in a display device 410 according to the fourth embodiment of the present invention, a first thin film transistor T1 which is a circuit thin film transistor is arranged in the first gate driver GD1 and the second gate driver GD2 of the non-display area NDA, and a second thin film transistor T2 which is a pixel thin film transistor, a storage capacitor Cs, and a light emitting diode De are arranged in each of the sub-pixels SP1 to SP4 of the display area DA.

[0266] Specifically, a first buffer layer 422 is disposed on the entire surface of the substrate 420, and a first semiconductor layer 424 is disposed on the first buffer layer 422 in the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA.

[0267] For example, the first buffer layer 422 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0268] The first semiconductor layer 424 includes an undoped channel region 424a and a doped source region 424b and a doped drain region 424c on either side of the channel region 424a.

[0269] For example, the first semiconductor layer 424 can be made of a polycrystalline semiconductor material, such as polycrystalline silicon.

[0270] A second gate insulating layer 425 is arranged on the first semiconductor layer 424 and on the first buffer layer 422 in each of the subpixels SP1 to SP4 of the display area DA, and a second semiconductor layer 426 is arranged on the second gate insulating layer 425 in each of the subpixels SP1 to SP4 of the display area DA.

[0271] The first semiconductor layer 424 and the second gate insulating layer 425 thereon may have the same shape in a planar view. Also, the second semiconductor layer 426 and the second gate insulating layer 425 thereunder may have the same shape in a planar view.

[0272] For example, the second gate insulating layer 425 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0273] The second semiconductor layer 426 includes an undoped channel region 426a, and a source region 426b and a drain region 426c that are doped with impurities (or made conductive) on either side of the channel region 426a.

[0274] For example, the second semiconductor layer 426 may be made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO).

[0275] A first gate insulating layer 428 is arranged on the second gate insulating layer 425 on the first semiconductor layer 424 and on the entire surface of the second semiconductor layer 426, a first gate electrode 430 and a second gate electrode 432 are arranged on the first gate insulating layer 428 corresponding to the first semiconductor layer 424 and the second semiconductor layer 426, respectively, and a first capacitor electrode 434 is arranged in each of the sub-pixels SP1 to SP4 of the display area DA on the first gate insulating layer 428.

[0276] By disposing the second gate insulating layer 425 on the first semiconductor layer 424, disposing the second semiconductor layer 426 on the second gate insulating layer 425, and disposing the first gate insulating layer 428 commonly on the first semiconductor layer 424 and the second semiconductor layer 426, the second gate insulating layer 425 can be formed so as to satisfy conditions suitable for the first semiconductor layer 424 of a polycrystalline semiconductor material (for example, changes in characteristics of the first semiconductor layer 424 due to an etching solution, changes in characteristics due to the deposition temperature of the first semiconductor layer 424 and the second gate insulating layer 425, changes in characteristics due to surface treatment of the first semiconductor layer 424), and the first gate insulating layer 428 can be formed so as to satisfy conditions suitable for the second semiconductor layer 426 of an oxide semiconductor material. As a result, the reliability of the first semiconductor layer 424 and the second semiconductor layer 426 can be improved.

[0277] For example, the thickness of the second gate insulating layer 425 may be thinner than the thickness of the first gate insulating layer 428, and the first gate insulating layer 428 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0278] The first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434 may be formed in the same layer and from the same material.

[0279] For example, the first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0280] The first gate electrode 430, the second gate insulating layer 425, the first gate insulating layer 428, and the first semiconductor layer 424 constitute a first thin film transistor T1, and the second gate electrode 432, the first gate insulating layer 428, and the second semiconductor layer 426 constitute a second thin film transistor T2.

[0281] A first interlayer insulating layer 436 is arranged on the entire surface of the first gate electrode 430, the second gate electrode 432, and the first capacitor electrode 434, a first gate extension electrode 444, a first source electrode 446, and a first drain electrode 448 are arranged on the first interlayer insulating layer 436 corresponding to the first thin film transistor T1, a second gate extension electrode 450, a second source electrode 452, and a second drain electrode 454 are arranged on the first interlayer insulating layer 436 corresponding to the second thin film transistor T2, and a second capacitor electrode 438 is arranged on the first interlayer insulating layer 436 corresponding to the first capacitor electrode 434.

[0282] For example, the first interlayer insulating layer 436 may be made of silicon oxide (SiO2), silicon nitride (SiN x The insulating layer may be a single layer or multiple layers of inorganic insulating material such as .

[0283] The first gate extension electrode 444 is connected to the first gate electrode 430 via a contact hole in the first interlayer insulating layer 436, the first source electrode 446 is connected to the source region 424b of the first semiconductor layer 424 via contact holes in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425, and the first drain electrode 448 is connected to the drain region 424c of the first semiconductor layer 424 via contact holes in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425.

[0284] The second gate extension electrode 450 is connected to the second gate electrode 432 via a contact hole in the first interlayer insulating layer 436, the second source electrode 452 is connected to the source region 426b of the second semiconductor layer 426 via contact holes in the first interlayer insulating layer 436 and the first gate insulating layer 428, and the second drain electrode 454 is connected to the drain region 426c of the second semiconductor layer 426 via contact holes in the first interlayer insulating layer 436 and the first gate insulating layer 428.

[0285] The first capacitor electrode 434, the first interlayer insulating layer 436, and the second capacitor electrode 438 constitute a storage capacitor Cs.

[0286] For example, the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452, the second drain electrode 454, and the second capacitor electrode 438 may be a single layer or multiple layers made of a metallic material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0287] A second buffer layer 440 is disposed over the entire surfaces of the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452, the second drain electrode 454, and the second capacitor electrode 438, and a first planarization layer 458 is disposed over the entire surfaces of the second buffer layer 440.

[0288] For example, the second buffer layer 440 may be made of silicon oxide (SiO2), silicon nitride (SiN x The first planarization layer 458 may be a single layer or a multi-layer made of an inorganic insulating material such as acrylic or benzocyclobutene (BCB). The first planarization layer 458 may be a single layer or a multi-layer made of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0289] A first source extension electrode 463 and a first drain extension electrode 461 are arranged on the first planarization layer 458 corresponding to the first thin film transistor T1, a second source extension electrode 462 and a second drain extension electrode 460 are arranged on the first planarization layer 458 corresponding to the second thin film transistor T2, and a second planarization layer 464 is arranged on the entire surface of the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462 and the second drain extension electrode 460.

[0290] The first source extension electrode 463 is connected to the first source electrode 446 via a contact hole in the second buffer layer 440 and the first planarization layer 458, the first drain extension electrode 461 is connected to the first drain electrode 448 via a contact hole in the second buffer layer 440 and the first planarization layer 458, the second source extension electrode 462 is connected to the second source electrode 452 and the second capacitor electrode 438 via contact holes in the second buffer layer 440 and the first planarization layer 458, and the second drain extension electrode 460 is connected to the second drain electrode 454 via a contact hole in the second buffer layer 440 and the first planarization layer 458.

[0291] The first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460 can be formed in the same layer and from the same material.

[0292] For example, the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460 may be a single layer or multiple layers made of a metal material such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0293] For example, the second planarization layer 464 can be a single layer or multiple layers made of an organic insulating material such as photoacryl or benzocyclobutene (BCB).

[0294] A first electrode 466 is disposed on the second planarization layer 464 in each of the sub-pixels SP1 to SP4 in the display area DA, and a bank layer 468 is disposed over the entire surface of the first electrode 466.

[0295] The first electrode 466 is connected to the second drain extension electrode 460 through a contact hole in the second planarization layer 464 .

[0296] For example, the first electrode 466 can be an anode, a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0297] The bank layer 468 has an opening that exposes the center of the first electrode 466 while covering the ends of the first electrode 466 .

[0298] For example, the bank layer 468 can be a single layer or multiple layers of an organic insulating material such as photoacrylic or benzocyclobutene (BCB).

[0299] Trenches TR are formed on the bank layer 468 corresponding to the boundaries between the sub-pixels SP1 to SP4, and spacers 470 are disposed on the bank layer 468.

[0300] A light emitting layer 472 is disposed on the entire surface of the first electrode 466 , and a second electrode 474 is disposed on the entire surface of the light emitting layer 472 .

[0301] The light-emitting layer 472 is in contact with the first electrode 466 exposed through the opening in the bank layer 468, the sidewall of the opening in the bank layer 468, the top surface of the bank layer 468, and the sidewall and top surface of the spacer 70, but can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0302] Light-emitting layer 472 can include a hole-related layer, such as a hole-injection layer or a hole-transport layer, a light-emitting material layer, and an electron-related layer, such as an electron-transport layer or an electron-injection layer.

[0303] The second electrode 474 is not separated by the trenches TR, but may be continuous and extend over the trenches TR.

[0304] For example, the second electrode 474 can be a cathode and can be a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transparent or opaque metallic material such as molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), titanium (Ti), or alloys thereof.

[0305] The first electrode 466, the light-emitting layer 472, and the second electrode 474 constitute a light-emitting diode De.

[0306] A first sealing layer 476, a second sealing layer 478, and a third sealing layer 480 that suppress moisture penetration are sequentially disposed on the entire surface of second electrode 474.

[0307] For example, the first sealing layer 476 and the third sealing layer 480 may be made of silicon oxide (SiO2), silicon nitride (SiN x The first sealing layer 476 may be made of an inorganic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin, and the second sealing layer 478 may be made of an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0308] A method for manufacturing such a display device 410 will be described with reference to the drawings.

[0309] 9A to 9E are cross-sectional views illustrating a method for manufacturing a display device according to a fourth embodiment of the present invention, which will be described with reference to FIG.

[0310] As shown in FIG. 9A, a first buffer layer 422 is formed on the entire surface of a substrate 420.

[0311] Thereafter, an amorphous semiconductor material layer (not shown) is formed on the first buffer layer 422, and then the amorphous semiconductor material layer of the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA is selectively crystallized, and the uncrystallized amorphous semiconductor material layer is selectively removed to form a polycrystalline semiconductor pattern 423 in the first gate driver GD1 and the second gate driver GD2 in the non-display area NDA.

[0312] Thereafter, a second gate insulating layer 425 is formed on the entire surface of the polycrystalline semiconductor pattern 423 and the first buffer layer 422 , and an oxide semiconductor material layer 427 is formed on the entire surface of the second gate insulating layer 425 .

[0313] As shown in FIG. 9B, a semi-transparent mask is used to etch the oxide semiconductor material layer 427, the second gate insulating layer 425, and the polycrystalline semiconductor pattern 423 in the non-display area NDA, and the oxide semiconductor material layer 427 and the second gate insulating layer 425 in the display area DA, and then the photoresist is ashed to expose the oxide semiconductor material layer 427 in the non-display area NDA. The exposed oxide semiconductor material layer 427 in the non-display area NDA is removed, and a first semiconductor layer 424 and a second gate insulating layer 425 are formed in the first gate driver GD1 and the second gate driver GD2 of the non-display area NDA on the first buffer layer 422, and a second gate insulating layer 425 and a second semiconductor layer 426 are formed in each of the sub-pixels SP1 to SP4 of the display area DA on the first buffer layer 422.

[0314] By using one mask to pattern the first semiconductor layer 424, the second gate insulating layer 425 and the second semiconductor layer 426, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0315] Thereafter, the first gate insulating layer 428 is formed on the entire surface of the second gate insulating layer 425 and the second semiconductor layer 426 .

[0316] As shown in FIG. 9C, a first metal material layer (not shown) is formed on the first gate insulating layer 428 and then patterned to form a first gate electrode 430 corresponding to the first semiconductor layer 424, a second gate electrode 432 corresponding to the second semiconductor layer 426, and a first capacitor electrode 434 in each of the sub-pixels SP1 to SP4 of the display area DA.

[0317] Then, using the first gate electrode 430 and the second gate electrode 432 as a doping mask, N-type or P-type impurities are injected into the first semiconductor layer 424 and the second semiconductor layer 426 to divide the first semiconductor layer 424 into an undoped channel region 424a and a source region 424b and a drain region 424c which are doped with impurities on both sides of the channel region 424a, and the second semiconductor layer 426 into an undoped channel region 426a and a source region 426b and a drain region 426c which are doped with impurities (or made conductive) on both sides of the channel region 426a.

[0318] The first gate electrode 430, the first gate insulating layer 428, the second gate insulating layer 425, and the first semiconductor layer 424 constitute a first thin film transistor T1, and the second gate electrode 432, the first gate insulating layer 428, and the second semiconductor layer 426 constitute a second thin film transistor T2.

[0319] Thereafter, a first interlayer insulating layer 436 is formed over the entire surfaces of the first gate electrode 430 , the second gate electrode 432 and the first capacitor electrode 434 .

[0320] As shown in FIG. 9D , patterning is performed on the first interlayer insulating layer 436, a contact hole exposing the first gate electrode 430 is formed on the first interlayer insulating layer 436, a contact hole exposing the source region 424b of the first semiconductor layer 424 is formed in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425, and a contact hole exposing the drain region 424c of the first semiconductor layer 424 is formed in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425. In addition, a contact hole exposing the second gate electrode 432 is formed in the first interlayer insulating layer 436, a contact hole exposing the source region 426b of the second semiconductor layer 426 is formed in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425, and a contact hole exposing the drain region 426c of the second semiconductor layer 426 is formed in the first interlayer insulating layer 436, the first gate insulating layer 428, and the second gate insulating layer 425.

[0321] Then, a second metal material layer (not shown) is formed on the first interlayer insulating layer 436 and then patterned to form a first gate extension electrode 444, a first source electrode 446, and a first drain electrode 448 corresponding to the first thin film transistor T1, a second gate extension electrode 450, a second source electrode 452, and a second drain electrode 454 corresponding to the second thin film transistor T2, and a second capacitor electrode 438 corresponding to the first capacitor electrode 434.

[0322] The first capacitor electrode 434, the first interlayer insulating layer 436, and the second capacitor electrode 438 constitute a storage capacitor Cs.

[0323] Thereafter, a second buffer layer 440 is formed on the entire surface of the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452, the second drain electrode 454, and the second capacitor electrode 438. A first planarization layer 458 is formed on the entire surface of the second buffer layer 440, and then patterning is performed to form a contact hole in the first planarization layer 458 and the second buffer layer 440 to expose the first source electrode 446. A contact hole exposing the drain electrode 448 is formed in the first planarization layer 458 and the second buffer layer 440, a contact hole exposing the second source electrode 452 is formed in the first planarization layer 458 and the second buffer layer 440, a contact hole exposing the second drain electrode 454 is formed in the first planarization layer 458 and the second buffer layer 440, and a contact hole exposing the second capacitor electrode 438 is formed in the first planarization layer 458 and the second buffer layer 440.

[0324] Then, a third metal material layer (not shown) is formed on the entire surface of the first planarization layer 458 and then patterned to form a first source extension electrode 463 and a first drain extension electrode 461 corresponding to the first thin film transistor T1, a second source extension electrode 462 corresponding to the second thin film transistor T2 and the storage capacitor Cs, and a second drain extension electrode 460 corresponding to the second thin film transistor T2.

[0325] As shown in FIG. 9E, a second planarization layer 464 is formed on the entire surface of the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462, and the second drain extension electrode 460, and then patterning is performed to form a contact hole in the second planarization layer 464 that exposes the second drain extension electrode 460.

[0326] Thereafter, a first electrode material layer (not shown) is formed on the entire surface of the second planarization layer 464 and then patterned to form the first electrodes 466 in the sub-pixels SP1 to SP4 of the display area DA.

[0327] Then, a bank layer 468 having an opening exposing the central portion of the first electrode 466 while covering the ends of the first electrode 466 is formed on the first electrode 466, and a spacer 470 is formed on the bank layer 468, while a trench TR is formed on the bank layer 468 corresponding to the boundary portion between the sub-pixels SP1 to SP4.

[0328] Thereafter, the light-emitting layer 472 is formed on the entire surface of the first electrode 466, and the light-emitting layer 472 can be separated at the boundaries between the sub-pixels SP1 to SP4 by the trenches TR.

[0329] Thereafter, the second electrode 474 is formed on the entire surface of the light emitting layer 472. The second electrode 474 is not separated by the trenches TR, but can be connected and extended over the trenches TR.

[0330] The first electrode 466, the light-emitting layer 472, and the second electrode 474 constitute a light-emitting diode De.

[0331] Thereafter, first sealing layer 476, second sealing layer 478, and third sealing layer 480 are formed in this order over the entire surface of second electrode 474, and display device 410 is completed.

[0332] As described above, in the display device 410 according to the fourth embodiment of the present invention, the first thin film transistor T1 using a polycrystalline semiconductor material for the semiconductor layer (active layer) and the second thin film transistor T2 using an oxide semiconductor material for the semiconductor layer (active layer) are formed on one substrate 420, so that the first thin film transistor T1 in the first gate driver GD1 and the second gate driver GD2 has a relatively high mobility, and the second thin film transistor T2 in each of the sub-pixels SP1 to SP4 has a relatively low off-current. As a result, a driving method such as a variable refresh rate (VRR) that drives a still image at a relatively low refresh rate and drives a moving image at a relatively high refresh rate is adopted, thereby reducing power consumption.

[0333] In addition, the first gate insulating layer 428 is commonly formed on the first semiconductor layer 424 including a polycrystalline semiconductor material and the second semiconductor layer 426 including an oxide semiconductor material, and the first gate electrode 430 and the second gate electrode 432 are formed in the same layer from the same material, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0334] In addition, by arranging the second gate insulating layer 425 on the first semiconductor layer 424, by arranging the second semiconductor layer 426 on the second gate insulating layer 425, and by arranging the first gate insulating layer 428 in common on the first semiconductor layer 424 and the second semiconductor layer 426, the reliability of the first semiconductor layer 424 and the second semiconductor layer 426 is improved.

[0335] In addition, the first semiconductor layer 424, the second gate insulating layer 425, and the second semiconductor layer 426 are patterned using one mask, which further simplifies the manufacturing process and further reduces manufacturing costs.

[0336] In addition, the first gate extension electrode 444, the first source electrode 446, the first drain electrode 448, the second gate extension electrode 450, the second source electrode 452 and the second drain electrode 454 are formed in the same layer and from the same material, and the first source extension electrode 463, the first drain extension electrode 461, the second source extension electrode 462 and the second drain extension electrode 460 are formed in the same layer and from the same material, thereby further simplifying the manufacturing process and further reducing manufacturing costs.

[0337] Although the present invention has been described above with reference to a preferred embodiment, it will be understood by those skilled in the art that the present invention can be modified and changed in various ways without departing from the technical idea and scope of the present invention as set forth in the claims. [Explanation of symbols]

[0338] 110, 210, 310, 410...display device, 120, 220, 320, 420...substrate, T1...first thin film transistor, T2...second thin film transistor, 124, 224, 324, 424...first semiconductor layer, 126, 226, 326, 426...second semiconductor layer, De...light emitting diode

Claims

1. a substrate including a display area and a non-display area surrounding the display area; a first semiconductor layer disposed in the non-display region on the substrate and including a polycrystalline semiconductor material; and a second semiconductor layer disposed in the display region on the substrate and including an oxide semiconductor material; a first gate insulating layer disposed on the first semiconductor layer and the second semiconductor layer; a first gate electrode and a second gate electrode disposed on the first gate insulating layer, the first gate electrode and the second gate electrode corresponding to the first semiconductor layer and the second semiconductor layer, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; A display device including a first source electrode and a first drain electrode arranged on the first interlayer insulating layer and respectively connected to both ends of the first semiconductor layer, and a second source electrode and a second drain electrode arranged on the first interlayer insulating layer and respectively connected to both ends of the second semiconductor layer.

2. The display device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer are in the same layer.

3. a first buffer layer disposed between the substrate and the first and second semiconductor layers; a second buffer layer, a second interlayer insulating layer, a first planarization layer, and a second planarization layer, which are sequentially disposed on the first interlayer insulating layer; a storage capacitor disposed between the first gate insulating layer and the second buffer layer; a light emitting diode disposed on the second planarization layer; The display device according to claim 2 , further comprising a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed on the light emitting diode.

4. a first gate extension electrode and a second gate extension electrode connected to the first gate electrode and the second gate electrode, respectively; a capacitor extension electrode connected to the storage capacitor, 4. The display device of claim 3, wherein the first gate extension electrode, the first source electrode, the first drain electrode, the second gate extension electrode, the second source electrode, and the second drain electrode are formed in a same layer and made of a same material on the second interlayer insulating layer.

5. The semiconductor device further includes a second gate insulating layer disposed on the entire surface of the first semiconductor layer, The display device according to claim 1 , wherein the second semiconductor layer is disposed on the second gate insulating layer.

6. The display device of claim 1 , further comprising a second gate insulating layer disposed above the first semiconductor layer and below the second semiconductor layer.

7. the first semiconductor layer and the second gate insulating layer on the first semiconductor layer have the same shape; The display device according to claim 6 , wherein the second semiconductor layer and the second gate insulating layer below the second semiconductor layer have the same shape.

8. a first gate extension electrode disposed on the first interlayer insulating layer and connected to a first gate electrode; and a second gate extension electrode disposed on the first interlayer insulating layer and connected to a second gate electrode; 2. The display device according to claim 1, wherein the first gate extension electrode, the first source electrode, the first drain electrode, the second gate extension electrode, the second source electrode, and the second drain electrode are formed in a same layer on the first interlayer insulating layer and from a same material.

9. a first buffer layer disposed between the substrate and the first and second semiconductor layers; a second buffer layer, a first planarization layer, and a second planarization layer sequentially disposed on the first interlayer insulating layer; a storage capacitor disposed between the first gate insulating layer and the second buffer layer; a light emitting diode disposed on the second planarization layer; The display device of claim 8 , further comprising a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed on the light emitting diode.

10. The semiconductor device further includes a first source extension electrode, a first drain extension electrode, a second source extension electrode, and a second drain extension electrode connected to the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, respectively; The display device according to claim 9 , wherein the first source extension electrode, the first drain extension electrode, the second source extension electrode, and the second drain extension electrode are formed in a same layer on the first planarization layer and made of a same material.

11. The display device of claim 10 , wherein the second source electrode is connected to the storage capacitor.

Images