Semiconductor device

Abstract

To reduce defects of a semiconductor device, such as defects of a shape and defects of characteristics, due to breakage, such as cracks, due to external stress, thereby to provide a highly reliable semiconductor device, and to improve manufacturing yield of a semiconductor device by reducing the defects also in a manufacturing process.SOLUTION: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By providing the impact resistance layer against external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably is low in elastic modulus and high in breaking modulus.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In semiconductor integrated circuit chips (also called IC chips), which are becoming smaller and thinner Therefore, it is important to increase its strength against external stress.

[0003] In order to improve the strength of the tip, various methods for reinforcing the tip have been proposed (see Patent Documents For example, in Patent Document 1, a chip is sandwiched between reinforcing metal plates and sealed with a sealing resin. A method of covering and curing has been reported. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-139802 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, when a reinforcing metal plate is provided as described above, the semiconductor device becomes thick and large. There is a problem.

[0006] Therefore, one aspect of the present invention is to provide a highly reliable sensor that has strength while achieving a reduction in thickness and size. Another object of the present invention is to provide a semiconductor device. An object of the present invention is to manufacture semiconductor devices with high yield while preventing defects in shape and characteristics. [Means for solving the problem]

[0007] A shock-resistant layer against external forces (also called external stress) applied to a semiconductor device, and The impact resistant layer and the impact diffusion layer are used to diffuse the impact force locally. This reduces the force required to prevent damage to semiconductor devices and poor characteristics. It becomes.

[0008] In the semiconductor device, a semiconductor integrated circuit is sandwiched between a pair of shock-resistant layers and a pair of shock-diffusing layers. The semiconductor integrated circuit is fabricated on a substrate, adhered to the shock-resistant layer, and peeled off from the substrate. In this specification, the semiconductor integrated circuit is peeled off from the substrate. The surface on which the path occurs is called the peeling surface. The peeling surface of a semiconductor integrated circuit is the shock diffusion layer (the second shock diffusion layer). The first surface is in contact with an impact-resistant layer (first impact-resistant layer), and the other surface is in contact with an impact-resistant layer (first impact-resistant layer). The shock diffusing layer is on the outside of the first shock resistant layer (the side opposite to the semiconductor integrated circuit), and the second shock resistant layer is on the outside of the second The shock diffusing layer is provided on the outer side (opposite side from the semiconductor integrated circuit).

[0009] In the semiconductor device, a semiconductor integrated circuit is sandwiched between a pair of shock-resistant layers, and shock-spreading is performed. The diffusion layer is provided in contact with the semiconductor integrated circuit. The first shock diffusing layer may be sandwiched between a pair of shock diffusing layers. The second shock resistant layer is on the outside of the second shock diffusing layer (the opposite side to the semiconductor integrated circuit). The conductor integrated circuit is located on the opposite side of the substrate.

[0010] The semiconductor integrated circuit is fabricated on a substrate, adhered to the impact resistant layer, and peeled off from the substrate. In the present invention, a surface on which a semiconductor integrated circuit is formed is formed by peeling the semiconductor integrated circuit from a substrate. The peeled surface of the semiconductor integrated circuit is in contact with the impact diffusion layer (second impact diffusion layer) and is called the peeled surface. One surface is provided in contact with an impact resistant layer (first impact resistant layer).

[0011] The impact-resistant layer may be a structure in which a fibrous body is impregnated with an organic resin. The layer preferably has an elastic modulus of 13 GPa or more and a modulus of rupture of less than 300 MPa.

[0012] It is preferable to use a material having a low elastic modulus and high breaking strength for the impact diffusion layer. A film with rubber elasticity should be used. The elastic modulus of the shock diffusion layer should be between 5 GPa and 12 GPa. The modulus of rupture is preferably 300 MPa or more.

[0013] The impact diffusion layer is preferably made of a high-strength material. Representative examples of high-strength materials include Polyvinyl alcohol resin, polyester resin, polyamide resin, polyethylene Aramid resin, polyparaphenylene benzobisoxazole resin, glass resin If an impact diffusion layer made of high-strength elastic material is provided, localized pressure and other Any load is spread and absorbed across the layers, preventing damage to the semiconductor device.

[0014] More specifically, the impact diffusion layer is made of aramid resin, polyethylene naphthalate (PEN ) resin, polyethersulfone (PES) resin, polyphenylene sulfide (PPS ) resin, polyimide (PI) resin, etc. can be used.

[0015] In this specification, the term "transfer" refers to a process in which a semiconductor integrated circuit formed on a certain substrate is transferred to a This means that the semiconductor integrated circuit is peeled off from the substrate and transferred to another substrate. This can also be said to move the circuit board to another circuit board.

[0016] One aspect of the semiconductor device of the present invention is a semiconductor device sandwiched between a pair of a first impact resistant layer and a second impact resistant layer. A semiconductor integrated circuit and an impact diffusion layer between the semiconductor integrated circuit and the second impact resistant layer, The diffusion layer has a lower elastic modulus and a higher breaking strength than the first impact resistant layer and the second impact resistant layer.

[0017] One aspect of the semiconductor device of the present invention is a semiconductor device sandwiched between a pair of a first impact resistant layer and a second impact resistant layer. a semiconductor integrated circuit; an impact diffusion layer between the semiconductor integrated circuit and the second impact resistant layer; The circuit has an adhesive layer between it and the shock diffusing layer, and the shock diffusing layer has a first shock resistant layer and a second shock resistant layer. It has a lower elastic modulus and higher breaking strength than the shock layer.

[0018] One aspect of the semiconductor device of the present invention is a semiconductor device sandwiched between a pair of a first impact resistant layer and a second impact resistant layer. a semiconductor integrated circuit; and a first shock diffusing layer on a surface of the first shock resistant layer opposite to the semiconductor integrated circuit; A second shock diffusing layer is provided between the semiconductor integrated circuit and the second shock resistant layer, and the first shock diffusing layer The second impact diffusion layer has a lower elastic modulus than the first impact resistant layer and the second impact resistant layer, and is resistant to breakage. High strength.

[0019] One aspect of the semiconductor device of the present invention is a semiconductor device sandwiched between a pair of a first impact resistant layer and a second impact resistant layer. a semiconductor integrated circuit; and a first shock diffusing layer on a surface of the first shock resistant layer opposite to the semiconductor integrated circuit; A second shock diffusing layer is provided between the semiconductor integrated circuit and the second shock resistant layer, and The first shock diffusing layer and the second shock diffusing layer have a first resistance and an adhesive layer between them. It has a lower elastic modulus and a higher breaking strength than the impact layer and the second impact resistant layer.

[0020] In the above structure, an antenna for receiving or transmitting a signal to or from the outside may be provided in the semiconductor device. For example, an antenna may be provided between the semiconductor integrated circuit and the first impact resistant layer. A protective layer may be provided over the integrated circuit, for example to cover an antenna provided on the integrated circuit. In this way, an inorganic insulating layer may be formed as a protective layer.

[0021] One embodiment of a method for manufacturing a semiconductor device of the present invention is a method for forming a semiconductor integrated circuit on a substrate via a peeling layer. A first impact resistant layer is bonded to the semiconductor integrated circuit, the semiconductor integrated circuit is peeled off from the substrate, and a second impact resistant layer is bonded to the semiconductor integrated circuit. The impact resistant layer and the impact diffusion layer of the second impact resistant layer are bonded to each other, and the impact diffusion layer bonded to the second impact resistant layer is attached to a substrate. The impact diffusion layer is bonded to the semiconductor integrated circuit that has been peeled off, and the impact diffusion layer is formed by the first impact resistant layer and the second impact resistant layer. It has a lower elastic modulus and a higher breaking strength than the layer.

[0022] One embodiment of a method for manufacturing a semiconductor device of the present invention is a method for forming a semiconductor integrated circuit on a substrate via a peeling layer. The first shock-resistant layer is bonded to the semiconductor integrated circuit by heat and pressure treatment, The path is peeled off from the substrate, and the second impact resistant layer and the impact diffusion layer are bonded together by heat and pressure treatment. The shock diffusing layer bonded to the second shock resistant layer is attached to the semiconductor integrated circuit peeled off from the substrate. The impact diffusion layer has a lower elastic modulus than the first impact resistant layer and the second impact resistant layer, High breaking strength.

[0023] One embodiment of a method for manufacturing a semiconductor device of the present invention is a method for forming a semiconductor integrated circuit on a substrate via a peeling layer. A first impact resistant layer is bonded to the semiconductor integrated circuit, and a first impact diffusion layer is bonded to the first impact resistant layer. The semiconductor integrated circuit is peeled off from the substrate, and the second impact resistant layer and the second impact diffusion layer are bonded to each other. The second shock diffusing layer bonded to the shock resistant layer of 2 is bonded to the semiconductor integrated circuit peeled off from the substrate. The first impact diffusion layer and the second impact diffusion layer are stronger than the first impact resistant layer and the second impact resistant layer. It has a low elastic modulus and high breaking strength.

[0024] One embodiment of a method for manufacturing a semiconductor device of the present invention is a method for forming a semiconductor integrated circuit on a substrate via a peeling layer. A first shock resistant layer is laminated on the semiconductor integrated circuit, and a first shock diffusion layer is laminated on the first shock resistant layer. Then, the semiconductor integrated circuit, the first shock resistant layer, and the first shock diffusion layer are bonded to each other by a heat and pressure treatment. The semiconductor integrated circuit is peeled off from the substrate, and the second impact resistant layer and the second impact diffusion layer are bonded to each other. The second shock diffusing layer is bonded to the second shock resistant layer by heat and pressure treatment, and the second shock diffusing layer is bonded to the second shock resistant layer by heat and pressure treatment. The semiconductor integrated circuit is bonded to the semiconductor integrated circuit by an adhesive layer, and a first shock diffusing layer and a second shock diffusing layer are formed. The diffusion layer has a lower elastic modulus and a higher breaking strength than the first impact resistant layer and the second impact resistant layer.

[0025] In the present invention, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to the use of the present invention to produce semiconductor elements (transistors, memory elements, diodes, etc.) It is possible to manufacture semiconductor devices such as devices having circuits and chips having processor circuits. can. Effect of the Invention

[0026] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit therebetween, and a semiconductor integrated circuit is laminated thereon. The impact diffusion layer allows for a thin, compact, and highly reliable semiconductor that is strong. In addition, defects in shape and characteristics can be prevented during the manufacturing process, and the yield can be improved. Therefore, a semiconductor device can be manufactured efficiently. [Brief description of the drawings]

[0027] [Figure 1] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 2] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C illustrate application examples of a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] FIG. 1 is a block diagram showing a configuration of a microprocessor obtained by using the semiconductor device. [Figure 13] FIG. 2 is a block diagram showing a configuration of an RFCP obtained by the semiconductor device. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 15] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 18] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 19] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 20] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 21] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 22] 1A to 1C illustrate a method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in the following manner. The present invention is not limited to the above-described embodiment. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. and the repeated explanation will be omitted.

[0029] (Embodiment 1) In this embodiment mode, a method for manufacturing a semiconductor device with higher reliability and a semiconductor device with high yield will be described. The method will be described in detail with reference to FIGS.

[0030] In the semiconductor device of this embodiment, the semiconductor integrated circuit is peeled off from the substrate during fabrication. The semiconductor integrated circuit is fabricated in the present specification. The substrate on which the semiconductor integrated circuit is formed is also called a production substrate. can be.

[0031] 1A and 1B show a semiconductor device according to this embodiment. The circuit 100 includes a first impact resistant layer 112, a second impact resistant layer 102, a first impact diffusion layer 113, The semiconductor integrated circuit 100 is sandwiched between the second shock diffusing layer 103 and the second shock resistant layer 10 The second impact diffusion layer 103 is provided between the first impact resistant layer 112 and the second impact resistant layer 113. The impact layer 102 is made of a structure in which a fiber body is impregnated with an organic resin, and the first impact resistant layer 11 2 is a structure in which a fibrous body 160 is impregnated with an organic resin 161, and the second impact resistant layer 102 is a fibrous body The structure is made by impregnating 150 with organic resin 151.

[0032] The peeled surface of the semiconductor integrated circuit 100 is in contact with the second shock diffusing layer 103, and the other surface is in contact with the first shock resistant layer 104. The first shock diffusing layer 113 is provided in contact with the first shock resistant layer 112. On the outer side (opposite the semiconductor integrated circuit 100), the second shock resistant layer 102 is 03 (opposite side to the semiconductor integrated circuit 100).

[0033] The top view of the fibrous body 160 is shown in FIG. 1(C) as a woven fabric made of fiber bundles as warp and weft yarns. .

[0034] As shown in FIG. 1C, the fibrous body 160 is made up of warp yarns spaced at regular intervals and The woven fabric is made of warp and weft yarns. Such a fibrous body 160 has an area where no weft yarn exists and an area where no weft yarn exists. This increases the proportion of the fibrous body 160 that is adhered to the semiconductor integrated circuit, thereby improving the adhesion between the fibrous body 160 and the semiconductor integrated circuit.

[0035] In addition, the fibrous body 160 has a high density of warp and weft yarns, and the ratio of the area where the warp and weft yarns are not present is It is also acceptable for the value to be low.

[0036] The structure in which the fibrous body 160 is impregnated with the organic resin 161 is also called a prepreg. Specifically, the leg is made by impregnating a fiber body with a varnish made by diluting a matrix resin with an organic solvent. After that, the organic solvent is evaporated by drying, and the matrix resin is semi-cured. The thickness of the film is preferably 10 μm or more and 100 μm or less, and more preferably 10 μm or more and 30 μm or less. By using a structure having such a thickness, a thin and bendable semiconductor device can be manufactured. The impact-resistant layer has an elastic modulus of 13 GPa or more and a modulus of rupture of less than 300 MPa. For example, the impact resistant layer has an elastic modulus of 13 GPa or more and 15 GPa or less, a modulus of rupture of 13 GPa or more and 15 GPa or less, and A prepreg of 140 MPa can be used.

[0037] The structure in which the fibrous body is impregnated with the organic resin may be laminated in multiple layers. The structure may be formed by stacking a plurality of structures in which a fibrous body of a layer is impregnated with an organic resin. Alternatively, a structure in which a plurality of laminated fibrous bodies are impregnated with an organic resin may be used. When stacking multiple structures in which the fibrous body of a layer is impregnated with an organic resin, another layer is sandwiched between each structure. It is also possible to do so.

[0038] As the organic resin 161, epoxy resin, unsaturated polyester resin, polyimide resin, Thermosetting resins such as bismaleimide triazine resins or cyanate resins can be used. Alternatively, the organic resin 161 may be a polyphenylene oxide resin, a polyetherimide resin, or the like. Thermoplastic resins such as fluororesins or organic resins can be used. As the organic resin, a plurality of the thermoplastic resins and the thermosetting resins may be used. By using the above, the fiber body can be fixed to the semiconductor integrated circuit by heat treatment. The higher the glass transition temperature of the organic resin 161, the more difficult it is to break due to local pressure, which is preferable. stomach.

[0039] A highly thermally conductive filler may be dispersed in the organic resin 161 or in the fiber bundle. Examples of conductive fillers include aluminum nitride, boron nitride, silicon nitride, and alumina. In addition, metal particles such as silver and copper are used as highly thermally conductive fillers. The presence of ruthenium in the organic resin or fiber bundles allows heat generated in the semiconductor integrated circuit to be released to the outside. Since the heat can be easily released, it is possible to suppress the heat accumulation in the semiconductor device, and the damage of the semiconductor device is prevented. This can reduce damage.

[0040] The fiber body 160 is a woven or nonwoven fabric made of high-strength fibers of organic or inorganic compounds. The high strength fibers are specifically those with a tensile modulus or A typical example of a high strength fiber is a polyvinyl alcohol fiber. Fibers, polyester fibers, polyamide fibers, polyethylene fibers, aramid fibers, Examples of the fiber include paraphenylene benzobisoxazole fiber, glass fiber, and carbon fiber. The glass fibers used are E glass, S glass, D glass, Q glass, etc. The fibrous body 160 may be formed of one type of the above-mentioned high strength fibers. It may also be formed from a plurality of the high strength fibers.

[0041] The fibrous body 160 is made of bundles of fibers (single yarns) (hereinafter referred to as yarn bundles) as warp and weft yarns. Woven fabric or nonwoven fabric made by stacking yarn bundles of multiple types of fibers randomly or in one direction. In the case of woven fabric, plain weave, twill weave, satin weave, etc. can be used appropriately.

[0042] The cross section of the yarn bundle may be circular or elliptical. Fiber yarn that has been opened and processed by high-frequency vibration, continuous ultrasonic vibration, pressing with a roll, etc. A bundle of fiber yarns that has been opened has a wider bundle width and a smaller number of single yarns in the thickness direction. It is possible to reduce the cross section of the yarn bundle to an elliptical or flat shape. By using low twist yarn, the yarn bundle is easily flattened, and the cross-sectional shape of the yarn bundle becomes elliptical or flat. In this way, by using a yarn bundle having an elliptical or flat cross section, the fiber body 16 Therefore, it is possible to make the structure thinner, and A semiconductor device can be manufactured.

[0043] In the drawings of this embodiment, the fibrous body 160 is plain woven with yarn bundles having an elliptical cross section. The material is shown in woven fabric.

[0044] In order to increase the penetration rate of the organic resin into the fiber bundle, the fiber may be subjected to a surface treatment. For example, corona discharge treatment and plasma discharge treatment are used to activate the fiber surface. In addition, surface treatments using silane coupling agents and titanate coupling agents are also available.

[0045] In addition, the impact diffusion layer (the first impact diffusion layer and the second impact diffusion layer) has a low elastic modulus, It is also preferable to use a material with high breaking strength, and a film having rubber elasticity may be used. The impact diffusion layer preferably has an elastic modulus of 5 GPa or more and 12 GPa or less and a modulus of rupture of 300 MPa or more. stomach.

[0046] The impact diffusion layer is preferably made of a high-strength material. Representative examples of high-strength materials include Polyvinyl alcohol resin, polyester resin, polyamide resin, polyethylene Aramid resin, polyparaphenylene benzobisoxazole resin, glass resin If an impact diffusion layer made of high-strength elastic material is provided, localized pressure and other Any load is spread and absorbed across the layers, preventing damage to the semiconductor device.

[0047] More specifically, the impact diffusion layer is made of aramid resin, polyethylene naphthalate (PEN ) resin, polyethersulfone (PES) resin, polyphenylene sulfide (PPS In this embodiment, the impact expansion Aramid resin film (elastic modulus 10GPa, breaking strength 480MPa) is used as the scattering layer. .

[0048] FIG. 1B shows a semiconductor integrated circuit 100 and a second shock diffusing layer 103 bonded together using an adhesive layer 104. 2. An example in which the first impact resistant layer 112 and the first impact diffusion layer 113 are fixed to each other by an adhesive layer 114. In this embodiment, an aramid film is used as the second impact diffusion layer 103, and the adhesive The adhesive layer 104 is made of acrylic resin. The adhesive layer 104 is connected to the shock diffusing layer and the semiconductor integrated circuit. It is sufficient to be able to bond the material, and it can be made of thermosetting resin, ultraviolet curing resin, acrylic resin, urethane, etc. The first impact resistant material can be a fluororesin, epoxy resin, silicone resin, or the like. When the layer 112 and the first shock diffusing layer 113 are bonded by heat and pressure treatment, the adhesive layer It is not necessary to use 114. The adhesive layer may have a thickness of about 3 μm to 15 μm.

[0049] A protective layer may be formed on the semiconductor integrated circuit. An example in which an inorganic insulating layer 105 is formed as a protective layer on the insulating film 100 is shown. An antenna 101 is formed on a semiconductor integrated circuit 100, and an inorganic insulating layer 1 is formed on the antenna 101. In this example, an inorganic insulating layer 105 is formed on the antenna 101. This can prevent the conductive layer, which functions as a tena, from being oxidized.

[0050] The inorganic insulating layer 105 is formed by a method such as sputtering, plasma CVD, coating, or printing. The insulating layer is formed in a single layer or a multilayer structure using an inorganic compound. A typical example of the inorganic compound is silicon oxide. Representative examples of silicon oxides and silicon nitrides include silicon oxide, Examples of such materials include silicon oxynitride, silicon nitride, and silicon nitride oxide.

[0051] Furthermore, the inorganic insulating layer 105 may have a stacked structure. For example, Typically, silicon oxide, silicon nitride oxide, and silicon oxynitride are stacked. That's fine.

[0052] A method for manufacturing a semiconductor device will be described with reference to FIGS. A semiconductor integrated circuit 100 is formed on a substrate 110 having a surface with a release layer 111 interposed therebetween (FIG. 3). See (A). ).

[0053] The substrate 110 used for the fabrication may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or the like. A metal substrate having an insulating layer formed on its surface can be used. A plastic substrate having heat resistance capable of withstanding the processing temperature of the semiconductor device may be used. In the manufacturing process, a manufacturing substrate can be appropriately selected depending on the process to be performed.

[0054] The peeling layer 111 is formed by sputtering, plasma CVD, coating, printing, or the like. W, Molybdenum (Mo), Titanium (Ti), Tantalum (Ta), Niobium (N b), Nickel (Ni), Cobalt (Co), Zirconium (Zr), Zinc (Zn), Ru Ruthenium (Ru), Rhodium (Rh), Palladium (Pd), Osmium (Os), Iridium (Ir) an element selected from the group consisting of iridium (Ir) and silicon (Si), or an alloy material mainly composed of such an element; Alternatively, a layer made of a compound material containing the above element as a main component is formed as a single layer or a laminated layer. The crystal structure of the layer containing may be any of amorphous, microcrystalline, and polycrystalline. The coating method includes a spin coating method, a droplet ejection method, and a dispense method.

[0055] When the release layer 111 has a single-layer structure, it is preferably a tungsten layer, a molybdenum layer, or a tungsten layer. A layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or a layer containing an oxynitride, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. A mixture of tungsten and molybdenum corresponds, for example, to an alloy of tungsten and molybdenum. do.

[0056] When the peeling layer 111 has a laminated structure, it is preferable that the first layer is a tungsten layer, the second layer is a molybdenum layer, and the third layer is a tungsten layer. A layer containing tungsten or a layer containing a mixture of tungsten and molybdenum is formed, and a second layer containing tungsten Oxides, nitrides, and oxynitrides of tungsten, molybdenum, or mixtures of tungsten and molybdenum Or, a nitride oxide is formed.

[0057] The peeling layer 111 has a stacked structure of a layer containing tungsten and a layer containing an oxide of tungsten. In the case of forming a tungsten-containing layer, an insulating layer made of oxide is formed on the tungsten-containing layer. By forming a layer containing tungsten oxide at the interface between the tungsten layer and the insulating layer, Furthermore, the surface of the tungsten-containing layer may be thermally oxidized. Treatment with oxygen plasma, ozone water or other highly oxidizing solutions to remove tungsten. In addition, the plasma treatment or the heat treatment may be performed by using oxygen, nitrogen, or other organic compounds. Nitrous oxide, nitrous oxide alone, or a mixture of these gases with other gases This may be done by forming layers containing tungsten nitride, oxynitride and oxynitride. The same applies when forming a tungsten-containing layer, and then a silicon nitride layer and an oxide layer are formed on the tungsten-containing layer. A silicon nitride layer or a silicon nitride oxide layer may be formed.

[0058] In addition, according to the above process, the release layer 111 is formed so as to be in contact with the substrate 110. The process is not limited to this. An insulating layer is formed as a base so as to contact the substrate 110, and the insulating layer is A release layer 111 may be provided adjacent the edge layer.

[0059] The semiconductor integrated circuit 100 and the first impact resistant layer 112 are bonded together, and the semiconductor integrated circuit is then separated from the first impact resistant layer 112 by using a release layer 111. The semiconductor integrated circuit 100 is peeled off from the substrate 110. Thus, the semiconductor integrated circuit 100 is It is provided on the layer 112 side (see FIG. 3(B)).

[0060] In this embodiment, the first impact resistant layer 112 is formed by impregnating a fibrous body 160 with an organic resin 161. The structure is heated and compressed to plasticize or harden the organic resin of the structure. If the organic resin is a plastic organic resin, it is then plasticized by cooling to room temperature. The organic resin is then cured by heating and pressing so that it adheres closely to the semiconductor integrated circuit. The process of compressing the structure is carried out under atmospheric pressure or reduced pressure. cormorant.

[0061] In the transfer process to another substrate, a separation layer is formed between the substrate and the semiconductor integrated circuit. A metal oxide film is provided between the semiconductor integrated circuit and the metal oxide film is weakened by crystallization, The method for peeling off the semiconductor integrated circuit, and removing the amorphous silicon film by irradiation with laser light or etching. A method for peeling off the semiconductor integrated circuit by forming a peeling layer between the substrate and the semiconductor integrated circuit. A metal oxide film is formed between the peeling layer and the semiconductor integrated circuit, and the metal oxide film is crystallized. The peeling layer becomes weaker and part of it is dissolved in the solution or NF. 3 ,BrF 3 , ClF 3 Fluorinated halogen gases such as After etching with a laser, the weakened metal oxide film is peeled off. The substrate on which the integrated circuit is formed is mechanically removed or the solution or NF 3 ,BrF 3 , ClF 3 etc. A method of removing the insulating layer by etching with halogen fluoride gas can be appropriately used. As a peeling layer, a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silicon film containing hydrogen, The peeling layer is irradiated with laser light to remove the oxygen contained in the peeling layer. This method releases nitrogen, oxygen, or hydrogen as gas to promote peeling between the semiconductor integrated circuit and the substrate. may also be used.

[0062] By combining the above peeling methods, the transposition process can be carried out more easily. irradiation of the light, etching of the peeling layer with gas or solution, or cutting with a sharp knife or scalpel Mechanical removal is performed to make it easier to separate the release layer from the semiconductor integrated circuit, and then Peeling can also be achieved by applying a gentle force (mechanically, etc.).

[0063] In addition, a liquid is permeated into the interface between the release layer and the semiconductor integrated circuit, so that the semiconductor integrated circuit is removed from the production substrate. may be peeled off.

[0064] The second impact-resistant layer 102 is similar to the first impact-resistant layer 112 in that the organic resin 151 is attached to the fibrous body 150. The impregnated structure is used. The structure is heated and pressed to form the second impact diffusion layer 103 and the second The impact resistant layer 102 is bonded to the opposite surface of the second impact diffusing layer 103. An adhesive layer 104 is provided.

[0065] An adhesive layer 104 is attached to the exposed peelable surface of the semiconductor integrated circuit 100, and a first impact resistant layer 1 The semiconductor integrated circuit 100 and the second shock diffusing layer 102 are sandwiched between the first shock resistant layer 102 and the second shock diffusing layer 104. A semiconductor device having the layer 103 can be manufactured (see FIG. 3C).

[0066] Furthermore, the first impact-resistant layer 112 is attached to the opposite side of the semiconductor integrated circuit 100 by using an adhesive layer 114. The first shock diffusing layer 113 is adhered (see FIG. 3(D)).

[0067] As shown in FIGS. 16A to 16C, the first shock diffusing layer 113 is disposed on the first shock resistant layer 11. 2 and the semiconductor integrated circuit 100 are bonded to the first impact resistant layer 112 at the same time. It is okay.

[0068] As shown in FIG. 3A, a substrate 110 having an insulating surface is formed on the substrate 110 via a peeling layer 111. A semiconductor integrated circuit 100 is formed (see FIG. 16(A)).

[0069] A first shock resistant layer 112 and a first shock diffusing layer 113 are laminated on the semiconductor integrated circuit 100, By performing the heat and pressure treatment, the first impact resistant layer 112 is formed on the semiconductor integrated circuit 100. Then, a first shock diffusing layer 113 is bonded to the substrate 110, and the first shock diffusing layer 113 is peeled off from the substrate 110 using a peeling layer 111 (FIG. 16(B). A bonding process between the semiconductor integrated circuit 100 and the first impact resistant layer 112, The bonding process of the impact resistant layer 112 and the first impact diffusion layer 113 may be performed simultaneously or separately. It may be done in about

[0070] A second shock resistant layer 102 is laminated on the peeled surface of the semiconductor integrated circuit 100 to form a second shock diffusing layer. 103 is bonded using an adhesive layer 104 to produce a semiconductor device (see FIG. 16(C)). .

[0071] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0072] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit and a pair of shock-diffusing layers are used to reduce thickness and It is possible to provide a semiconductor device having high strength and high reliability while achieving miniaturization.

[0073] (Embodiment 2) In this embodiment mode, a method for manufacturing a semiconductor device with higher reliability and a semiconductor device with high yield will be described. 4 and 5. In this embodiment, a semiconductor device CMOS (Complementary Metal Oxide Semiconductor) This article explains about ide Semiconductor.

[0074] A peeling layer 201 and a base insulating layer 202 are formed on a substrate 200 having an insulating surface, which is a substrate to be fabricated. Then, transistors 210 and 211, an insulating film 212, an insulating film 213, and an insulating layer 214 are provided. Thus, a semiconductor integrated circuit 250 is formed (see FIG. 4(A)).

[0075] The transistor 210 is a thin film transistor, and includes a source or drain region 224a, 224b, which is a lower concentration impurity region than the source or drain regions 224a and 224b. Impurity regions 223a and 223b, a channel forming region 226, a gate insulating layer 227, a gate The electrode layer 228 and the insulating layers 229a and 229b having sidewall structures are included. The drain regions 224a and 224b are wirings that function as source and drain electrode layers. The layers 230a and 230b are in contact with each other and electrically connected to each other. 210 is a p-channel thin film transistor, which has a source or drain region 224a, 224b, impurity region 22 which is an LDD (Lightly Doped Drain) region 3a, 223b are doped with impurity elements that give p-type conductivity (e.g., boron (B) or aluminum (Al ) and gallium (Ga, etc.).

[0076] The transistor 211 is a thin film transistor, and has a source or drain region 204a, 204b, which is a lower concentration impurity region than the source or drain regions 204a and 204b. Impurity regions 203a and 203b, a channel forming region 206, a gate insulating layer 207, a gate The electrode layer 208 and the insulating layers 209a and 209b having sidewall structures are included. The drain regions 204a and 204b are wirings that function as source and drain electrode layers. The layers 210a and 210b are in contact with each other and electrically connected to each other. 211 is an n-channel thin film transistor, and has a source region or drain region 204a, 204b, an impurity element that imparts n-type to the impurity regions 203a and 203b, which are LDD regions; (e.g. phosphorus (P) and arsenic (As), etc.).

[0077] The first impact resistant layer 262 is a structure in which a fibrous body 280 is impregnated with an organic resin 281. The semiconductor integrated circuit 250 and the first impact resistant layer 262 are bonded together, and the semiconductor integrated circuit 250 is then bonded to the first impact resistant layer 262 using the release layer 201. The semiconductor integrated circuit 250 is peeled off from the substrate 200. It is provided on the impact layer 262 side (see FIGS. 4(B) and (C)).

[0078] The second impact-resistant layer 252 is similar to the first impact-resistant layer 262 in that the organic resin 271 is attached to the fibrous body 270. The impregnated structure is used. The structure is heated and pressed to form the second shock diffusing layer 253 and the second The impact-resistant layer 252 is bonded (see FIG. 5(A)). The first impact-resistant layer 253 of the second impact diffusion layer 253 is bonded (see FIG. 5(B)). The opposite surface of the impact layer 252 is provided with an adhesive layer 254 .

[0079] An adhesive layer 254 is attached to the exposed peeled surface of the semiconductor integrated circuit 250 (see FIG. 5(B)). In addition, a first shock diffusing layer 262 is formed on the opposite side of the semiconductor integrated circuit 250 of the first shock resistant layer 262. The layer 263 is bonded using an adhesive layer 264, and the first impact resistant layer 262 and the second impact resistant layer 252 are bonded using an adhesive layer 264. The semiconductor integrated circuit 2 is sandwiched between the first shock diffusing layer 263 and the second shock diffusing layer 253. A semiconductor device having the structure 50 can be manufactured (see FIG. 5C).

[0080] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0081] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit therebetween, and a semiconductor integrated circuit is laminated thereon. The impact diffusion layer allows for a thin, compact, and highly reliable semiconductor that is strong. An apparatus can be provided.

[0082] The semiconductor device manufactured in this embodiment uses a flexible impact resistant layer and an impact diffusion layer. In this way, a flexible semiconductor device can be obtained.

[0083] The semiconductor layers of the transistors 210 and 211 are formed of a material other than silane or germanium. Amorphous (Al) semiconductors are produced by vapor phase epitaxy or sputtering using the semiconductor material gases shown in the table. Amorphous semiconductors, hereafter referred to as "AS", are semiconductors that are converted into amorphous semiconductors by light energy or thermal energy. Polycrystalline semiconductors crystallized using electrons, or microcrystalline (semi-amorphous or Also called microcrystals. Hereinafter referred to as "SAS".) Using semiconductors, etc. The semiconductor layer is formed by sputtering, LPCVD, plasma CVD, etc. It is possible.

[0084] Microcrystalline semiconductors are metastable, intermediate between amorphous and single crystal, when considering the Gibbs free energy. In other words, a semiconductor that has a third state that is stable in terms of free energy The crystals are of a short-range order and have lattice distortion. Microcrystalline silicon, a typical example of a microcrystalline semiconductor, is a type of Raman The spectrum shows single crystal silicon at 520 cm -1 It is shifted to the lower wavenumber side. That is, 520 cm, which indicates single crystal silicon.-1 and 480 cm, which indicates amorphous silicon. - 1 The Raman spectrum of microcrystalline silicon has a peak between the two. Contains at least 1 atomic % or more of hydrogen or halogen to terminate the ring bonds. In addition, it contains rare gas elements such as helium, argon, krypton, and neon. By further promoting the lattice distortion, the stability is increased and a good microcrystalline semiconductor layer can be obtained. .

[0085] This microcrystalline semiconductor layer is formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz. Alternatively, it can be formed by a microwave plasma CVD apparatus with a frequency of 1 GHz or more. Representative examples include SiH 4 , Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , S iF 4 The hydrogenated silicon can be diluted with hydrogen to form the silicon hydride. In addition to hydrogen, one or more of the following gases are selected: helium, argon, krypton, and neon A microcrystalline semiconductor layer can be formed by diluting the silicon hydride with a rare gas element. The flow rate ratio of hydrogen to nitrogen is 5 to 200 times, preferably 50 to 150 times. More preferably, it is set to 100 times.

[0086] Representative examples of amorphous semiconductors include hydrogenated amorphous silicon and crystalline semiconductors. A typical example is polysilicon. Polysilicon (polycrystalline silicon) has the following features: The so-called "polysilicon-based" semiconductor is formed at a process temperature of 800°C or higher. The main materials are high-temperature polysilicon and polysilicon formed at process temperatures below 600°C. The so-called low-temperature polysilicon is used as a material for the crystallization of amorphous silicon. Of course, as mentioned above, it contains microcrystalline polysilicon. A semiconductor or a semiconductor layer that includes a crystalline phase in part can also be used.

[0087] In addition, semiconductor materials include elements such as silicon (Si) and germanium (Ge), Compound semiconductors such as GaAs, InP, SiC, ZnSe, GaN, and SiGe are also used. In addition, zinc oxide (ZnO) and tin oxide (SnO 2 ) When ZnO is used for the semiconductor layer, the gate insulating layer is made of Y. 2 O 3 , A l 2 O 3 , TiO 2 , and a laminate thereof may be used. The drain electrode layer may be made of ITO, Au, Ti, or the like. It is also possible to add elements such as Ga.

[0088] When a crystalline semiconductor layer is used as the semiconductor layer, the method for manufacturing the crystalline semiconductor layer can be various. Methods (laser crystallization, thermal crystallization, or methods using elements that promote crystallization such as nickel) In addition, the SAS microcrystalline semiconductor can be irradiated with laser to form a crystal. If no element that promotes crystallization is introduced, the material will be amorphous. Before irradiating the silicon layer with laser light, the layer was heated at 500°C for 1 hour in a nitrogen atmosphere. The hydrogen concentration in the amorphous silicon layer is 1×10 20 atoms / cm 3Release to the following: This is because when a hydrogen-rich amorphous silicon layer is irradiated with laser light, the amorphous silicon layer is destroyed. Because it will be put away.

[0089] The method of introducing a metal element into an amorphous semiconductor layer is to deposit the metal element on the surface of the amorphous semiconductor layer. There is no particular limitation as long as the method can make the surface or interior of the material present thereon. For example, sputtering, CVD, etc. method, plasma treatment method (including plasma CVD method), adsorption method, method of applying a solution of metal salts Among these, the method using a solution is simple and easy, and the concentration of the metal element can be adjusted. In addition, the wettability of the surface of the amorphous semiconductor layer is improved. In order to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, UV light was applied in an oxygen atmosphere. by irradiation, thermal oxidation, or treatment with ozone water or hydrogen peroxide containing hydroxyl radicals. It is preferable to form an oxide film on the silicon substrate.

[0090] In addition, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, The crystallization-promoting element (also called catalytic element or metallic element) is added to the layer, and the layer is heat-treated (550 Crystallization may be performed by heating at 50°C to 750°C for 3 minutes to 24 hours. The elements that can be used are iron (Fe), nickel (Ni), cobalt (Co), and ruthenium (Ru ), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) , platinum (Pt), copper (Cu) and gold (Au) can be done.

[0091] In order to remove or reduce the element that promotes crystallization from the crystalline semiconductor layer, A semiconductor layer containing an impurity element is formed in contact with the substrate and functions as a gettering sink. As for the pure elements, impurity elements that give n-type, impurity elements that give p-type, and rare gas elements For example, phosphorus (P), nitrogen (N), arsenic (As), antimony ( Sb), Bismuth (Bi), Boron (B), Helium (He), Neon (Ne), Argon (Ar) One or more of the following elements are used: Ar (Ar), Kr (Krypton), and Xe (Xenon) A semiconductor layer containing a rare gas element may be formed on a crystalline semiconductor layer containing an element that promotes crystallization. A conductor layer is formed and heat treatment is performed (at 550°C to 750°C for 3 minutes to 24 hours). Crystalline semiconductor The elements contained in the layer that promote crystallization move into the semiconductor layer containing the rare gas element, and crystallization is promoted. The elements that promote crystallization in the semiconductor layer are removed or reduced. The semiconductor layer containing the rare gas element that has become a mask is then removed.

[0092] The crystallization of the amorphous semiconductor layer may be performed by combining a heat treatment and crystallization by laser light irradiation. The heat treatment or the laser light irradiation may be performed alone a plurality of times.

[0093] The crystalline semiconductor layer may be formed directly on the substrate by a plasma method. A crystalline semiconductor layer may be selectively formed on a substrate by using the method.

[0094] The gate insulating layers 207 and 227 are formed of silicon oxide or a laminated structure of silicon oxide and silicon nitride. The gate insulating layers 207 and 227 are formed by forming an insulating film by a plasma CVD method or a low pressure CVD method. The insulating film may be formed by depositing an insulating film, or by solid-phase oxidation or solid-phase nitridation using plasma treatment. The single crystal semiconductor layer is preferably formed by oxidizing or nitriding the single crystal semiconductor layer through plasma treatment. This is because the gate insulating layer formed is dense, has a high dielectric strength, and is highly reliable. For example, , nitrous oxide (N 2 O) is diluted 1 to 3 times (flow ratio) with Ar and the pressure is 10 to 30 Pa. The surface of the semiconductor layer was oxidized or heated by applying microwave (2.45 GHz) power of 3 to 5 kW at 400 K. This treatment reduces the insulating film thickness to 1 nm to 10 nm (preferably 2 nm to 6 nm). It also forms a membrane that absorbs nitrous oxide (N 2 O) and silane (SiH 4 ) and 10~3 Vapor growth method using 3 to 5 kW microwave (2.45 GHz) power at 0 Pa pressure A silicon oxynitride film is formed by solid-phase reaction and vapor phase growth to form a gate insulating layer. By combining the above reactions, a gate insulating layer with low interface state density and excellent dielectric strength can be created. It can be formed.

[0095] The gate insulating layers 207 and 227 may be made of zirconium dioxide, hafnium oxide, or titanium dioxide. Alternatively, a high dielectric constant material such as titanium oxide or tantalum pentoxide may be used. By using a high dielectric constant material for 27, the gate leakage current can be reduced.

[0096] The gate electrode layers 208 and 228 are formed by using a CVD method, a sputtering method, a droplet discharge method, or the like. The gate electrode layer can be made of Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, Selected from W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, and Ba. The insulating layer 11 may be made of an element, or an alloy or compound material containing the element as a main component. Semiconductor films, such as polycrystalline silicon films doped with impurity elements such as phosphorus, and Ag A PdCu alloy may be used. The structure may be a single layer or a multi-layer structure. For example, nitride It may have a two-layer structure of a tungsten film and a molybdenum film, or a tungsten film with a thickness of 50 nm. a 500 nm thick aluminum-silicon alloy (Al-Si) film; The titanium nitride film may be laminated in this order to form a three-layer structure. Tungsten may be used instead of tungsten in the first conductive film, and tungsten nitride may be used instead of tungsten in the second conductive film. Instead of an alloy of aluminum and silicon (Al-Si) film, an alloy of aluminum and titanium ( Alternatively, a titanium film may be used instead of the titanium nitride film of the third conductive film. Good too.

[0097] The gate electrode layers 208 and 228 are made of a light-transmitting material that transmits visible light. The transparent conductive material includes indium tin oxide (ITO) and silicon oxide. Use indium tin oxide (ITSO), organic indium, organic tin, zinc oxide, etc. In addition, indium zinc oxide (IZO) containing zinc oxide (ZnO) can be used. Zinc Oxide), zinc oxide (ZnO), ZnO doped with gallium (Ga) tin oxide (SnO 2 ), indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing ingested indium, indium oxide containing titanium oxide, titanium oxide Indium tin oxide containing indium may also be used.

[0098] When etching is required to form the gate electrode layers 208 and 228, a mask Then, the ICP( Induatively Coupled Plasma Etch The etching conditions (power applied to the coil-type electrode, power applied to the electrode on the substrate side) were By appropriately adjusting the amount of power applied, the temperature of the electrode on the substrate side, etc., the electrode layer can be tapered. The etching gas is Cl 2 , BCl 3 , SiCl 4 Or CCl 4 Chlorine gases such as CF 4 ,SCIENCE FICTION 6 Or N F 3 Fluorine gases such as O 2 can be used appropriately.

[0099] The insulating layers 209a, 209b, 229a, and 229b are insulating layers that cover the gate electrode layer and the semiconductor layer. After forming the layer, it is etched by RIE (Reactive Ion Etching). The sidewall is processed in a self-aligned manner by anisotropic etching using the on-etching method. Insulating layers 209a, 209b, 229a, and 229b having a hexagonal structure may be formed. There is no particular limitation on the border layer, and TEOS (Tetra-Ethyl-Ortho-Sil icate) or silane, etc., reacted with oxygen or nitrous oxide, etc. The insulating layer is preferably silicon oxide, which has good coating properties. It can be formed by methods such as pressure CVD, bias ECRCVD, and sputtering. do.

[0100] In this embodiment, a single gate structure has been described, but a multi-gate structure such as a double gate structure may also be used. In this case, a gate electrode layer may be provided above and below the semiconductor layer. Alternatively, a structure in which a plurality of gate electrode layers are provided on only one side (upper or lower) of a semiconductor layer may be used.

[0101] Also, a structure in which silicide is provided in the source and drain regions of the transistor may be used. Silicide is formed by forming a conductive film on the source and drain regions of a semiconductor layer and then subjecting the conductive film to a heat treatment. , GRTA method, LRTA method, etc., the semiconductor layer of the exposed source region and drain region The silicon in the film reacts with the conductive film. The silicon is formed by irradiating it with a laser or lamp light. The conductive film for forming the silicide may be made of titanium (Ti ), Nickel (Ni), Tungsten (W), Molybdenum (Mo), Cobalt (Co), Zirconium (Zr), Hf (Hafnium), Tantalum (Ta), Vanadium (V), Nb (niobium), chromium (chromium), platinum (platinum), palladium (palladium), etc. can be used. can.

[0102] Wiring layers 210a, 210b, and 230a functioning as source and drain electrode layers. 230b is a film formed by a PVD method, a CVD method, a deposition method, etc., and then etched into a desired shape. Alternatively, the predetermined area can be formed by printing, electrolytic plating, etc. Furthermore, a reflow method or a damascene method may be used. The materials of the wiring layers 210a, 210b, 230a, and 230b are Ag, Au, Cu, Ni, etc. , Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, B It is formed by using metals such as a, semiconductors such as Si and Ge, or alloys thereof, or nitrides thereof. Also, a light-transmitting material may be used.

[0103] In addition, transparent conductive materials include indium tin oxide (ITO) and indium oxide containing silicon oxide. Indium tin oxide (ITSO), indium zinc oxide (IZO) O(indium zinc oxide), zinc oxide (ZnO), ZnO with gallium (Ga) doped, tin oxide (SnO 2 ), indium oxide with tungsten Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, etc. can be used.

[0104] The insulating films 212, 213, and 214 are made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. Aluminum, aluminum nitride, aluminum oxide nitride and other inorganic insulating materials can be used. Cut.

[0105] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0106] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit and a pair of shock-diffusing layers are used to reduce thickness and It is possible to provide a semiconductor device having high strength and high reliability while achieving miniaturization.

[0107] One embodiment of the semiconductor device of the present invention is a semiconductor element including, of course, a field effect transistor, It can also be used for memory elements that use semiconductor layers, providing functions required for a wide range of applications. It is possible to manufacture and provide a semiconductor device that satisfies the requirements.

[0108] (Embodiment 3) In this embodiment, a semiconductor device is provided with the objective of achieving higher integration, thinner size, and smaller size. FIG. 1 is a diagram showing an example of a semiconductor device having a memory in a semiconductor device manufacturing method. 6 to 8.

[0109] The semiconductor device of this embodiment includes a memory cell array and a memory cell driving circuit for driving the memory cell array. It has a drive circuit section.

[0110] A release layer 301 is formed on a substrate 300, which is a substrate to be prepared having an insulating surface. An insulating film 302 serving as a base film is formed thereon.

[0111] Next, a semiconductor film is formed on the insulating film 302. The semiconductor film has a thickness of 25 to 200 nm (preferably The thickness is 30 to 150 nm and the method is (sputtering, LPCVD, or plasma CVD) The film may be formed by a method such as a method for forming a thin film.

[0112] In this embodiment mode, an amorphous semiconductor film is formed over the insulating film 302. By crystallizing the semiconductor film, a crystalline semiconductor film is formed.

[0113] The threshold voltage of a thin film transistor is controlled for the semiconductor film thus obtained. To achieve this, a small amount of impurity element (boron or phosphorus) is selectively doped. The doping of the element may be performed on the amorphous semiconductor film before the crystallization process. When impurity elements are doped in the crystalline state, the intrinsic It is also possible to activate the pure material. It is also possible to improve defects that occur during doping. can be done.

[0114] Next, the semiconductor film is processed into a desired shape using a mask. After removing the oxide film that was formed, a new oxide film is formed. Then, a photomask is created. Then, the semiconductor layers 303, 304, 305, 306 is formed. An inclination angle (taper angle) may be provided at the end of the semiconductor layer.

[0115] Etching is done by plasma etching (dry etching) or wet etching. Either method may be used, but plasma etching is more suitable for processing large-area substrates. The etching gas is CF 4 , N.F. 3 , Cl 2 , BCl 3 Fluorine-based compounds or salts thereof An inert gas such as He or Ar may be added as appropriate. By applying this etching process, localized discharge machining is also possible. There is no need to form it.

[0116] An insulating film 310 is formed on the semiconductor layer 305. The insulating film 310 is made of silicon oxide or The insulating film 310 may be formed by a layered structure of silicon and silicon nitride. The insulating layer may be deposited by a plasma deposition method or a low pressure CVD method. It is preferable to form the semiconductor layer (typically silicon) by solid-phase oxidation or solid-phase nitridation. The insulating layer formed by oxidizing or nitriding the insulating layer (layer) by plasma treatment is dense and insulating. This is because the insulating film 310 has a high withstand voltage and is excellent in reliability. Since it is used as a tunnel insulating layer for implantation, such a strong material is preferable. The insulating film 310 is formed to a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm. is preferred.

[0117] An example of a suitable insulating film 310 formed by plasma processing is a plasma processing in an oxidizing atmosphere. A silicon oxide layer with a thickness of 3 nm to 6 nm is formed on the semiconductor layer by a process, and then the silicon oxide layer is etched under a nitrogen atmosphere. The surface of the silicon oxide layer is treated with nitriding plasma to form a nitrogen plasma treated layer. Specifically, first, a 3-6 nm thick film is formed on the semiconductor layer by plasma treatment in an oxygen atmosphere. Then, a silicon oxide layer is formed by performing a plasma treatment in a nitrogen atmosphere. A nitrogen plasma-treated layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer. The vicinity of the surface refers to a depth of approximately 0.5 nm to 1.5 nm from the surface of the silicon oxide layer. For example, By performing plasma treatment in a nitrogen atmosphere, the silicon oxide layer was formed to a depth of approximately 1 nm from the surface. Furthermore, the structure contains nitrogen at a ratio of 20 to 50 atomic %.

[0118] By oxidizing the surface of a silicon layer, which is a typical example of a semiconductor layer, by plasma treatment, the interface is free of distortion. In addition, the oxide layer can be nitrided by plasma treatment. By replacing oxygen in the surface layer with nitrogen to form a nitride layer, the material can be made even denser. This makes it possible to form an insulating layer with high dielectric strength.

[0119] In any case, the solid-phase oxidation treatment or solid-phase nitriding treatment by the plasma treatment as described above is By using this, even if a glass substrate with a heat resistance of 700℃ or less is used, the temperature can be increased to 950℃ to 1050℃. In other words, it is possible to obtain an insulating layer equivalent to the thermal oxide film formed by the non-volatile memory element. As a result, a highly reliable tunnel insulating layer can be formed as the tunnel insulating layer of the semiconductor device.

[0120] A charge storage layer 311 is formed on the insulating film 310. This charge storage layer 311 may be a single layer. Alternatively, a plurality of layers may be laminated.

[0121] The charge storage layer 311 is a floating gate formed of a layer or particles of a semiconductor material or a conductive material. Semiconductor materials include silicon and silicon germanium. When silicon is used, amorphous silicon or polysilicon can be used. Furthermore, phosphorus-doped polysilicon can be used. consists of tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W). Selected elements, alloys mainly composed of the above elements, alloy films combining the above elements (representatively If the film is made of Mo-W alloy film, Mo-Ta alloy film, or a silicon film with electrical conductivity, Under the conductive layer made of such materials, tantalum nitride, tungsten nitride, titanium nitride, Tungsten, nitrides such as molybdenum nitride, tungsten silicide, titanium silicide, moly Silicide such as buten silicide may be formed. Alternatively, a laminated structure of conductive materials or a laminated structure of a semiconductor material and a conductive material may be used. For example, Alternatively, the insulating layer 11 may have a laminated structure of a silicon layer and a germanium layer.

[0122] The charge storage layer 311 is formed of an insulating layer having traps for holding charges. Representative examples of such materials include silicon compounds and gels. Silicon compounds include silicon nitride, silicon oxynitride, and hydrogen-doped silicon compounds. Examples of germanium compounds include germanium nitride, silicon oxide nitride, and silicon oxynitride. germanium nitride doped with nitrogen, germanium oxide doped with oxygen and hydrogen, Germanium compounds such as germanium nitride and germanium oxide doped with nitrogen and hydrogen There are things etc.

[0123] Next, a mask is formed to cover the semiconductor layers 303, 304, and 306. 1 is used as a mask to add an impurity element that imparts n-type, forming n-type impurity region 362a and n-type impurity region 362b. In this embodiment, the impurity element is an n-type impurity. The impurity element phosphorus (P) is used. Here, n-type impurity region 362a, n-type impurity region 362b, impurity element that gives n-type is 1×10 17 ~5×10 18 atoms / cm 3 The semiconductor layers 303, 304, and 306 are covered with a mask. Remove.

[0124] The oxide film on the semiconductor layer 306 is removed, and the semiconductor layer 305, the semiconductor layer 306, the insulating film 310, A gate insulating layer 309 is formed to cover the charge storage layer 311. If the gate insulating layer 309 is thick, the thin film transistor and the memory element may not be able to withstand high voltage. Therefore, the stability can be improved and the reliability can be increased.

[0125] The gate insulating layer 309 formed above the semiconductor layer 305 is a gate insulating layer for a memory element to be completed later. The thin film transistor formed on the semiconductor layer 306 functions as a control insulating layer in the device. In the present specification, the gate insulating layer 3 is used because the gate insulating layer 3 functions as a gate insulating layer in the transistor. Let's call it 09.

[0126] The oxide film on the semiconductor layers 303 and 304 is removed, and the gate insulating film covering the semiconductor layers 303 and 304 is removed. A gate insulating layer 308 is formed (see FIG. 6(A)). The gate insulating layer 308 is formed by plasma CV The thin film provided in the driver circuit section can be formed by the D method, sputtering method, or the like. The thickness of the gate insulating layer 308 of the transistor is preferably 1 nm or more and 10 nm or less. The thickness of the gate insulating layer 308 is about 5 nm. This has the effect of enabling the transistor to operate at high speed at low voltage.

[0127] The gate insulating layer 308 may be formed of silicon oxide or a laminated structure of silicon oxide and silicon nitride. The gate insulating layer 308 is formed by depositing an insulating film by plasma CVD or low pressure CVD. Alternatively, it may be formed by solid phase oxidation or solid phase nitridation using plasma treatment. The gate insulating layer formed by oxidizing or nitriding the semiconductor layer by plasma treatment is This is because it is dense, has high dielectric strength and is highly reliable.

[0128] Alternatively, a high dielectric constant material may be used for the gate insulating layer 308. By using a high dielectric constant material, the gate leakage current can be reduced. Materials include zirconium dioxide, hafnium oxide, titanium dioxide, and tantalum pentoxide. In addition, a silicon oxide layer can be formed by solid-phase oxidation using plasma processing. It is okay to do so.

[0129] In addition, as a method for forming a thin silicon oxide film, the GRTA method, LRTA method, etc. are used to form a thin silicon oxide film in the semiconductor area. By oxidizing the surface of the region and forming a thermal oxide film, a thin silicon oxide film can be formed. In order to form a dense insulating film with low gate leakage current at a low film formation temperature, It is advisable to include a rare gas element such as argon in the reaction gas and mix it into the insulating film to be formed.

[0130] Next, a 20 to 100 nm thick film is deposited on the gate insulating layers 308 and 309 to be used as a gate electrode layer. The insulating film is formed by laminating a first conductive film having a thickness of 100 nm and a second conductive film having a thickness of 100 to 400 nm. The first conductive film and the second conductive film are formed by a method such as a sputtering method, a vapor deposition method, or a CVD method. The first conductive film and the second conductive film can be made of tantalum (Ta), tungsten (Tb), or the like. (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), An element selected from chromium (Cr) and neodymium (Nd), or an alloy material whose main component is the above element The first conductive film and the second conductive film may be formed of a silicon or compound material. Semiconductor films, such as polycrystalline silicon films doped with impurity elements such as AgPd A Cu alloy may be used. The structure is not limited to a two-layer structure. For example, the first conductive film may be a film The first conductive layer is a 500 nm thick tungsten film, and the second conductive layer is a 500 nm thick aluminum and silicon film. The first conductive layer is an alloy (Al-Si) film, and the second conductive layer is a titanium nitride film with a thickness of 30 nm. In the case of a three-layer structure, the first conductive film is made of tungsten. Instead of the first conductive film, tungsten nitride may be used, and the aluminum and silicon of the second conductive film may be used. Even if an alloy film of aluminum and titanium (Al-Ti) is used instead of the alloy (Al-Si) film, Alternatively, a titanium film may be used instead of the titanium nitride film of the third conductive film. In this embodiment, the first conductive film is made of tantalum nitride having a thickness of 30 nm. Then, a tungsten (W) film is formed to a thickness of 370 nm as a second conductive film.

[0131] The first conductive film and the second conductive film are etched to form first gate electrode layers 312 and 313. , 314, second gate electrode layers 316, 317, 318, and first control gate electrode layer 315. , and a second control gate electrode layer 319 are formed (see FIG. 6B).

[0132] In this embodiment, the first gate electrode layer, the second gate electrode layer (the first control gate electrode layer, Although an example in which the second control gate electrode layer is formed to have vertical side surfaces is shown, the present invention is not limited to this. The first gate electrode layer and the second gate electrode layer (the first control gate electrode layer, the second The gate electrode layer (control gate electrode layer) may have a tapered shape. Only one of the electrode layers (the first control gate electrode layer and the second control gate electrode layer) has a tapered shape. The taper angle may be such that one side of the first recess is perpendicular to the other side of the first recess, and the other side of the first recess is perpendicular to the other side of the first recess. The thickness of the gate electrode layer may be different from that of the gate electrode layer. By doing so, the coverage of the film laminated on top is improved and defects are reduced, resulting in higher reliability. Improve.

[0133] The gate electrode layer (and the control gate electrode layer) is formed through an etching process. The insulating layers 308 and 309 may be etched to some extent, resulting in a reduction in film thickness (so-called film loss). .

[0134] Next, masks 321 and 363 are formed to cover the semiconductor layers 304, 305, and 306. 321, 363, the first gate electrode layer 312, and the second gate electrode layer 316 are used as a mask. An impurity element 320 that imparts p-type is added to form a p-type impurity region 322a and a p-type impurity region 3 In this embodiment, boron (B) is used as the impurity element. The p-type impurity region 322a and the p-type impurity region 322b each contain an impurity element that imparts p-type conductivity. ×10 20 ~5×10 21 atoms / cm 3 Add it so that it is contained at a concentration of about In addition, a channel formation region 323 is formed in the semiconductor layer 303 (see FIG. 6C).

[0135] The p-type impurity region 322a and the p-type impurity region 322b are high-concentration p-type impurity regions. It functions as a source region and a drain region.

[0136] Next, a mask 325 is formed to cover the semiconductor layer 303. The mask 325, the first gate electrode layer 313, second gate electrode layer 317, first gate electrode layer 314, second gate electrode layer 3 18, the first control gate electrode layer 315 and the second control gate electrode layer 319 are used as a mask. An impurity element 324 that imparts n-type is added to the n-type impurity regions 326a, 326b, and 326c. 4a, 364b, 327a, 327b, 328a, and 328b are formed. In this embodiment, phosphorus (P) is used as the impurity element. The impurity element that gives n-type to b, 327a, 327b, 328a, and 328b is 5×10 1 9 ~5×10 20 atoms / cm 3 The concentration of the semiconductor is about A channel forming region 329 is formed in the semiconductor layer 304, a channel forming region 330 is formed in the semiconductor layer 305, and A channel formation region 331 is formed in the semiconductor layer 306 (see FIG. 6(D)).

[0137] The n-type impurity regions 326a, 326b, 327a, 327b, 328a, and 328b are high-concentration It is an n-type impurity region and functions as a source region and a drain region. The n-type impurity region 364a and the n-type impurity region 364b are low-concentration impurity regions and serve as LDD regions.

[0138] Mask 325 O 2 The oxide film is also removed by ashing or using a resist remover. Thereafter, an insulating film, a so-called sidewall, may be formed to cover the side surface of the gate electrode layer. The sidewalls are made of silicon using plasma CVD or low pressure CVD (LPCVD). The insulating film may be formed of an insulating material having the above structure.

[0139] In order to activate the impurity elements, heat treatment, irradiation with strong light, or irradiation with laser light may be performed. At the same time as activation, plasma damage to the gate insulating layer and the boundary between the gate insulating layer and the semiconductor layer are also prevented. It can heal plasma damage to surfaces.

[0140] Next, an interlayer insulating layer is formed to cover the gate electrode layer and the gate insulating layer. The insulating film 367 and the insulating film 368 are laminated. Silicon nitride film, silicon oxynitride film, silicon oxynitride film, etc., using the deposition method or plasma CVD. It may be a silicon oxide film, or other insulating film containing silicon may be used as a single layer or a laminated structure of three or more layers. That's fine.

[0141] Furthermore, a heat treatment is performed in a nitrogen atmosphere at 300 to 550°C for 1 to 12 hours to form a semiconductor layer. A hydrogenation process is carried out. Preferably, the process is carried out at 400 to 500° C. This process is carried out on the interlayer insulating layer. A process of terminating dangling bonds of a semiconductor layer by hydrogen contained in an insulating film 367. In this embodiment, heat treatment is performed at 410° C. for one hour.

[0142] Other examples of the insulating film 367 and the insulating film 368 include aluminum nitride (AlN) and aluminum oxynitride. (AlON), aluminum oxide nitride (AlN) O) or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon film It can be formed of a material selected from substances including (CN) and other inorganic insulating materials. Siloxane resin may also be used. Siloxane resin is a resin having a Si-O-Si bond. This corresponds to a resin containing

[0143] Next, the insulating film 367, the insulating film 368, and the gate insulating layer 3 are formed using a mask made of resist. Contact holes (openings) are formed on the semiconductor layers at 308 and 309. Depending on the selection ratio of the materials used, etching may be performed once or multiple times. Then, the insulating film 368, the insulating film 367, and the gate insulating layers 308 and 309 are removed, and the source region or The drain regions are p-type impurity regions 322a and 322b, n-type impurity regions 326a and 3 Openings are formed reaching 26b, 327a, 327b, 328a, and 328b. The etching may be wet etching or dry etching, or both may be used. The etchant used for the etching is a mixture containing ammonium hydrogen fluoride and ammonium fluoride. It is recommended to use a hydrofluoric acid-based solution such as a mixed solution. 2 , B Cl 3 , SiCl 4 Or CCl 4 Chlorine gases such as CF4 ,SCIENCE FICTION 6 if NF 3 Fluorine gases such as O 2 can be used appropriately. An inert gas may be added to the etching gas. One or more elements selected from the group consisting of Ne, Ar, Kr and Xe can be used.

[0144] A conductive film is formed so as to cover the openings, and the conductive film is etched to form each source region or drain region. A wiring layer 3 which is a source electrode layer or a drain electrode layer electrically connected to a part of the region 69a, wiring layer 369b, wiring layer 370a, wiring layer 370b, wiring layer 371a, wiring layer 3 The wiring layers 71b, 372a, and 372b are formed. The wiring layers are formed by a PVD method, a CVD method, or the like. After forming a conductive film by deposition or the like, the conductive film can be etched into a desired shape. In addition, a conductive layer can be selectively formed at a desired location by a droplet discharge method, a printing method, an electrolytic plating method, etc. Furthermore, a reflow method or a damascene method may be used. The materials for the drain electrode layer are Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al. Metals such as Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, and Si, Ge, or other metals. The insulating film 10 may be formed using an alloy of the above-mentioned or a nitride thereof. In this embodiment, a titanium (Ti) film is formed to a thickness of 60 nm, and a titanium nitride film is formed to a thickness of 40 nm. Then, aluminum is formed to a thickness of 700 nm, and titanium (Ti) is formed to a thickness of 200 nm. This is then laminated to form a layered structure, which is then processed into a desired shape.

[0145] In the above steps, a p-channel thin film transistor having a p-type impurity region is formed as a driver circuit section. A thin film transistor 373 is an n-channel thin film transistor having an n-type impurity region. A thin film transistor 374 having an n-type impurity region as a memory cell array. Element 375 is a thin-film transistor that is an n-channel thin-film transistor having an n-type impurity region. A semiconductor integrated circuit 350 having a star 376 can be manufactured (see FIG. 6(E)). .

[0146] In this embodiment, an insulating layer 390 is formed over a semiconductor integrated circuit 350 (see FIG. 7A). Next, a conductive layer 380 functioning as an antenna is formed over the insulating layer 390. An inorganic insulating layer 381 is formed thereon as a protective layer (see FIG. 7(B)).

[0147] The first impact resistant layer 382 is a structure in which a fiber body 383 is impregnated with an organic resin 384. The structure is heated and compressed to bond the semiconductor integrated circuit 350, the first impact resistant layer 382, ​​and the first impact resistant layer 383. The shock diffusing layer 391 is bonded, and the semiconductor integrated circuit 350 is detached from the substrate 300 using the release layer 301. Therefore, the semiconductor integrated circuit 350 is provided on the first impact resistant layer 382 side (FIG. 7). See (C). ).

[0148] The second impact-resistant layer 385 is also formed of a fibrous body 386 and an organic resin 387 in the same manner as the first impact-resistant layer 382. The impregnated structure is used. The structure is heated and pressed to form the second shock diffusing layer 388 and the second The impact resistant layer 385 is adhered (see FIG. 8(A)). The second impact resistant layer 388 of the second impact diffusion layer 388 is adhered (see FIG. 8(B)). An adhesive layer 389 is provided on the opposite side of the impact layer 385 .

[0149] An adhesive layer 389 is attached to the exposed peelable surface of the semiconductor integrated circuit 350, and the first impact resistant layer 3 82 and a semiconductor integrated circuit 350 sandwiched between a second shock resistant layer 385 and a second shock diffusion layer A semiconductor device having the structure 388 can be manufactured (see FIG. 8(B)). A semiconductor device having the memory of this embodiment mode can be manufactured.

[0150] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0151] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit and a pair of shock-diffusing layers are used to reduce thickness and It is possible to provide a semiconductor device having high strength and high reliability while achieving miniaturization.

[0152] (Embodiment 4) In this embodiment mode, a method for manufacturing a semiconductor device with higher reliability and a semiconductor device with high yield will be described. The method will be described in detail with reference to FIGS.

[0153] In the semiconductor device of this embodiment, the semiconductor integrated circuit is peeled off from the substrate during fabrication. The semiconductor integrated circuit is fabricated in the present specification. The substrate on which the semiconductor integrated circuit is formed is also called a production substrate. can be.

[0154] 17A and 17B show the semiconductor device of this embodiment mode. In FIG. The integrated circuit 100 is sandwiched between a first impact resistant layer 112 and a second impact resistant layer 102. An impact diffusion layer 103 is provided between the conductor integrated circuit 100 and the second impact resistant layer 102 . The first impact resistant layer 112 and the second impact resistant layer 102 are structures in which a fibrous body is impregnated with an organic resin. The first impact resistant layer 112 has a structure in which a fibrous body 160 is impregnated with an organic resin 161. The second impact resistant layer 102 is a structure in which a fibrous body 150 is impregnated with an organic resin 151.

[0155] The top view of the fibrous body 160 is shown in FIG. 17(C). vinegar.

[0156] As shown in FIG. 17(C), the fibrous body 160 is made up of warp yarns spaced at regular intervals and It is woven with weft threads.

[0157] In the drawings of this embodiment, the fibrous body 160 is plain woven with yarn bundles having an elliptical cross section. The material is shown in woven fabric.

[0158] In this embodiment, an aramid resin film (elastic modulus 10 GPa, breaking strength 10 ... A pressure of 480MPa is used.

[0159] FIG. 17B shows a semiconductor integrated circuit 100 and an impact diffusion layer 103 fixed together using an adhesive layer 104. In this embodiment, an aramid film is used as the impact diffusion layer 103, and the adhesive is The adhesive layer 104 is made of acrylic resin.

[0160] A protective layer may be formed on the semiconductor integrated circuit. An example in which an inorganic insulating layer 105 is formed as a protective layer on the path 100 is shown. B) An antenna 101 is formed on a semiconductor integrated circuit 100, and an inorganic insulator is formed on the antenna 101. In this example, the inorganic insulating layer 105 is formed. By covering the antenna 101 with the inorganic insulating layer 105, It is possible to prevent oxidation of the conductive layer that functions as an antenna.

[0161] A method for manufacturing a semiconductor device will be described with reference to FIGS. A semiconductor integrated circuit 100 is formed on a substrate 110 having a surface via a release layer 111 (FIG. See 19(A). ).

[0162] The semiconductor integrated circuit 100 and the first impact resistant layer 112 are bonded together, and the semiconductor integrated circuit is then separated from the first impact resistant layer 112 by using a release layer 111. The semiconductor integrated circuit 100 is peeled off from the substrate 110. Thus, the semiconductor integrated circuit 100 is It is provided on the layer 112 side (see FIG. 19(B)).

[0163] In this embodiment, the first impact resistant layer 112 is formed by impregnating a fibrous body 160 with an organic resin 161. The structure is heated and compressed to plasticize or harden the organic resin of the structure. If the organic resin is a plastic organic resin, it is then plasticized by cooling to room temperature. The organic resin is then cured by heating and pressing so that it adheres closely to the semiconductor integrated circuit. The process of compressing the structure is carried out under atmospheric pressure or reduced pressure. cormorant.

[0164] The second impact-resistant layer 102 is similar to the first impact-resistant layer 112 in that the organic resin 151 is attached to the fibrous body 150. The impregnated structure is used. The structure is heated and pressed to form the shock diffusing layer 103 and the second shock resistant layer 104. The second impact resistant layer 102 is bonded to the impact diffusion layer 103 (see FIG. 19(C)). On the opposite side, an adhesive layer 104 is provided.

[0165] An adhesive layer 104 is attached to the exposed peelable surface of the semiconductor integrated circuit 100, and a first impact resistant layer 1 12 and a semiconductor integrated circuit 100 and an impact diffusion layer 103 sandwiched between the second impact resistant layer 102. It is possible to manufacture a semiconductor device having the above structure (see FIG. 19D).

[0166] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0167] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit therebetween, and a semiconductor integrated circuit is laminated thereon. The impact diffusion layer allows for a thin, compact, and highly reliable semiconductor that is strong. An apparatus can be provided.

[0168] (Embodiment 5) In this embodiment mode, a method for manufacturing a semiconductor device with higher reliability and a semiconductor device with high yield will be described. 4 and 20, the method will be described in detail. In this embodiment, Next, we will explain CMOS.

[0169] FIG. 20(A) shows the next step after FIG. 4(C) in the second embodiment. The detailed description of the steps from FIG. 4(A) to FIG. 4(C) will be omitted. .

[0170] The second impact-resistant layer 252 is similar to the first impact-resistant layer 262 in that the organic resin 271 is attached to the fibrous body 270. The impregnated structure is used. The structure is heated and pressed to form the shock diffusing layer 253 and the second shock resistant layer 254. The second impact resistant layer 252 is bonded to the impact diffusion layer 253 (see FIG. 20(A)). The opposite surface is provided with an adhesive layer 254 .

[0171] An adhesive layer 254 is attached to the exposed peelable surface of the semiconductor integrated circuit 250, and a first impact resistant layer 2 62 and a semiconductor integrated circuit 250 and an impact diffusion layer 253 sandwiched between the second impact resistant layer 252. A semiconductor device having the above structure can be manufactured (see FIG. 20B).

[0172] The semiconductor device manufactured in this embodiment uses a flexible impact resistant layer and an impact diffusion layer. In this way, a flexible semiconductor device can be obtained.

[0173] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0174] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit therebetween, and a semiconductor integrated circuit is laminated thereon. The impact diffusion layer allows for a thin, compact, and highly reliable semiconductor that is strong. An apparatus can be provided.

[0175] (Embodiment 6) In this embodiment, a semiconductor device is provided with the objective of achieving higher integration, thinner size, and smaller size. FIG. 1 is a diagram showing an example of a semiconductor device having a memory in a semiconductor device manufacturing method. 6, FIG. 21 and FIG. 22.

[0176] The semiconductor device of this embodiment includes a memory cell array and a memory cell driving circuit for driving the memory cell array. It has a drive circuit section.

[0177] FIG. 21(A) shows the next step after FIG. 6(E) in the third embodiment. The detailed description of the steps from FIG. 6(A) to FIG. 6(E) will be omitted. .

[0178] In this embodiment, an insulating layer 390 is formed on a semiconductor integrated circuit 350 (see FIG. 21(A)). Next, a conductive layer 380 functioning as an antenna is formed on the insulating layer 390. An inorganic insulating layer 381 is formed as a protective layer (see FIG. 21B).

[0179] The first impact resistant layer 382 is a structure in which a fiber body 383 is impregnated with an organic resin 384. The semiconductor integrated circuit 350 and the first impact resistant layer 382 are bonded together, and the semiconductor integrated circuit 350 is then bonded to the first impact resistant layer 382 using the release layer 301. The semiconductor integrated circuit 350 is peeled off from the substrate 300. It is provided on the impact layer 382 side (see FIG. 21(C)).

[0180] The second impact-resistant layer 385 is also formed of a fibrous body 386 and an organic resin 387 in the same manner as the first impact-resistant layer 382. The impregnated structure is used. The structure is heated and pressed to form the shock diffusing layer 388 and the second shock resistant layer 390. The second impact resistant layer 385 is bonded to the impact diffusion layer 388 (see FIG. 22(A)). The opposite surface is provided with an adhesive layer 389 .

[0181] An adhesive layer 389 is attached to the exposed peelable surface of the semiconductor integrated circuit 350, and the first impact resistant layer 3 82 and a semiconductor integrated circuit 350 and an impact diffusion layer 388 sandwiched between the second impact resistant layer 385. Through the above steps, a semiconductor device having the above structure can be manufactured (see FIG. 22(B)). A semiconductor device having the memory of the embodiment can be manufactured.

[0182] In order to provide an impact diffusion layer in contact with the semiconductor integrated circuit, a pressure treatment is performed in the manufacturing process. This does not have any adverse effects on the semiconductor integrated circuit, such as damage or defective characteristics. A device can be fabricated.

[0183] A pair of shock-resistant layers sandwiching a semiconductor integrated circuit therebetween, and a semiconductor integrated circuit is laminated thereon. The impact diffusion layer allows for a thin, compact, and highly reliable semiconductor that is strong. An apparatus can be provided.

[0184] (Embodiment 7) In semiconductor devices, various types of field effect transistors are used as semiconductor elements included in semiconductor integrated circuits. In this embodiment, a transistor can be used. A field effect transistor having a single crystal semiconductor layer will be described in detail as a semiconductor element. do.

[0185] Hereinafter, a single crystal semiconductor layer is formed on a formation substrate having an insulating surface. A method for forming a semiconductor element included in a semiconductor integrated circuit portion will be described with reference to FIGS. 14 and 15. I will explain this in more detail.

[0186] The single crystal semiconductor substrate 1108 shown in FIG. 14A is cleaned, and the surface of the substrate is heated by an electric field. Accelerated ions are irradiated to a predetermined depth to form a weakened layer 1110. The ion irradiation is The thickness of the single crystal semiconductor layer to be transferred to the formation substrate is taken into consideration. The fast voltage is set so as to be applied to the single crystal semiconductor substrate 1108 while taking into consideration such a thickness. A single crystal semiconductor substrate is irradiated with ions to weaken it so that it has minute cavities. The affected area is called the weakened zone.

[0187] A commercially available single crystal semiconductor substrate can be used as the single crystal semiconductor substrate 1108. For example, Single crystal silicon substrate, single crystal germanium substrate, single crystal silicon germanium substrate, etc. A single crystal semiconductor substrate made of a Group 4 element can be used. A compound semiconductor substrate such as GaN or GaN can also be used. Of course, the single crystal semiconductor substrate is not limited to a circular wafer. For example, a rectangular, pentagonal, or other single crystal semiconductor substrates may be used. A substrate with a polygonal shape such as a hexagon can be used. Of course, a commercially available circular single crystal semiconductor A single crystal semiconductor wafer may be used as the single crystal semiconductor substrate. The company produces semiconductor wafers such as silicon and germanium, and gallium arsenide and indium phosphide. Compound semiconductor wafers and the like. A typical example of a single crystal semiconductor wafer is a single crystal silicon wafer. 5 inch (125 mm), 6 inch (150 mm), 8 inch (2 00mm), 12 inch (300mm) diameter, 400mm diameter, 450mm diameter A circular wafer can be used. A rectangular single crystal semiconductor substrate can be a commercially available circular wafer. The substrate can be formed by cutting a single crystal semiconductor wafer. - Or cutting equipment such as wire saws, laser cutting, plasma cutting, electron beam cutting, etc. Any cutting means can be used. Also, the semiconductor substrate manufacturing method before being sliced ​​into substrates can be used. The ingot for use is processed into a rectangular parallelepiped shape so that its cross section is rectangular. A rectangular single crystal semiconductor substrate can also be manufactured by slicing an ingot. In addition, the thickness of the single crystal semiconductor substrate is not particularly limited. Considering this, a thicker wafer can form more single crystal semiconductor layers from one raw wafer. The thickness of the single crystal silicon wafers available on the market is The size is based on the SEMI standard. For example, a 6-inch wafer has a thickness of 625 μm and a diameter of The thickness of the 8-inch wafer is 725 μm, while that of the 12-inch diameter wafer is 775 μm. The SEMI standard wafer thickness includes a tolerance of ±25μm. The thickness of the single crystal semiconductor substrate is not limited to the SEMI standard, and can be obtained by slicing the ingot. Of course, the thickness of the single crystal semiconductor substrate can be appropriately adjusted. When 1108 is used, the thickness is thinner than the SEMI standard. The single crystal semiconductor layer to be formed can be determined by selecting a semiconductor substrate to be a base. Cut.

[0188] The single crystal semiconductor substrate 1108 is a substrate for forming a semiconductor element (in this embodiment, an electric field The crystal plane orientation can be selected depending on the type of device (e.g., a GaN- ... A single crystal semiconductor substrate having a {100} plane, a {110} plane, or the like can be used.

[0189] In this embodiment mode, hydrogen, helium, or fluorine is ionized to a predetermined depth of a single crystal semiconductor substrate. Ion irradiation and doping is then performed, followed by heat treatment to separate the surface single crystal semiconductor layer. The method involves epitaxially growing single crystal silicon on the porous silicon, followed by A method of cleaving and peeling off the porous silicon layer with a water jet may also be applied.

[0190] A single crystal silicon substrate is used as the single crystal semiconductor substrate 1108, and the surface is treated with dilute hydrofluoric acid. The native oxide film and contaminants such as dust attached to the surface are removed, and the single crystal semiconductor substrate 1108 is Clean the surface.

[0191] The weakened layer 1110 is formed by ion doping (abbreviated as ID method) or ion implantation. The weakened layer 1110 may be irradiated with hydrogen, helium or They are formed by irradiating halogen ions, typically fluorine ions. When irradiating the fluorine ions, the source gas is BF 3 It is sufficient to use Ion implantation refers to a method in which ionized gas is mass-separated and irradiated onto a semiconductor substrate.

[0192] For example, ionized hydrogen gas can be mass-separated using ion implantation to produce H + Only (or H 2 + The laser beam (only the laser beam) can be selectively accelerated and irradiated onto the single crystal semiconductor substrate.

[0193] The ion doping method does not separate the ionized gas by mass, but instead separates multiple ion species in the plasma. These are then accelerated and irradiated onto a single crystal semiconductor substrate. + , H 2 + , H 3 + In the case of hydrogen containing ions, the ions irradiated are typically H 3 + Ions are more than 50%, e.g. BaH 3 + ions are 80%, other ions (H 2 + , H 3 + ions) is generally 20%. H 3 + Irradiation of ions as ion species alone is also referred to as ion doping here.

[0194] Alternatively, one or more ions of the same atom but different masses may be irradiated. For example, When irradiating with hydrogen ions, H + , H 2 + , H3 + ions and H 3 + It is preferable to increase the ratio of hydrogen ions. + , H 2 + , H 3 + ions and H 3 + Increasing the ion ratio increases the irradiation efficiency. This allows the irradiation time to be shortened. It can be easily done.

[0195] The ion doping method and the ion implantation method will be described in detail below. In the ion doping device (also called ID device) used in On the other hand, the ions used in the ion implantation method can be irradiated to a single crystal semiconductor substrate. The ion implantation device (also called the Ion Injection Device) uses mass spectrometry to identify ions extracted from the plasma. It has the advantage that only the ion species of the above can be implanted into the semiconductor substrate, and it is basically a point beam scanning method. The data is then processed.

[0196] In both devices, the plasma is generated by heating a filament. The plasma state is created by electrons. However, the hydrogen ions (H + , H 2 + , H 3 + The ratio of hydrogen ion species when irradiating a semiconductor substrate with hydrogen ions is The on-injection method makes a big difference.

[0197] H 3 +From the viewpoint of irradiating more ions, ion doping is more effective than ion implantation. It is preferable to use a device.

[0198] When a single crystal silicon substrate is irradiated with halogen ions such as hydrogen ions or fluorine ions, The added hydrogen or fluorine knocks out silicon atoms in the silicon crystal lattice ( By expelling the particles, it effectively creates voids and creates tiny cavities in the weakened layer. In this case, the volume of the microcavities formed in the weakened layer changes due to the relatively low-temperature heat treatment. Thus, separation along the weakened layer can be performed to form a thin single crystal semiconductor layer. After irradiating with fluorine ions, hydrogen ions are irradiated to make the cavity contain hydrogen. The weakened layer formed in order to separate the thin single crystal semiconductor layer from the single crystal semiconductor substrate is preferably The separation is achieved by utilizing the volume change of the tiny cavities formed in the weakened layer. It is preferable to effectively utilize the action of fluorine ions and hydrogen ions.

[0199] In addition, a protective layer is formed between the single crystal semiconductor substrate and the insulating layer bonded to the single crystal semiconductor layer. The protective layer may be a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, or an oxide. The silicon nitride layer may be formed as a single layer or a multilayer structure. These layers can be formed on the single crystal semiconductor substrate before a weakened layer is formed in the single crystal semiconductor substrate. In addition, after forming the weakened layer in the single crystal semiconductor substrate, The semiconductor device may be formed on a solid substrate.

[0200] Note that a silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. Rutherford Backscattering (RBS) Scattering Spectrometry (HSS) and Hydrogen Forward Scattering Spectroscopy (HFS) n Forward Scattering) is used for the measurement. Oxygen is 50-70 atomic %, nitrogen is 0.5-15 atomic %, Si is 25-35 atomic %, and hydrogen is The range of silicon oxide nitride film is 0.1 to 10 atomic percent. The composition is such that the nitrogen content is greater than the oxygen content, and the measured values ​​are When the concentration range is set, oxygen is 5 to 30 atomic %, nitrogen is 20 to 55 atomic %, and Si is The atomic percentage of nitrogen is 25-35% and the atomic percentage of hydrogen is 10-30%. When the total number of atoms constituting silicon nitride or silicon oxynitride is taken as 100 atomic %, The content ratios of elemental, oxygen, silicon and hydrogen are within the above ranges.

[0201] To form the weakened layer, it is necessary to irradiate ions at a high dose. The surface of the substrate 1108 may become rough. Silicon nitride film, silicon oxynitride film, silicon oxide film, etc. are used to protect the film from ion irradiation. A protective layer may be provided to the substrate with a thickness of 50 nm to 200 nm.

[0202] For example, a silicon oxynitride film is formed on the single crystal semiconductor substrate 1108 as a protective layer by plasma CVD. Silicon film (thickness: 5 nm to 300 nm, preferably 30 nm to 150 nm (for example, 50 nm )) and a silicon oxynitride film (thickness 5 nm to 150 nm, preferably 10 nm to 100 nm As an example, a stack of a SiO 2 film (e.g., 50 nm) is formed on a single crystal semiconductor substrate 1108. A silicon oxynitride film is formed to a thickness of 50 nm, and silicon nitride oxide is deposited on the silicon oxynitride film. The silicon oxynitride film is chemically formed using organic silane gas. A silicon oxide film formed by vapor phase growth may also be used.

[0203] In addition, the single crystal semiconductor substrate 1108 is degreased and washed, the oxide film on the surface is removed, and thermal oxidation is performed. Thermal oxidation may be performed by ordinary dry oxidation, but it is also possible to add halogen to the oxidation atmosphere. For example, oxidation is preferably performed using 0.5 to 10% by volume of HCl relative to oxygen (preferably The heat treatment is carried out at a temperature of 700° C. or higher in an atmosphere containing 0.1% by volume or less of 0.1% by volume of SiO 2 . The thermal oxidation is preferably carried out at a temperature of 950°C to 1100°C. The treatment time is preferably 0.1 to 6 hours. The time is usually 0.5 to 3.5 hours. The thickness of the oxide film formed is 10 nm to 1 The thickness is set to be 100 nm, preferably 50 nm to 200 nm, for example.

[0204] In addition to HCl, HF and NF also contain halogens. 3 , HBr, Cl 2 , ClF 3 , BCl 3 , F 2 , Br 2 , dichloroethylene, etc. It is possible.

[0205] By carrying out heat treatment in this temperature range, a gettering effect by the halogen element can be obtained. The gettering is particularly effective in removing metal impurities. The action of chlorine causes metal and other impurities to become volatile chlorides, which are released into the gas phase and removed. The surface of a single crystal semiconductor substrate 1108 is subjected to chemical mechanical polishing (CMP) processing. Hydrogen is effective against the interface between the single crystal semiconductor substrate 1108 and the insulating layer. The single crystal semiconductor substrate 110 is then heated to a temperature of 1000° C. for 10 minutes. The interface between 8 and the insulating layer is passivated, stabilizing the electrical characteristics.

[0206] The oxide film formed by this heat treatment can contain halogen. is 1×10 17 atoms / cm 3 ~5×10 20 atoms / cm 3 Contained at a concentration of This traps impurities such as metals and prevents contamination of the single crystal semiconductor substrate 1108. The layer can exhibit its function.

[0207] When forming the weakened layer 1110, the acceleration voltage and the total number of ions are The thickness of the film and the single crystal to be separated from the target single crystal semiconductor substrate and transferred onto the preparation substrate This can be adjusted by the film thickness of the semiconductor layer and the type of ions to be irradiated.

[0208] For example, hydrogen gas is used as the source material in the ion doping method, and the acceleration voltage is set to 40 kV and the total ion Number of pieces: 2 x 10 16 ions / cm 2 A weakened layer can be formed by irradiating ions at If the thickness of the protective layer is increased, the desired effect can be obtained when ion irradiation is performed under the same conditions to form a weakened layer. A single crystal semiconductor layer separated from a single crystal semiconductor substrate and transferred (transferred) onto a formation substrate. By using this method, a single crystal semiconductor layer with a thin film thickness can be formed. For example, the ion species (H + , H 2 + , H 3 +Although it depends on the ratio of ions, the weakened layer is formed under the above conditions, and the protective layer is A silicon oxynitride film (thickness 50 nm) and a silicon nitride oxide film ( When a protective layer (thickness 50 nm) is laminated, the film of the single crystal semiconductor layer transferred to the formation substrate The thickness is about 120 nm, and a silicon oxynitride film (thickness 100 nm) is formed on a single crystal semiconductor substrate. When a silicon nitride oxide film (thickness 50 nm) is laminated as a protective layer, it is transferred to the production substrate. The thickness of the single crystal semiconductor layer is about 70 nm.

[0209] When using helium (He) or hydrogen as the source gas, the acceleration voltage should be in the range of 10 kV to 200 kV. So the dose is 1×10 16 ions / cm 2 ~6×10 16 ions / cm 2 In the range By irradiating the gas, a weakened layer can be formed. If helium is used as the raw gas, mass separation is not performed. Even without He + Ions can be used as the main ions. Hydrogen can also be used as the source gas. Then, H 3 + Ions and H 2 + Ions can be used as the main ions. The species also change depending on the plasma generation method, pressure, amount of source gas supplied, and acceleration voltage.

[0210] As an example of forming a weakened layer, a silicon oxynitride film (thickness 50 nm) is formed on a single crystal semiconductor substrate. A silicon oxynitride film (50 nm thick) and a silicon oxide film (50 nm thick) are used as protective layers. Hydrogen was injected at an acceleration voltage of 40 kV and a dose of 2 × 10 16 ions / cm 2 Irradiation with The silicon oxide layer is then formed on the single crystal semiconductor substrate to form a weakened layer. A silicon oxide film (50 nm thick) is formed on the film as an insulating layer with a bonding surface. Another example of layer formation is a silicon oxide film (thickness 100 nm) on a single crystal semiconductor substrate, A silicon oxynitride film (50 nm thick) was laminated as a protective layer, and hydrogen was accelerated at an accelerating voltage of 40 kV. , dose 2×10 16 ions / cm 2 A weakened layer is formed in a single crystal semiconductor substrate by irradiating the substrate with light. Then, an insulating layer having a bonding surface is formed on the silicon oxynitride film, which is the top layer of the protective layer. A silicon oxide film (thickness: 50 nm) is formed. The silicon oxide film may be formed by a plasma CVD method, and the silicon oxide film may be formed by an organic silicide. The film may be formed by a CVD method using nitrogen gas.

[0211] Further, an insulating layer may be formed between the formation substrate and the single crystal semiconductor substrate. The bonding may be formed on either the side of the semiconductor substrate or the side of the single crystal semiconductor substrate, or on both sides. The insulating layer formed on the surface on which the insulating layer is formed has a smooth surface and forms a hydrophilic surface. A silicon oxide film can be used. The silicon oxide film can be formed by using an organic silane gas. A silicon oxide film made by chemical vapor deposition using silane gas is preferable. Alternatively, a silicon oxide film formed by chemical vapor deposition using a silicon nitride film may be used.

[0212] As an organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC 2 H 5 ) 4 ), Tori Methylsilane (TMS:(CH 3 ) 3 SiH, tetramethylsilane (chemical formula Si(CH 3 ) 4), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane Triethoxysilane (OMCTS), Hexamethyldisilazane (HMDS), Triethoxysilane Ran(SiH(OC 2 H 5 ) 3 ), trisdimethylaminosilane (SiH(N(CH 3 ) 2 ) 3 In addition, the source gas may contain organic silane. When a silicon oxide layer is formed by chemical vapor deposition using a gas that provides oxygen, The gas that provides oxygen is oxygen, nitrous oxide, nitrogen dioxide, etc. In addition, an inert gas such as argon, helium, nitrogen or hydrogen can be mixed. They may also be combined.

[0213] In addition, the insulating layer formed on the surface where the bond is to be formed is made of monosilane, disilane, or trisilane. Silicon oxide film formed by chemical vapor deposition using silane such as silane as a source gas is applied. In this case, a gas that provides oxygen or an inert gas may be mixed. In addition, the silicon oxide film which is to be an insulating layer bonded to the single crystal semiconductor layer preferably contains chlorine. In this specification, the term "chemical vapor deposition (CVD)" refers to a method for depositing a layer of a semiconductor substrate. The apor deposition method includes the plasma CVD method, the thermal CVD method, and the photo-CVD method. Included in the category.

[0214] In addition, as an insulating layer formed on the surface where the joint is to be formed, heat treatment is performed in an oxidizing atmosphere. silicon oxide formed by the reaction of oxygen radicals; A chemical oxide formed by an oxidizing chemical solution may also be used. Alternatively, an insulating layer containing a siloxane (Si-O-Si) bond may be used. The insulating layer may be formed by reacting an organosilane gas with oxygen radicals or nitrogen radicals. stomach.

[0215] In addition, an oxide film mainly composed of aluminum oxide is used as an insulating layer formed on the surface where the bond is to be formed. An oxide film containing aluminum oxide as a main component may be used. When the total of the components is 100% by weight, the oxide containing 10% by weight or more of aluminum oxide is Other insulating layers include those made of aluminum oxide as the main component and magnesium oxide. A film containing one or both of nitrogen and strontium oxide can be applied. Aluminum oxide containing may also be used.

[0216] The insulating layer can be formed by a sputtering method. The target may be, for example, a metal containing aluminum or a metal oxide such as aluminum oxide. The target material can be appropriately selected depending on the film to be formed. Good.

[0217] When using a metal as a target, the target is heated while introducing a reactive gas (e.g., oxygen). The insulating layer is formed by sputtering (reactive sputtering method). In addition to aluminum, magnesium (Mg), alloys containing aluminum and magnesium, Alloys containing aluminum and strontium (Sr), aluminum, magnesium and strontium In this case, the sputtering is performed with a direct current (DC) current. This may be done using a power source or a radio frequency (RF) power source.

[0218] When using metal oxide as a target, sputtering is performed using a radio frequency (RF) power source. The insulating layer is formed by RF sputtering. In addition to aluminum, magnesium oxide, strontium oxide, aluminum and magnesium oxide Oxides containing aluminum, oxides containing aluminum and strontium, aluminum and oxides containing magnesium and strontium can be used.

[0219] Alternatively, the insulating layer may be formed by using a bias sputtering method. By using the tarring method, both the deposition of a film and the planarization of the surface can be achieved.

[0220] The oxide film, which is mainly composed of aluminum, is made of impurities such as mobile ions and moisture contained in the substrate. In addition, it is possible to prevent the impurities from diffusing into a single crystal semiconductor layer that is formed later over a formation substrate.

[0221] In the insulating layer, the surface of the surface that forms the bond has an arithmetic mean roughness Ra of less than 0.8 nm and a square The root mean square roughness (Rms) is preferably less than 0.9 nm, with Ra being 0.4 nm or less and Rms being 0 .5nm or less is more preferable, and even better, Ra is 0.3nm or less and Rms is 0.4nm or less. For example, Ra is 0.27 nm and Rms is 0.34 nm. In this case, Ra is the arithmetic mean roughness, Rms is the root mean square roughness, and the measurement range is 2 μm 2 , or 10 μm 2 It is.

[0222] When bonding a formation substrate and a single crystal semiconductor substrate, one or both of the surfaces forming the bond An insulating layer is provided on the substrate, which is preferably a silicon oxide film formed using organic silane as a raw material. A strong bond can be formed.

[0223] In this embodiment, as shown in FIG. 14(B), an insulating layer 11 is formed on the surface to be bonded to the fabrication substrate. 04 is a silicon oxide film. The silicon oxide film is formed using organic silane gas. A silicon oxide film made by chemical vapor deposition is preferable. A silicon oxide film formed by chemical vapor deposition can also be used. In the deposition method, outgassing occurs from the weakened layer 1110 formed on the single crystal semiconductor substrate. For example, a film formation temperature of 350°C or less (specifically, 300°C) is suitable as a temperature that does not cause the film to be heated. In addition, the heat treatment for separating the single crystal semiconductor layer from the single crystal semiconductor substrate is performed at a temperature higher than the film formation temperature. A higher heat treatment temperature is applied.

[0224] In this embodiment mode, after a semiconductor integrated circuit is formed on a manufacturing substrate, the semiconductor integrated circuit is In order to separate the semiconductor integrated circuit from the substrate, a separation layer is provided between the substrate and the semiconductor integrated circuit. The single crystal semiconductor layer to be separated from the substrate and bonded is formed by a separation layer (and If the surface of the peeling layer has unevenness, the single crystal semiconductor substrate and the fabrication substrate are not uniform. In the joining process with the plate, the contact area of ​​the joining surface is small, ensuring sufficient joining strength. Therefore, a step of planarizing the release layer is necessary.

[0225] The peeling layer may be provided between the formation substrate and the single crystal semiconductor layer. The insulating film may be formed on the side of the single crystal semiconductor substrate. The formed release layer is subjected to a planarization process.

[0226] The insulating layer may be formed on the formation substrate side or the single crystal semiconductor substrate side, or on the peeling layer side. In addition, the formation substrate or the single crystal semiconductor substrate may be peeled off. If the layer can be directly bonded, the insulating layer does not need to be provided.

[0227] In this embodiment, a peeling layer 1125 is formed on the formation substrate 1101 side. An example of forming a blocking layer 1109 is shown.

[0228] As the flattening process, a polishing process or an etching process may be performed. The polishing process may be a chemical mechanical polishing (CMP) method or a liquid etching method. Jet polishing can be used. Etching can be performed using wet etching, Dry etching, or both may be used as appropriate.

[0229] Alternatively, a planarization process may be performed by plasma treatment. For example, a reverse sputtering method may be used. When the planarization process is performed by the reverse sputtering method, the planarization can be performed from the formation of the insulating layer. Since the steps from purification to polymerization can be carried out in the same apparatus, the throughput is improved, which is preferable.

[0230] In the reverse sputtering method, for example, an inert gas, such as Ar gas, is introduced into a high vacuum chamber. The treatment is performed by applying an electric field to the surface to be treated, creating a plasma state. Ar atoms and Ar positive ions are present, and the Ar positive ions are accelerated toward the cathode. The positive ions sputter the surface to be treated. At this time, the sputtering occurs preferentially from the convex portions of the surface to be treated. The particles sputtered from the surface to be treated are deposited on another part of the surface. In this way, the protrusions are scraped off and the recesses are filled in, so that the The flatness of the treated surface is improved.

[0231] In this embodiment, the peeling layer is formed by a sputtering method, and the planarization is performed by a reverse sputtering method. A smoothing treatment is carried out.

[0232] The substrate is provided with a silicon nitride film or a nitride oxide film to prevent diffusion of impurity elements between the substrate and the peeling layer. A silicon film may be provided as a blocking layer (also called a barrier layer). A silicon oxynitride film may be combined as an insulating film having a neutralizing effect.

[0233] FIG. 14C shows a blocking layer 1109 and a single crystal semiconductor A mode in which the surface of the substrate 1108 on which the insulating layer 1104 is formed is brought into intimate contact with the surface of the substrate 1108, and the two are bonded together. The blocking layer 1109 surface is provided on a planarized release layer 1125. The surfaces to be bonded must be thoroughly cleaned. A blocking layer 1109 provided on a semiconductor substrate 1101 and a single crystal semiconductor substrate 1108 are insulated from each other. The surface on which the edge layer 1104 is formed may be cleaned by megasonic cleaning or the like. Even if the surface is cleaned with ozone water after megasonic cleaning to remove organic matter and improve the hydrophilicity of the surface, good.

[0234] The blocking layer 1109 and the insulating layer 1104 on the fabrication substrate 1101 are placed opposite each other, and When pressure is applied from the outside, the distance between the bonding surfaces is locally reduced, resulting in a van der Waals effect. They attract each other due to the strengthening of the electron-electrode interactions and the contribution of hydrogen bonds. The distance between the blocking layer 1109 and the insulating layer 1104 on the fabrication substrate 1101 facing each other in the region Since the molecular weight shrinks, the area where van der Waals forces are strong and hydrogen bonds are involved As the bonding spreads, the bonding process progresses and the bond spreads across the entire bonding surface. .

[0235] When pressing, press one of the four corners of the board with a pressure of 100kPa to 5000kPa. As the surfaces approach each other, the van der Waals forces can be replaced by hydrogen bonds. When one bonding surface in the substrate approaches another, the adjacent bonding surfaces also approach each other and transition to hydrogen bonding. Therefore, the entire bonding surface can transition to hydrogen bonding.

[0236] In order to form a good bond, the surface may be activated. For example, Atomic or ion beams are irradiated onto the surface. When using an inert gas neutral atom beam such as argon or an inert gas ion beam, Alternatively, plasma irradiation or radical treatment can be used. Such surface treatment allows the formation of bonds between different materials even at temperatures between 200°C and 400°C. This makes it easier to

[0237] In addition, in order to improve the bonding strength of the bonding interface between the production substrate and the insulating layer, a heat treatment is performed. For example, it is preferable to heat the material in an oven or furnace at 70°C to 350°C (for example, at 200°C for 2 hours). Heat treatment is performed under certain temperature conditions.

[0238] In FIG. 14D, after the formation substrate 1101 and the single crystal semiconductor substrate 1108 are bonded to each other, Then, a heat treatment is performed to prepare a single crystal semiconductor substrate 1108 using the weakened layer 1110 as a cleavage plane. For example, by heat treatment at 400℃ to 700℃, A volume change occurs in the minute cavities formed in the layer 1110, and cleavage occurs along the weakened layer 1110. The insulating layer 1104 is connected to the formation substrate 11 via a blocking layer 1109. Since the single crystal semiconductor substrate 1108 is bonded to the formation substrate 1101, the same crystal structure as the single crystal semiconductor substrate 1108 is formed on the formation substrate 1101. As a result, the porous single crystal semiconductor layer 1102 remains.

[0239] Heat treatment in the temperature range of 400℃ to 700℃ is the heat treatment for improving the bonding strength mentioned above. It may be performed continuously in the same equipment or in separate equipment. For example, it may be performed in a furnace at 200°C for 2 hours. After the short-term heat treatment, the temperature was raised to around 600°C and held for 2 hours, and then the temperature was lowered from 400°C to room temperature. The temperature may be raised from room temperature during the heat treatment. After heat treatment at 00℃ for 2 hours, it is heated to 600℃~700℃ by a rapid thermal annealing (RTA) device. Heat treatment is performed for 1 to 30 minutes in the temperature range of ℃ (for example, 600℃ for 7 minutes, 650℃ for 7 minutes). This is also possible.

[0240] By heat treatment at temperatures between 400℃ and 700℃, the bond between the insulating layer and the substrate is formed by hydrogen bonding. The element added to the weakened layer precipitates, the pressure increases, and the single crystal semiconductor substrate After the heat treatment, the single crystal semiconductor layer can be peeled off from the formation substrate. The conductor substrate is placed on top of the other, and the substrate and the single crystal are separated without applying a large force. The semiconductor substrate can be released. For example, the substrate placed above can be lifted up by a vacuum chuck. In this case, the vacuum chuck and the mechanical By fixing the substrate with a chuck, there is no misalignment in the horizontal direction and both the substrate and the single crystal semiconductor substrate can be You can remove the board.

[0241] 14 and 15, the single crystal semiconductor substrate 1108 is smaller than the formation substrate 1101. Although a small size example is shown, the present invention is not limited thereto. The substrates 1101 may be of the same size, and the single crystal semiconductor substrate 1108 may be the same size as the substrate 11. It may be a size larger than 01.

[0242] FIG. 15 shows a process of forming a single crystal semiconductor layer by providing an insulating layer on the side of a substrate. ) is applied to a single crystal semiconductor substrate 1108 on which a silicon oxide film is formed as a protective layer 1121. 11 shows a process of irradiating ions accelerated at 1000 K to a predetermined depth to form a weakened layer 1110. The ion irradiation is performed in the same manner as in FIG. 14(A). By forming a protective layer 1121 on the surface, the surface is protected from damage by ion irradiation and becomes flat. In addition, the protective layer 1121 can prevent the single crystal semiconductor substrate from being damaged. The plate 1108 exerts an effect of preventing the diffusion of impurities into the single crystal semiconductor layer 1102 formed therefrom. do.

[0243] FIG. 15B shows a production substrate 11 on which a blocking layer 1109 and an insulating layer 1104 are formed. The surface of the single crystal semiconductor substrate 1108 on which the protective layer 1121 is formed is brought into close contact with the surface of the single crystal semiconductor substrate 1108 to form a bond. The insulating layer 1104 on the formation substrate 1101 and the single crystal semiconductor substrate 11 The bond is formed by adhering protective layer 1121 of 08 to the substrate.

[0244] After that, the single crystal semiconductor substrate 1108 is peeled off as shown in FIG. The heat treatment for peeling off the layers is carried out in the same manner as in FIG. 14(D). In this way, a semiconductor substrate having an SOI structure having a single crystal semiconductor layer can be obtained through an insulating layer shown in FIG. Cut.

[0245] In addition, the single crystal semiconductor layer separated from the single crystal semiconductor substrate and transferred to the formation substrate is The ion irradiation process causes crystal defects and the surface becomes less flat. In some cases, unevenness may be formed. When manufacturing a GaN photodiode, a thin insulating film with high dielectric strength is applied to the top surface of the single crystal semiconductor layer with such unevenness. It is difficult to form a high-quality gate insulating layer. In addition, the single-crystal semiconductor layer has crystal defects. This increases the density of localized interface states with the gate insulating layer, which can adversely affect the performance and reliability of transistors. Affects gender.

[0246] Therefore, it is possible to reduce crystal defects by irradiating a single crystal semiconductor layer with electromagnetic waves such as laser light. It is preferable that at least a part of the single crystal semiconductor layer is melted by irradiation with electromagnetic waves. By melting the single crystal semiconductor layer, crystal defects in the single crystal semiconductor layer can be reduced. The oxide film (natural oxide film or chemical oxide film) formed on the surface of the single crystal semiconductor layer is then removed. It is recommended to remove it with hydrofluoric acid.

[0247] The electromagnetic wave may be any wave capable of supplying high energy to the single crystal semiconductor layer. The light can be used.

[0248] The energy supply is performed by irradiating high-energy particles to the single-crystal semiconductor layer. It can also be achieved by bombarding the object with highly energetic particles, primarily through thermal conduction. The heat source may be plasma, and may be atmospheric pressure plasma, high pressure plasma, or thermal plasma. Flames such as plasma jets and gas burners can be used. Other heat sources include electric A child beam or the like can be used.

[0249] The wavelength of the electromagnetic wave is a wavelength that can be absorbed by the single crystal semiconductor layer. For example, the wave length of the electromagnetic wave can be determined by taking into account the skin depth. The length of the electromagnetic wave can be 190 nm to 600 nm. The wavelength of the electromagnetic wave, the skin depth of the electromagnetic wave, the thickness of the single crystal semiconductor layer to be irradiated, etc. should be taken into consideration. This can be done.

[0250] Lasers that emit laser light include continuous wave lasers, pseudo continuous wave lasers, and pulsed lasers. A pulsed laser is preferred for partial melting. For example, a K There are excimer lasers such as rF lasers, and gas lasers such as Ar lasers and Kr lasers. In addition, solid-state lasers such as YAG laser and YVO 4 Laser, YLF laser, YAlO 3 R -The GdVO 4 Laser, KGW laser, KYW laser, Alexandrite laser, T i: sapphire laser, Y 2 O 3 Lasers and the like. Excimer lasers are pulsed lasers. However, solid-state lasers such as YAG lasers have both continuous wave and pseudo continuous wave lasers. There are solid-state lasers that can be either oscillation lasers or pulsed lasers. It is preferable to use the second to fifth harmonics of the main wave. Semiconductor lasers such as AlAs and InGaAsP can also be used.

[0251] Furthermore, if the single crystal semiconductor layer can be irradiated with electromagnetic wave energy, lamp light may be used. For example, ultraviolet lamps, black lights, halogen lamps, metal halide lamps, Xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp The light emitted from a lamp may be used. Flash annealing is preferably performed using a halogen lamp or a xenon lamp. Since the process requires only a very short time, the temperature rise of the substrate can be suppressed.

[0252] In order to adjust the shape and path of electromagnetic waves, shutters, mirrors, half mirrors, etc. An optical system consisting of a reflector, cylindrical lens, convex lens, etc. is installed. This is also fine.

[0253] The electromagnetic wave irradiation method may be selective irradiation, or light (electromagnetic wave) may be projected along the XY axis. In this case, a polygon mirror is used in the optical system. It is preferable to use a galvanometer mirror or a galvanometer mirror.

[0254] Electromagnetic radiation is applied in an oxygen-containing atmosphere such as air or in an inert atmosphere such as nitrogen. To irradiate electromagnetic waves in an inert atmosphere, an airtight chamber is required. The electromagnetic wave is irradiated in the chamber, and the atmosphere in the chamber is controlled. If you do not use an inert gas, such as nitrogen gas, you can spray it onto the surface to be irradiated with the electromagnetic waves. It is also possible to form an atmosphere of oxygen.

[0255] Furthermore, single-crystal semiconductors with reduced crystal defects can be produced by supplying high energy such as electromagnetic radiation. The surface of the single crystal semiconductor layer may be polished. It is possible.

[0256] The polishing process can be performed using chemical mechanical polishing (CMP) or liquid jet polishing. Before the polishing process, the surface of the single crystal semiconductor layer is washed and cleaned. The cleaning may be performed by using a jet cleaning method or a two-fluid jet cleaning method. Also, the natural oxide film on the surface of the single crystal semiconductor layer is removed using dilute hydrofluoric acid. It is preferable to expose the single crystal semiconductor layer.

[0257] In addition, the surface of the single crystal semiconductor layer is polished (or etched) before irradiation with electromagnetic waves. You may go.

[0258] In addition, a process for repeatedly using the separated single crystal semiconductor substrate (semiconductor substrate recycling process) is performed. This can reduce costs.

[0259] In addition, when transferring a single crystal semiconductor layer from a single crystal semiconductor substrate, the single crystal semiconductor substrate is selectively A plurality of single crystal semiconductor layers that have been etched and shaped may be transferred onto a formation substrate. A plurality of island-shaped single crystal semiconductor layers can be formed on the formation substrate. Since the shape is processed and transferred using a solid substrate, there are no restrictions on the size or shape of the single crystal semiconductor substrate. Therefore, the transfer of the single crystal semiconductor layer onto a large manufacturing substrate can be performed more efficiently. Cut.

[0260] Furthermore, the single crystal semiconductor layer bonded to the formation substrate is etched to form a single The shape of the crystalline semiconductor layer may be precisely controlled by processing and modifying it. It can be processed into the shape of the crystalline semiconductor layer, and the pattern caused by exposure wraparound during resist mask formation is eliminated. The formation position of the single crystal semiconductor layer may be affected by the misalignment of the wafer or the positional deviation caused by the bonding process during transfer. This allows for correction of positioning errors and shape defects.

[0261] In addition, a single crystal semiconductor layer may be separated from a single crystal semiconductor substrate and then attached to a formation substrate. The surface of the single crystal semiconductor layer exposed by cleavage may be attached to the formation substrate. Preferably, the surface of the single crystal semiconductor layer exposed by cleavage is in contact with the gate insulating film. A single crystal semiconductor layer may be attached to a formation substrate.

[0262] In this embodiment, a single crystal silicon substrate is used as the single crystal semiconductor substrate 1108. In this case, a single crystal silicon layer can be obtained as the single crystal semiconductor layer 1102. In the method for manufacturing a semiconductor device according to the present embodiment, the process temperature can be set to 700° C. or less. Therefore, a glass substrate can be used as the substrate 1101. It can be formed on a glass substrate like the thin film transistor of the above, and can be formed on a single crystal silicon layer. This allows high-speed operation and It has low threshold voltage, high field effect mobility, and can be driven with low power consumption. A reliable transistor can be fabricated on a fabrication substrate such as a glass substrate.

[0263] This embodiment mode can be combined with any of the first to sixth embodiments as appropriate.

[0264] (Embodiment 8) In this embodiment, an example of a semiconductor device intended to provide higher reliability will be described. In more detail, a semiconductor device that is an example of a microprocessor and a non-contact data An example of a semiconductor device having a computing function capable of transmitting and receiving data will be described.

[0265] FIG. 12 shows an example of a microprocessor 500 as an example of a semiconductor device. The processor 500 is manufactured using the semiconductor device according to the above embodiment. This microprocessor 500 includes an arithmetic circuit 501 (arithmetic logic ALU control unit 502 (ALU Control r), instruction analysis unit 503 (Instruction Decoder), interrupt control unit 504 (Interrupt Controller), Timing Control Unit 505 (Ti ming Controller), Register 506 (Register), Register Control Register Controller 507, Bus Interface 508 (Bus I / F), read-only memory 509, and memory interface 510 ( It has a ROM I / F.

[0266] An instruction input to the microprocessor 500 via the bus interface 508 is The instruction is input to the command analysis unit 503, decoded, and then passed to the arithmetic circuit control unit 502 and the interrupt control unit 503. The signal is input to the register control unit 504, the register control unit 507, and the timing control unit 505. 502, an interrupt control unit 504, a register control unit 507, and a timing control unit 505. In particular, the arithmetic circuit control unit 502 controls the arithmetic circuit The interrupt control unit 504 generates a signal for controlling the operation of the microphone 501. During program execution of the processor 500, an interrupt from an external input / output device or a peripheral circuit occurs. The request is processed based on its priority and mask state. 506 and writes the address of register 500 according to the state of microprocessor 500. The timing control unit 505 controls the arithmetic circuit 501 and the arithmetic circuit 6. Operations of the control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507 For example, the timing control unit 505 generates a signal to control the timing of the reference clock. An internal clock generating unit generates an internal clock signal CLK2 based on a clock signal CLK1. The clock signal CLK2 is supplied to the various circuits. The processor 500 is merely an example of a simplified configuration, and in reality, the processor may vary depending on the application. The present invention can have a wide variety of configurations.

[0267] Next, an example of a semiconductor device having a computing function capable of transmitting and receiving data in a non-contact manner will be described. This will be described with reference to Fig. 13. Fig. 13 shows a wireless communication system for transmitting and receiving signals to and from an external device. The following shows an example of a computer that operates according to the RFCPU5. The analog circuit section 511 has an analog circuit section 512 and a digital circuit section 513. 12, a resonant circuit 514 having a resonant capacitance, a rectifier circuit 515, a constant voltage circuit 516, It has a set circuit 517 , an oscillation circuit 518 , a demodulation circuit 519 , and a modulation circuit 520 . The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock Controller 523, interface 524, central processing unit 525, random access The memory 526 includes a read only memory 527 .

[0268] The operation of the RFCPU 511 having such a configuration is as follows. The received signal generates an induced electromotive force in the resonant circuit 514. The induced electromotive force is then fed to the rectifier circuit 515. The capacitor 529 is charged through the power supply. It is preferable that the capacitance part 529 is formed of a capacitor such as a multilayer capacitor. It does not have to be integral with the FCPU511, but rather the RFCPU511 must be configured as a separate part. It is sufficient that the semiconductor device is attached to a substrate having an insulating surface that supports the semiconductor device.

[0269] The reset circuit 517 generates a signal that resets and initializes the digital circuit section 513 . For example, a signal that rises with a delay after the power supply voltage rises is generated as a reset signal. The circuit 518 varies the frequency of the clock signal in response to a control signal generated by the constant voltage circuit 516. The demodulation circuit 519, which is formed by a low-pass filter, changes the frequency and duty ratio. For example, the modulation circuit 520 converts the amplitude fluctuation of a received signal in an amplitude shift keying (ASK) format into a binary signal. The transmission data is transmitted by varying the amplitude of the transmission signal using the amplitude shift keying (ASK) method. 520 changes the amplitude of the communication signal by changing the resonance point of the resonant circuit 514. The clock controller 523 controls the power supply voltage or the power consumption of the central processing unit 525. A control signal is generated to change the frequency and duty ratio of the clock signal according to the current. The power supply voltage is monitored by a power supply management circuit 530.

[0270] The signal input from the antenna 528 to the RFCPU 511 is demodulated by the demodulation circuit 519 and then The control command is then decomposed into control commands and data by the RF interface 521. The control command is stored in the control register 522. reading data stored in the memory 526; writing data to the random access memory 526; It contains operation instructions to the central processing unit 525. The central processing unit 525 A read-only memory 527 and a random access memory 525 are connected via an interface 524. 26, access to the control register 522. The interface 524 is From the address requested by the address register 525, the read-only memory 527 and the random access memory 528 are 526, and the control register 522. do.

[0271] The central processing unit 525 operates by storing an OS (operating system) in a read-only memory 527. The operating system is stored in the memory, and the program is read and executed when the computer is started. In addition, a dedicated circuit can be used to configure the arithmetic circuit, and the arithmetic processing can be performed in hardware. It is also possible to use a method that uses both hardware and software. The CPU performs some of the processing in a dedicated arithmetic circuit and the remaining calculations are performed by a central processing unit using a program. The method executed by the CPU 525 can be applied.

[0272] In the microprocessor of this embodiment, a pair of semiconductor integrated circuits are sandwiched between the pair of The impact resistant layer and the impact diffusion layer laminated on the semiconductor integrated circuit enable the device to be thin and It is possible to provide a semiconductor device that is compact, strong, and highly reliable.

[0273] (Embodiment 9) In this embodiment mode, an example of a usage mode of the semiconductor device described in the above embodiment mode will be described. Specifically, an application example of a semiconductor device capable of contactless data input / output is shown in FIG. The following will explain the use of semiconductor devices that can input and output data without contact. Depending on the state, it can be RFID tag, ID tag, IC tag, IC chip, RF tag, wireless tag, electric Also called a child tag or wireless chip.

[0274] An example of a top surface structure of the semiconductor device described in this embodiment mode will be described with reference to FIG. The semiconductor device 2180 shown in FIG. 10 includes a plurality of transistors constituting a memory section and a logic section. A thin film integrated circuit 2131 having an element such as a transistor and a conductive layer 213 functioning as an antenna are provided. The conductive layer 2132 functioning as an antenna is connected to the thin film integrated circuit 2131. The thin film integrated circuit 2131 is electrically connected to the transistor shown in the above embodiment mode 2. A stamp can be applied. The conductive layer functioning as an antenna may be provided above or below the thin film integrated circuit. A conductive layer that functions as an antenna may be provided on the outside of the impact-resistant layer. A conductive layer 2132 functioning as a photoresist is separately provided on a substrate 2133, and then the substrate 2133 and A thin film integrated circuit 2131 is attached so that a conductive layer 2132 is placed between the thin film integrated circuit 2131 and the conductive layer 2132. The connection terminal of the thin film integrated circuit 2131 and the conductive layer functioning as an antenna are bonded to each other. Alternatively, the electrical connection may be made via conductive particles contained in a resin having electrical conductivity. A non-contact current is applied between the antenna electrically connected to the thin film integrated circuit and the interrogator. The present invention is applied to a semiconductor device provided with a booster antenna capable of converting the frequency of a wave. It is also possible to apply

[0275] Semiconductor devices include not only field effect transistors as semiconductor elements, but also recording devices using semiconductor layers. This allows the creation of semiconductor devices that meet the requirements for a wide range of applications, including memory elements. It can be produced and provided.

[0276] In this embodiment mode, the conductive layer 2132 functioning as an antenna is provided in a coil shape. Although an example of applying a magnetic induction method or an electromagnetic coupling method is shown, the semiconductor device is not limited to this. It is also possible to use a microwave system. In the case of the microwave system, the wavelength of the electromagnetic wave used is The shape of the conductive layer 2132 functioning as an antenna can be determined appropriately depending on the shape.

[0277] For example, a microwave method (e.g., UHF band) is used as a signal transmission method in semiconductor devices. When applying the signal The shape of the conductive layer, such as its length, that functions as an antenna is determined taking into account the wavelength of the electromagnetic waves used to transmit the signal. For example, the conductive layer that functions as an antenna may be formed in a linear shape (e.g., a dipole). antenna), flat shape (e.g. patch antenna or ribbon type shape), etc. In addition, the shape of the conductive layer 2132 functioning as an antenna is not limited to a linear shape. The electromagnetic wave wavelength is taken into consideration and the shape is curved, meandering, or a combination of these. This is also fine.

[0278] The conductive layer that functions as an antenna can be formed by CVD, sputtering, screen printing, or gravure printing. Using printing methods such as inkjet printing, droplet ejection, dispenser method, plating method, etc., the device is shaped using conductive materials. The conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu ), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), tantalum (Ta ), molybdenum (Mo), or other metal elements, or alloy materials or compounds containing such metal elements The material is formed into a single layer structure or a laminated structure.

[0279] For example, in the case where the conductive layer 2132 functioning as an antenna is formed by screen printing, In this case, conductive particles with a particle size of several nm to several tens of μm are dissolved or dispersed in an organic resin. The conductive particles can be formed by selectively printing a conductive paste. , silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo), titanium (Ti), etc. One or more metal particles or silver halide microparticles or dispersible nanoparticles can be used. In addition, the organic resin contained in the conductive paste acts as a binder, solvent, dispersant, and and an organic resin functioning as a coating material. Representative examples include organic resins such as epoxy resin and silicon resin. In the case of forming the conductive paste, it is preferable to sinter it after extruding the conductive paste. The paste material is made of silver-based fine particles (for example, particles with a diameter of 1 nm or more and 100 nm or less). When using the fine particles below, hardening is achieved by baking at temperatures ranging from 150°C to 300°C. The conductive layer can be formed by bonding the solder or lead-free solder. Fine particles may be used, and in this case, it is preferable to use fine particles having a particle size of 20 μm or less. Solder and lead-free solder have the advantage of being low cost.

[0280] The semiconductor device to which the present invention is applied comprises a pair of shock-resistant layers sandwiching a semiconductor integrated circuit therebetween, and a semiconductor The impact diffusion layer is laminated on the integrated circuit, achieving a thinner and smaller size. A semiconductor device having high strength and high reliability can be obtained. This is effective for a small semiconductor device that can input and output data without contact. .

[0281] (Embodiment 10) In this embodiment, a non-contact data input / output device formed using the above-described present invention is used. An example of application of a certain semiconductor device will be described below with reference to the drawings. Depending on the form of use, semiconductor devices that can be used for input include RFID tags, ID tags, and IC tags. It is also called an IC chip, RF tag, wireless tag, electronic tag or wireless chip.

[0282] The semiconductor device 800 has a function of contactlessly exchanging data, and includes a high-frequency circuit 810, a power supply circuit 820, and a a reset circuit 830, a clock generating circuit 840, a data demodulation circuit 850, and a data A data modulation circuit 860, a control circuit 870 for controlling other circuits, a memory circuit 880, and an antenna The high-frequency circuit 810 has an antenna 890 (see FIG. 11(A)). A signal is received, and the signal received by the data modulation circuit 860 is output from the antenna 890. The power supply circuit 820 is a circuit that generates a power supply potential from a received signal, and the reset circuit A circuit 830 is a circuit for generating a reset signal, and a clock generating circuit 840 is a circuit for generating a reset signal. It is a circuit that generates various clock signals based on the received signal input from 0, and is a data demodulation circuit. The circuit 850 demodulates the received signal and outputs it to the control circuit 870. Reference numeral 60 denotes a circuit for modulating a signal received from a control circuit 870. For example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and and an output unit circuit 940. The code extraction circuit 910 is a control circuit A circuit that extracts each of the multiple codes contained in the command sent to 870. The command decision circuit 920 compares the extracted code with the code corresponding to the reference. The CRC determination circuit 930 is a circuit that determines the contents of the transmitted This is a circuit that detects the presence or absence of errors.

[0283] Next, an example of the operation of the above-described semiconductor device will be described. A radio signal is received. The radio signal is sent to the power supply circuit 820 via the high frequency circuit 810. A high power supply potential (hereinafter, referred to as VDD) is generated. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is also supplied to the data demodulation circuit 850. The signal is demodulated (hereinafter, demodulated signal). The signal passing through the clock generating circuit 840 and the demodulated signal are sent to the control circuit 870. The signal sent to the control circuit 870 is input to the chord extraction circuit 910, the chord determination circuit 920, and and a CRC determination circuit 930, etc., analyze the signal. The information on the semiconductor device stored in the memory circuit 880 is output. The device information is encoded through the output unit circuit 940. The information of the body device 800 passes through a data modulation circuit 860 and is converted into a radio signal by an antenna 890. In addition, in the multiple circuits constituting the semiconductor device 800, The power supply voltage VSS is common to both terminals, and VSS can be set to GND.

[0284] In this manner, a signal is sent from the communication device to the semiconductor device 800, and the signal is transmitted from the semiconductor device 800. The data of the semiconductor device 800 is read by receiving the transmitted signal with a communication device. It becomes possible to do so.

[0285] In addition, the semiconductor device 800 does not have a power source (battery) to supply the power supply voltage to each circuit. It can be a type that uses electromagnetic waves, or it can be equipped with a power source (battery) and uses electromagnetic waves and a power source ( The power supply voltage may be supplied to each circuit from a power source such as a battery.

[0286] Next, an example of a usage form of a semiconductor device capable of contactless data input / output will be described. A communication device 3200 is provided on the side of the mobile terminal including the display unit 3210, and an item 3220 A semiconductor device 3230 is provided on the side of the article 3220 (FIG. 11(B)). When the communication device 3200 is held over the body device 3230, the raw materials and origin of the product are displayed on the display unit 3210. Information about the product, such as inspection results for each production process, distribution history, and product descriptions, is also available. In addition, when the product 3260 is conveyed by the belt conveyor, the communication device 324 0 and a semiconductor device 3250 provided on the product 3260 is used to inspect the product 3260. In this way, the semiconductor device can be used in the system. This makes it easy to obtain information, resulting in high functionality and high added value.

[0287] As described above, the highly reliable semiconductor device of the present invention has a very wide range of applications, and is applicable to a wide range of electronic fields. It can be used in equipment.

[0288] (Embodiment 11) According to the present invention, a chip having a processor circuit (hereinafter referred to as a processor chip, a wireless chip, a wireless The present invention also provides a semiconductor device that functions as a wireless processor, a wireless memory, or a wireless tag. The semiconductor device of the present invention can be used in a wide range of applications, and can be used to obtain information such as the history of an object in a non-contact manner. It can be applied to any product that is useful for production and management. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, etc. , recording media, personal belongings, vehicles, food, clothing, health products, daily necessities, medicines, and The device can be installed in electronic devices, etc. Examples of the device will be described with reference to FIG.

[0289] Banknotes and coins are money that circulates in the market and are used in the same way as currency in a particular region. This includes (cash vouchers), commemorative coins, etc. Securities include checks, securities, promissory notes, etc. A chip 190 having a processor circuit may be provided (see FIG. 9(A)). This refers to a driver's license, a resident's card, etc., and includes a chip 191 having a processor circuit. (See Figure 9(B)). Personal items refer to bags, glasses, etc., and are items that have a processor circuit. A chip 197 for storing the bearer bond can be provided (see FIG. 9(C)). This refers to rice coupons, various gift certificates, etc. Packaging containers include wrapping paper for lunch boxes, plastic bottles, etc. and the like, and a chip 193 having a processor circuit can be provided (see FIG. 9(D)). The books refer to books, etc., and are provided with a chip 194 having a processor circuit. (See Figure 9(E)). Recording media refers to DVD software, video tapes, etc. A chip 195 having a processor circuit can be provided (see FIG. 9(F)). The vehicle may be equipped with a chip 196 having a processor circuit. (See Figure 9(G)). Foodstuffs refer to foodstuffs, beverages, etc. Clothing refers to clothing, footwear, etc. Healthcare products include medical equipment, health equipment, etc. Living goods include furniture, lighting, etc. Equipment, etc. Chemicals include medicines, pesticides, etc. Electronic devices include liquid crystal display devices, EL This refers to display devices, television devices (television sets, flat-screen television sets), mobile phones, etc.

[0290] Such a semiconductor device can be provided by attaching it to the surface of an article or by embedding it in an article. For example, in the case of a book, it can be embedded in the paper, and if the packaging is made of organic resin, it can be used The device can be embedded in resin.

[0291] In this way, packaging containers, recording media, personal items, food, clothing, daily necessities, electronic devices, By installing semiconductor devices in equipment, the efficiency of inspection systems and rental store systems can be improved. Furthermore, by providing a semiconductor device in vehicles, it is possible to prevent counterfeiting and theft. In addition, by embedding the information in animals and other living things, it is possible to identify individual living things. For example, by embedding a semiconductor device equipped with a sensor in a living thing such as livestock, By fitting or attaching it, you can record information such as birth year, gender, breed, body temperature, etc. It becomes possible to easily manage health conditions.

[0292] This embodiment mode can be implemented in appropriate combination with any of the above-described embodiment modes 1 to 10. It is Noh.

Claims

[Claim 1] a semiconductor integrated circuit sandwiched between a pair of a first impact resistant layer and a second impact resistant layer; an impact diffusion layer between the semiconductor integrated circuit and the second impact resistant layer; The semiconductor device according to the present invention is characterized in that the impact diffusion layer has a lower elastic modulus and a higher breaking strength than the first impact resistant layer and the second impact resistant layer.

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