Gate-all-around integrated circuit structure having differential NANO wire thickness and gate oxide thickness

Abstract

To provide a gate-all-around integrated circuit structure having a differential nanowire thickness and a gate oxide thickness, a computing device, and a manufacturing method for the same.SOLUTION: An integrated circuit structure includes a nanowire 102 having an outer thickness Th1 and an inner thickness Th2, and the inner thickness is smaller than the outer thickness. The nanowire tapers from an outer region 104A having an outer thickness to an inner region 104C having the inner thickness. A dielectric material is on the nanowire so that combined thickness of the nanowire and the dielectric material in the inner region is about the same as outer thickness of the nanowire and surrounds the nanowire.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] For the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for an increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing the size of transistors allows for a greater number of memory or logic devices to be integrated onto a chip, resulting in increased performance of the manufactured products. However, this push towards ever greater performance is not without problems. The need to optimize the performance of each device becomes increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more widely used as device dimensions continue to shrink. In conventional processes, tri-gate transistors are generally fabricated on substrates, either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and because they allow for a less complex tri-gate fabrication process. In another aspect, maintaining mobility improvement and short-channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node presents a challenge to device fabrication. Nanowires used to fabricate devices provide improved short-channel control.

[0003] However, multi-gate and nanowire transistors have not been scaled without consequences. As the dimensions of these building blocks of microelectronic circuits decrease, and as the number of very many building blocks manufactured in a given area increases, the constraints on the lithographic processes used to pattern these building blocks increase. In particular, there can be a trade-off between the minimum dimensions (critical dimensions) of features patterned in the semiconductor stack and the spacing between such features. [Brief description of the drawings]

[0004] [Figure 1A] 1A-1D are cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having an increased effective gate oxide thickness according to one embodiment of the present disclosure. [Figure 1B] 1A-1D are cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having an increased effective gate oxide thickness according to one embodiment of the present disclosure.

[0005] [Figure 2A] 1A-1D are cross-sectional views illustrating various steps in a method of nanowire conversion according to one embodiment of the present disclosure. [Figure 2B] 1A-1D are cross-sectional views illustrating various steps in a method of nanowire conversion according to one embodiment of the present disclosure.

[0006] [Figure 3A] 1A-1C are cross-sectional views illustrating various steps in a method of fabricating another gate-all-around integrated circuit structure having a depopulated channel structure according to one embodiment of the present disclosure. [Figure 3B] 1A-1C are cross-sectional views illustrating various steps in a method of fabricating another gate-all-around integrated circuit structure having a depopulated channel structure according to one embodiment of the present disclosure. [Figure 3C]1A-1C are cross-sectional views illustrating various steps in a method of fabricating another gate-all-around integrated circuit structure having a depopulated channel structure according to one embodiment of the present disclosure. [Figure 3D] 1A-1C are cross-sectional views illustrating various steps in a method of fabricating another gate-all-around integrated circuit structure having a depopulated channel structure according to one embodiment of the present disclosure.

[0007] [Figure 4A] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4B] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4C] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4D] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4E] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4F] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4G] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4H] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4I] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4J] 1A-1D are cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure.

[0008] [Diagram 5] 1 is a cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to one embodiment of the present disclosure.

[0009] [Figure 6] FIG. 1 shows a cross-sectional view cut through the nanowires and fins of a no-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)), according to one embodiment of the present disclosure.

[0010] [Figure 7] 1A-1D are cross-sectional views illustrating various steps in a method for fabricating a self-aligned gate endcap (SAGE) structure with a gate-all-around device according to one embodiment of the present disclosure.

[0011] [Figure 8A] 1 is a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to one embodiment of the present disclosure.

[0012] [Figure 8B] 8B is a cross-sectional view of the source or drain of the nanowire-based integrated circuit structure of FIG. 8A taken along the a-a' axis according to one embodiment of the present disclosure.

[0013] [Figure 8C] 8B is a cross-sectional channel diagram of the nanowire-based integrated circuit structure of FIG. 8A taken along the bb' axis according to one embodiment of the present disclosure.

[0014] [Figure 9A]1A-1D are three-dimensional cross-sectional views illustrating various steps in a method for fabricating the nanowire portion of a fin / nanowire structure according to one embodiment of the present disclosure. [Figure 9B] 1A-1D are three-dimensional cross-sectional views illustrating various steps in a method for fabricating the nanowire portion of a fin / nanowire structure according to one embodiment of the present disclosure. [Figure 9C] 1A-1D are three-dimensional cross-sectional views illustrating various steps in a method for fabricating the nanowire portion of a fin / nanowire structure according to one embodiment of the present disclosure. [Figure 9D] 1A-1D are three-dimensional cross-sectional views illustrating various steps in a method for fabricating the nanowire portion of a fin / nanowire structure according to one embodiment of the present disclosure. [Figure 9E] 1A-1D are three-dimensional cross-sectional views illustrating various steps in a method for fabricating the nanowire portion of a fin / nanowire structure according to one embodiment of the present disclosure.

[0015] [Figure 10] A computing device according to one implementation of one embodiment of the present disclosure.

[0016] [Figure 11] 1 is an interposer including one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] A gate-all-around integrated circuit structure having differential nanowire thickness and gate oxide thickness, and a method for fabricating a gate-all-around integrated circuit structure having differential nanowire thickness and gate oxide thickness are described. In the following description, numerous specific details are described, such as specific integration and material regimes, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail in order to avoid unnecessarily obscuring the embodiments of the present disclosure. It should further be understood that the various embodiments shown in the drawings are illustrative and not necessarily drawn to scale.

[0018] Certain terms may also be used in the following description for reference purposes only and are not intended to be limiting. For example, terms such as "top," "bottom," "upper," and "lower" refer to directions within the referenced drawings. Terms such as "front," "back," "rear," and "side" describe the orientation and / or location of parts of a component within any consistent frame of reference that is made clear by reference to the text and associated drawings that describe the component under discussion. Such terms may include those specifically mentioned above, derivatives thereof, and words of similar import.

[0019] The embodiments described herein may relate to semiconductor processing and construction at the substrate end of line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned on a semiconductor substrate or layer. FEOL generally encompasses everything up to but not including the deposition of metal interconnect layers. After the last FEOL step, the result is typically a wafer with isolated (e.g., no wires) transistors.

[0020] The embodiments described herein may relate to semiconductor processing and structures at the back-end of the interconnect (BEOL). BEOL is the second part of IC manufacturing where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with the wiring on the wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added at the BEOL.

[0021] The embodiments described below may be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, while exemplary processing schemes may be illustrated using a FEOL processing scenario, such approaches may also be applied to BEOL processing. Similarly, while exemplary processing schemes may be illustrated using a BEOL processing scenario, such approaches may also be applied to FEOL processing.

[0022] One or more embodiments described herein relate to complementary field effect transistors (CFETs) with differential nanowire thickness and gate oxide thickness (tox) for high voltage applications. One or more embodiments relate to high voltage CFET devices with differential nanowire tox for I / O applications. It should be understood that unless expressly stated otherwise, references to nanowires herein may refer to nanowires or nanoribbons or nanosheets.

[0023] The embodiments described herein may be implemented to enable thick gate high voltage devices in CFET (stacked CMOS) architectures by creating tapered ribbons and growing thicker oxides in the channel region to support high voltage applications. Structurally, a cross-sectional view of the channel may show a tapered ribbon with a thermally grown or deposited thick oxide.

[0024] To explain, thick gate or high voltage device formation in finFETs and planar types is achieved by having long channel devices with roughly 10 times wider channels (more space between source or drain (S / D) compared to logic computing devices). Concomitantly, thick gate devices also require thicker tox (gate oxide) to support high gate voltages. Thermally grown gate oxide may be the best option since it can be manufactured without defects, however, fin consumption and degraded performance prevent finFETs from using all thermally grown oxide. Alternatively, starting with wider fins is an option, but this leads to poor work function complications between fins resulting in short channel losses. Another option is to deposit thicker oxide on narrow fins, but this leads to transition between gate oxides resulting in degraded gate reliability modes. In the case of SiGe fins, growing oxide with SiGe consumption leads to performance and reliability issues. For SiGe channels, oxide deposition may be the approach of choice.

[0025] For gate-all-around (GAA) architectures, providing thick oxides is tricky due to the close spacing between vertically adjacent nanowires or nanoribbons. There can be problems associated with depositing thick gate oxides that reduce ribbon-ribbon spacing. Thermally grown oxides consume ribbons, resulting in yield issues. In constrained ribbon space environments, thick oxides can prevent work function gate material from being present between nanoribbons. This can result in short channel loss and reliability concerns.

[0026] The GAA problem described above (narrow spacing between ribbons) can also be present in CFET architectures where two transistors are stacked on top of each other. In a CFET architecture, the top device can be either NMOS or PMOS, and the bottom device can be the inverse type of the top type. Both NMOS and PMOS devices can be created by having the respective S / D materials. However, problems with current state of the art architectures include that, since it is necessary to deposit a thicker oxide for wide gate devices to support high voltages, the spacing between nanoribbons is reduced, which can cause problems with metal gates that should be present.

[0027] According to one embodiment of the present disclosure, the CFET architecture has a wider channel for high voltage devices, but starts with a thicker nanoribbon during the epitaxy stage. For PMOS, the approach involves converting the silicon nanoribbon to SiGe by depositing a thin SiGe film around the silicon nanoribbon and annealing at 900-1000°C. Without being bound by theory, the understanding is that this process allows the SiGe to diffuse into the Si, causing the nanoribbon to convert from silicon to SiGe (NMOS nanoribbons remain silicon). During the process, the nanoribbon becomes structurally tapered (dumbbell shaped) starting from the source of the channel towards the drain. This taper allows space for the deposition of a thick oxide.

[0028] Advantages associated with implementing the embodiments described herein may include high performance due to thick gate oxide that does not compromise the SiGe channel in PMOS and the spacing between nanoribbons.

[0029] As an exemplary approach to providing increased tox to a device, FIGS. 1A and 1B show cross-sectional views illustrating various steps in a method for fabricating an integrated circuit structure having an increased effective gate oxide thickness according to one embodiment of the present disclosure.

[0030] 1A, the starting structure 100 includes a released nanowire 102 supported by a source structure (S) 106 and a drain structure (D) 108, and a dielectric gate spacer 110. The starting structure 100 may represent an intermediate structure following a dummy gate removal (to form a gate cavity 112) and nanowire release process. In one embodiment, the intermediate structure is shown following a conversion process from a silicon nanowire to a silicon germanium nanowire 102, for example using a process as described above. In one embodiment, the conversion process provides the nanowire 102 with an outer thickness (Th1) that is approximately the same as the initial thickness, and an inner thickness (Th2) that is smaller than the initial thickness. The nanowire 102 tapers from a region 104A having a thickness Th1 along region 104B to an inner region 104C having a thickness Th2 that is smaller than Th1.

[0031] 1B, a dielectric material 152 is formed on the structure of FIG. 1A to form a structure 150. In one embodiment, the dielectric material 152, such as a silicon oxide or silicon dioxide material, surrounds the silicon germanium nanowire 102 in the gate cavity 112, such that the combined thickness of the silicon germanium nanowire 102 and the dielectric material 152 in region 104C (inner region) is approximately the same as the thickness of the silicon germanium nanowire 102 in region 104A (outer region). The structure 150 effectively allows the dielectric 152 to be provided to increase the tox of the ultimately formed device without crowding out the deposition of the gate electrode material. For example, in one embodiment, following deposition of the dielectric material 152, a gate stack including a high-k gate dielectric layer and one or more metal gate electrode layers can be formed around the dielectric material 152 on the silicon germanium nanowire 102. The tox of the resulting structure is greater than the tox of a device that does not include the dielectric material 152 between the nanowires and the high-k gate dielectric layer and the metal gate electrode layer or layers.

[0032] In another aspect, only selected wires undergo conversion from silicon nanowires to silicon germanium nanowires. As an exemplary process, Figures 2A and 2B show cross-sectional diagrams illustrating various steps in a method of nanowire conversion according to one embodiment of the present disclosure.

[0033] 2A, the structure includes a logic region 204 and an I / O region 206 above a substrate 202. The logic region 204 includes lower silicon nanowires 208 and upper silicon nanowires 210 between gate spacers 216. The I / O region 206 includes lower silicon nanowires 212 and upper silicon nanowires 214 between gate spacers 218. In one embodiment, for the same vertical height, there are fewer upper silicon nanowires 214 than upper silicon nanowires 210, and for the same vertical height, there are fewer lower silicon nanowires 212 than lower silicon nanowires 208. Furthermore, each of the nanowires 212 and 214 has a thickness greater than the thickness of each of the nanowires 208 and 210.

[0034] 2B, the lower silicon nanowires 208 and 212 are masked and the upper silicon nanowires 210 and 214 are converted into silicon germanium nanowires 210A and 214A, respectively, to provide structure 250. In one embodiment, the upper silicon germanium nanowires 210A define a PMOS region for the logic region 204, and the lower silicon nanowires 208 define an NMOS region for the logic region 204. The upper silicon germanium nanowires 214A define a PMOS region for the I / O region 206, and the lower silicon nanowires 212 define an NMOS region for the I / O region 206. In one embodiment, for the same vertical height, there are fewer upper silicon germanium nanowires 214A than upper silicon germanium nanowires 210A. In one embodiment, subsequent processing may include forming gate dielectric and gate electrode layers around the nanowires of structure 250. In one such embodiment, the top silicon germanium nanowires 214A in the PMOS region of the I / O region 206 are first subjected to the process described in connection with Figure 1B to effectively increase to for the I / O PMOS device without crowding out the subsequently formed gate structure. In one such embodiment, the resulting to can support greater than 1.2V versus 1.2V or less for a structure without the dielectric material.

[0035] In another aspect, one or more embodiments described herein relate to self-aligned bottom-up oxidation for nanowire transistor channel depopulation and nanoribbon transistor channel depopulation.

[0036] To explain, the integration of nanowire and / or nanoribbon complementary metal oxide semiconductor (CMOS) transistors faces the challenge of forming devices with different strengths. In current finFET technology, device strength granularity is realized by varying the number of fins in the device channel. This option is unfortunately not easily available for nanowire and nanoribbon architectures since the channels are vertically stacked. This requirement is even more demanding for nanowire and / or nanoribbon (NW / NR) structures in self-aligned stacked CMOS structures where the NMOS and PMOS channels are patterned with the same width. Previous attempts to address the above problem have included (1) integrating NW / NR devices with various channel widths (an option only available for nanoribbons that require complex patterning) or (2) subtractively removing the wires / ribbons from the source / drain or channel regions (a difficult option for stacked CMOS architectures).

[0037] To further explain, transistors with different drive currents may be required for different circuit types. The embodiments disclosed herein relate to achieving different drive currents by de-populating (de-popping) a number of nanowire transistor channels in a device structure. One or more embodiments provide a technique to remove a discrete number of wires from a transistor structure. The technique may be suitable for both ribbons and wires (RAW). Furthermore, transistor leakage currents flowing through the sub-fins must be controlled for proper circuit function. The embodiments disclosed herein provide a method for sub-fin isolation for nanowire transistors. With regard to de-population, techniques using FinFETs may de-populate a number of fins in each device to achieve different drive current strengths. With regard to sub-fin isolation, sub-fin implants are used to dope the sub-fins to reduce leakage. However, because nanowires are stacked and self-aligned, they cannot be de-populated (de-popped) in the same manner as fins. Furthermore, the sub-fin dopants must be targeted and can back-diffuse into the channel, degrading carrier transport.

[0038] According to one embodiment of the present disclosure, described herein is a process flow for achieving self-aligned bottom-up oxide nanowire transistor channel depopulation and / or sub-fin isolation. The embodiments may include nanowire transistor channel depopulation to enable modulation of drive current in various devices that may be required for various circuits. The embodiments may be implemented as a self-aligned approach that enables deep scaling for future nanowire technologies.

[0039] According to one embodiment of the present disclosure, nanowire fabrication of alternating Si / SiGe stacks includes patterning the stacks into fins. A generic dummy gate (which may or may not be a poly dummy gate) is patterned and etched. During a subsequent step, the NW / NR channel is released. Following the NW / NR channel release, a thin oxide catalyst layer (e.g., Al 2 O 3 ) is deposited on the NW / NR channel using, for example, an atomic layer deposition (ALD) process. In a particular embodiment, a masking film (e.g., carbon hardmask (CHM)) is then deposited to fill the gate trench, followed by a recess etch, leaving the CHM covering the ribbons to be converted to an oxide. The oxidation catalyst layer is then removed from the exposed ribbons using a selective wet etchant such as dilute hydrogen fluoride or aqueous ammonium hydroxide-peroxide solution. The hardmask is then subsequently removed by exposing it to an oxygen plasma to reveal the oxidation catalyst layer (e.g., Al 2 O 3 ) encapsulates only the bottom NW / NR channel(s). The bottom NW / NR channel(s) are then selectively converted to an oxide (e.g., silicon oxide from oxidizing the silicon NW / NR channel) by subjecting them to wet oxidation annealing. An oxidation catalyst layer (e.g., Al 2 O 3 ) promotes oxygen diffusion into silicon (Si), so that the bottom NW / NR channel or channels are formed by oxide (e.g., SiO 2) is rapidly converted to Si. The oxidation conditions selected may be very mild so that little oxidation occurs on the top ribbons that are not encapsulated by the oxidation catalyst layer. In this way, the Si nanowires are oxidized bottom-up. Although some embodiments describe the use of Si (wire or ribbon) and SiGe (sacrificial) layers, other pairs of semiconductor materials that can be alloyed and epitaxially grown, such as InAs and InGaAs, or SiGe and Ge, can be implemented to realize various embodiments herein. The embodiments described herein enable the fabrication of self-aligned stacked transistors with a variable number of active nanowires or nanoribbons in the channel, and methods to realize such structures.

[0040] It is to be understood that the embodiments described herein may be implemented to fabricate nanowire and / or nanoribbon structures having various numbers of active wire / ribbon channels. It is to be understood that the embodiments described herein may involve selective oxidation approaches to achieve such structures. The embodiments described herein may be implemented to enable the fabrication of nanowire / nanoribbon-based CMOS architectures.

[0041] In one embodiment, to design different devices with different drive current strengths, a self-aligned depopulation (depop) flow can be patterned using lithography so that ribbons and wires (RAWs) are depopped only from certain devices. In one embodiment, the entire wafer can be depopped uniformly so that all devices have the same number of RAWs. It should be understood that when depop is performed through the gate trench, some epitaxial (epi) source or drain (S / D) material may be oxidized from the nearest gate electrode, which is different from performing depop through the S / D location.

[0042] In another aspect, front-to-back vias can be fabricated through the deposited gate region. The embodiments described herein can enable a space-efficient way of transmitting signals from a front-side interconnect to a back-side interconnect (or vice versa) without necessarily involving extensive etching or additional patterning steps.

[0043] To explain, the fabrication of state-of-the-art vias that transmit either signals or power from one side of a wafer to the other side of the wafer requires additional lithographic patterning and aggressive etching that can damage the surrounding material. Such prior approaches have designs that allow the vias to short to adjacent source or drain regions. However, such shorts may not be allowed in the current design of the self-aligned transistor.

[0044] According to one or more embodiments of the present disclosure, fins, nanowires, or nanoribbon structures, or the like, are fabricated to include conductive via structures in a self-aligned transistor technique. In a particular embodiment, a front-to-back via occupies the space of a fully populated gate region of its corresponding channel. In one embodiment, the via is composed of the same gate metal as the surrounding active gate region. The via connects the front and back interconnects in the same manner as the surrounding active gate region.

[0045] Advantages to implementing the embodiments described herein include, for example, enabling the ability to fabricate front-to-back vias that do not necessarily require additional lithographic patterning steps since depopulation processing is already required elsewhere in the self-aligned transistor processing flow. Embodiments may be implemented to enable front-to-back vias that do not necessarily require extremely aggressive etching that would otherwise damage surrounding materials (e.g., gate spacers, isolation caps / walls, plugs, etc.).

[0046] As an overview, in one embodiment, a self-aligned transistor is fabricated by polysilicon (or other dummy) gate removal. The transistor channel is exposed in the gate region. Upon exposure of the transistor channel, a portion of the channel may be populated as defined by lithographic patterning. In one example, the population may be, for example, a thin metal oxide (e.g., Al 2 O 3 Or La 2 O 3 ) may be conformally deposited around a particular channel to enhance the oxidation rate compared to a channel without a metal oxide thereon.

[0047] As an example dual oxidation processing scheme, Figures 3A-3D show cross-sectional views depicting various steps in a method of fabricating another gate-all-around integrated circuit structure having a depopulated channel structure according to one embodiment of the present disclosure. Although illustrated as two groups of three nanowires in each transistor region, it should be understood that any number of groupings, any number of channels in each grouping, or any channel geometry (e.g., nanoribbons, nanowires, fins) may be used. It should be understood that according to one or more embodiments described herein, one or more nanowires described in connection with Figures 3A-3D may undergo a differential gate oxide thickness process and / or a differential nanowire thickness process, as described in connection with Figures 1A-1B and / or 2A-2B.

[0048] 3A, a method of fabricating an integrated circuit structure includes forming a vertical arrangement 300 of active nanowires or nanoribbons above a substrate 302. A plurality of adjacent device locations, such as device locations 330A, 330B, and 330C, may be fabricated adjacent to one another. In one embodiment, a gate endcap structure separates the device locations 330A, 330B, and 330C. In one such embodiment, each of the gate endcap structures rests within a trench isolation layer 320A and includes a linear dielectric layer 320B and a fill dielectric layer 320C. A dielectric cap 320D may be formed on each of the endcap structures, examples of which are described in more detail below.

[0049] In one embodiment, each of device locations 330A, 330B, and 330C includes a bottom set of nanowires 304A, 304B, and 304C and an upper set of nanowires 314A, 314B, and 314C arranged as a vertical stack. A dielectric nanowire cap layer 314D is included above each set of nanowires, an example of the formation of which is described below. As will be explained in more detail in other embodiments described below, the channel regions of the bottom set of nanowires 304A, 304B, and 304C and the upper set of nanowires 314A, 314B, and 314C may be exposed during a replacement gate process during which an open trench 308A is formed to expose the channel regions. Trench 308A may be separated from other replacement gate trenches (eg, 308B and 308C) by sidewall spacers 310A, a trench fill dielectric layer 310B, and a hardmask cap or helmet 310C.

[0050] 3B, the bottom set of nanowires 304A, 304B, and 304C at device locations 330A and 330B are depopulated in a first oxidation process. The bottom set of nanowires 304A, 304B, and 304C at device location 330C is not depopulated. In one embodiment, the bottom set of nanowires 304A, 304B, and 304C at device locations 330A and 330B are depopulated using an oxidation catalyst layer that is first formed on all the nanowires and then patterned to restrict the oxidation catalyst layer to the bottom set of nanowires 304A, 304B, and 304C at device locations 330A and 330B. A first oxidation process, such as the oxidation process described in connection with FIG. 2, is then performed to form oxide nanowires 350A, 350B, and 350C. The bottom set of active nanowires 304A, 304B, and 304C is held at device location 330C.

[0051] 3C, the bottommost nanowires 314A, 314B, and 314C of the top set of nanowires at device locations 330A and 330C are depopulated in a second oxidation process. The bottommost nanowires 314A, 314B, and 314C of the top set of nanowires at device location 330B are not depopulated. In one embodiment, the bottommost nanowires 314A, 314B, and 314C of the top set of nanowires at device locations 330A and 330C are depopulated using an oxidation catalyst layer that is first formed on all nanowires of the top set of nanowires and then patterned to restrict the oxidation catalyst layer to the bottommost nanowires 314A, 314B, and 314C of the top set of nanowires at device locations 330A and 330C.

[0052] In one embodiment, the bottom set of nanowires that previously underwent the first oxidation process are blocked by a bottom masking layer to allow the second selective oxidation process to be restricted to the top set of nanowires, allowing for a second "bottom-up" oxidation depopulation approach. A second oxidation process, such as that described in connection with FIG. 2, is then performed to form oxide nanowires 360A, 360B, and 360C. It should be understood that specific examples of depopulated nanowires versus active nanowires may include any suitable number of nanowires that may be retained or oxidized to form oxide nanowires using a first oxidation depopulation approach for the bottom set of nanowires and then a second oxidation depopulation approach for the top set of nanowires.

[0053] Referring to FIG. 3D, a permanent gate structure may be fabricated in trench 308A. In one exemplary embodiment, the permanent gate structure includes a lower gate dielectric 370 and a lower P-type gate electrode 372 thereon, and an upper gate dielectric 370 and an upper N-type gate electrode 374 thereon. In another exemplary embodiment, the permanent gate structure includes a lower gate dielectric and a lower N-type gate electrode thereon, and an upper gate dielectric and an upper P-type gate electrode thereon. In one embodiment, the permanent gate structure is formed around all of the nanowire / nanoribbon (NW / NR) channels, including the oxide NW / NR channels. In certain such embodiments, the oxidation catalyst layer is not removed and remains included in the final structure. However, in other embodiments, the oxidation catalyst layer is removed prior to permanent gate structure fabrication.

[0054] Referring again to FIG. 3D, according to one embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of nanowires (e.g., nanowires 350A, 350B, and 350C at device location 308B). The first vertical arrangement of nanowires has one or more oxide nanowires (e.g., nanowires 350A, 350B, and 350C). A first gate stack (e.g., 370 / 372) covers the first vertical arrangement of nanowires and is around the one or more oxide nanowires of the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the first vertical arrangement of nanowires (e.g., nanowires 314A, 314B, and 314C at device location 308B). The second vertical arrangement of nanowires has one or more active nanowires. A second gate stack covers the vertical arrangement of nanowires and surrounds one or more active nanowires of the second vertical arrangement of nanowires.

[0055] In one embodiment, one or more oxide nanowires have an oxidation catalyst layer thereon, for example as a residual or artifact layer remaining from multiple bottom-up channel depopulation processes. In one embodiment, the oxidation catalyst layer comprises aluminum oxide. In another embodiment, the oxidation catalyst layer comprises lanthanum oxide.

[0056] In one embodiment, the integrated circuit structure includes epitaxial source or drain structures at the ends of the first and second vertical arrangements of nanowires. In one such embodiment, the epitaxial source or drain structures are separate epitaxial source or drain structures, an example structure of which is described below. In another such embodiment, the epitaxial source or drain structures are non-separate epitaxial source or drain structures, an example structure of which is described below. In one embodiment, the first and second gate stacks have dielectric sidewall spacers and the epitaxial source or drain structures are buried epitaxial source or drain structures that extend below the dielectric sidewall spacers of the gate stacks, an example structure of which is described below.

[0057] In one embodiment, the integrated circuit structure further includes a pair of conductive contact structures coupled to the epitaxial source or drain structures. In one such embodiment, the pair of conductive contact structures is an asymmetric pair of conductive contact structures, example structures of which are described below.

[0058] In one embodiment, the first vertical arrangement of nanowires is above the fin, an example structure of which is described below. In one embodiment, the first gate stack comprises a first high-k gate dielectric layer and a first metal gate electrode, and the second gate stack comprises a second high-k gate dielectric layer and a second metal gate electrode.

[0059] It is to be understood that the embodiments described herein may be implemented to fabricate nanowire and / or nanoribbon structures having various numbers of active wire / ribbon channels. It is to be understood that the embodiments described herein may involve selective oxidation approaches to achieve such structures. The embodiments described herein may be implemented to enable the fabrication of nanowire / nanoribbon-based CMOS architectures.

[0060] Referring again to FIG. 3D, according to one embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of nanowires (e.g., nanowires at device location 308B) and a second vertical arrangement of nanowires (e.g., nanowires at device location 308C). The first vertical arrangement of nanowires has an active top nanowire (e.g., active nanowire 314C at device location 308B) and an oxide bottom nanowire (e.g., oxide nanowire 304A at device location 308B). The second vertical arrangement of nanowires has an oxide top nanowire (e.g., oxide nanowire 360C at device location 308C) and an active bottom nanowire (e.g., active nanowire 304C at device location 308C), and the first and second vertical arrangements of nanowires have coplanar top nanowires and coplanar bottom nanowires. A first gate structure 370 / 372 covers the first vertical arrangement of nanowires. A second gate structure 370 / 374 covers the second vertical arrangement of nanowires.

[0061] In one embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is the same as the horizontal width of the nanowires of the second vertical arrangement of nanowires. In one embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is greater than the horizontal width of the nanowires of the second vertical arrangement of nanowires. In one embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is smaller than the horizontal width of the nanowires of the second vertical arrangement of nanowires.

[0062] Referring again to FIG. 3D, in accordance with one or more embodiments of the present disclosure, all of the nanowire channels of the integrated circuit structure formed at device location 330A are depopulated, e.g., resulting in a "fully" depopulated structure at device location 330A. In one embodiment, the full depopulation is achieved using two successive bottom-up oxidation approaches. In one embodiment, the gate structures (e.g., 372 / 374) highlighted within the illustrated box 382 function as conductive vias. In one embodiment, the conductive vias are front-to-back vias.

[0063] Additionally, in one embodiment, the substrate 302 of Figures 3A-3C is replaced with a backside interconnect layer. The backside interconnect layer may include conductive lines 394 and conductive vias 396 in a dielectric layer 392 formed on an etch stop layer 398. In one embodiment, the substrate portion of Figure 3C is removed in a backgrinding process, an example of which is described in more detail below, and then an interconnect layer is formed thereon. Additionally, the structure in Figure 3D includes front side gate contacts or vias 380A, 380B, and 380C, which may include an insulating cap layer 390 formed thereon.

[0064] 3D, in one embodiment, integrated circuit structure 330A includes a vertical arrangement of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. All nanowires 350A, 350B, 350C, 360A, 360B, and 360C in the vertical arrangement of nanowires are oxide nanowires. Gate stacks 370 / 372 / 374 cover the vertical arrangement of nanowires and are around each of oxide nanowires 350A, 350B, 350C, 360A, 360B, and 360C. Gate stacks 370 / 372 / 374 include conductive gate electrodes 372 / 374.

[0065] In one embodiment, the integrated circuit structure 330A further includes a gate contact 380A above the vertical arrangement of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. The gate contact 380A contacts the top surface of the conductive gate electrode 372 / 374. The interconnect structure 394 / 396 is below the vertical arrangement of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. The conductive via 396 of the interconnect structure 394 / 396 contacts the bottom surface of the conductive gate electrode 372 / 374. The conductive gate electrode 372 / 374 serves as a conductive via between the gate contact 380A and the interconnect structure 394 / 396. In certain embodiments, oxide nanowires 350A, 350B, 350C, 360A, 360B, and 360C of the vertical arrangement of nanowires have an oxidation catalyst layer thereon.

[0066] According to one embodiment of the present disclosure, fabrication of the gate region that will become the front-to-back via does not necessarily require dedicated lithographic patterning to define the via. For example, in one embodiment, complete depopulation at selected locations is achieved by combining other depopulation steps. As described herein, such front-to-back via fabrication may not need to involve an aggressive etch to remove the depopulated channel so that surrounding materials (e.g., gate spacers, isolation walls, etc.) are not attacked. However, in some embodiments, the depopulated channel is selectively removed in the front-to-back via region prior to gate metallization using a less aggressive etch than would otherwise be associated with the opening of a similar via.

[0067] As mentioned above, nanowire release processing can be performed through replacement gate trenches. Examples of such release processes are described below. Additionally, in another aspect, backend (BE) interconnect scaling can result in reduced performance and increased manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to enable front and backside interconnect integration for nanowire transistors. The embodiments described herein can provide an approach to achieving relatively wide interconnect pitch. The result can be improved product performance and reduced patterning costs. The embodiments can be implemented to enable robust functioning of scaled nanowire or nanoribbon transistors with low power and high performance.

[0068] One or more embodiments described herein are directional dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In one embodiment, an integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides allows for direct contact with a backside interconnect level.

[0069] In an exemplary process flow, Figures 4A-4J show cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. It should be understood that, according to one or more embodiments described herein, one or more nanowires described in connection with Figures 4A-4J may undergo a differential gate oxide thickness process and / or a differential nanowire thickness process, such as described in connection with Figures 1A-1B and / or 2A-2B.

[0070] 4A, a method of manufacturing an integrated circuit structure includes forming a starting stack 400 including alternating silicon germanium layers 404 and silicon layers 406 over a fin 402, such as a silicon fin. The silicon layers 406 may be referred to as a vertical arrangement of silicon nanowires. As shown, a protective cap 408 may be formed over the alternating silicon germanium layers 404 and silicon layers 406.

[0071] 4B, a gate stack 410 is formed above the vertical arrangement of nanowires 406. As illustrated in FIG 4C, a portion of the vertical arrangement of nanowires 406 is then released by removing a portion of the silicon germanium layer 404 to provide a recessed silicon germanium layer 404' and a cavity 412.

[0072] It should be understood that the structure of FIG. 4C may be manufactured to completion without first performing the deep etch and asymmetric contact processing described below in connection with FIG. 4D.

[0073] Referring to Figure 4D, an upper gate spacer 414 is formed on the sidewalls of the gate structure 410. A cavity spacer 416 is formed in the cavity 412 below the upper gate spacer 414. A deep trench contact etch is then performed to form a trench 418 and form the recessed nanowire 406'. A sacrificial material 420 is then formed in the trench 418, as shown in Figure 4E.

[0074] 4F, a first epitaxial source or drain structure (e.g., left feature 422) is formed at a first end of the vertical arrangement of nanowire 406'. A second epitaxial source or drain structure (e.g., right feature 422) is formed at a second end of the vertical arrangement of nanowire 406'. As shown in FIG. 4G, an inter-layer dielectric (ILD) material 424 is then formed on either side of gate electrode 410 and adjacent to source or drain structure 422.

[0075] Referring to FIG. 4H, a replacement gate process is used to form a permanent gate dielectric 428 and a permanent gate electrode 426. In one embodiment, after removing the gate structure 410 and forming the permanent gate dielectric 428 and the permanent gate electrode 426, the recessed silicon germanium layer 404' is removed to leave the upper active nanowire or nanoribbon 406'. In one embodiment, the recessed silicon germanium layer 404' is selectively removed using a wet etch that does not etch the silicon layer but selectively removes the silicon germanium. For example, etching compounds such as a carboxylic acid / nitric acid / HF compound and a citric acid / nitric acid / HF compound may be utilized to selectively etch the silicon germanium. Halide-based dry etches or plasma-enhanced gas-phase etches may also be used to realize the embodiments herein.

[0076] 4H, one or more of the bottommost nanowires or nanoribbons 406' are then oxidized to form one or more oxide nanowires or nanoribbons 499, for example, by techniques described in connection with Figures 2 and 3A-3D. A permanent gate dielectric 428 and a permanent gate electrode 426 are then formed surrounding the nanowire or nanoribbon 406' and the one or more oxide nanowires or nanoribbons 499.

[0077] 4I, the ILD material 424 is then removed. The sacrificial material 420 is then removed from one of the source-drain locations (e.g., the right side) to form trench 432, but not from the other of the source-drain locations to form trench 430.

[0078] 4J, a first conductive contact structure 434 is formed and coupled to the first epitaxial source or drain structure (e.g., left feature 422). A second conductive contact structure 436 is formed and coupled to the second epitaxial source or drain structure (e.g., right feature 422). The second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434. In one embodiment, although not shown in FIG. 4J, the method further includes forming an exposed surface of the second conductive contact structure 436 at a bottom of the fin 402.

[0079] In one embodiment, as shown, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434. In one such embodiment, as shown, the first conductive contact structure 434 is not along the fin 402. In another such embodiment, not shown, the first conductive contact structure 434 is partially along the fin 402.

[0080] In one embodiment, the second conductive contact structure 434 is along the entirety of the fin 402. In one embodiment, not shown, the second conductive contact structure 434 may have an exposed surface at the bottom of the fin 402 if the bottom of the fin 402 is exposed by a backside substrate removal process.

[0081] In another aspect, to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein may be fabricated using backside exposure of frontside structure fabrication techniques. In some exemplary embodiments, exposing the backside of a transistor or other device structure involves backside processing at the wafer level. In contrast to conventional through-silicon-via TSV-type techniques, exposing the backside of a transistor as described herein may be performed at the density of device cells, even within sub-regions of a device. Furthermore, such exposure of the backside of a transistor may be performed to remove substantially all of the donor substrate on which the device layers are disposed during frontside device processing. Therefore, micron-deep TSVs may be unnecessary, since the semiconductor thickness in the device cells after exposing the backside of the transistor may potentially be only tens or hundreds of nanometers.

[0082] The exposure techniques described herein may enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer that is utilized in front-side fabrication, exposed from the back-side, and utilized again in back-side fabrication. Processing of both the front-side and exposed back-side of a device structure may address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0083] The technique of exposing the backside of the transistor can be utilized, for example, to remove at least a portion of the carrier layer and the intervening layer of the donor / host substrate assembly. The process flow starts with the input of the donor / host substrate assembly. The thickness of the carrier layer in the donor / host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be utilized. For example, if the carrier layer is a group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be utilized. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can be utilized.

[0084] In some embodiments, the above is preceded by cutting the carrier layer along a fracture surface substantially parallel to the intervening layer. The cutting or fracturing process may be utilized to remove a significant portion of the carrier layer as a bulk mass, reducing the grinding or etching time required to remove the carrier layer. For example, if the carrier layer is 400-900 μm thick, 100-700 μm may be cut off by performing any blanket implant known to promote wafer-level fracturing. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture surface is desired. Following such a cutting process, the thickness of the carrier layer remaining in the donor / host substrate assembly may then be ground or etched to complete removal. Alternatively, if the carrier layer is not fractured, grinding, polishing, and / or etching steps may be utilized to remove a larger thickness of the carrier layer.

[0085] The exposure of the intervening layer is then detected. The detection is used to identify when the back surface of the donor substrate has progressed approximately to the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials utilized for the carrier layer and the intervening layer may be implemented. In some embodiments, the one or more endpoint criteria are based on detecting a change in the optical absorption or emission of the back surface of the donor substrate during the polishing or etching performed. In some other embodiments, the endpoint criteria are related to a change in the optical absorption or emission of by-products during the polishing or etching of the donor substrate back surface. For example, the absorption or emission wavelengths associated with the carrier layer etching by-products may vary as a function of the different compositions of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are related to a change in the mass of species in the by-products of polishing or etching the back surface of the donor substrate. For example, the by-products of processing may be sampled by a quadrupole mass spectrometer, and the change in species mass may be correlated to the different compositions of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criterion is related to the change in friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0086] Detection of the intervening layer may be enhanced if the removal process is selective for the carrier layer compared to the intervening layer, since non-uniformity of the carrier removal process may be mitigated by the etch rate delta between the carrier layer and the intervening layer. Detection may even be skipped if the grinding, polishing, and / or etching step removes the intervening layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If no end point criteria are utilized, a grinding, polishing, and / or etching step of a pre-determined fixed duration may stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch. In some instances, the carrier etch rate:intervening layer etch rate is 3:1 to 10:1 or greater.

[0087] Upon exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. The thickness of the intervening layer may be uniformly removed, for example, by polishing. Alternatively, the thickness of the intervening layer may be removed using a mask or blanket etching process. The process may utilize the same polishing or etching process utilized to thin the carrier, or may be a different process having different process parameters. For example, if the intervening layer provides an etch stop for the carrier removal process, the subsequent step may utilize a different polishing or etching process that prioritizes removal of the intervening layer over removal of the device layer. If intervening layer thicknesses less than a few hundred nanometers are to be removed, the removal process may be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than those utilized for removal of the carrier layer. The CMP process utilized may utilize a slurry that provides very high (e.g., 100:1 to 300:1 or greater) selectivity between, for example, the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) that surrounds the device layer and is embedded within the intervening layer, for example, as electrical isolation between adjacent device regions.

[0088] For embodiments in which the device layer is exposed via complete removal of the intervening layer, backside processing may begin with the exposed backside of the device layer or specific device regions therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer that is disposed between the intervening layer and previously fabricated device regions in the device layer, such as source or drain regions.

[0089] In some embodiments where the carrier layer, intervening layer, or device layer backside is recessed using wet and / or plasma etching, such etching may be a patterned etch or a substantially selective etch that imparts significant non-planarity or topography to the device layer backside surface. As described further below, the patterning may be done within the device cells (i.e., "intra-cell" patterning) or across the device cells (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a partial thickness of the intervening layer is utilized as a hard mask for the backside device layer patterning. Thus, the mask etch process may be a precursor to a corresponding mask device layer etch.

[0090] The processing schemes described above may result in a donor / host substrate assembly including an IC device that exposes the backside of an intervening layer, the backside of a device layer, and / or the backside of one or more semiconductor regions within a device layer, and / or the front side metallization. Additional backside processing of any of these exposed regions may then be performed during downstream processing.

[0091] It should be understood that the structures resulting from the above exemplary processing schemes may be used in the same or similar form for subsequent processing steps to complete device fabrication, such as CMOS, PMOS, and / or NMOS device fabrication. As one example of a completed device, FIG. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure cut along a gate line, according to one embodiment of the present disclosure. It should be understood that, according to one or more embodiments described herein, one or more nanowires described in connection with FIG. 5 may undergo a differential gate oxide thickness process and / or a differential nanowire thickness process, as described in connection with FIGS. 1A-1B and / or 2A-2B.

[0092] 5, a semiconductor structure or device 500 includes a non-planar active area (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In one embodiment, instead of a solid fin, the non-planar active area is divided into nanowires (such as nanowires 504A and 504B) above the sub-fin region 505, as represented by the dashed lines. In either case, for ease of description of the non-planar integrated circuit structure 500, the non-planar active area 504 is referred to below as a protruding fin portion. For example, in one embodiment, the lower nanowire 504B is an oxide nanowire and the upper nanowire 504A is an active nanowire. In one embodiment, the lower oxide nanowire 504B includes an oxide catalyst layer thereon.

[0093] The gate line 508 is disposed above the overhanging portion 504 of the non-planar active area (including surrounding nanowires 504A and 504B, if applicable) and above a portion of the trench isolation region 506. As shown, the gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, the gate line 508 may also include a dielectric cap layer 554. Further visible from this perspective are a gate contact 514 and an overlying gate contact via 516, along with an overlying metal interconnect 560, all of which are disposed in a multiple interlayer dielectric stack or layer 570. As can be seen similarly from the perspective of FIG. 5, the gate contact 514, in one embodiment, is disposed above the trench isolation region 506 rather than above the non-planar active area.

[0094] In one embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In one such embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional object. In one such embodiment, the gate electrode stack of the gate line 508 encompasses at least a top surface and a pair of sidewalls of the three-dimensional object.

[0095] 5, in one embodiment, there is a boundary 580 between the protruding fin portion 504 and the sub-fin region 505. The boundary 580 can be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0096] Although not shown in FIG. 5, it should be understood that source or drain regions of or adjacent to the protruding fin portion 504 are on both sides of the gate line 508, i.e., the side leading into the page and the side leading out of the page. In one embodiment, the source or drain regions are doped portions of the original material of the protruding fin portion 504. In another embodiment, the material of the protruding fin portion 504 is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form an isolated epitaxial nub or a non-isolated epitaxial structure. In either embodiment, the source or drain regions may extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to one embodiment of the present disclosure, the more heavily doped sub-fin region, i.e., the doped portion of the fin below the boundary 580, inhibits source-to-drain leakage through this portion of the bulk semiconductor fin. In one embodiment, the source and drain structures are N-type epitaxial source and drain structures, both of which include phosphorus dopant impurity atoms. According to one or more embodiments of the present disclosure, the source and drain regions have associated asymmetric source and drain contact structures, as described above in connection with FIG.

[0097] Referring again to FIG. 5, in one embodiment, the fins 504 / 505 (and possibly the nanowires 504A and 504B) are comprised of crystalline silicon, silicon / germanium, or germanium layers doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof. In one embodiment, the concentration of silicon atoms is greater than 97%. In another embodiment, the fins 504 / 505 are comprised of III-V materials such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. The trench isolation region 506 may be comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0098] The gate line 508 may be comprised of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, lead zinc niobate, or combinations thereof. Additionally, a portion of the gate dielectric layer may include a layer of native oxide formed from the top several layers of the protruding fin portion 504. Additionally, it is comprised of a -k portion and a lower portion comprised of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, the portion of the gate dielectric is a "U" shaped structure that includes a bottom portion that is substantially parallel to the top surface of the substrate and two sidewall portions that are substantially perpendicular to the surface of the substrate.

[0099] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to, metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a particular embodiment, the gate electrode is composed of a non-work function setting fill material formed above a metal work function setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. In a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer allows for the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. In an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer allows for the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.2 eV. In some implementations, the gate electrode may consist of a "U" shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a flat layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of U-shaped and flat non-U-shaped structures, for example, the gate electrode may be comprised of one or more U-shaped metal layers formed on one or more flat non-U-shaped layers.

[0100] The spacers associated with the gate electrode stack may ultimately be composed of a material suitable for electrically isolating or contributing to the isolation of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts, etc. For example, in one embodiment, the spacers are composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0101] The gate contact 514 and the overlying gate contact via 516 may be composed of a conductive material. In one embodiment, one or more of the contacts or vias are composed of a metallic species. The metallic species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as an intermetallic alloy or a metal-semiconductor alloy (e.g., a silicide material, etc.).

[0102] In one embodiment (not shown), a contact pattern is formed that is essentially perfectly aligned to the existing gate pattern 508, eliminating the use of a lithography step with very limited alignment margin. In one embodiment, the contact pattern is a vertically asymmetric contact pattern, such as that described in connection with FIG. 4J. In another embodiment, all contacts are front-side connections and are not asymmetric. In one such embodiment, this self-aligned approach inherently enables the use of highly selective wet etches (e.g., versus conventionally performed dry or plasma etches) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, the present approach allows for the elimination of the need for an otherwise critical lithography step to create the contact pattern, as used in conventional approaches. In one embodiment, the trench contact grid is formed between the poly (gate) lines, rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning, but prior to the gate grid cut.

[0103] In one embodiment, providing the structure 500 involves fabricating the gate stack structure 508 by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from previous processing. In one embodiment, the dummy gate is removed by a dry or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is formed of SF 6In another embodiment, the dummy gate is made of polycrystalline or amorphous silicon and is removed using a dry etching process that includes the use of hydrous NH 4 The dummy gate is removed with a wet etch process that includes the use of tetramethylammonium hydroxide or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed with a wet etch that includes aqueous phosphoric acid.

[0104] 5, the layout of the semiconductor structure or device 500 positions the gate contact above the isolation region. Such a layout may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure above the active region, e.g., above the sub-fin 505, that contacts a portion of the gate electrode formed in the same layer as the trench contact via.

[0105] It should be understood that not all aspects of the process described above need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a gate-all-around (GAA) device, a tri-gate device, an independently accessed double-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-ten nanometer (10 nm) technology nodes.

[0106] In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulator material. Examples of suitable dielectric materials include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO 2 )), doped silicon oxide, fluorinated silicon oxide, carbon doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0107] In one embodiment, as also used throughout this specification, metal line or interconnect line material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper lines and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnect line may be a single material layer or may be formed from multiple layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect line. In one embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof, and are sometimes referred to in the art as wiring, wires, lines, metals, or simply interconnects.

[0108] In one embodiment, as also used throughout this specification, the hardmask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hardmask, capping, or plug materials may be used in different regions to provide different growth or etch selectivities with respect to each other and to the underlying dielectric and metal layers. In some embodiments, the hardmask layer, capping, or plug layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hardmask, capping, or plug layers known in the art may be used. The hardmask, capping, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0109] In one embodiment, as used throughout this specification, the lithography process is performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive tone or negative tone resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topography masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0110] In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate endcap (SAGE) structure. Particular embodiments relate to the integration of multiple width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture, which may be separated by SAGE walls. In one embodiment, the nanowires / nanoribbons are integrated with multiple Wsi in a SAGE architecture portion of a front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next-generation transistors with low power and high performance. The associated epitaxial source or drain regions may be formed by either embedding (e.g., a portion of the nanowire is removed and then source or drain (S / D) growth is performed) or by vertical merging (e.g., an epitaxial region is formed around an existing wire), as described in more detail below in connection with Figures 9A-9E.

[0111] To further illustrate, advantages of the self-aligned gate endcap (SAGE) architecture may include enabling higher layout density and, in particular, scaling of diffusion layer to diffusion layer spacing. For an exemplary comparison, FIG. 6 shows a cross-sectional view cut through a nanowire and fin of a no-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)) according to one embodiment of the present disclosure. It should be appreciated that, according to one or more embodiments described herein, one or more nanowires described in connection with FIG. 6 may undergo a differential gate oxide thickness process and / or a differential nanowire thickness process, as described in connection with FIGS. 1A-1B and / or 2A-2B.

[0112] Referring to the left side (a) of FIG. 6, an integrated circuit structure 600 includes a substrate 602 having a sub-fin 604 protruding therefrom within an isolation structure 608 that laterally surrounds the sub-fin 604. Corresponding nanowires 649 and 605 are above the sub-fin 604. In one embodiment, the bottom nanowire 649 is an oxide nanowire and the top nanowire 605 is an active nanowire. In one embodiment, the bottom oxide nanowire 649 includes an oxidation catalyst layer thereon. A gate structure may be formed above the integrated circuit structure 600 to fabricate a device. However, discontinuities in such gate structures may be accommodated by increasing the spacing between the sub-fin 604 / nanowire 649 / 605 pairs.

[0113] In contrast, referring to the right side (b) of FIG. 6, an integrated circuit structure 650 includes a substrate 652 having a sub-fin 654 protruding therefrom within an isolation structure 658 that laterally surrounds the sub-fin 654. Corresponding nanowires 699 and 655 are above the sub-fin 654. In one embodiment, the lower nanowire 699 is an oxide nanowire and the upper nanowire 655 is an active nanowire. In one embodiment, the lower oxide nanowire 699 includes an oxidation catalyst layer thereon. An isolation SAGE wall 660 is included within the isolation structure 658 and between adjacent sub-fin 654 / nanowire 699 / 655 pairs. The distance between the isolation SAGE wall 660 and the nearest sub-fin 654 / nanowire 699 / 655 pair defines a gate endcap spacing 662. A gate structure can be formed above the integrated circuit structure 600 between the isolation SAGE walls to fabricate a device. Such discontinuities in the gate structure are imposed by the isolating SAGE walls. Because the isolating SAGE walls 660 are self-aligned, constraints from conventional approaches can be minimized to allow for more aggressive diffusion layer to diffusion layer spacing. Furthermore, because the gate structure includes discontinuities at all locations, the individual gate structure portions may be layered and connected by local interconnects formed above the isolating SAGE walls 660. In one embodiment, as shown, the SAGE walls 660 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion as shown.

[0114] The self-aligned gate endcap (SAGE) processing scheme involves the formation of gate / trench contact endcaps that are self-aligned to the fins without requiring additional length to account for mask misalignment. Thus, embodiments may be implemented to enable area reduction of transistor layouts. The embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls, or self-aligned gate endcap (SAGE) walls.

[0115] In an exemplary processing scheme for a structure having SAGE walls separating adjacent devices, Figure 7 shows cross-sectional views depicting various steps in a method of fabricating a self-aligned gate endcap (SAGE) structure with a gate-all-around device according to one embodiment of the present disclosure. It should be understood that according to one or more embodiments described herein, one or more nanowires described in connection with Figure 7 may undergo a differential gate oxide thickness process and / or a differential nanowire thickness process, such as those described in connection with Figures 1A-1B and / or 2A-2B.

[0116] Referring to portion (a) of FIG. 7, a starting structure includes a nanowire patterning stack 704 above a substrate 702. A lithographic patterning stack 706 is formed above the nanowire patterning stack 704. The nanowire patterning stack 704 includes alternating silicon germanium layers 710 and silicon layers 712. A protective mask 714 is between the nanowire patterning stack 704 and the lithographic patterning stack 706. In one embodiment, the lithographic patterning stack 706 is a three-layer mask comprised of a topographic masking portion 720, an antireflective coating (ARC) layer 722, and a photoresist layer 724. In certain such embodiments, the topographic masking portion 720 is a carbon hard mask (CHM) layer and the antireflective coating layer 722 is a silicon ARC layer.

[0117] Referring to part (b) of FIG. 7, the stack of part (a) is lithographically patterned and then etched to result in an etched structure including a patterned substrate 702 and trenches 730.

[0118] Referring to part (c) of Figure 7, the structure of part (b) has an isolation layer 740 and a SAGE material 742 formed in trench 730. The structure is then planarized to leave the patterned topographical masking layer 720' as the exposed upper layer.

[0119] Referring to portion (d) of FIG. 7, an isolation layer 740 is recessed below the upper surface of the patterned substrate 702, for example to define a protruding fin portion, resulting in a trench isolation structure 741 below the SAGE walls 742.

[0120] Referring to part (e) of FIG. 7, the silicon germanium layer 710 is removed at least in the channel region to release the silicon nanowires 712A and 712B.

[0121] According to one embodiment of the present disclosure, the fabrication process of the structure associated with FIG. 7 involves using a process scheme that results in a gate-all-around integrated circuit structure with a depopulated channel structure. For example, referring to portion (e) of FIG. 7, in one embodiment, nanowire 712B and nanoribbon 712A are active nanowires and nanoribbons, respectively. In one such embodiment, nanowire 799B is an oxide nanowire and nanoribbon 799A is an oxide nanoribbon, as shown. In another such embodiment, nanowire 799B is an oxide nanowire and nanoribbon 799A is an active nanoribbon. In another such embodiment, nanowire 799B is an active nanowire and nanoribbon 799A is an oxide nanoribbon. In either case, in one embodiment, the oxide nanowire or oxide nanoribbon includes an oxide catalyst layer thereon.

[0122] 7, part (e), one or more gate stacks may be formed around the active and oxide nanowires and / or nanoribbons, above the protruding fins of substrate 702, and between SAGE walls 742. In one embodiment, the remaining portions of protective mask 714 are removed prior to formation of the gate stacks. In another embodiment, the remaining portions of protective mask 714 are retained as insulating fin hats, an artifact of the processing scheme.

[0123] Referring again to portion (e) of FIG. 7, it should be understood that the channel diagram is shown with the source or drain regions in and out of the page. In one embodiment, the channel region containing nanowire 712B has a smaller width than the channel region containing nanowire 712A. Thus, in one embodiment, the integrated circuit structure includes a multi-width (multi-Wsi) nanowire. Although the structures of 712B and 712A may be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to herein as nanowires. It should also be understood that references or illustrations of fin / nanowire pairs throughout may refer to structures including a fin and one or more overlying nanowires (e.g., two overlying nanowires are shown in FIG. 7), in which one or more bottom wires have been oxidized for depopulation.

[0124] Referring again to portion (e) of FIG. 7 and the ensuing description, according to one embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of active nanowires than the second vertical arrangement of nanowires. The first and second vertical arrangements of nanowires have coplanar top nanowires and coplanar bottom nanowires. The second vertical arrangement of nanowires has oxide bottom nanowires. A first gate stack covers the first vertical arrangement of nanowires. A second gate stack covers the second vertical arrangement of nanowires and surrounds the oxide bottom nanowires.

[0125] In one embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is the same as the horizontal width of the nanowires of the second vertical arrangement of nanowires. In another embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is greater than the horizontal width of the nanowires of the second vertical arrangement of nanowires. In another embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is smaller than the horizontal width of the nanowires of the second vertical arrangement of nanowires.

[0126] To highlight an exemplary integrated circuit structure comprising three vertically arranged nanowires, FIG. 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to one embodiment of the present disclosure. FIG. 8B illustrates a source or drain cross-sectional view of the nanowire-based integrated circuit structure of FIG. 8A taken along the a-a′ axis. FIG. 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG. 8A taken along the b-b′ axis. It should be understood that according to one or more embodiments described herein, one or more nanowires described in connection with FIG. 8A and FIG. 8B may undergo a differential gate oxide thickness process and / or a differential nanowire thickness process, as described in connection with FIG. 1A-1B and / or FIG. 2A-2B.

[0127] Referring to FIG. 8A, an integrated circuit structure 800 includes one or more vertically stacked nanowires (set of 804) above a substrate 802. An optional fin between the bottom nanowire and the substrate 802 is not shown for purposes of emphasizing the nanowire portion for illustrative purposes. The embodiments herein are directed to both single-wire and multiple-wire devices. As one example, a three-nanowire-based device having nanowires 804A, 804B, and 804C is shown for illustrative purposes. For ease of description, nanowire 804A is used as an example where the description focuses on one of the nanowires. It should be understood that where attributes of one nanowire are described, embodiments based on multiple nanowires may have the same or essentially the same attributes for each of the nanowires.

[0128] Each of the nanowires 804 includes a nanowire channel region 806. The channel region 806 has a length (L). Referring to FIG. 8C, the channel region also has a perimeter (Pc) that is orthogonal to the length (L). Referring to both FIGS. 8A and 8C, a gate electrode stack 808 surrounds the entire perimeter (Pc) of each of the channel regions 806. The gate electrode stack 808 includes a gate electrode with a gate dielectric layer between the channel region 806 and the gate electrode (not shown). In one embodiment, the channel region is separate in that it is completely surrounded by the gate electrode stack 808, without any intervening material, such as an underlying substrate material or an overlying channel fabrication material. Thus, in an embodiment having multiple nanowires 804, the nanowire channel regions 806 are also separate with respect to each other.

[0129] 8A and 8B, the integrated circuit structure 800 includes a pair of non-isolated source or drain regions 810 / 812. The pair of non-isolated source or drain regions 810 / 812 are on either side of the channel region 806 of the vertically stacked nanowires 804. Furthermore, the pair of non-isolated source or drain regions 810 / 812 are adjacent with respect to the channel region 806 of the vertically stacked nanowires 804. In one such embodiment, not shown, the pair of non-isolated source or drain regions 810 / 812 are directly vertically adjacent with respect to the channel region 806 in that epitaxial growth is on and between portions of the nanowires that extend beyond the channel region 806, with the nanowire ends shown within the source or drain structures. In another embodiment, as shown in FIG. 8A, the pair of non-isolated source or drain regions 810 / 812 are indirectly vertically adjacent with respect to the channel region 806 in that they are formed at the ends of the nanowires, rather than between them.

[0130] In one embodiment, as shown, the source or drain regions 810 / 812 are non-separate in that there are no separate and separate source or drain regions for each channel region 806 of the nanowire 804. Thus, in an embodiment with multiple nanowires 804, the nanowire source or drain regions 810 / 812 are global or integrated source or drain regions rather than separate for each nanowire. In one embodiment, as shown in FIG. 8B, from a cross-sectional perspective view perpendicular to the length of the separate channel region 806, each of the pair of non-separate source or drain regions 810 / 812 is approximately rectangular in shape with a tapered portion at the bottom and a vertex portion at the top. However, in other embodiments, the nanowire source or drain regions 810 / 812 are relatively large but separate, non-vertically merged epitaxial structures, such as the nubs described in connection with FIGS. 4F-4J.

[0131] According to one embodiment of the present disclosure, and as illustrated in Figures 8A and 8B, the integrated circuit structure 800 further includes a pair of contacts 814, each contact 814 on one of the pair of non-isolated source or drain regions 810 / 812. In one such embodiment, in a vertical perspective, each contact 814 is completely surrounded by the respective non-isolated source or drain region 810 / 812. In another aspect, the entire perimeter of the non-isolated source or drain region 810 / 812 may not be accessible for contact with the contact 814, and the contact 814 thus only partially surrounds the non-isolated source or drain region 810 / 812, as illustrated in Figure 8B. In a contrasting embodiment, not illustrated, the entire perimeter of the non-isolated source or drain region 810 / 812 is surrounded by the contact 814, as cut along the a-a' axis. According to one embodiment of the present disclosure, although not shown, the pair of contacts 814 is an asymmetric pair of contacts, as described in connection with FIG. 4J.

[0132] 8B and 8C, the non-isolated source or drain regions 810 / 812 are global in the sense that a single integrated feature is used as a source or drain region for multiple (in this case, three) nanowires 804, and more specifically, for more than one isolated channel region 806. In one embodiment, the pair of non-isolated source or drain regions 810 / 812 is composed of a different semiconductor material than the semiconductor material of the isolated channel region 806, e.g., the pair of non-isolated source or drain regions 810 / 812 is composed of silicon germanium, while the isolated channel region 806 is composed of silicon. In another embodiment, the pair of non-isolated source or drain regions 810 / 812 is composed of the same or essentially the same semiconductor material as the semiconductor material of the isolated channel region 806, e.g., both the pair of non-isolated source or drain regions 810 / 812 and the isolated channel region 806 are composed of silicon.

[0133] 8A , in one embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As shown, outer portions of the pair of spacers 816 may overlap portions of the non-isolated source or drain regions 810 / 812, providing a "buried" portion of the non-isolated source or drain regions 810 / 812 below the pair of spacers 816. Also as shown, the buried portions of the non-isolated source or drain regions 810 / 812 may not extend entirely below the pair of spacers 816.

[0134] The substrate 802 may be composed of a material suitable for the fabrication of integrated circuit structures. In one embodiment, the substrate 802 includes a lower bulk substrate composed of a single crystal of a material that may include, but is not limited to, silicon, germanium, silicon germanium, or a III-V compound semiconductor material. An upper insulating layer, composed of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride, is on the lower bulk substrate. Thus, the structure 800 may be fabricated from a starting semiconductor on insulating substrate. Alternatively, the structure 800 is formed directly from a bulk substrate and localized oxidation is used to form electrically insulating portions in place of the upper insulating layer described above. In another alternative embodiment, the structure 800 is formed directly from a bulk substrate and doping is used to form electrically isolated active regions thereon, such as nanowires. In one such embodiment, the first nanowire (i.e., closest to the substrate) is in the form of an omegaFET type structure.

[0135] In one embodiment, the nanowires 804 may be wire or ribbon sized and may have angular or rounded corners, as described below. In one embodiment, the nanowires 804 are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, with respect to silicon nanowires 804, single crystalline nanowires have a global orientation (100), e.g., a crystalline orientation (100) in the z direction. <100> The nanowire 804 may be based on a plane. Other orientations are also possible, as described below. In one embodiment, the dimensions of the nanowire 804 are nanoscale from a cross-sectional perspective view. For example, in certain embodiments, the smallest dimension of the nanowire 804 is less than approximately 20 nanometers. In one embodiment, the nanowire 804 is composed of a strained material, particularly in the channel region 806.

[0136] 8C, in one embodiment, each of the channel regions 806 has a width (Wc) and a height (Hc), where the width (Wc) is approximately the same as the height (Hc). That is, in both cases, the channel regions 806 are square-shaped in cross-sectional profile, or circular, with rounded corners. In another embodiment, such as in the case of nanoribbons as described throughout, the width and height of the channel regions need not be the same.

[0137] In another aspect, a method for fabricating a nanowire portion of a fin / nanowire integrated circuit structure is provided. For example, Figures 9A-9E show three-dimensional cross-sectional views illustrating various steps in a method for fabricating a nanowire portion of a fin / nanowire structure according to one embodiment of the present disclosure. It should be understood that according to one or more embodiments described herein, one or more nanowires described in connection with Figures 9A-9E may be subjected to a differential gate oxide thickness process and / or a differential nanowire thickness process, such as described in connection with Figures 1A-1B and / or 2A-2B.

[0138] A method for fabricating a nanowire integrated circuit structure can include forming a nanowire above a substrate. In a specific example illustrating the formation of two silicon nanowires, Figure 9A shows a substrate 902 (e.g., comprised of a bulk substrate silicon substrate 902A having an insulating silicon dioxide layer 902B thereon) having a silicon layer 904 / silicon germanium layer 906 / silicon layer 908 stack thereon. It will be appreciated that in another embodiment, the silicon germanium layer / silicon layer / silicon germanium layer stack can be used to ultimately form two silicon germanium nanowires.

[0139] Referring to FIG. 9B, a portion of the silicon layer 904 / silicon germanium layer 906 / silicon layer 908 stack and the top of the silicon dioxide layer 902B are patterned into a fin-type structure 910, for example, using a mask and plasma etching process. It should be understood that for illustrative purposes, the etch in FIG. 9B is shown as forming two silicon nanowire precursor portions. While the etch is shown as terminating in the bottom isolation layer for ease of illustration, more complex stacks are contemplated within the context of embodiments of the present disclosure. For example, the process can be applied to a nanowire / fin stack as described in connection with FIG. 7.

[0140] The method may also include forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length. In a specific example illustrating forming a three gate structure above two silicon nanowires, Figure 9C shows a fin-type structure 910 having three sacrificial gates 912A, 912B, and 912C thereon. In one such embodiment, the three sacrificial gates 912A, 912B, and 912C are comprised of a sacrificial gate oxide layer 914 and a sacrificial polysilicon gate layer 916 that are patterned using a blanket deposition and plasma etching process.

[0141] Following patterning to form the three sacrificial gates 912A, 912B, and 912C, spacers may be formed on sidewalls of the three sacrificial gates 912A, 912B, and 912C, doping may be performed (e.g., tip and / or source and drain type doping), and an interlayer dielectric layer may be formed to cover the three sacrificial gates 912A, 912B, and 912C. The interlayer dielectric layer may be polished back to expose the three sacrificial gates 912A, 912B, and 912C for a replacement gate or gate last process.

[0142] 9D, the three sacrificial gates 912A, 912B, and 912C are removed, leaving the spacer 918 and a portion of the interlevel dielectric layer 920. Additionally, a portion of the silicon germanium layer 906 and a portion of the insulating silicon dioxide layer 902B of the fin structure 910 are removed in the areas originally covered by the three sacrificial gates 912A, 912B, and 912C. The isolated portions of the silicon layers 904 and 908 thus remain, as shown in FIG.

[0143] The separated portions of silicon layers 904 and 908 shown in FIG. 9D, in one embodiment, will eventually become the channel regions in a nanowire-based device. Thus, at the process stage shown in FIG. 9D, channel manipulation or tuning may be performed. For example, in one embodiment, the separated portions of silicon layers 904 and 908 shown in FIG. 9D are thinned using an oxidation and etching process. Such an etching process may be performed at the same time that the wires are separated by etching of silicon germanium layer 906. Thus, the initial wire formed from silicon layers 904 and 908 starts out thicker and is thinned to a size suitable for the channel region in a nanowire device, independent of the size of the source and drain regions of the device. Thus, in one embodiment, forming the channel region includes removing a portion of the nanowire, such that the resulting perimeter (described below) of the source and drain regions is larger than the resulting perimeter of the channel region.

[0144] According to one embodiment of the present disclosure, following removal of the three sacrificial gates 912A, 912B, and 912C, and portions of the silicon germanium layer 906 and insulating silicon dioxide layer 902B of the fin structure 910 from the areas originally covered by the three sacrificial gates 912A, 912B, and 912C, a fabrication process is performed that results in a gate-all-around integrated circuit structure.

[0145] The method may also include forming a gate electrode stack surrounding the entire perimeter of the channel region. In a specific example showing the formation of a three gate structure above two silicon nanowires, FIG. 9E shows the structure following deposition of a gate dielectric layer 922 (such as a high-k gate dielectric layer) and a gate electrode layer 924 (such as a metal gate electrode layer) between spacers 918 and subsequent polishing. That is, the gate structure is formed in trench 921 of FIG. 9D. Furthermore, FIG. 9E shows the result of subsequent removal of interlayer dielectric layer 920 after the formation of the permanent gate stack. Portions of silicon germanium layer 906 and insulating silicon dioxide layer 902B of fin structure 910 are also removed in the areas originally covered by portions of interlayer dielectric layer 920 shown in FIG. 9D. Separate portions of silicon layers 904 and 908 thus remain as shown in FIG. 9E.

[0146] The method may also include forming a pair of nanowire source and drain regions on either side of the channel region, each of the source and drain regions having a perimeter perpendicular to the length of the channel region. Specifically, the separated portions of silicon layers 904 and 908 shown in FIG. 9E, in one embodiment, will eventually become at least a portion of the source and drain regions in the nanowire-based device. In one such embodiment, epitaxial source or drain structures are formed by merging epitaxial material around existing nanowires 904 and 908. In another embodiment, epitaxial source or drain structures are embedded, for example, by removing portions of nanowires 904 and 908 and then performing source or drain (S / D) growth. In the latter case, according to one embodiment of the present disclosure, such epitaxial source or drain structures may be non-separated, as illustrated in connection with FIG. 8A and FIG. 8B, or separated, as illustrated in connection with FIG. 4J. In either case, in one embodiment, the source or drain structures are N-type epitaxial source or drain structures, both of which contain phosphorus dopant impurity atoms.

[0147] The method may then include forming a pair of contacts, a first of the pair of contacts completely or nearly completely surrounding the periphery of the source region, and a second of the pair of contacts completely or nearly completely surrounding the periphery of the drain region. In one embodiment, the pair of contacts is an asymmetric pair of source and drain contact structures, such as those described in connection with FIG. 4J. In another embodiment, the pair of contacts is a symmetric pair of source and drain contact structures. Specifically, the contacts are formed in trenches 925 of FIG. 9E following epitaxial growth. One of the trenches may initially be recessed deeper than the other of the trenches. In one embodiment, the contacts are formed from a metal species. In one such embodiment, the metal species is formed by conformally depositing a contact metal and then filling any remaining trench volume. The conformal aspect of the deposition may be performed by using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow.

[0148] In one embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device, having a corresponding one or more overlying nanowire structures. In one such embodiment, the corresponding semiconductor channel region is comprised of or formed within a three-dimensional object, and one or more separate nanowire channel portions are overlying the three-dimensional object. In one such embodiment, a gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional object, and further surrounds each of the one or more separate nanowire channel portions.

[0149] In one embodiment, the substrate may be composed of a semiconductor material capable of withstanding the manufacturing processes and through which charges can travel, as described throughout. In one embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof, to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a separate crystalline substrate, for example, a silicon epitaxial layer grown on a bulk silicon single crystal substrate doped with boron. The bulk substrate may alternatively be composed of III-V materials. In one embodiment, the bulk substrate is comprised of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is comprised of a III-V material and the charge carrier dopant impurity atoms are, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0150] In one embodiment, as described throughout, the trench isolation layer may be composed of a material suitable for isolating active areas formed in the underlying bulk substrate, such as ultimately electrically isolating or contributing to the isolation of portions of a permanent gate structure from the underlying bulk substrate, or isolating fin active areas, etc. For example, in one embodiment, the trench isolation layer is composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0151] In one embodiment, as described throughout, the self-aligned gate endcap isolation structure may be composed of one or more materials suitable for ultimately electrically isolating or contributing to the isolation of portions of the permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multi-layer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a high-k material such as hafnium oxide.

[0152] The embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. Additionally, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular telephones, personal electronic devices, and the like. The integrated circuits may be coupled with buses and other components of the system. For example, a processor may be coupled with a memory, a chipset, and the like by one or more buses. Each of the processor, memory, and chipset may potentially be manufactured using the techniques disclosed herein.

[0153] 10 illustrates a computing device 1000 according to one implementation of an embodiment of the present disclosure. The computing device 1000 houses a board 1002. The board 1002 may include multiple components including, but not limited to, a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations, the at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In further implementations, the communication chip 1006 is part of the processor 1004.

[0154] Depending on its application, computing device 1000 may include other components that may or may not be physically and electrically coupled to board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0155] The communications chip 1006 enables wireless communications for the transfer of data to and from the computing device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data by use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not include any wires, which in some embodiments may not. The communications chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 1000 may include multiple communications chips 1006. For example, a first communications chip 1006 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and a second communications chip 1006 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0156] The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. The integrated circuit die of the processor 1004 may comprise one or more structures, such as a gate-all-around integrated circuit structure with differential nanowire thickness and gate oxide thickness constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0157] The communications chip 1006 also includes an integrated circuit die packaged within the communications chip 1006. The integrated circuit die of the communications chip 1006 may include one or more structures, such as a gate-all-around integrated circuit structure having differential nanowire thickness and gate oxide thickness constructed in accordance with implementations of embodiments of the present disclosure.

[0158] In a further implementation, another component contained within the computing device 1000 may include an integrated circuit die including one or more structures, such as a gate-all-around integrated circuit structure having differential nanowire thickness and gate oxide thickness constructed in accordance with an implementation of an embodiment of the present disclosure.

[0159] In various implementations, computing device 1000 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 1000 may be any other electronic device that processes data.

[0160] FIG. 11 illustrates an interposer 1100 including one or more embodiments of the present disclosure. The interposer 1100 is an intervening substrate used to bridge a first substrate 1102 and a second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. The second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of the interposer 1100 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 1100 may bond an integrated circuit die to a ball grid array (BGA) 1106 that may later be bonded to the second substrate 1104. In some embodiments, the first substrate and the second substrate 1102 / 1104 are attached to opposite sides of the interposer 1100. In other embodiments, the first substrate and the second substrate 1102 / 1104 are attached to the same side of the interposer 1100. And, in further embodiments, three or more substrates are interconnected by the interposer 1100.

[0161] The interposer 1100 may be formed of a polymeric material such as epoxy, fiberglass reinforced epoxy, ceramic material, or polyimide. In further implementations, the interposer 1100 may be formed from alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0162] The interposer 1100 may include metal interconnects 1108 and vias 1110, including but not limited to through silicon vias (TSVs) 1112. The interposer 1100 may further include embedded devices 1114, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1100. According to an embodiment of the present disclosure, an apparatus or process disclosed herein may be used in the manufacture of the interposer 1100 or components included in the interposer 1100.

[0163] Accordingly, embodiments of the present disclosure include gate-all-around integrated circuit structures having differential nanowire thicknesses and gate oxide thicknesses, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thicknesses and gate oxide thicknesses.

[0164] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the art will recognize.

[0165] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the disclosure should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0166] Exemplary embodiment 1: An integrated circuit structure includes a nanowire having an outer thickness and an inner thickness, the inner thickness being less than the outer thickness. The nanowire tapers from an outer region having the outer thickness to an inner region having the inner thickness. A dielectric material overlies and surrounds the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

[0167] Exemplary embodiment 2: The integrated circuit structure of exemplary embodiment 1, wherein the nanowires comprise silicon and germanium.

[0168] Exemplary embodiment 3: The integrated circuit structure of exemplary embodiment 1 or 2, wherein the dielectric material comprises silicon and oxygen.

[0169] Exemplary embodiment 4: The integrated circuit structure of exemplary embodiment 1, 2 or 3, further comprising a high-k gate dielectric layer overlying and surrounding the dielectric material.

[0170] Exemplary embodiment 5: The integrated circuit structure of exemplary embodiment 4, further comprising one or more gate electrode layers overlying and surrounding the high-k gate dielectric layer.

[0171] Exemplary embodiment 6: An integrated circuit structure includes a first plurality of nanowires laterally spaced apart from a second plurality of nanowires, the second plurality of nanowires having fewer nanowires than the first plurality of nanowires for the same vertical height, each of the nanowires of the second plurality of nanowires having a greater thickness than each of the nanowires of the first plurality of nanowires.

[0172] Exemplary embodiment 7: The integrated circuit structure of exemplary embodiment 6, wherein the first plurality of nanowires and the second plurality of nanowires comprise silicon and germanium.

[0173] Exemplary embodiment 8: The integrated circuit structure of exemplary embodiment 6 or 7, further comprising a dielectric material overlying and surrounding each of the second plurality of nanowires.

[0174] Exemplary embodiment 9: The integrated circuit structure of exemplary embodiment 8, further comprising a high-k gate dielectric layer overlying and surrounding the dielectric material.

[0175] Exemplary embodiment 10: The integrated circuit structure of exemplary embodiment 9, further comprising one or more gate electrode layers overlying and surrounding the high-k gate dielectric layer.

[0176] Exemplary embodiment 11: A computing device includes a substrate and a component coupled to the substrate. The component includes an integrated circuit structure including a nanowire having an outer thickness and an inner thickness, the inner thickness being less than the outer thickness. The nanowire tapers from an outer region having the outer thickness to an inner region having the inner thickness. A dielectric material overlies and surrounds the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

[0177] Exemplary embodiment 12: The computing device of exemplary embodiment 11, wherein the nanowires comprise silicon and germanium.

[0178] Exemplary embodiment 13: The computing device of exemplary embodiment 11, wherein the dielectric material comprises silicon and oxygen.

[0179] Exemplary embodiment 14: The computing device of exemplary embodiment 11, 12, or 13, further comprising a memory coupled to the substrate.

[0180] Exemplary embodiment 15: The computing device of exemplary embodiment 11, 12, 13, or 14, further comprising a communications chip coupled to the substrate.

[0181] Exemplary embodiment 16: The computing device of exemplary embodiment 11, 12, 13, 14, or 15, further comprising a camera coupled to the substrate.

[0182] Exemplary embodiment 17: The computing device of exemplary embodiment 11, 12, 13, 14, 15 or 16, further comprising a display coupled to the substrate.

[0183] Exemplary embodiment 18: The computing device of exemplary embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a battery coupled to the substrate.

[0184] Exemplary embodiment 19: The computing device of exemplary embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0185] Exemplary embodiment 20: The computing device of exemplary embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor. [Other possible items] [Item 1] a nanowire having an outer thickness and an inner thickness, said inner thickness being less than said outer thickness, wherein said nanowire tapers from an outer region having said outer thickness to an inner region having said inner thickness; a dielectric material overlying and surrounding the nanowire such that the combined thickness of the nanowire and the dielectric material in the interior region is approximately the same as the exterior thickness of the nanowire; 1. An integrated circuit structure comprising: [Item 2] Item 1 : The integrated circuit structure of item 1 , wherein the nanowires comprise silicon and germanium. [Item 3] Item 1. The integrated circuit structure of item 1, wherein the dielectric material comprises silicon and oxygen. [Item 4] a high-k gate dielectric layer overlying and surrounding the dielectric material; Item 1. The integrated circuit structure of item 1 further comprising: [Item 5] one or more gate electrode layers overlying and surrounding the high-k gate dielectric layer; Item 5. The integrated circuit structure of item 4 further comprising: [Item 6] a first plurality of nanowires laterally spaced apart from a second plurality of nanowires, where for the same vertical height, the second plurality of nanowires has fewer nanowires than the first plurality of nanowires, where each of the nanowires of the second plurality of nanowires has a greater thickness than each of the nanowires of the first plurality of nanowires; 1. An integrated circuit structure comprising: [Item 7] Item 7. The integrated circuit structure of item 6, wherein the first plurality of nanowires and the second plurality of nanowires comprise silicon and germanium. [Item 8] Item 7. The integrated circuit structure of item 6, further comprising a dielectric material overlying and surrounding each of the second plurality of nanowires. [Item 9] a high-k gate dielectric layer overlying and surrounding the dielectric material; Item 9. The integrated circuit structure of item 8, further comprising: [Item 10] one or more gate electrode layers overlying and surrounding the high-k gate dielectric layer; Item 10. The integrated circuit structure of item 9, further comprising: [Item 11] Substrate; and a component coupled to the substrate, the component comprising: a nanowire having an outer thickness and an inner thickness, said inner thickness being less than said outer thickness, wherein said nanowire tapers from an outer region having said outer thickness to an inner region having said inner thickness; a dielectric material overlying and surrounding the nanowire such that the combined thickness of the nanowire and the dielectric material in the interior region is approximately the same as the exterior thickness of the nanowire; an integrated circuit structure including: A computing device comprising: [Item 12] Item 12. The computing device of item 11, wherein the nanowires comprise silicon and germanium. [Item 13] Item 12. The computing device of item 11, wherein the dielectric material comprises silicon and oxygen. [Item 14] A memory coupled to the substrate. Item 12. The computing device of item 11, further comprising: [Item 15] A communications chip coupled to the substrate. Item 12. The computing device of item 11, further comprising: [Item 16] A camera coupled to the substrate. Item 12. The computing device of item 11, further comprising: [Item 17] A display bonded to the substrate. Item 12. The computing device of item 11, further comprising: [Item 18] A battery coupled to the substrate. Item 12. The computing device of item 11, further comprising: [Item 19] Item 12. The computing device of item 11, wherein the component is a packaged integrated circuit die. [Item 20] Item 12. The computing device of item 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Claims

1. a nanowire having an outer thickness and an inner thickness, said inner thickness being less than said outer thickness, wherein said nanowire tapers from an outer region having said outer thickness to an inner region having said inner thickness; a dielectric material overlying and surrounding the nanowire such that the combined thickness of the nanowire and the dielectric material in the interior region is approximately the same as the exterior thickness of the nanowire; 1. An integrated circuit structure comprising:

2. The integrated circuit structure of claim 1 wherein the nanowires comprise silicon and germanium.

3. 3. The integrated circuit structure of claim 1, wherein the dielectric material comprises silicon and oxygen.

4. a high-k gate dielectric layer overlying and surrounding the dielectric material; 3. The integrated circuit structure of claim 1 or 2, further comprising:

5. one or more gate electrode layers overlying and surrounding the high-k gate dielectric layer; The integrated circuit structure of claim 4 further comprising:

6. a first plurality of nanowires laterally spaced apart from a second plurality of nanowires, where for the same vertical height, the second plurality of nanowires has fewer nanowires than the first plurality of nanowires, where each of the nanowires of the second plurality of nanowires has a greater thickness than each of the nanowires of the first plurality of nanowires; 1. An integrated circuit structure comprising:

7. 7. The integrated circuit structure of claim 6, wherein said first and second plurality of nanowires comprise silicon and germanium.

8. 8. The integrated circuit structure of claim 6 or 7, further comprising a dielectric material overlying and surrounding each of the second plurality of nanowires.

9. a high-k gate dielectric layer overlying and surrounding the dielectric material; The integrated circuit structure of claim 8 further comprising:

10. one or more gate electrode layers overlying and surrounding the high-k gate dielectric layer; 10. The integrated circuit structure of claim 9 further comprising:

11. A substrate; and a component coupled to the substrate, the component comprising: a nanowire having an outer thickness and an inner thickness, said inner thickness being less than said outer thickness, wherein said nanowire tapers from an outer region having said outer thickness to an inner region having said inner thickness; a dielectric material overlying and surrounding the nanowire such that the combined thickness of the nanowire and the dielectric material in the interior region is approximately the same as the exterior thickness of the nanowire; an integrated circuit structure including: A computing device comprising:

12. The computing device of claim 11 , wherein the nanowires comprise silicon and germanium.

13. The computing device of claim 11 , wherein the dielectric material comprises silicon and oxygen.

14. A memory coupled to the substrate. The computing device of claim 11 further comprising:

15. A communications chip coupled to the substrate. The computing device of claim 11 further comprising:

16. A camera coupled to the substrate. The computing device of claim 11 further comprising:

17. A display bonded to the substrate. The computing device of claim 11 further comprising:

18. A battery coupled to the substrate. The computing device of claim 11 further comprising:

19. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

20. 14. The computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

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