Semiconductor package

Abstract

To prevent an increase in a manufacturing process.SOLUTION: A semiconductor package includes a semiconductor chip 20 on which a semiconductor element is formed, an insulating heat dissipation member 10 on which the semiconductor chip 20 is mounted, and a sealing member 30 that seals the semiconductor chip 20. The sealing member 30 includes a resin portion 31 and a wiring portion 32 electrically connected to the semiconductor chip 20, and the wiring portion 32 includes a plurality of wiring layers 322 extending along the surface direction of the semiconductor chip 20 and a connection via 321 that extends along the stacking direction of the semiconductor chip 20 and the insulating heat dissipation member 10 and connects adjacent wiring layers 322 along the stacking direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package in which a semiconductor chip is sealed with a sealing member. [Background technology]

[0002] Conventionally, semiconductor packages in which a semiconductor chip is sealed with a sealing member have been proposed (see, for example, Patent Document 1). Specifically, the sealing member of this semiconductor package has a resin part made of liquid crystal polymer that covers the semiconductor chip, and a wiring part that is electrically connected to the semiconductor chip. The wiring part has a plurality of wiring layers that extend along the surface direction of the semiconductor chip, and a plurality of connection vias that are connected to each wiring layer. The plurality of wiring layers are disposed at different heights within the sealing member, and the plurality of connection vias are disposed so as to connect the wiring layers to each other.

[0003] Such a semiconductor package is manufactured as follows. That is, first, a sheet-shaped base member made of liquid crystal polymer is prepared. Then, a wiring layer is formed on one surface of the base member, and conductive paste is filled into through holes formed to reach the wiring layer to prepare a wiring sheet. The wiring layer of the wiring sheet is formed by disposing a metal film on one surface of the base member by plating, vapor deposition, sputtering, etc., and then disposing a mask on the metal film and patterning it into a predetermined shape. Also, multiple wiring sheets are prepared according to the thickness of the sealing member to be constructed.

[0004] Next, multiple wiring sheets are stacked in order with the semiconductor chip placed inside, and then heated and pressurized to sinter the conductive paste and form connection vias, thereby producing a semiconductor package in which the semiconductor chip is sealed in a sealing material. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 4568718 Summary of the Invention [Problem to be solved by the invention]

[0006] The present inventors are studying how to provide a novel structure for a semiconductor package in which a semiconductor chip is sealed with a sealing member.

[0007] In view of the above, an object of the present invention is to provide a semiconductor package having a novel structure. [Means for solving the problem]

[0008] To achieve the above object, claim 1 provides a semiconductor package in which a semiconductor chip (20) is sealed with a sealing member (30), the semiconductor chip having a semiconductor element formed thereon, an insulating heat dissipation member (10) on which the semiconductor chip is mounted, and the sealing member that seals the semiconductor chip, the sealing member having a resin portion (31) and a wiring portion (32) electrically connected to the semiconductor chip, the wiring portion having a plurality of wiring layers (322) extending along the surface direction of the semiconductor chip, and connection vias (321) that extend along the stacking direction of the semiconductor chip and the insulating heat dissipation member and connect adjacent wiring layers along the stacking direction.

[0009] This allows a semiconductor package with a novel structure to be achieved.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a semiconductor package according to a first embodiment. [Figure 2A] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor package shown in FIG. [Figure 2B]2B is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2A. [Figure 2C] 2C is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2B. [Figure 2D] 2D is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2C. [Figure 2E] 2E is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2D. [Figure 2F] 2F is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2E. [Diagram 3] 13 is a cross-sectional view showing a through hole formed in a base member in a second embodiment. FIG. [Figure 4] 4 is a cross-sectional view of the vicinity of a connection via when a semiconductor package is constructed using the base member of FIG. [Diagram 5] FIG. 11 is a cross-sectional view of the vicinity of a connection via in a modified example of the second embodiment. [Figure 6] FIG. 11 is a cross-sectional view of the vicinity of a connection via in a modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) A first embodiment will be described with reference to the drawings. The semiconductor package of the present embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

[0014] As shown in FIG. 1, the semiconductor package includes an insulating heat dissipation member 10, a semiconductor chip 20, a sealing member 30, and the like.

[0015] The insulating heat dissipation member 10 is made of silicon nitride (SiN), aluminum nitride (ALN), or the like, and is in the form of a plate having one surface 10a and another surface 10b opposite to the first surface 10a. The insulating heat dissipation member 10 has a connection wiring 11 made of copper or the like formed on the first surface 10a. The connection wiring 11 has a thickness of about 10 to 100 μm.

[0016] In this embodiment, the semiconductor chip 20 is configured using a semiconductor substrate 23 in which a semiconductor layer 22 containing gallium nitride is laminated on a support substrate 21 made of silicon. In other words, the semiconductor chip 20 is configured using a semiconductor substrate 23 made of so-called GaN-on-Si. The front surface 20a side of the semiconductor chip 20 is configured as the semiconductor layer 22 side, and the back surface 20b side is configured as the support substrate 21 side.

[0017] The gallium nitride-containing semiconductor layer 22 of this embodiment is formed by stacking epitaxial layers such as a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer, etc. In this embodiment, a two-dimensional electron gas (i.e., 2DEG) is formed at the interface between the gallium nitride layer and the aluminum gallium nitride layer.

[0018] Although details are omitted, the semiconductor chip 20 has a drain electrode, a source electrode, and a gate electrode formed on the front surface 20a side, and a high electron mobility transistor is formed as a semiconductor element that uses two-dimensional electron gas to pass a current between the drain electrode and the source electrode. That is, the semiconductor chip 20 of this embodiment has a horizontal transistor formed thereon that passes a current in the surface direction of the semiconductor substrate 23.

[0019] In addition, a back electrode 24 is formed on the back surface 20b side of the semiconductor chip 20. The back electrode 24 is electrically connected to the source electrode through a connection via 321 and a wiring layer 322 formed in the sealing member 30, which will be described in detail later. Thereby, the semiconductor chip 20 of this embodiment is designed to suppress current collapse.

[0020] Such a semiconductor chip 20 is disposed on the connection wiring 11 formed on the insulating heat dissipation member 10 with the back electrode 24 facing the insulating heat dissipation member 10.

[0021] The sealing member 30 is disposed on the insulating heat dissipation member 10 so as to seal the semiconductor chip 20 and one surface 10a of the insulating heat dissipation member 10. The sealing member 30 is also disposed between the semiconductor chip 20 and the insulating heat dissipation member 10. However, the sealing member 30 is disposed on the insulating heat dissipation member 10 so as to expose the other surface 10b of the insulating heat dissipation member 10.

[0022] The sealing member 30 of this embodiment has a resin part 31 made of liquid crystal polymer (hereinafter, simply referred to as LCP) and a wiring part 32 electrically connected to the semiconductor chip 20. Specifically, the wiring part 32 has a plurality of wiring layers 322 extending along the surface direction of the semiconductor chip 20, and a plurality of connection vias 321 electrically connected to the wiring layers 322 and extending along the stacking direction (hereinafter, simply referred to as the stacking direction) of the insulating heat dissipation member 10 and the semiconductor chip 20. More specifically, the plurality of wiring layers 322 are arranged at different positions along the stacking direction. The plurality of connection vias 321 are arranged so as to electrically connect the respective wiring layers 322.

[0023] Furthermore, the outermost wiring layer 322a formed on the outermost layer of the wiring layer 322 on the side opposite to the insulating heat dissipation member 10 side is arranged so as to be electrically connected to a source electrode or the like formed on the semiconductor chip 20 through a connection via 321. An opening 33 exposing a part of the outermost wiring layer 322a is formed in the sealing member 30. As a result, a part of the outermost wiring layer 322a is exposed, and a pad part 322b for connecting to an external circuit is formed in the exposed part.

[0024] In the semiconductor chip 20 of this embodiment, a source electrode, a drain electrode, a gate electrode, etc. are formed on the front surface 20a side. Therefore, a plurality of outermost wiring layers 322a are formed so as to be connected to the source electrode, the drain electrode, the gate electrode, etc., respectively. Also, the sealing member 30 is formed with an opening 33 that exposes a part of the outermost wiring layer 322a connected to each electrode. Therefore, at least three pad portions 322b are formed in the semiconductor package of this embodiment.

[0025] In addition, the back side connection via 321a, which is formed closest to the insulating heat dissipation member 10 among the multiple connection vias 321, is formed so as to connect the back side electrode 24 of the semiconductor chip 20 and the connection wiring 11, and is also formed so as to connect the connection wiring 11 and the wiring layer 322.

[0026] Each wiring layer 322 and each connection via 321 is made of a sintered body obtained by sintering a conductive paste. In this embodiment, the conductive paste is made by adding a viscosity adjusting agent, an organic solvent, and the like to AgSn powder.

[0027] In this embodiment, the connection vias 321 adjacent to each other in the stacking direction are arranged at offset positions in the stacking direction. In other words, the connection vias 321 adjacent to each other in the stacking direction are arranged so as not to overlap in the stacking direction. This makes it possible to prevent the stress along the stacking direction from becoming too high, compared to a case in which the connection vias 321 adjacent to each other in the stacking direction are arranged so as to overlap.

[0028] The above is the configuration of the semiconductor package in this embodiment. Next, a method for manufacturing the semiconductor package will be described with reference to Figures 2A to 2F.

[0029] First, as shown in Fig. 2A, a sheet-like base member 310 is prepared, which constitutes the resin part 31 of the sealing member 30 and has one surface 310a and the other surface 310b. The base member 310 is made of a sheet-like LCP. Although Fig. 2A shows only one base member 310, in practice, a plurality of base members 310 required for carrying out the step of Fig. 2E described below are prepared.

[0030] 2B, through holes 311 are formed in each base member 310. In this embodiment, the through holes 311 are formed by punching. As a result, compared to when the through holes 311 are formed in the base member 310 by laser processing, for example, foreign matter such as chips originating from the base member 310 is less likely to scatter when the through holes 311 are formed, and adhesion of foreign matter to the base member 310 can be suppressed.

[0031] 2C, a protective sheet 330 is placed on the other surface 310b of the base member 310. The protective sheet 330 is made of a material that is breathable and can prevent the conductive paste for vias 341 described later from flowing out. For example, a paper sheet having minute voids is used as the protective sheet 330. Then, the conductive paste for vias 341 is filled into the through holes 311 by a printing method or the like. The conductive paste for vias 341 is made by adding a viscosity adjusting agent, an organic solvent, or the like to AgSn powder to form a paste, and the viscosity is adjusted so that the paste does not easily flow out of the protective sheet 330.

[0032] In this case, the protective sheet 330 is made of a material having air permeability. Therefore, when the conductive paste for vias 341 is filled, the conductive paste for vias 341 can be filled while discharging air bubbles. Therefore, it is possible to prevent air bubbles from remaining in the conductive paste for vias 341.

[0033] 2D, protective sheet 330 is peeled off from base member 310. Then, conductive paste for wiring layer 342 is arranged on one surface 310a of base member 310 so as to contact conductive paste for vias 341. This results in wiring sheet 400 in which conductive paste for vias 341 and conductive paste for wiring layer 342 are arranged on base member 310. Note that conductive paste for wiring layer 342 of this embodiment is made of the same material as conductive paste for vias 341.

[0034] Moreover, the conductive paste 342 for wiring layers in this embodiment is disposed by a printing method or the like. In this case, when forming the same wiring sheet 400, a common mask can be used. Therefore, it is not necessary to prepare a new mask every time the conductive paste 342 for wiring layers is disposed, and the manufacturing process can be simplified.

[0035] 2C and 2D, via conductive paste 341 and wiring layer conductive paste 342 are not yet sintered, but may be pre-sintered as necessary to prevent flow. In the steps of Fig. 2B to Fig. 2D, the placement positions of via conductive paste 341 and wiring layer conductive paste 342 are adjusted according to the position of wiring sheet 400 placed in the step of Fig. 2E described later.

[0036] 2A to 2D, an insulating heat dissipation member 10 on which connection wiring 11 is formed and a semiconductor chip 20 are prepared. After that, as shown in FIG. 2E, a wiring sheet 400 and a semiconductor chip 20 are stacked and arranged on the insulating heat dissipation member 10. In this embodiment, the wiring sheets 400 are stacked so that the other surface 310b of the base member 310 faces one surface 10a of the insulating heat dissipation member 10. In this embodiment, a base member 310 on which an opening 33 is formed is also arranged in the outermost layer on the side opposite the insulating heat dissipation member 10 in the stacking direction.

[0037] Incidentally, among the multiple wiring sheets 400 (i.e., base member 310), a wiring sheet 400 on which the semiconductor chip 20 is to be arranged is also formed with an arrangement hole 401 for arranging the semiconductor chip 20 before stacking. Then, the semiconductor chip 20 is arranged so as to be accommodated in the arrangement hole 401.

[0038] 2F, the wiring sheets 400 are integrated by applying pressure in the stacking direction while heating, to form the sealing member 30. At this time, the LCP forming the base member 310 flows, and the conductive paste for vias 341 and the conductive paste for wiring layers 342 are pressurized from the surroundings. As a result, the conductive paste for vias 341 is sintered to form the connection vias 321, and the conductive paste for wiring layers 342 is sintered to form the wiring layers 322.

[0039] According to the embodiment described above, the connection via 321 is made of a sintered body obtained by sintering the conductive paste 341 for vias, and the wiring layer 322 is made of a sintered body obtained by sintering the conductive paste 342 for wiring layers. The conductive paste 342 for wiring layers is arranged by a printing method, and the mask used for the printing method can be shared. For this reason, the manufacturing process can be simplified compared to the case where, for example, a metal film such as copper foil is arranged on the base member 310, a new mask is prepared for each metal film, and a wiring layer is formed by etching. Furthermore, the mask used for etching or the like requires waste liquid treatment or the like when it is removed, and there is a concern about the impact on the environment. However, the mask used by the printing method can be shared, so the impact on the environment can also be reduced.

[0040] (1) In this embodiment, the connection vias 321 and the wiring layer 322 are made of the same sintered material, which makes it easy to prepare the material and simplifies the manufacturing process.

[0041] (2) In the present embodiment, when wiring sheet 400 is formed, through holes 311 are formed in base member 310 by punching. This makes it possible to suppress adhesion of foreign matter to base member 310, as compared to, for example, a case in which through holes 311 are formed by irradiating base member 310 with a laser beam.

[0042] (3) In this embodiment, when the conductive paste for vias 341 is filled, the protective sheet 330 having breathability is disposed. Therefore, when the conductive paste for vias 341 is filled, the conductive paste for vias 341 can be filled while discharging air bubbles. This makes it possible to prevent air bubbles from remaining in the conductive paste for vias 341. As a result, when the connection vias 321 and the wiring layer 322 are made of a sintered body, it is possible to prevent the portion of the wiring layer 322 connected to the connection vias 321 from being recessed toward the connection vias 321, and it is possible to prevent the wiring layer 322 from being disconnected and causing a connection failure.

[0043] Second embodiment A second embodiment will be described. In this embodiment, the shape of the through hole 311 formed in the base member 310 is changed from that of the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0044] In this embodiment, when the through hole 311 is formed by performing the step of Fig. 2B, the through hole 311 is formed with a tapered portion 311a whose opening on the one surface 310a side is wider than the central portion between the one surface 310a and the other surface 310b. The tapered portion 311a in this embodiment is tapered so that the width gradually narrows from the one surface 310a side toward the central portion. Such a through hole 311 is formed, for example, by adjusting conditions such as the shape of the punch used in punching and the punching speed.

[0045] When such through-hole 311 is filled with conductive paste for vias 341 to manufacture a semiconductor package, connection via 321 and wiring layer 322 are connected as shown in Fig. 4. Specifically, since through-hole 311 is formed as described above, connection via 321 has a shape in which the width of the portion on the wiring layer 322 side is wider than the width of the central portion of connection via 321. Note that the width refers to the length in a direction intersecting the extension direction of connection via 321, and refers to the length in the left-right direction of the paper in Fig. 4.

[0046] According to the present embodiment described above, since the wiring layer 322 is made of a sintered body obtained by sintering the conductive paste 342 for wiring layer, it is possible to obtain the same effects as those of the first embodiment.

[0047] (1) In this embodiment, the width of the connection via 321 on the wiring layer 322 side is wider than the width of the central portion. This makes it easier to ensure the bonding with the wiring layer 322. In addition, such a connection via 321 is formed by filling a through hole 311, the opening of which is wider on the side of the first surface 310a than the central portion, with a conductive via paste 341. At this time, since the opening of the through hole 311 on the side of the first surface 310a is wider, it is easier to fill the conductive via paste 341.

[0048] (2) Modification of the Second Embodiment A modified example of the second embodiment will be described. In the second embodiment, the tapered portion 311a (i.e., the portion of the connection via 321 on the wiring layer 322 side) may be rounded as shown in FIG. 5. By providing the rounded portion in this manner, it is possible to suppress stress concentration. Also, the tapered portion 311a may be formed on both sides of the central portion that are connected to the wiring layer 322 as shown in FIG. 6. That is, the connection via 321 may be shaped so that the width of both end portions that are connected to each wiring layer 322 is wider than the width of the central portion. This can improve the bondability with the wiring layers 322 on both sides of the connection via 321.

[0049] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0050] For example, in each of the above embodiments, the resin portion 31 (i.e., the base member 310) of the sealing member 30 may be made of an LCP material having an isotropic thermal expansion coefficient. The thermal expansion coefficient is adjusted by adjusting the amount of the added material. This allows thermal stress to be evenly released to the surroundings, thereby preventing localized concentration of thermal stress and preventing resin peeling.

[0051] In each of the above embodiments, the connection via 321 and the wiring layer 322 may be made of sintered bodies of different materials. For example, the wiring layer 322 may be made of a sintered body containing CuSn in order to adjust the wiring resistance.

[0052] In each of the above-described embodiments, the through-hole 311 may be formed by laser processing or the like.

[0053] Furthermore, in each of the above embodiments, a transfer method or the like may be used when disposing the conductive paste for wiring layer 342. Even if the conductive paste for wiring layer 342 is disposed by such a method, it is not necessary to prepare a new mask every time the conductive paste for wiring layer 342 is disposed, and therefore the manufacturing process can be simplified.

[0054] Furthermore, in each of the above embodiments, the semiconductor chip 20 may be configured by forming a superjunction MOSFET or an IGBT. Also, the semiconductor chip 20 may be configured using a support substrate 21 made of gallium oxide, gallium nitride, or the like, instead of the support substrate 21 made of silicon or SiC. [Explanation of symbols]

[0055] 10. Insulating heat dissipation material 20. Semiconductor Chips 30 Sealing member 31 Resin part 321 Connection vias 322 wiring layer

Claims

1. A semiconductor package in which a semiconductor chip (20) is sealed with a sealing member (30), The semiconductor chip on which a semiconductor element is formed; An insulating heat dissipation member (10) on which the semiconductor chip is mounted; the sealing member that seals the semiconductor chip, The sealing member has a resin portion (31) and a wiring portion (32) electrically connected to the semiconductor chip, The wiring portion is a semiconductor package having a plurality of wiring layers (322) extending along the surface direction of the semiconductor chip, and connection vias (321) extending along the stacking direction of the semiconductor chip and the insulating heat dissipation member and connecting adjacent wiring layers along the stacking direction.

2. 2. The semiconductor package according to claim 1, wherein the wiring layer and the connection vias are made of a sintered body.

3. 3. The semiconductor package according to claim 1, wherein the width of the connection via at a portion connected to the wiring layer is wider than the width of a portion located at a central portion in the stacking direction.

4. The semiconductor chip has an electrode (24) on the insulating heat dissipation member side, A semiconductor package as described in any one of claims 1 to 3, wherein the wiring portion has a pad portion (322b) exposed from the side of the sealing member opposite the insulating heat dissipation member side, and has a portion that electrically connects the pad portion and the electrode.

5. The insulating heat dissipation member has a connection wiring (11) made of copper formed on the semiconductor chip side, 5. The semiconductor package according to claim 4, wherein the electrodes of the semiconductor chip and the pads are electrically connected to each other also via the connection wiring.

6. 6. The semiconductor package according to claim 5, wherein the connection wiring has a thickness of 10 to 100 μm.

7. 7. The semiconductor package according to claim 1, wherein the insulating heat dissipation member includes an insulating substrate.

8. 8. The semiconductor package according to claim 7, wherein the insulating heat dissipation member is made of silicon nitride or aluminum nitride.

9. 9. The semiconductor package according to claim 1, wherein the semiconductor chip is a lateral element in which a current flows in a planar direction, and a transistor, a superjunction MOSFET, or an IGBT is formed as the semiconductor element.

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