Semiconductor device and power control unit

Abstract

To provide a semiconductor device and a power control unit, which are capable of both arranging a temperature sensor in an outer peripheral region and expanding an area of an active region without providing a special structure for preventing the influence of an electric field in the outer peripheral region.SOLUTION: A semiconductor device includes: a semiconductor substrate 41 having an active region 411 and an outer peripheral region 412 in which a voltage withstanding structure 413 is formed; and a temperature sensor 91 configured to detect a temperature of the semiconductor substrate in the outer peripheral region. The semiconductor device is electrically connected to a control device configured to detect whether there is an abnormality in a cooling system 140 based on the temperature detected by the temperature sensor. The semiconductor device further includes a conductive spacer 70 on the active region on the semiconductor substrate. The temperature sensor is positioned not to overlap the conductive spacer in a plate thickness direction, and positioned closer to a center of the semiconductor substrate in an orthogonal direction than the voltage withstanding structure is.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The disclosure described in this specification relates to a semiconductor device and a power control unit. [Background technology]

[0002] Patent Document 1 describes a semiconductor device including a semiconductor substrate, a surface electrode, a field plate electrode, and a temperature sensor. The semiconductor substrate has an element section in which a functional structure is provided, and a peripheral section in which a termination voltage withstanding structure is provided. The surface electrode is provided on the element section. The field plate electrode is in contact with the surface electrode and is provided on the termination voltage withstanding structure. The temperature sensor is provided on the field plate electrode. Joule heat generated in the element section is transferred to the temperature sensor via the surface electrode and the field plate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6872933 Summary of the Invention [Problem to be solved by the invention]

[0004] When arranging the temperature sensor on the termination voltage-resistant structure, it was necessary to provide a special structure such as a field plate electrode between the termination voltage-resistant structure and the temperature sensor to prevent it from being affected by the electric field in the surrounding area. It was difficult to achieve both arranging the temperature sensor in the surrounding area without providing a special structure and expanding the area of ​​the element part.

[0005] The object of the present disclosure is to provide a semiconductor device and a power control unit that can simultaneously place a temperature sensor in the peripheral region and expand the area of ​​the active region without providing a special structure to prevent the effects of the electric field in the peripheral region. [Means for solving the problem]

[0006] A semiconductor device according to an aspect of the present disclosure includes: A semiconductor device (20) comprising: a semiconductor substrate (41) having an active region (411) in which an element is formed, and an outer periphery region (412) surrounding the active region in a plan view in a plate thickness direction (Z) and in which a pressure-resistant structure (413) is formed; and a temperature sensor (91) for detecting a temperature of the semiconductor substrate in the outer periphery region, the semiconductor substrate (20) being electrically connected to a control device (13) for detecting whether or not there is an abnormality in a cooling system (140) for cooling the semiconductor substrate based on the temperature detected by the temperature sensor, a conductive spacer (70) disposed on the active area on one side (41a) of the semiconductor substrate; The temperature sensor is disposed so as not to overlap the conductive spacer in the plate thickness direction and closer to the center of the semiconductor substrate than the breakdown voltage structure in the direction perpendicular to the plate thickness direction.

[0007] The function required of the temperature sensor (91) is not to detect the maximum temperature of the semiconductor substrate (41) but to detect an abnormality in the cooling system (140), so there are few restrictions on the placement of the temperature sensor. Since the temperature sensor is provided closer to the center of the semiconductor substrate than the voltage-resistant structure (413), there is no need to provide a special structure to prevent the influence of the electric field caused by the voltage-resistant structure. Furthermore, since it does not overlap with the conductive spacer (70) in the plate thickness direction (Z), there is no need to provide a gap in the active region to provide the temperature sensor. It has become possible to both place the temperature sensor in the peripheral region (412) without providing a special structure to prevent the influence of the electric field caused by the voltage-resistant structure and to expand the area of ​​the active region.

[0008] According to another aspect of the present disclosure, a power control unit includes: A semiconductor substrate (41) having an active region (411) in which elements are formed, and an outer peripheral region (412) surrounding the active region in a plan view in the thickness direction and in which a breakdown voltage structure (413) is formed; a conductive spacer (70) disposed on one side of a semiconductor substrate over an active area; a temperature sensor (91) for detecting a temperature of the semiconductor substrate in the peripheral region; a control device (13) that detects whether or not there is an abnormality in a cooling system (140) that cools the semiconductor substrate based on a detected temperature detected by the temperature sensor; The temperature sensor is disposed so as not to overlap the conductive spacer in the plate thickness direction and closer to the center of the semiconductor substrate than the breakdown voltage structure in the direction perpendicular to the plate thickness direction.

[0009] In the power control unit as well, it has become possible to arrange the temperature sensor (91) in the peripheral region (412) without providing a special structure to prevent the influence of the electric field caused by the pressure-resistant structure (413), and to enlarge the area of ​​the active region (411).

[0010] It should be noted that the reference numbers in parentheses above merely indicate the corresponding relationship with the configurations described in the embodiments described below, and do not in any way limit the technical scope. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing a schematic configuration of a drive system of a vehicle to which a semiconductor device according to a first embodiment is applied; [Diagram 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Diagram 3] 3 is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 2. [Figure 4] FIG. 2 is a cross-sectional view of a power control unit. [Diagram 5] FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. [Figure 8] 4 is a flowchart relating to abnormality detection in a cooling system. [Figure 9] FIG. 11 is a plan view showing a semiconductor substrate according to a second embodiment. [Figure 10]FIG. 11 is a plan view showing a semiconductor substrate according to a third embodiment. [Figure 11] FIG. 13 is a plan view showing a semiconductor substrate according to a fourth embodiment. [Figure 12] FIG. 13 is a plan view showing a semiconductor substrate according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, several embodiments for carrying out the present disclosure will be described with reference to the drawings. In each embodiment, the same reference numerals may be used to designate parts corresponding to matters described in the preceding embodiment, and duplicated descriptions may be omitted. In each embodiment, when only a part of the configuration is described, the other embodiment described previously may be applied to the other parts of the configuration.

[0013] In addition to combinations of parts that are explicitly stated as possible in each embodiment, it is also possible to partially combine embodiments, embodiments and variations, and variations even if not explicitly stated, provided that there are no particular problems with the combination.

[0014] (First embodiment) The semiconductor device 20 of this embodiment is applied to, for example, a power control unit 4 of a moving object using a rotating electric machine as a drive source. The moving object is, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0015] <Vehicle drive system> First, a schematic configuration of a vehicle drive system 1 will be described with reference to Fig. 1. The vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power control unit 4.

[0016] The DC power supply 2 is a DC voltage source composed of a chargeable and dischargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power control unit 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0017] <Power control unit> Next, a description will be given of the circuit configuration of the power control unit 4. The power control unit 4 includes a power conversion circuit and a control device 13. As shown in Fig. 1, the power control unit 4 includes a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0018] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7 which is a power line on the high potential side and an N line 8 which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0019] The inverter 6 is a DC-AC conversion circuit. The inverter 6 has a semiconductor device 20. The semiconductor device 20 of this embodiment includes a MOSFET as a switching element. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by the control device 13 and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 upon receiving rotational force from the wheels into a DC voltage in accordance with switching control by the control device 13 and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

[0020] The control device 13 has a control circuit that controls the on / off of the MOSFETs 11. The on / off of the multiple MOSFETs 11 is controlled by the control circuit. Accordingly, the power control unit 4 can supply three-phase AC currents with different periods to the motor generator 3. Note that the control device 13 may also include a drive circuit that drives the MOSFETs in addition to the control circuit. The drive circuit supplies a drive current to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit.

[0021] The control device 13 outputs, for example, a PWM signal as a drive command. The control device 13 is configured to include, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation. The drive circuit drives the corresponding MOSFET 11, i.e., drives it on and off, by applying a drive current. The drive circuit is sometimes called a driver.

[0022] The control device 13 and the method described herein may be implemented by a dedicated computer having a processor programmed to execute one or more functions embodied in a computer program. Alternatively, the device and the method described herein may be implemented by a dedicated hardware logic circuit. Alternatively, the device and the method described herein may be implemented by one or more dedicated computers configured by a combination of a processor that executes a computer program and one or more hardware logic circuits. The computer program may also be stored on a computer-readable non-transitory tangible recording medium as instructions to be executed by the computer.

[0023] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. A connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is formed of a conductive member such as a bus bar.

[0024] In this embodiment, an n-channel MOSFET 11 is used as a switching element constituting each arm. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0025] A freewheeling diode 12 is connected in anti-parallel to each of the MOSFETs 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0026] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in inverse parallel.

[0027] The power control unit 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. With this configuration, voltage can be increased and decreased. The power control unit 4 may include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

[0028] The power control unit 4 includes a cooler 110 in addition to the components described above. The cooler 110 is a device for cooling a plurality of semiconductor devices 20. The cooler 110 is included in a cooling system 140 having a coolant pump 130 for circulating a coolant through the cooler 110. The power module 120 is configured by a plurality of semiconductor devices 20 and the cooler 110. The cooler 110 has a stacked cooling structure in which the cooler 110 is connected to a pump or the like and stacked in the Z direction. The cooler 110 includes a supply pipe, a discharge pipe, and a plurality of relay pipes 111. The plurality of relay pipes 111 are bridged in a ladder shape between the supply pipe and the discharge pipe. The supply pipe and the discharge pipe are connected via the relay pipe 111 in a manner that allows the coolant to flow. The semiconductor devices 20 are individually stored between the adjacent relay pipes 111. The semiconductor devices 20 are sandwiched between the adjacent relay pipes 111. Both sides of the semiconductor devices 20 are cooled by the cooler 110.

[0029] <Semiconductor device> Next, a schematic configuration of the semiconductor device 20 will be described with reference to Figs. 2 to 7. Fig. 2 is a plan view showing the semiconductor device 20 according to the first embodiment. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2. Fig. 4 is a cross-sectional view of the power control unit 4. Fig. 5 is a plan view of the semiconductor substrate 41. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5.

[0030] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the orthogonal direction. A first direction among the orthogonal directions is referred to as the Y direction. A second direction among the orthogonal directions that is different from the first direction is referred to as the X direction. Unless otherwise specified, a shape viewed from a plane in the Z direction, in other words a shape along the XY plane defined by the X and Y directions, is referred to as a planar shape. Also, a planar view from the Z direction may simply be referred to as a planar view.

[0031] 2 to 7, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50 and 60, a conductive spacer 70, and an external connection terminal 80. The semiconductor device 20 further includes a bonding wire 90 and a bonding material 100. The semiconductor device 20 constitutes one of the above-mentioned arms. In other words, two semiconductor devices 20 constitute an upper and lower arm circuit 9 for one phase.

[0032] The encapsulant 30 encapsulates a part of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of the resin is an epoxy resin. The encapsulant 30 is made of a resin and molded by, for example, a transfer molding method. Such an encapsulant 30 may be called an encapsulating resin body, a molded resin, a resin molded body, or the like. The encapsulant 30 may be formed by using, for example, a gel. The gel is disposed in the opposing regions of the pair of wiring members 50, 60.

[0033] As shown in FIG. 2 or 3, the sealing body 30 has a substantially rectangular shape in plan view. The sealing body 30 has one surface 30a and a back surface 30b, which is the surface opposite to the one surface 30a in the Z direction, as surfaces forming an outer periphery. The one surface 30a and the back surface 30b are, for example, substantially flat surfaces. The sealing body 30 also has side surfaces 30c, 30d, 30e, and 30f that are continuous with the one surface 30a and the back surface 30b. The side surface 30c is a surface from which the main terminals 81 and 82 of the external connection terminal 80 protrude. The side surface 30d is a surface opposite to the side surface 30c in the Y direction. The side surface 30d is a surface from which the signal terminal 83 protrudes. The side surfaces 30e and 30f are surfaces from which the external connection terminal 80 does not protrude. The side surface 30e is a surface opposite to the side surface 30f in the X direction.

[0034] The semiconductor element 40 includes a semiconductor substrate 41, a source electrode 42, a drain electrode 43, and a pad 44. A gate electrode (not shown) is further formed on the semiconductor substrate 41. The gate electrode has a trench structure, for example. The gate electrode does not have to have a trench structure. The gate electrode may have a planar structure. The semiconductor element 40 is sometimes called a semiconductor chip. The semiconductor substrate 41 is made of a vertical element formed from materials such as silicon (Si) and wide band gap semiconductors having a wider band gap than silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0035] The vertical element is configured to pass a main current in the thickness direction of the semiconductor substrate 41. The semiconductor element 40 is arranged so that the thickness direction is approximately parallel to the Z direction. The semiconductor element 40 has main electrodes on both sides in the thickness direction. The semiconductor substrate 41 of this embodiment is formed by forming an n-channel MOSFET 11 as a vertical element on a semiconductor substrate 41 made of SiC. As shown in FIG. 3, the semiconductor substrate 41 has a source electrode 42 on one surface 41a facing the wiring member 50 as a main electrode, and a drain electrode 43 on a back surface 41b opposite to the one surface 41a.

[0036] When MOSFET 11 is turned on, a current (main current) flows between the main electrodes, that is, between drain electrode 43 and source electrode 42. When diode 12 is a parasitic diode, source electrode 42 also serves as an anode electrode, and drain electrode 43 also serves as a cathode electrode. Diode 12 may be formed on a chip separate from MOSFET 11. Drain electrode 43 is a main electrode on the high potential side, and source electrode 42 is a main electrode on the low potential side. Drain electrode 43 is formed over almost the entire lower surface. Source electrode 42 is formed on a part of the upper surface.

[0037] The pad 44 is an electrode for signals. The pad 44 is formed on one surface 41a of the semiconductor substrate 41 in a region different from the region where the source electrode 42 is formed. As an example, as shown in Fig. 5, the semiconductor substrate 41 has five pads 44. Specifically, the pads 44 include a gate pad 44G, a Kelvin source pad 44KS, a pad 44K for detecting a cathode potential of the temperature sensor 91, a pad 44A for detecting an anode potential of the temperature sensor 91, and a current sense pad 44SS.

[0038] The five pads 44 are arranged in the X direction. From the side surface 30f to the side surface 30e, the five pads 44 are arranged in the following order: a Kelvin source pad 44KS, a current sense pad 44SS, a gate pad 44G, an anode potential detection pad 44A, and a cathode potential detection pad 44K. Each pad 44 is electrically connected to a corresponding signal terminal 83 via a bonding wire 90. Two adjacent pads 44 are spaced apart to an extent that the insulation of the bonding wire 90 can be ensured. Note that the number and arrangement order of the pads 44 are not limited to this.

[0039] The wiring member 50 is electrically connected to the source electrode 42 and provides a wiring function. Similarly, the wiring member 60 is electrically connected to the drain electrode 43 and provides a wiring function. The wiring members 50, 60 are arranged to sandwich the semiconductor element 40 in the Z direction. The wiring members 50, 60 are arranged so that at least a portion of each of them faces each other in the Z direction. The wiring members 50, 60 include the semiconductor element 40 in a plan view.

[0040] The wiring members 50, 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. The wiring members 50, 60 may be referred to as a heat dissipation plate, a heat sink, or the like. The wiring members 50, 60 of this embodiment are metal plates made of metals with good electrical conductivity, such as Cu and Cu alloys. The metal plates are provided, for example, as part of a lead frame. Instead of metal plates, a substrate in which metal bodies are arranged on both sides of an insulating base material may be used. The wiring members 50, 60 may have a plating film of Ni, Au, or the like on the metal surface.

[0041] The wiring member 50 has an opposing surface 50a which is the surface on the semiconductor element 40 side, and a back surface 50b which is the surface opposite to the opposing surface 50a. Similarly, the wiring member 60 also has an opposing surface 60a and a back surface 60b. The wiring members 50 and 60 are, for example, substantially rectangular in plan view. The back surfaces 50b and 60b of the wiring members 50 and 60, respectively, are exposed from the sealing body 30. The back surfaces 50b and 60b may be referred to as heat dissipation surfaces, exposed surfaces, etc. The back surface 50b of the wiring member 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30.

[0042] The conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 provides a spacer function that ensures a predetermined distance between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 ensures the loop height of the bonding wire 90 when connecting the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40 by the bonding wire 90. The conductive spacer 70 is located midway along the electrical conduction and heat conduction paths between the source electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function.

[0043] The conductive spacer 70 contains a metal material having good electrical conductivity and thermal conductivity, such as Cu (copper). The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 may be called a terminal, a metal block, or the like. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. The conductive spacers 70 are individually connected to the semiconductor elements 40. The conductive spacers 70 are, for example, columnar.

[0044] The external connection terminals 80 are terminals for electrically connecting the semiconductor device 20 to an external device. The external connection terminals 80 are formed using a metal material with good conductivity, such as copper. The external connection terminals 80 are, for example, a plate material. The external connection terminals 80 are sometimes called leads. The external connection terminals 80 include main terminals 81 and 82 and a signal terminal 83. The main terminals 81 and 82 are external connection terminals 80 electrically connected to main electrodes of the semiconductor element 40.

[0045] The main terminal 81 is electrically connected to the source electrode 42. The main terminal 81 may be referred to as a source terminal. The main terminal 81 is connected to the source electrode 42 via the wiring member 50. The main terminal 81 is connected to one end of the wiring member 50 in the Y direction. The thickness of the main terminal 81 is thinner than that of the wiring member 50. The main terminal 81 is connected to the wiring member 50 so as to be substantially flush with the opposing surface 50a, for example. The main terminal 81 may be connected to the wiring member 50 by being provided continuously and integrally therewith, or may be provided as a separate member and connected by joining.

[0046] The main terminal 81 in this embodiment is provided integrally with the wiring member 50 as a part of the lead frame. The main terminal 81 extends in the Y direction from the wiring member 50 and protrudes to the outside from the side surface 30c of the sealing body 30. The main terminal 81 has a bent portion midway through the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.

[0047] The main terminal 82 is electrically connected to the drain electrode 43. The main terminal 82 may be referred to as a drain terminal. The main terminal 82 is connected to the drain electrode 43 via the wiring member 60. The main terminal 82 is connected to one end of the wiring member 60 in the Y direction. The thickness of the main terminal 82 is thinner than that of the wiring member 60. The main terminal 82 is connected to the wiring member 60, for example, so as to be substantially flush with the opposing surface 60a. The main terminal 82 may be connected to the wiring member 60 by being provided continuously and integrally therewith, or may be provided as a separate member and connected by joining.

[0048] The main terminal 82 in this embodiment is provided integrally with the wiring member 60 as a part of a lead frame separate from the main terminal 81. The main terminal 82 extends in the Y direction from the wiring member 60 and protrudes to the outside from the same side surface 30c as the main terminal 81. The main terminal 82 also has a bent portion midway through the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 81, 82 are arranged side by side in the X direction with their side surfaces facing each other.

[0049] The signal terminals 83 are electrically connected to the corresponding pads 44 of the semiconductor element 40. The signal terminals 83 are electrically connected to the pads 44 via bonding wires 90. The signal terminals 83 extend in the Y direction and protrude from the side surface 30d of the sealing body 30 to the outside. The semiconductor device 20 of this embodiment includes five signal terminals 83 corresponding to the pads 44. The five signal terminals 83 are arranged side by side in the X direction. The signal terminals 83 are formed on a lead frame common to the wiring member 60 and the main terminals 82, for example. The multiple signal terminals 83 are electrically separated from each other by cutting tie bars (not shown).

[0050] The bonding material 100 is interposed between elements constituting the semiconductor device 20 and bonds the elements together. The bonding material 100 is, for example, solder. The semiconductor device 20 includes a plurality of bonding materials 100. One of the bonding materials 100 is interposed between the source electrode 42 and the conductive spacer 70 and bonds the source electrode 42 and the conductive spacer 70. The other bonding material 100 is interposed between the conductive spacer 70 and the wiring member 50 and bonds the conductive spacer 70 and the wiring member 50. The other bonding material 100 is interposed between the drain electrode 43 and the wiring member 60 of the semiconductor element 40 and bonds the drain electrode 43 and the wiring member 60.

[0051] The semiconductor element 40 is disposed between the wiring members 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the wiring members 50 and 60 disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the wiring member 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0052] <Semiconductor substrate> The semiconductor substrate 41 has a generally rectangular shape in plan view. As shown in Fig. 5, the semiconductor substrate 41 has an active region 411 and a peripheral region 412. The active region 411 is a region in which vertical elements are formed. The active region 411 may also be referred to as a main region, a cell region, or the like. In the drawings, the active region 411 is hatched in the plan view to distinguish between the active region 411 and the peripheral region 412.

[0053] The active region 411 has a central active region 411a, a right end active region 411b, and a left end active region 411c. The central active region 411a has a substantially rectangular shape in plan. The central active region 411a is aligned with the pads 44 in the Y direction. The central active region 411a includes a conductive spacer 70 in plan view. The conductive spacer 70 is indicated by a two-dot chain line in FIG. 5. The central active region 411a may be referred to as a main region. The right end active region 411b and the left end active region 411c may be referred to as extension regions.

[0054] The right-end active region 411b is connected to the right end of the end of the central active region 411a on the pad 44 side. The right end refers to the end on the side of side 30e. The left-end active region 411c is connected to the left end of the central active region 411a on the pad 44 side. The left end refers to the end on the side of side 30f. The active region 411 is substantially U-shaped in plan view. The active region 411 has a plurality of cells (unit structures). The plurality of cells are connected in parallel to each other to form a MOSFET.

[0055] The outer periphery region 412 surrounds the active region 411 in a plan view. The two-dot chain line shown in FIG. 6 indicates the boundary between the active region 411 and the outer periphery region 412. The outer periphery region 412 has a first outer periphery region 412a and a second outer periphery region 412b. The first outer periphery region 412a corresponds to an annular region that surrounds the active region 411 and the first outer periphery region 412a along the periphery of the semiconductor substrate 41. The second outer periphery region 412b corresponds to a region in the outer periphery region 412 adjacent to the central active region 411a, the right end active region 411b, and the left end active region 411c. The second outer periphery region 412b can also be said to be a region surrounded by the central active region 411a, the right end active region 411b, and the left end active region 411c.

[0056] A breakdown voltage structure 413 is formed in the first outer periphery region 412a. In this embodiment, as an example, a guard ring is formed as the breakdown voltage structure 413. The breakdown voltage structure 413 is configured in an annular shape along the outer periphery of the semiconductor substrate 41. An insulating film 414 is provided on one surface 41a of the semiconductor substrate 41 corresponding to the outer periphery region 412. Although not shown, a gate insulating film is formed on the wall surface of the trench. A gate electrode is formed on the surface of the gate insulating film so as to fill the trench. Furthermore, although not shown, an insulating film 414 is provided so as to cover the gate electrode.

[0057] The semiconductor element 40 further includes a protective film 45 disposed on the insulating film 414. The protective film 45 is a film provided on the insulating film 414 so as to cover the peripheral portion of the source electrode 42. As a material for the protective film 45, for example, polyimide, silicon nitride film, or the like can be adopted.

[0058] The protective film 45 has a first opening 451a and a second opening 451b. The first opening 451a defines a bonding region between the source electrode 42 and the bonding material 100. The first opening 451a and the second opening 451b are through holes penetrating the protective film 45 in the Z direction. The first opening 451a is provided so as to overlap with the source electrode 42 in a plan view. The first opening 451a is approximately aligned with the active region 411 in a plan view. The second opening 451b is provided so as to overlap with the pad 44 in a plan view. Five second openings 451b are provided corresponding to the respective pads. The second openings 451b will be described later.

[0059] The source electrode 42 has a first exposed portion 421a that is exposed from the first opening 451a of the protective film 45 and provides a bonding region with the conductive spacer 70. The first exposed portion 421a is disposed on the active region 411 of the semiconductor substrate 41. The source electrode 42 has a multi-layer structure. The source electrode 42 has a base electrode 422 and a connection electrode 423.

[0060] The base electrode 422 is a metal layer disposed on the semiconductor substrate 41 side of the multi-layered source electrode 42. The base electrode 422 is formed, for example, using a material mainly composed of Al (aluminum). The base electrode 422 of this embodiment is formed using an Al alloy such as AlSi or AlSiCu. The base electrode 422 may be referred to as a wiring electrode, a base layer, a first metal layer, etc.

[0061] The base electrode 422 is extended onto the outer peripheral region 412 while including the active region 411 in a plan view. The base electrode 422 is connected to the source and anode of the vertical element. The base electrode 422 is connected to the insulating film 414 in the perpendicular direction. The protective film 45 is disposed on the insulating film 414 so as to cover the peripheral portion of the base electrode 422.

[0062] The connection electrode 423 is disposed on the base electrode 422. The connection electrode 423 is also referred to as an upper electrode, an upper electrode, an upper layer electrode, an upper layer, or a second metal layer. The connection electrode 423 includes at least a metal for solder connection with the conductive spacer 70. The connection electrode 423 may include a non-metal as well as a metal. The connection electrode 423 is disposed on the base electrode 422 in the first opening 451a of the protective film 45. The outer peripheral end of the connection electrode 423 is in contact with the inner peripheral surface of the protective film 45 that defines the first opening 451a. A first exposed portion 421a is provided on the outer surface of the connection electrode 423.

[0063] The pad 44 also has a similar configuration to the source electrode 42. The base electrode 422 of the pad 44 is disposed on the semiconductor substrate 41 side of the multi-layered source electrode 42. The connection electrode 423 of the pad 44 is disposed by stacking on the base electrode 422 of the pad 44. The source electrode 42 of the pad 44 has a second exposed portion 421b that is exposed from the second opening 451b of the protective film 45 and provides a bonding area between the bonding electrode 422 and the bonding wire 90. The outer peripheral end of the connection electrode 423 of the pad 44 is in contact with the inner peripheral surface of the protective film 45 that defines the second opening 451b. The second exposed portion 421b is provided on the outer surface of the connection electrode 423 of the pad 44.

[0064] The semiconductor element 40 also includes a gate wiring 46 as a wiring portion. The gate wiring 46 is disposed at a position not overlapping with the source electrode 42 and the pad 44 in a plan view, and is covered with a protective film 45. The gate wiring 46 electrically connects the gate electrode of the MOSFET 11 formed on the semiconductor substrate 41 to the gate pad 44G. The gate wiring 46 is a metal wiring formed using a material mainly composed of Al (aluminum), for example. The gate wiring 46 is electrically connected to the gate electrode via a wiring not shown.

[0065] As an example, the entire length of the gate wiring 46 in this embodiment is disposed on the first outer periphery region 412a. The gate wiring 46 is disposed in a ring shape so as to surround the active region 411 and the second outer periphery region 412b. The breakdown voltage structure 413 is configured in a ring shape along the outer periphery of the semiconductor substrate 41 so as to surround the gate wiring 46. In a plan view, the gate wiring 46 is provided closer to the active region 411 and the second outer periphery region 412b than the breakdown voltage structure 413. In a plan view, the breakdown voltage structure 413 is provided away from the active region 411 and the second outer periphery region 412b to an extent that the gate wiring 46 can be disposed therein.

[0066] <Temperature sense> The semiconductor device 20 has a temperature sensor 91. The temperature sensor 91 has a P-type anode region 92 and an N-type cathode region 93. The anode region 92 and the cathode region 93 form a PN diode. The anode region 92 and the cathode region 93 are formed by doping impurities into polysilicon arranged on the semiconductor substrate 41. The temperature sensor 91 is provided in a non-active region. The anode region 92 and the cathode region 93 are covered with an insulating film 414. Through a wiring 415 that is a part of the polysilicon wiring covered with the insulating film 414, the anode region 92 is electrically connected to the anode potential detection pad 44A, and the cathode region 93 is electrically connected to the cathode potential detection pad 44K. The anode potential detection pad 44A and the cathode potential detection pad 44K are electrically connected to the control device 13 through a bonding wire 90 and a signal terminal 83.

[0067] The control device 13 applies a voltage to the anode region 92 that is more positive than the cathode region 93, and controls so that a constant current flows between the anode region 92 and the cathode region 93. When the semiconductor device 20 is in the on mode, a current flows through the active region 411, and Joule heat is generated in the active region 411. This causes the temperature of the semiconductor substrate 41 to rise. Then, the forward voltage of the PN diode of the temperature sensor 91 changes depending on the temperature of the semiconductor substrate 41. The control device 13 measures the forward voltage of the PN diode of the temperature sensor 91, and detects the temperature from the measured value.

[0068] It is generally known that in semiconductor substrate 41, the temperature is higher closer to the center of active region 411. When temperature sensor 91 is used for the purpose of protecting semiconductor substrate 41 from overheating, temperature sensor 91 is often disposed near the center where the temperature is highest. This allows temperature sensor 91 to detect the maximum temperature of semiconductor substrate 41. By detecting the maximum temperature with temperature sensor 91, overheating of semiconductor substrate 41 can be prevented as early as possible.

[0069] In this embodiment, the temperature sensor 91 is not provided in the center of the active area 411. In this embodiment, the temperature sensor 91 is provided in the second outer circumferential area 412b. The temperature sensor 91 in this embodiment does not detect the maximum temperature, but detects the temperature of the second outer circumferential area 412b. In this embodiment, the temperature sensor 91 is used for the purpose of detecting an abnormality in the cooling system 140. Detection of an abnormality in the cooling system 140 will be described later.

[0070] The arrangement of the temperature sensor 91 will be further described below. As described above, the conductive spacer 70 is included in the central active region 411a in plan view. The second outer periphery region 412b is an area surrounded by the central active region 411a, the right end active region 411b, and the left end active region 411c. The second outer periphery region 412b is surrounded in an annular shape by the first outer periphery region 412a in which the breakdown voltage structure 413 is provided. According to this, the temperature sensor 91 does not overlap the conductive spacer 70 in plan view, and can be said to be provided closer to the center of the semiconductor substrate 41 than the breakdown voltage structure 413 in the orthogonal direction. More specifically, the temperature sensor 91 is provided in the gap between the anode potential detection pad 44A and the cathode potential detection pad 44K in the second outer periphery region 412b. The arrangement of the temperature sensor 91 is not limited to this.

[0071] As described above, the semiconductor device 20 is cooled by the cooler 110. Because the heat of the semiconductor substrate 41 is dissipated to the cooler 110, the temperature of the semiconductor substrate 41 is lower than when the semiconductor device 20 is not cooled by the cooler 110. The temperature sensor 91 detects the actual temperature of the second outer periphery region 412b in a state in which the heat of the semiconductor substrate 41 is dissipated to the cooler 110. The actual temperature detected by the temperature sensor 91 may be referred to as the detected temperature.

[0072] The temperature sensor 91 is electrically connected to the control device 13. The control device 13 has a first control unit 14 and a second control unit 15. The first control unit 14 has the drive circuit and control circuit described above. The second control unit 15 detects that an abnormality has occurred in the cooling system 140 when the actual temperature of the detection target area in the semiconductor substrate 41 is outside the expected temperature range described below. The detection target area is, for example, the second outer circumferential area 412b. In this embodiment, for example, the second control unit 15 is applied to a microcomputer. In the drawings, the first control unit 14 is abbreviated as "1CTR". The second control unit 15 is abbreviated as "2CTR".

[0073] The second control unit 15 includes a calculation unit 16 such as a CPU, a storage unit 17 including a volatile memory such as a RAM and a non-volatile memory such as a ROM, and an input / output interface (not shown). In the second control unit 15, the calculation unit 16 executes a program stored in the storage unit 17. The calculation unit 16 executes the program to perform various calculation processes. The calculation unit 16 executes a predetermined mathematical formula when performing various calculation processes. The calculation unit 16 also performs calculation processes using various signals input to the interface.

[0074] The memory unit 17 stores an expected temperature of the detection target area. The expected temperature is the temperature of the second outer circumferential area 412b having a predetermined temperature range that is expected to be detected by the temperature sensor 91 when the cooling system 140 is not clogged and the refrigerant flows normally. The calculation unit 16 has a temperature acquisition unit 16A, a temperature comparison unit 16B, and an abnormality detection unit 16C as functional blocks. The second control unit 15 can detect whether or not an abnormality has occurred in the cooling system 140 by executing each functional block.

[0075] FIG. 8 is a flow chart for detecting an abnormality of the cooler 110 by the second control unit 15. In step S10, the temperature acquisition unit 16A acquires the actual temperature of the detection target area in the semiconductor substrate 41. In step S20, the temperature comparison unit 16B compares the actual temperature of the detection target area with the expected temperature. In step S30, if the actual temperature is outside the expected temperature range, in step S40, the abnormality detection unit 16C detects that there is an abnormality in the cooling system 140, and proceeds to END. Thereafter, the control device 13 performs a protective operation to protect the inverter 6. Note that the protective operation may be performed by the second control unit 15, or may not be performed by the second control unit 15. It is sufficient that the protective operation is performed by the control device 13. It is sufficient that the control device 13 includes a protection unit that performs a protective operation of the inverter 6. In addition, in step S30, if the actual temperature is within the expected temperature range, in step S50, the abnormality detection unit 16C detects that there is no abnormality in the cooling system 140, and returns to START. If the actual temperature is within the expected temperature range in step S30, the flow is repeated until an abnormality in the cooling system 140 is detected.

[0076] In the drawings, the calculation unit 16 is abbreviated as "ALU". The temperature acquisition unit 16A is abbreviated as "TAS". The temperature comparison unit 16B is abbreviated as "TCS". The abnormality detection unit 16C is abbreviated as "ADS". The memory unit 17 is abbreviated as "STU".

[0077] <Current sense> The semiconductor device 20 further includes a current sensor 94. The current sensor 94 has a function of detecting an overcurrent flowing through the vertical element. The current sensor 94 includes unit cells having the same configuration as the vertical element, but the number of unit cells is smaller than the number of unit cells of the main semiconductor element 11.

[0078] The current sense 94 occupies a smaller surface area of ​​the active region on the semiconductor substrate 41 than the main vertical element. In the current sense 94 with a smaller surface area, the leakage current of the gate insulating film due to static electricity generated during the manufacturing process is higher. Therefore, the current sense 94 has a lower ESD resistance and is more susceptible to dielectric breakdown than the main vertical element. In this embodiment, as described above, a gap having a predetermined distance that can maintain the insulation of adjacent bonding wires 90 is provided between two adjacent pads 44. The width of the gap between the two pads 44 is shorter than the length of the pad 44 in the Y direction. In this embodiment, the current sense 94 is provided in the gap between the gate pad 44G and the current sense pad 44SS in the X direction.

[0079] The length of the current sense 94 in the X direction corresponds to the width of the gap in the X direction. The length of the current sense 94 in the Y direction corresponds to the length of the pad 44 in the Y direction. The length of the current sense 94 in the X direction is longer than the length of the current sense 94 in the Y direction. In this embodiment, the width of the gap between the two pads 44 is regulated by design requirements, so the length of the current sense 94 in the Y direction is made longer than the length of the current sense 94 in the X direction, thereby increasing the surface area of ​​the current sense 94. This makes it easier to suppress a decrease in ESD resistance.

[0080] <Action and effect> The semiconductor device 20 has a semiconductor substrate 41 and a temperature sensor 91. The semiconductor substrate 41 has an active region 411 and a peripheral region 412. The active region 411 is a region in which vertical elements are formed. The peripheral region 412 surrounds the active region 411 in a plan view, and has a breakdown voltage structure 413 formed therein. The temperature sensor 91 detects the temperature of the semiconductor substrate 41. The semiconductor device 20 is electrically connected to a control device 13. The control device 13 has a function of detecting whether or not there is an abnormality in a cooling system 140 that cools the semiconductor substrate 41, based on the temperature detected by the temperature sensor 91.

[0081] The semiconductor device 20 further includes a source electrode 42, a drain electrode 43, and a conductive spacer 70. The source electrode 42 is disposed on an active region 411 on one surface 41a of the semiconductor substrate 41 and is electrically connected to the vertical element. The drain electrode 43 is disposed on the back surface and is electrically connected to the vertical element. The conductive spacer 70 is disposed on the source electrode 42 and is connected to the source electrode 42. A temperature sensor 91 is disposed so as not to overlap the conductive spacer 70 in the Z direction and closer to the center of the semiconductor substrate 41 than the breakdown voltage structure 413 in the orthogonal direction.

[0082] If the function of the temperature sensor 91 is to detect the maximum temperature of the semiconductor substrate 41, then as described above, it is required to place the temperature sensor 91 near the center in the orthogonal direction of the semiconductor substrate 41, which has the highest temperature. However, in this embodiment, the function of the temperature sensor 91 is to detect an abnormality in the cooling system 140. For this reason, it is not necessary to place the temperature sensor 91 near the center in the orthogonal direction of the semiconductor substrate 41. There are few restrictions on the placement of the temperature sensor 91.

[0083] When arranging the temperature sensor 91 on the voltage-resistant structure 413, it is necessary to provide a special structure such as a field plate electrode to prevent the temperature sensor 91 from being affected by the electric field of the voltage-resistant structure 413. However, in this embodiment, the temperature sensor 91 is provided in a region closer to the center of the semiconductor substrate 41 than the peripheral region 412. Therefore, it is not necessary to provide a special structure such as a field plate electrode to prevent the effect of the electric field from the voltage-resistant structure 413. It is possible to suppress the concentration of the electric field on the temperature sensor 91.

[0084] Furthermore, if the temperature sensor 91 overlaps with the conductive spacer 70 in the Z direction, the active region 411 is reduced by an area equivalent to the temperature sensor 91. However, in this embodiment, the temperature sensor 91 does not overlap with the conductive spacer 70 in the Z direction. This makes it possible to prevent the active region 411 from being reduced by an area equivalent to the temperature sensor 91. In other words, it is now possible to both arrange the temperature sensor 91 in the outer periphery region 412 and increase the area of ​​the active region 411 without providing a special structure for preventing the influence of the electric field caused by the voltage-resistant structure 413.

[0085] The semiconductor device 20 has a plurality of pads 44 arranged on the outer periphery region 412. The plurality of pads 44 are arranged apart from the conductive spacer 70 in the Y direction. The plurality of pads 44 are arranged with gaps between them in the X direction. A temperature sensor 91 is arranged between two adjacent pads 44. The active region 411 can be expanded to a region adjacent to the pads 44.

[0086] The active area 411 has a central active area 411a, a right end active area 411b, and a left end active area 411c. The central active area 411a is arranged alongside the multiple pads 44 in the Y direction. The right end active area 411b is continuous with the right end of the central active area 411a on the pad 44 side. The left end active area 411c is continuous with the left end of the right end active area 411b on the pad 44 side. The active area 411 can be expanded to the central active area 411a, the right end active area 411b, and the left end active area 411c. The active area 411 can be expanded.

[0087] The power control unit 4 includes the semiconductor device 20 described above and a control device 13. The control device 13 detects whether or not there is an abnormality in the cooling system 140 that cools the semiconductor substrate 41, based on the temperature detected by the temperature sensor 91. The power control unit 4 also achieves the same effect.

[0088] The control device 13 has a memory unit 17, a temperature acquisition unit 16A, a temperature comparison unit 16B, and an abnormality detection unit 16C. The memory unit 17 stores an estimated temperature having a predetermined temperature range that is expected to be detected by the temperature sensor 91 when the refrigerant flows normally through the cooling system 140. The temperature acquisition unit 16A acquires an actual temperature, which is the actual temperature of the semiconductor substrate 41 detected by the temperature sensor 91. The temperature comparison unit 16B compares the actual temperature of the semiconductor substrate 41 with the estimated temperature. The abnormality detection unit 16C detects that there is an abnormality in the cooling system 140 when the actual temperature is outside the estimated range. An abnormality in the cooling system 140 can be detected based on the temperature detected by the temperature sensor 91.

[0089] Second embodiment Specific embodiments of the second to fifth embodiments will be described below. In addition, in Figs. 9 to 12, the breakdown voltage structure 413 and the gate wiring 46 in the semiconductor substrate 41 are omitted. Fig. 9 is a plan view showing the semiconductor substrate 41 according to the second embodiment. In the second embodiment, the active region 411 does not have the right end active region 411b and the left end active region 411c, but only has the central active region 411a. This also achieves the same effects as the first embodiment. In addition, the semiconductor device 20 does not need to have the current sense 94.

[0090] Third embodiment 10 is a plan view showing a semiconductor substrate 41 according to the third embodiment. In the third embodiment, the arrangement of the temperature sensor 91 is changed from that of the second embodiment. In the third embodiment, the temperature sensor 91 is provided adjacent to one of the five pads 44, which is provided at the end in the X direction, on the right side in the X direction. As an example, the temperature sensor 91 is provided adjacent to the cathode potential detection pad 44K. As another example, the temperature sensor 91 may be provided adjacent to the Kelvin source pad 44KS. This also provides the same effects as the first embodiment.

[0091] (Fourth embodiment) FIG. 11 is a plan view showing a semiconductor substrate 41 according to the fourth embodiment. In FIG. 11, five pads 44 are provided close to the end in the X direction. As an example, when the five pads 44 are provided close to the left end, the active region 411 has a central active region 411a and a right end active region 411b. The temperature sensor 91 is provided between two pads 44 or adjacent to the endmost part of the five pads 44 in the X direction. In particular, if the temperature sensor 91 is provided between two pads 44, the range of the right end active region 411b is not narrowed. The active region 411 can be expanded.

[0092] Fifth embodiment 12 is a plan view showing a semiconductor substrate 41 according to the fifth embodiment. The fifth embodiment has four pads 44. The number of pads 44 is not limited to five. This also provides the same effects as the first embodiment.

[0093] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, although various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more than one, or less than one element are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0094] 13 control device, 140 cooling system, 16A temperature acquisition section, 16B temperature comparison section, 16C abnormality detection section, 17 memory section, 20 semiconductor device, 41 semiconductor substrate, 411 active area, 411a main area, 411b, 411c extension area, 412 outer periphery area, 413 pressure resistant structure, 41a one surface, 44 pad, 70 conductive spacer, 91 temperature sense, X second direction, Y first direction, Z plate thickness direction.

Claims

1. A semiconductor device (20) comprising: a semiconductor substrate (41) having an active region (411) which is an element formation region; and an outer periphery region (412) which surrounds the active region in a plan view in a plate thickness direction (Z) and in which a voltage-resistant structure (413) is formed; and a temperature sensor (91) which detects the temperature of the semiconductor substrate in the outer periphery region, the semiconductor substrate (20) being electrically connected to a control device (13) which detects whether or not there is an abnormality in a cooling system (140) which cools the semiconductor substrate based on the temperature detected by the temperature sensor, a conductive spacer (70) disposed on the active area on one side (41a) of the semiconductor substrate; The semiconductor device includes a temperature sensor disposed so as not to overlap with the conductive spacer in the plate thickness direction and closer to the center of the semiconductor substrate than the voltage-resistant structure in a direction perpendicular to the plate thickness direction.

2. a plurality of pads (44) which are electrodes for signals and are arranged on the outer peripheral region on the one surface; The pads are spaced apart from the conductive spacer in a first direction (Y) that is one of the orthogonal directions; The pads are arranged with gaps between them in a second direction (X) different from the first direction among the orthogonal directions, 2. The semiconductor device according to claim 1, wherein the temperature sensor is disposed between two of the pads or adjacent to the most extreme pad in the second direction.

3. 3. The semiconductor device according to claim 2, wherein the active region has a main region (411a) arranged in parallel with the plurality of pads in the first direction, and extension regions (411b, 411c) that are smaller in area than the main region in the planar view, are connected to an end of the main region that is located on the pad side, and are arranged in parallel with the pads in the second direction.

4. A semiconductor substrate (41) having an active region (411) in which an element is formed, and an outer peripheral region (412) surrounding the active region in a plan view in the thickness direction and in which a breakdown voltage structure (413) is formed; a conductive spacer (70) disposed on one side of the semiconductor substrate over the active area; a temperature sensor (91) for detecting a temperature of the semiconductor substrate in the peripheral region; a control device (13) that detects whether or not there is an abnormality in a cooling system (140) that cools the semiconductor substrate based on the detected temperature detected by the temperature sensor; The power control unit has a temperature sensor disposed so as not to overlap with the conductive spacer in the plate thickness direction and closer to the center of the semiconductor substrate than the voltage-resistant structure in a direction perpendicular to the plate thickness direction.

5. The control device includes: a memory unit (17) storing an estimated temperature of the semiconductor substrate having a predetermined temperature range that is estimated to be detected by the temperature sensor when a coolant flows normally through the cooling system; a temperature acquisition unit (16A) for acquiring an actual temperature, which is an actual temperature of the semiconductor substrate detected by the temperature sensor; A temperature comparison unit (16B) that compares the actual temperature with the estimated temperature; 5. The power control unit according to claim 4, further comprising an abnormality detection section (16C) that detects that there is an abnormality in the cooling system when the actual temperature is outside the range of the assumed temperature.

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