Photodetector

Abstract

To provide a photodetector capable of improving charge conversion efficiency.SOLUTION: A photodetector includes a photoelectric conversion element disposed inside a first substrate for converting light into an electric charge, a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element, a conductor electrically connected to a side of the floating diffusion, and an amplifying transistor having a gate electrode including the conductor.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a light detection device. [Background technology]

[0002] Patent Document 1 discloses an imaging element. This imaging element includes a first semiconductor substrate and a second semiconductor substrate stacked on the first semiconductor substrate. A photoelectric conversion unit that converts light into electric charges and a charge storage unit that stores the electric charges transferred from the photoelectric conversion unit are disposed on the first semiconductor substrate. An amplification transistor is disposed on the second semiconductor substrate. The amplification transistor generates a signal according to the level of the electric charges stored in the charge storage unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. WO2020 / 189534A1 Summary of the Invention [Problem to be solved by the invention]

[0004] In the image sensor disclosed in the above Patent Document 1, the charge holding portion is electrically connected to the gate electrode of the amplifying transistor through wiring formed on the first semiconductor substrate side, contact hole wiring penetrating the second semiconductor substrate, etc. In other words, the length of the wiring path from the charge holding portion to the gate electrode of the amplifying transistor becomes long. In an image sensor configured in this manner, the parasitic capacitance value increases with an increase in the wiring path length, which increases random noise and makes it difficult to obtain a sufficient charge conversion efficiency. Therefore, there has been a demand for the development of a photodetector device that can improve the charge conversion efficiency. [Means for solving the problem]

[0005] The photodetection device according to the first embodiment of the present disclosure includes a photoelectric conversion element disposed inside a first substrate for converting light into an electric charge, a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element, a conductor electrically connected to a side of the floating diffusion, and an amplifying transistor having a gate electrode including the conductor.

[0006] In a photodetector according to a second embodiment of the present disclosure, in the photodetector according to the first embodiment, the conductor is formed integrally or integrally with the gate electrode.

[0007] A photodetector according to a third embodiment of the present disclosure is the photodetector according to the first embodiment, further comprising a transfer transistor, one of a pair of main electrodes being electrically connected to the photoelectric conversion element and the other being electrically connected to the floating diffusion. The photoelectric conversion element and the transfer transistor constitute a pixel. A plurality of pixels are arranged in a first direction and a second direction intersecting the first direction. In the first substrate, a pixel isolation region is disposed around at least the side surface of the photoelectric conversion element of each pixel, electrically or optically isolating adjacent pixels. The conductor is formed as a shared wiring that electrically connects the floating diffusions disposed in each of a plurality of adjacent pixels.

[0008] In a photodetection device according to a fourth embodiment of the present disclosure, in the photodetection device according to the third embodiment, when viewed from the direction of incidence of light or the side opposite to the direction of incidence of light, the conductor is arranged to overlap the pixel isolation region.

[0009] In a photodetection device according to a fifth embodiment of the present disclosure, in the photodetection device according to the third embodiment, when viewed from the direction of incidence of light or the side opposite to the direction of incidence of light, the amplification transistor is arranged to overlap the pixel isolation region.

[0010] The photodetection device according to the sixth embodiment of the present disclosure comprises a photoelectric conversion element disposed within a first substrate for converting light into an electric charge, a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element, a pixel isolation region disposed between the photoelectric conversion element and another photoelectric conversion element adjacent to the photoelectric conversion element for electrically or optically isolating the photoelectric conversion element from the other photoelectric conversion elements, a conductor disposed overlapping the pixel isolation region and electrically connected to the floating diffusion, and a reset transistor having a first main electrode of a pair of main electrodes electrically connected to the conductor and a second main electrode of the other main electrode electrically connected to a power supply voltage.

[0011] A photodetector according to a seventh embodiment of the present disclosure is the photodetector according to the sixth embodiment, further comprising a floating diffusion conversion gain switching transistor in which a third main electrode of one of the pair of main electrodes is electrically connected to a conductor and a fourth main electrode of the other is electrically connected to a first main electrode of the reset transistor. The first main electrode of the reset transistor is electrically connected to the conductor via the floating diffusion conversion gain switching transistor. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic system configuration diagram of a photodetector according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic exploded plan view of the photodetector shown in FIG. [Diagram 3] FIG. 3 is a circuit configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. [Figure 4] FIG. 4 is a plan view of the pixel and pixel circuit of the photodetector shown in FIG. 1 on a first substrate. [Diagram 5] FIG. 5 is a plan view of the pixels and pixel circuits of the photodetector shown in FIG. 1 on a second substrate. [Figure 6]6 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. 4 in a first base body (a cross-sectional view taken along the line AA shown in FIG. 4). [Figure 7] 7 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. 4 on the first base and the second base (a cross-sectional view taken along the BB cutting line shown in FIG. 4 and the CC cutting line shown in FIG. 5). [Figure 8] FIG. 8 is a first process cross-sectional view (a process cross-sectional view taken along the AA cutting line shown in FIG. 4) illustrating the method for manufacturing the photodetector according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view of the second step. [Figure 10] FIG. 10 is a cross-sectional view of the third step. [Figure 11] FIG. 11 is a cross-sectional view of the fourth step. [Figure 12] FIG. 12 is a cross-sectional view of the fifth step. [Figure 13] FIG. 13 is a cross-sectional view of the sixth step. [Figure 14] FIG. 14 is a cross-sectional view of the seventh step. [Figure 15] FIG. 15 is a cross-sectional view of the eighth step. [Figure 16] FIG. 16 is a cross-sectional view of the ninth step. [Figure 17] FIG. 17 is a cross-sectional view of the tenth step. [Figure 18] FIG. 18 is a cross-sectional view of the 11th step. [Figure 19] FIG. 19 is a cross-sectional view of the twelfth step. [Figure 20] FIG. 20 is a cross-sectional view of the thirteenth step. [Figure 21] FIG. 21 is a cross-sectional view of the 14th step. [Figure 22] FIG. 22 is a cross-sectional view of the 15th step. [Figure 23] FIG. 23 is a cross-sectional view of the 16th step. [Figure 24] FIG. 24 is a cross-sectional view of the 17th step. [Diagram 25]FIG. 25 is a cross-sectional view of the 18th step. [Figure 26] FIG. 26 is a cross-sectional view of the 19th step. [Figure 27] FIG. 27 is a cross-sectional view of the 20th step. [Figure 28] FIG. 28 is a cross-sectional view of the 21st step. [Figure 29] FIG. 29 is a cross-sectional view of the 22nd step. [Diagram 30] FIG. 30 is a cross-sectional view of the 23rd step. [Diagram 31] FIG. 31 is a cross-sectional view of the 24th step. [Diagram 32] FIG. 32 is a cross-sectional view of the 25th step. [Diagram 33] FIG. 33 is a cross-sectional view of the 26th step. [Diagram 34] FIG. 34 is a cross-sectional configuration diagram corresponding to FIG. 6 of a pixel and a pixel circuit of a photodetector according to the second embodiment of the present disclosure. [Diagram 35] FIG. 35 is a cross-sectional configuration diagram corresponding to FIG. 6 of a pixel and a pixel circuit of a photodetector according to a third embodiment of the present disclosure. [Diagram 36] FIG. 36 is a cross-sectional configuration diagram corresponding to FIG. 6 of a pixel and a pixel circuit of a photodetector according to a fourth embodiment of the present disclosure. [Figure 37] FIG. 37 is a plan configuration diagram of a pixel and a pixel circuit of a photodetector according to a fifth embodiment of the present disclosure, corresponding to FIG. [Figure 38] FIG. 38 is a plan configuration diagram of a pixel and a pixel circuit of a photodetector according to the sixth embodiment of the present disclosure, corresponding to FIG. [Figure 39] FIG. 39 is a plan configuration diagram of a pixel and a pixel circuit of a photodetector according to the sixth embodiment, corresponding to FIG. [Diagram 40] FIG. 40 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIGS. 38 and 39 (a cross-sectional view taken along the line DD shown in FIGS. 38 and 39). [Diagram 41] FIG. 41 is a circuit configuration diagram of a pixel and a pixel circuit of a photodetector according to the seventh embodiment of the present disclosure, corresponding to FIG. [Diagram 42] FIG. 42 is a plan view showing the configuration of the pixels and pixel circuits of the photodetector shown in FIG. 41 on a first base. [Diagram 43] 43 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. 42 in a first base body (a cross-sectional view taken along the E-E line shown in FIG. 42). [Diagram 44] FIG. 44 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. 42 in a first base body (a cross-sectional view taken along the FF cutting line shown in FIG. 42). [Diagram 45] FIG. 45 is a plan configuration diagram of pixels and pixel circuits of a photodetector according to the eighth embodiment of the present disclosure, on a first base. [Figure 46] FIG. 46 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. 45 in a first base body (a cross-sectional view taken along line GG shown in FIG. 45). [Figure 47] FIG. 47 is a cross-sectional configuration diagram of the pixel and pixel circuit of the photodetector shown in FIG. 45 in a first base body (a cross-sectional view taken along the HH cutting line shown in FIG. 45). [Figure 48] FIG. 48 is a cross-sectional configuration diagram (corresponding to the cross-sectional view taken along the E-E line shown in FIG. 42) of a pixel and a pixel circuit of a photodetector according to a ninth embodiment of the present disclosure in a first base body. [Figure 49] FIG. 49 is a cross-sectional configuration diagram (corresponding to the cross-sectional view taken along line FF shown in FIG. 42) of the pixel and pixel circuit of the photodetector according to the ninth embodiment in a first base body. [Figure 50] FIG. 50 is a plan configuration diagram of pixels and pixel circuits of a photodetector according to a tenth embodiment of the present disclosure, on a first base. [Figure 51] FIG. 51 is a plan configuration diagram of pixels and pixel circuits of a photodetector according to an eleventh embodiment of the present disclosure, on a first base. [Figure 52] FIG. 52 is a block diagram showing an example of a schematic configuration of a vehicle control system. [Diagram 53]FIG. 53 is an explanatory diagram showing an example of the installation positions of the outside-of-vehicle information detection unit and the imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First embodiment The first embodiment describes a first example in which the present technology is applied to a photodetector. In the present technology, the photodetector is constructed by a solid-state imaging device or includes a solid-state imaging device. The first embodiment describes the overall configuration of the photodetector, the configuration of a pixel, and the configuration of a pixel circuit. Furthermore, the first embodiment describes a manufacturing method of the photodetector. 2. Second embodiment The second embodiment describes a second example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. In particular, the second embodiment changes the connection structure between the amplification transistor and the reset transistor of the pixel circuit. 3. Third embodiment The third embodiment describes a third example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. In particular, the third embodiment changes the structure of the amplifying transistor of the pixel circuit. 4. Fourth embodiment The fourth embodiment describes a fourth example in which the configuration of the base on which the pixels and pixel circuits are disposed is changed in the photodetector according to the first embodiment. 5. Fifth embodiment The fifth embodiment describes a fifth example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. 6. Sixth embodiment The sixth embodiment describes a sixth example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. 7. Seventh embodiment The seventh embodiment describes a seventh example in which the configuration of a pixel circuit is changed in the photodetector according to the first embodiment. In particular, the seventh embodiment changes the connection structure between the amplification transistor and the reset transistor of the pixel circuit. 8. Eighth embodiment The eighth embodiment describes an eighth example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the eighth embodiment changes the structure of the conductor that realizes the connection structure. 9. Ninth embodiment The ninth embodiment describes a ninth example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the ninth embodiment changes the structure of the conductor that realizes the connection structure. 10. Tenth embodiment The tenth embodiment describes a tenth example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the tenth embodiment changes the connection structure between the amplification transistor and the reset transistor of the pixel circuit. 11. Eleventh embodiment The eleventh embodiment describes an eleventh example in which the configuration of a pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the eleventh embodiment changes the connection structure between the amplification transistor and the reset transistor of the pixel circuit. 12. Mobile application examples In this application example, an example in which the present technology is applied to a vehicle control system, which is an example of a mobile body control system, will be described. 13. Other embodiments

[0014] <1. First embodiment> A light detection device 1 according to a first embodiment of the present disclosure and a method for manufacturing the light detection device 1 will be described with reference to FIGS.

[0015] Here, the arrow X direction shown in the drawings indicates one planar direction of the photodetector 1 placed on a flat surface for the sake of convenience. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates the upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly coincide with the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are shown for the sake of convenience in order to facilitate understanding of the description, and are not intended to limit the directions of the present technology.

[0016] [Configuration of photodetector 1] (1) Overall configuration of the photodetector 1 Fig. 1 shows an example of a system configuration of a photodetector 1 according to a first embodiment. The photodetector 1 is constructed by or including a solid-state imaging device. Here, the photodetector 1 is constructed as a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device. The solid-state imaging device detects light L (see Fig. 6) incident from the outside, converts the detected light L into electric charges, and generates an image such as a still image or a video based on the converted electric charges.

[0017] The photodetector 1 includes a pixel region (pixel array portion) 100 having a plurality of pixels 10 regularly arranged two-dimensionally within a plane in the directions of the arrows X and Y, and peripheral circuits.

[0018] As will be described later, the pixel 10 includes a photoelectric conversion element PD (see FIG. 3) and a transfer transistor TR (see FIG. 3). The photoelectric conversion element PD is formed of, for example, a photodiode. The photoelectric conversion element PD converts light L into electric charges. The transfer transistor TR transfers the electric charges converted by the photoelectric conversion element PD. In addition, a pixel circuit 20 (see FIG. 3) is electrically connected to the pixel 10. In the pixel circuit 20, the charge converted in the pixel 10 is read out.

[0019] The peripheral circuits are constructed to include a vertical drive circuit VD, a column signal processing circuit CS, a horizontal drive circuit HD, an output circuit Out, a control circuit CC, and the like.

[0020] The control circuit CC receives an input clock and data instructing the operation mode etc., and outputs data such as internal information of the photodetector 1. That is, the control circuit CC generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit VD, the column signal processing circuit CS, the horizontal drive circuit HD etc., based on a vertical synchronizing signal, a horizontal synchronizing signal and a master clock. These signals are then input to the vertical drive circuit VD, the column signal processing circuit CS, the horizontal drive circuit HD etc.

[0021] The vertical drive circuit VD is composed of, for example, a shift register. The vertical drive circuit VD selects a pixel drive line Ld and supplies a pulse for driving the pixel 10 to the selected pixel drive line Ld. The pixels 10 are driven row by row. That is, the vertical drive circuit VD sequentially selects and scans each pixel 10 in the pixel region 100 in the vertical direction row by row. A signal charge generated in the photoelectric conversion element PD of each pixel 10 according to the amount of light received is supplied to the column signal processing circuit CS as a pixel signal through the vertical signal line Lv.

[0022] The column signal processing circuit CS is arranged, for example, for each column of the pixels 10. In the column signal processing circuit CS, signal processing such as noise removal is performed for each pixel column on signals output from one row of the pixels 10. That is, the column signal processing circuit CS performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels 10, signal amplification, AD (Analog-to-Digital) conversion, etc. At the output stage of the column signal processing circuit CS, a horizontal selection switch (not shown) is connected between the output stage and the horizontal signal line Lh.

[0023] The horizontal driving circuit HD is formed of, for example, a shift register. The horizontal driving circuit HD sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits CS in turn, and outputs pixel signals from each of the column signal processing circuits CS to the horizontal signal line Lh.

[0024] The output circuit Out processes and outputs signals sequentially supplied from each of the column signal processing circuits CS through the horizontal signal line Lh. For example, the output circuit Out may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal In exchanges signals between the photodetector 1 and the outside.

[0025] (2) Configuration of the photodetector 1 FIG. 2 shows an example of a schematic exploded planar configuration of the photodetector 1 shown in FIG. The light detection device 1 has a three-layer structure in which a first substrate 1A, a second substrate 1B, and a third substrate 1C are stacked and bonded together. Here, the third substrate 1C, the second substrate 1B, and the first substrate 1A are stacked in this order in the direction of the arrow Z. In the first embodiment and the second to fourth and sixth embodiments described later, the light detection device 1 has a three-layer structure. In the fifth, seventh to eleventh embodiments described later, the light detection device 1 has a two-layer structure in which the first base 1A and the second base 1B are combined into one base.

[0026] The first base 1A is formed in a rectangular shape when viewed in the direction of the arrow Z or the direction opposite to the direction of the arrow Z (hereinafter simply referred to as "in a plan view"). To explain in detail, the first base 1A is formed in a square shape here. The first base 1A includes a semiconductor substrate (see reference numeral 30 in Figs. 5 and 6) made of, for example, single crystal silicon. A photoelectric conversion element PD and a transfer transistor TR constituting a pixel 10 are disposed on the semiconductor substrate of the first base body 1A. A pixel region 100 is disposed over substantially the entire area of ​​the first base body 1A. As described above, a plurality of pixels 10 are arranged in the pixel region 100. In other words, the first base body 1A constitutes a light detection surface as an imaging surface for capturing an image.

[0027] The semiconductor substrate of the first base body 1A further includes at least some of pixel transistors (not shown) that constitute the pixel circuit 20. In the first embodiment, among the pixel transistors, the amplifier transistor AMP and the reset transistor RST (see FIG. 3) are provided on the first base body 1A.

[0028] The second base 1B is formed in a rectangular shape similar to the first base 1A in plan view, and is formed to have a planar size similar to that of the first base 1A. The second base 1B includes a semiconductor substrate (see reference numeral 40 in FIG. 7) made of, for example, single crystal silicon, similar to the first base 1A.

[0029] The pixel transistors other than the amplification transistor AMP and the reset transistor RST that constitute the pixel circuit 20 are disposed on the semiconductor substrate of the second base 1B. In the first embodiment, among the pixel transistors, the selection transistor SEL (see FIG. 3) is disposed on the second base 1B. When the pixel circuit 20 is constructed including a floating diffusion conversion gain switching transistor (hereinafter simply referred to as an "FD conversion gain switching transistor") FDG, the selection transistor SEL and the FD conversion gain switching transistor FDG are disposed on the second base 1B. The FD conversion gain switching transistor FDG will be described in a seventh embodiment described later (see FIG. 41).

[0030] In particular, although there is no limitation on the number of pixels 10, in the first embodiment, one pixel circuit 20 is provided for four pixels 10. The configuration of a plurality of pixel transistors that constitute the pixel circuit 20 will be described later. The second base 1B is also provided with pixel drive wiring Ld that overlaps the pixel region 100 in a plan view and extends through the pixel region 100 in the X direction and vertical signal lines Lv that extend in the Y direction.

[0031] In the case of a photodetector 1 having a two-layer structure, the pixel circuit 20 is disposed on a substrate that combines the first substrate 1A and the second substrate 1B into one substrate.

[0032] The third base 1C is formed in a rectangular shape in plan view similar to that of the first base 1A, and is formed to have a planar size similar to that of the first base 1A. The third base 1C includes a semiconductor substrate (illustration and description of the cross-sectional structure are omitted) made of, for example, single crystal silicon, similar to the first base 1A. Peripheral circuits are disposed on the semiconductor substrate of the third base body 1C, and as described above, the peripheral circuits include the vertical drive circuit VD, the column signal processing circuit CS, the horizontal drive circuit HD, the output circuit Out, and the control circuit CC.

[0033] In the first embodiment, each circuit of the peripheral circuit is a logic circuit. The logic circuit is constructed to include one or more semiconductor elements selected from a transistor, a capacitor, and a resistor. An insulated gate field effect transistor (IGFET) is used as the transistor. A low resistance layer formed by using a salicide (self-aligned silicide) process of, for example, CoSi2, NiSi, etc. is formed on the surface of at least a pair of main electrodes of the transistor. The resistance value of the low resistance layer is smaller than the resistance value of the semiconductor layer formed by the n-type semiconductor region.

[0034] (3) Circuit configuration of pixel 10 and pixel circuit 20 FIG. 3 shows an example of a circuit configuration of the pixel 10 and the pixel circuit 20 of the photodetector 1. As shown in FIG. In the first embodiment, four pixels 10 are electrically connected to one pixel circuit 20, and the four pixels 10 share one pixel circuit 20. That is, the electric charges converted from the light L in each of the four pixels 10 are read out in the one pixel circuit 20.

[0035] The pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR, and is configured as a series circuit of the two. More specifically, the photoelectric conversion element PD is constituted by a photodiode, which has an anode region and a cathode region. On the other hand, the transfer transistor TR is an IGFET, which includes a pair of main electrodes (a source region and a drain region) and a gate electrode. The anode region of the photoelectric conversion element PD is electrically connected to a reference voltage GND, and the cathode region is electrically connected to one of the main electrodes of the transfer transistor TR. The other main electrode of the transfer transistor TR is electrically connected to one end of the floating diffusion FD. A control signal for controlling the conduction or non-conduction is input to the gate electrode.

[0036] As described above, four pixels 10 are disposed for one pixel circuit 20. For this reason, the photoelectric conversion element PD and transfer transistor TR of each of the four pixels 10 are distinguished from one another by adding an identification number 1, 2, 3, or 4 to the end of the reference numerals of the components within the pixel 10. For example, one of the four pixels 10 is configured with a photoelectric conversion element PD1 and a transfer transistor TR1. In addition, when there is no need to distinguish between them, no identification number is given.

[0037] Although a detailed structure will be described later, in the first embodiment, the transfer transistor TR is configured as a vertical transistor, that is, the transfer transistor TR is configured as a vertical IGFET. The transfer transistor TR corresponds to a "transfer transistor" according to the present technology.

[0038] The pixel circuit 20 is constructed of a plurality of pixel transistors. Here, the pixel transistors include a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. Each of the pixel transistors is constructed of a lateral IGFET.

[0039] One main electrode (for example, a source region) of the reset transistor RST is electrically connected to the other end of the floating diffusion FD, and the other main electrode is electrically connected to a power supply voltage VDD. A reset signal is input to the gate electrode. When the reset transistor RST becomes conductive, it resets the floating diffusion FD to a potential equivalent to the power supply voltage VDD.

[0040] One main electrode of the amplification transistor AMP is electrically connected to one main electrode of the selection transistor SEL, and the other main electrode is electrically connected to a power supply voltage VDD. One main electrode of the reset transistor RST and the other end of the floating diffusion FD are electrically connected to the gate electrode. The amplifier transistor AMP constitutes a source follower type amplifier. In other words, the amplifier transistor AMP generates a pixel signal according to the charge transferred through the floating diffusion FD.

[0041] The other main electrode of the selection transistor SEL is electrically connected to the vertical signal line Lv. A selection signal is input to the gate electrode. The selection transistor SEL outputs the generated pixel signal to a vertical signal line Lv.

[0042] The pixel circuit 20 may include an FD conversion gain switching transistor FDG. In this case, one main electrode of the FD conversion gain switching transistor FDG is electrically connected to the floating diffusion FD, and the other main electrode is electrically connected to one main electrode (for example, a source region) of the reset transistor RST. A detailed configuration will be described in the seventh embodiment. Furthermore, one pixel circuit 20 may be provided for two pixels 10, eight pixels 10, etc., and the charges from these pixels 10 may be read out in one pixel circuit 20.

[0043] (4) Device configuration of pixel 10 Fig. 4 shows an example of a planar configuration of a first base 1A of a pixel 10 of a photodetector 1. Fig. 5 shows an example of a planar configuration of a second base 1B of a pixel 10 of a photodetector 1. Fig. 6 shows an example of a cross-sectional configuration of a pixel 10 shown in Fig. 4. Fig. 7 shows an example of a cross-sectional configuration of a pixel 10 shown in Figs. 4 and 5.

[0044] As described above, the photodetector 1 according to the first embodiment has a three-layer structure. The pixels 10 are disposed on the semiconductor substrate 30 forming the first base 1A that constitutes the three-layer structure. The pixel circuits 20 are disposed on the semiconductor substrate 30 forming the first base 1A and the semiconductor substrate 40 forming the second base 1B.

[0045] 4, 6, and 7, the pixel 10 is formed in a square shape in plan view with the sides in the directions of arrow X and Y being equal in length. A pixel isolation region 31 is disposed around the side surfaces of the pixel 10. The planar shape of the pixel 10 is not limited to a square shape, and may be, for example, a rectangular shape.

[0046] In the first embodiment, the pixel isolation region 31 includes two types of pixel isolation region 31A and pixel isolation region 31B. The pixel isolation region 31A is configured to surround at least the side surfaces of the photoelectric conversion elements PD, and electrically and optically isolates adjacent pixels 10 from each other. On the other hand, the pixel isolation region 31B is configured to surround the side surfaces of the transistors, specifically, the side surfaces of the amplifying transistor AMP and the reset transistor RST. The pixel isolation region 31B electrically isolates adjacent transistors, etc.

[0047] The pixel isolation region 31A includes a groove 311 and a filler 312. The groove 311 is formed by digging deeply in the thickness direction of the semiconductor substrate 30 from a surface 30B of the semiconductor substrate 30 toward another surface 30A opposite to the surface 30B. Here, surface 30B corresponds to a "first surface" according to the present technology, while surface 30A corresponds to a "second surface" according to the present technology. The grooves 311 extend in the direction of the arrow X and are disposed at regular intervals in the direction of the arrow Y, and also extend in the direction of the arrow Y and are disposed at regular intervals in the direction of the arrow X. That is, in plan view, the grooves 311 are formed in a lattice shape. The filler 312 fills the grooves 311. The filler 312 is made of an insulating material such as SiO2 that can optically and electrically separate adjacent pixels 10.

[0048] The pixel isolation region 31B includes a groove 313 and a filler 314. The groove 313 is formed by digging shallower than the groove 311 in the thickness direction of the semiconductor substrate 30 from the surface 30B of the semiconductor substrate 30 toward the other surface 30A opposite to the surface 30B. The filler 314 is filled in the groove 313. As with the filler 312, the filler 314 is made of an insulating material such as SiO 2 that can separate electrically adjacent transistors, for example.

[0049] The pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR. Fig. 4 shows a unit pixel. That is, as shown in Fig. 3 above, four pixels 10 electrically connected to one pixel circuit 20 are regarded as a unit pixel. The four pixels 10 are two pixels 10 arranged in the direction of the arrow X and two pixels 10 arranged in the direction of the arrow Y. These four pixels 10 are formed in a shape that is linearly symmetrical with respect to a center line (not shown) that passes between adjacent pixels 10.

[0050] (4-1) Photoelectric conversion element PD device configuration Although detailed structural illustration and description are omitted, the photoelectric conversion element PD is disposed inside the semiconductor substrate 30 in a region surrounded by pixel isolation regions 31 in the arrow X and arrow Y directions.

[0051] The photoelectric conversion element PD includes a p-type semiconductor region as an anode region and an n-type semiconductor region as a cathode region. In addition, in a surface portion of the semiconductor substrate 30 along the pixel isolation region 31A of the pixel isolation region 31, a pinning region (not shown) formed of a p-type semiconductor region having a high impurity density is disposed.

[0052] (4-2) Device configuration of transfer transistor TR The transfer transistor TR is disposed on a surface 30B on the arrow Z direction side of the photoelectric conversion element PD in the pixel isolation region 31. Although a detailed structure and description will be omitted, the transfer transistor TR includes a channel formation region, a gate insulating film 321, a gate electrode 322, and a pair of main electrodes (a source region and a drain region) as main components.

[0053] In the first embodiment, the transfer transistor TR is configured as a vertical IGFET. That is, the gate electrode 322 extends in the thickness direction of the semiconductor substrate 30 from the surface 30B of the semiconductor substrate 30 to the photoelectric conversion element PD. The gate insulating film 321 is disposed between the semiconductor substrate 30 and the gate electrode 322.

[0054] The gate insulating film 321 is made of an insulating material such as SiO2. The gate electrode 322 is made of a gate electrode material such as polycrystalline silicon. When polycrystalline silicon is used as the gate electrode material, impurities that reduce the resistance value are added to the polycrystalline silicon.

[0055] One of the pair of main electrodes is electrically connected to the cathode region of the photoelectric conversion element PD, or in other words, the cathode region is used as one of the main electrodes of the transfer transistor TR. On the other hand, the other of the pair of main electrodes is electrically connected to the floating diffusion FD. Similarly, the floating diffusion FD is used as the other main electrode of the transfer transistor TR.

[0056] (4-3) Floating diffusion FD device configuration In a region surrounded by the pixel isolation region 31, a floating diffusion FD is disposed in the vicinity of the gate electrode 322 of the transfer transistor TR. More specifically, the floating diffusions FD of the four pixels 10 are arranged in a concentrated manner in the center of the unit pixel. That is, in the pixel 10 having the photoelectric conversion element PD1 and the transfer transistor TR1, the floating diffusion FD is arranged in the upper right corner. In the pixel 10 having the photoelectric conversion element PD2 and the transfer transistor TR2, the floating diffusion FD is arranged in the upper left corner. In the pixel 10 having the photoelectric conversion element PD3 and the transfer transistor TR3, the floating diffusion FD is arranged in the lower right corner. And, in the pixel 10 having the photoelectric conversion element PD4 and the transfer transistor TR4, the floating diffusion FD is arranged in the lower left corner.

[0057] The floating diffusion FD is disposed on the surface 30B side of the semiconductor substrate 30, and is formed by an n-type semiconductor region 330 having a pn junction depth on the surface 30A side. This n-type semiconductor region 330 is electrically isolated from the semiconductor substrate (p-type semiconductor region) 30 by the pn junction.

[0058] (4-4) Device configuration of conductor 35 In the first embodiment, in the unit pixel, the floating diffusions FD of two pixels 10 adjacent to each other in the direction of the arrow Y are electrically connected to each other through the conductor 35 and are shared. Furthermore, the conductor 35 is electrically connected to a gate electrode 324 of the amplification transistor AMP, which will be described later. As a result, the floating diffusions FD of the four pixels 10 of the unit pixel, including the two pixels 10 adjacent to each other in the direction of the arrow X, are electrically connected to each other and are shared. The conductor 35 is configured as a shared wiring or a shared electrode. In addition, the conductor 35 configures (a part of) the gate electrode 324 of the amplification transistor AMP. The configuration of the amplification transistor AMP will be described later.

[0059] The conductor 35 is disposed so as to overlap the pixel isolation region 31A between two pixels 10 adjacent in the direction of the arrow Y in plan view. In other words, one end of the conductor 35 is electrically connected to a side surface of the floating diffusion FD of one of the two pixels 10 adjacent in the direction of the arrow Y. The other end of the conductor 35 straddles the pixel isolation region 31A and is electrically connected to the side surface of the other floating diffusion FD of the two pixels 10 adjacent in the direction of the arrow Y. The conductor 35 is embedded from the surface 30B toward the surface 30A of the semiconductor substrate 30. The conductor 35 is made of a gate electrode material, such as polycrystalline silicon or a metal such as tungsten (W).

[0060] Here, in the first embodiment, the conductor 35 is formed of, for example, polycrystalline silicon, and the floating diffusion FD is formed of an n-type semiconductor region 330. For this reason, the conductor 35 and the floating diffusion FD are described as separate components. The conductor 35 is disposed in a current path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP. In other words, in the present technology, the conductor 35 or a part thereof constitutes the floating diffusion FD. Also, in the present technology, even when a conductor such as a semiconductor region or a diffusion region that electrically connects the floating diffusion FD and the conductor 35 is formed between them, the conductor constitutes the floating diffusion FD.

[0061] (4-5) Configuration of the amplifier transistor AMP In the first embodiment, the amplifier transistor AMP and the reset transistor RST that constitute the pixel circuit 20 (see FIG. 3) are disposed on a first base body 1A.

[0062] The amplification transistor AMP overlaps, in plan view, a pixel isolation region 31 (pixel isolation region 31A) that separates the four pixels 10 that constitute the unit pixel, and is disposed in the center of the unit pixel. The amplification transistor AMP includes a channel formation region, a gate insulating film 323, a gate electrode 324, and a pair of main electrodes 325 as main components.

[0063] The channel formation region of the amplification transistor AMP is formed in a p-type semiconductor region (p-type well region) 300 disposed in the pixel isolation region 31 on the front surface 30B side of the semiconductor substrate 30. The gate insulating film 323 is formed on the surface of the p-type semiconductor region 300 .

[0064] The gate electrode 324 of the amplification transistor AMP is formed integrally or integrally with the conductor 35 on the front surface 30B side, and is configured to include the conductor 35. Here, the term "integrally formed" is used to mean that the gate electrode 324 and the conductor 35 are each formed of the same conductive material and by the same manufacturing process, and that both are formed continuously. Also, the term "integrally formed" is used to mean that the gate electrode 324 and the conductor 35 are each formed of the same or different conductive materials and by different manufacturing processes, but that both are at least electrically connected.

[0065] Moreover, the conductor 35 extends from the surface 30B to the surface 30A of the semiconductor substrate 30, and therefore constitutes a fin portion of the gate electrode 324 when viewed in the direction of the arrow Y (hereinafter simply referred to as "in a side view"). That is, the amplification transistor AMP has a fin structure capable of increasing the gate capacitance. The gate electrode 324 is formed, for example, from a gate electrode material, similar to the conductor 35 .

[0066] The pair of main electrodes 325 are disposed on both sides of the gate electrode 324 in the gate length direction that coincides with the direction of the arrow Y of the gate electrode 324. The pair of main electrodes 325 are disposed so as to overlap the pixel isolation region 31 in a plan view. The pair of main electrodes 325 are formed of an n-type semiconductor region. That is, the amplification transistor AMP is composed of an n-channel IGFET. Although not shown, a sidewall spacer is formed on the sidewall of the gate electrode 324 of the amplification transistor AMP.

[0067] (4-6) Device configuration of reset transistor RST The reset transistor RST, like the amplification transistor AMP, is arranged so as to overlap the pixel isolation region 31 between the pixels 10 adjacent to each other in the direction of the arrow Y in plan view. The reset transistor RST includes a channel formation region, a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328 as main components.

[0068] The channel formation region of the reset transistor RST is formed in a p-type semiconductor region 300 disposed in the pixel isolation region 31 on the front surface 30B side of the semiconductor substrate 30. The gate insulating film 326 is formed on the surface of the p-type semiconductor region 300 .

[0069] A gate electrode 327 of the reset transistor RST is formed on the gate insulating film 326. Here, the gate electrode 327 is formed from the same conductive material and in the same manufacturing process as the gate electrode 324 of the amplification transistor AMP.

[0070] The pair of main electrodes 328 are disposed on both sides of the gate electrode 327 in the gate length direction that coincides with the direction of the arrow X of the gate electrode 327. The pair of main electrodes 328 are disposed so as to overlap the pixel isolation region 31 in plan view. The pair of main electrodes 328 are formed of an n-type semiconductor region, similar to the pair of main electrodes 325 of the amplification transistor AMP. As with the amplification transistor AMP, although the reference numeral is omitted, a sidewall spacer is formed on the sidewall of the gate electrode 327 of the reset transistor RST.

[0071] (4-7) Device configuration of selection transistor SEL 5 and 7, the selection transistor SEL constituting the pixel circuit 20 (see FIG. 3) is disposed on a second base 1B. The second base 1B includes a semiconductor substrate 40. The second base 1B is laminated on the first base 1A with an insulator (interlayer insulator) 301 disposed on a surface 30B of the semiconductor substrate 30 interposed therebetween.

[0072] The selection transistor SEL is disposed so as to overlap, in a plan view, a region corresponding to two pixels 10 constituting a unit pixel. The selection transistor SEL includes a channel formation region, a gate insulating film 423, a gate electrode 424, and a pair of main electrodes 425 as main components.

[0073] The channel formation region of the selection transistor SEL is formed in the semiconductor substrate (p-type well region) 400 on the front surface 40B side of the semiconductor substrate 40. The gate insulating film 423 is formed on the surface of the semiconductor substrate 400 . The gate electrode 424 is disposed on the gate insulating film 423. The gate electrode 424 is formed of the same gate electrode material as the gate electrode 324 of the amplification transistor AMP. The pair of main electrodes 425 are disposed on both sides of the gate electrode 424 in the gate length direction that coincides with the direction of the arrow X of the gate electrode 424. The pair of main electrodes 425 are formed of an n-type semiconductor region. Although the reference numerals are omitted, a sidewall spacer is formed on the sidewall of the gate electrode 424 of the selection transistor SEL.

[0074] One of a pair of main electrodes 425 of the selection transistor SEL is electrically connected to one of a pair of main electrodes 325 of the amplification transistor AMP through a through-wire 5 or the like. The through-wire 5 is formed to penetrate in the thickness direction through the insulator 401, the semiconductor substrate 40, and the insulator 301 arranged on the front surface 40B of the semiconductor substrate 40 of the second base 1B. In addition, wiring arranged in the third base 1C (not shown) is used for the electrical connection between the two.

[0075] (4-8) Device configuration of connection area 36 4, 6 and 7, in the first embodiment, a connection region 36 is disposed in a region overlapping with the pixel isolation region 31 corresponding to the four corners of the unit pixel. This connection region 36 is electrically connected to the p-type semiconductor region 300. The connection region 36 is formed to have the same conductivity type as the p-type semiconductor region 300, and is formed to have a higher impurity density than the p-type semiconductor region 300. In other words, the connection region 36 is used as a substrate contact region or a well contact region, and is shared by adjacent unit pixels.

[0076] (5) Configuration of Optical Filter 7 In the pixel 10, an optical filter 7 and an optical lens 8 are sequentially disposed on a surface 30A of a semiconductor substrate 30 with a protective film 6 interposed therebetween. The optical filter 7 is formed, for example, as a red color filter that transmits light L in the red light band, a green color filter that transmits light L in the green light band, or a blue color filter that transmits light L in the blue light band. The optical filter 7 may be a filter that transmits near-infrared light. The optical filter 7 is made of, for example, a resin material to which an organic pigment is added. As the resin material, an acrylic resin, a styrene resin, or the like can be used.

[0077] (6) Configuration of Optical Lens 8 The optical lens 8 is disposed for each pixel 10 or for every plurality of pixels 10 in side view. The optical lens 8 is formed in a curved shape protruding in the direction of the arrow Z in side view. The optical lens 8 is formed of, for example, a resin material having optical transparency. Although not shown in the drawings and detailed description, the optical lens 8 may be formed with an anti-reflection film. The optical lenses 8 are connected to adjacent other optical lenses 8, and a plurality of optical lenses 8 are integrally formed. The optical lenses 8 are configured as on-chip lenses.

[0078] Incidentally, illustration and detailed description of the peripheral circuits disposed on the third base 1C of the photodetector 1 will be omitted.

[0079] [Method of manufacturing the photodetector 1] 8 to 33 show an example of process cross sections for explaining each step of the method for manufacturing the photodetector 1. FIG. The method for manufacturing the photodetector 1 according to the first embodiment is mainly a method for manufacturing the amplifying transistor AMP of the pixel 10 in the first base body 1A. The method for manufacturing the photodetector 1 is as follows.

[0080] First, a semiconductor substrate 30 is prepared (see FIG. 8). This semiconductor substrate 30 is in the state of a semiconductor wafer before a dicing process, and has photoelectric conversion elements PD (see FIGS. 6 and 7) formed thereon (not shown).

[0081] As shown in FIG. 8, a mask 371 and a mask 372 are sequentially formed on a surface 30B of a semiconductor substrate 30. The mask 371 is formed as a hard mask. The mask 731 is formed by sequentially stacking a first mask and a second mask. The first mask is made of, for example, SiO2. The second mask is made of, for example, SiN. The mask 372 is made of, for example, photoresist. An opening 372H is formed in the mask 372 in a region where the pixel isolation region 31A is to be formed.

[0082] The mask 371 is patterned using the mask 372, and then the trench 311 is formed from the surface 30B toward the surface 30A of the semiconductor substrate 30 (see FIG. 9). The trench 311 is formed by anisotropic etching such as RIE (Reactive Ion Etching). As shown in FIG. 9, the mask 372 is stripped away.

[0083] 10, a filler 312 is formed on the entire surface 30B of the semiconductor substrate 30, including on the mask 371. The filler 312 is embedded in the grooves 311. The filler 312 is formed by using, for example, a CVD (Chemical Vapor Deposition) method, and is made of SiO2 here. When the filling material 312 is formed, the pixel isolation region 31A is substantially completed by the groove 311 and the filling material 312.

[0084] 11, a mask 373 is formed on the filling material 312. The mask 373 has an opening 373H in a region overlapping a part of the pixel isolation region 31A. The mask 373 is made of, for example, a photoresist.

[0085] 12, a portion of the filling material 312 in the pixel isolation region 31A is removed using a mask 373, and a groove 312H is formed in a portion of the pixel isolation region 31A. To form the groove 312H, for example, anisotropic etching is used. After this, the mask 373 is stripped off.

[0086] 13, a semiconductor layer 300S is formed in the groove 312H. The semiconductor layer 300S is, for example, a single crystal silicon layer grown by epitaxial growth.

[0087] 14, p-type impurities are introduced into the semiconductor layer 300S, and the semiconductor layer 300S forms a p-type semiconductor region 300. The p-type impurities are introduced by using an ion implantation method.

[0088] 15, the unnecessary filling material 312 and the mask 373 are removed from the surface 30B of the semiconductor substrate 30, and the surface 30B is planarized. For example, a chemical mechanical polishing (CMP) method is used for this planarization.

[0089] As shown in FIG. 16, a mask 374 and a mask 375 are sequentially formed on the surface 30B of the semiconductor substrate 30. The mask 374 is formed as a hard mask. The mask 374 is formed by sequentially stacking a first mask and a second mask. The first mask is made of, for example, SiO2. The second mask is made of, for example, SiN. The mask 375 is made of, for example, photoresist. An opening 375H is formed in the mask 375 in a region where the pixel isolation region 31B is to be formed.

[0090] The mask 374 is patterned using the mask 375, and the trench 313 is subsequently formed from the surface 30B toward the surface 30A of the semiconductor substrate 30 (see FIG. 17). The trench 313 is formed by, for example, anisotropic etching. The mask 375 is stripped away, as shown in FIG.

[0091] 18, a filler 314 is formed on the entire surface 30B of the semiconductor substrate 30, including on the mask 374. The filler 314 is embedded in the grooves 313. The filler 314 is formed by using, for example, a CVD method, and is made of SiO2 here. When the filling material 314 is formed, the pixel isolation region 31B is substantially completed by the groove 313 and the filling material 314. Furthermore, when the pixel isolation region 31B is formed, the pixel isolation region 31 consisting of the pixel isolation region 31A and the pixel isolation region 31B is substantially completed.

[0092] 19, the unnecessary filling material 314 is removed from the surface 30B of the semiconductor substrate 30, and the surface 30B is planarized by, for example, the CMP method.

[0093] 20, a mask 376 is formed on the surface 30B of the semiconductor substrate 30. The mask 376 is made of, for example, photoresist. An opening 376H is formed in the mask 376 in a part of the pixel isolation region 31, in a region where the conductor 35 is to be formed. This region where the conductor 35 is to be formed is also a region where the gate electrode 324 of the amplification transistor AMP is to be formed, and is also a region where a shared wiring that connects between the floating diffusions FD is to be formed.

[0094] Using the mask 376, the filling material 312 in the pixel isolation region 31 is dug down to form the trench 35H. The trench 35H is formed by, for example, anisotropic etching. The mask 376 is stripped away, as shown in FIG.

[0095] 22, a gate insulating film 323A is formed on the entire surface 30B of the semiconductor substrate 30. The gate insulating film 323A is formed in at least the formation regions of the amplification transistor AMP, the reset transistor RST, and the transfer transistor TR. The gate insulating film 323A is formed of, for example, SiO2 using, for example, a thermal oxidation method.

[0096] 23, a gate electrode material 324A is formed on a gate insulating film 323A. The gate electrode material 324A is formed of, for example, polycrystalline silicon by, for example, a CVD method. The gate electrode material 324A is formed as a part of the gate electrode 324 of the amplification transistor AMP.

[0097] 24, a mask 377 is formed on the gate electrode material 324A. For example, a photoresist is used for the mask 377. An opening 377H is formed in the mask 377 in a region where the conductor 35 is to be formed.

[0098] Using the mask 377, a portion of the gate electrode material 324A is removed, for example by anisotropic etching. Mask 377 is stripped away, as shown in FIG.

[0099] 26, the gate electrode material 324A is used as a mask to remove the gate insulating film 323A exposed from the gate electrode material 324A. That is, the gate insulating film 323A is patterned. As a result, the gate insulating film 321 of the transfer transistor TR, the gate insulating film 323 of the amplification transistor AMP, and the gate insulating film 326 of the reset transistor RST are each formed from the gate insulating film 323A.

[0100] 27, a gate electrode material 324B is newly formed on the entire surface of the gate electrode material 324A. The gate electrode material 324B is formed of, for example, polycrystalline silicon using, for example, a CVD method. The gate electrode material 324B is formed as a part of each of the gate electrode 322 of the transfer transistor TR, the gate electrode 324 of the amplification transistor AMP, and the gate electrode 327 of the reset transistor RST. Furthermore, when the gate electrode material 324B is formed, the gate electrode material 324B is buried in the trench 35H of the pixel isolation region 31, and the conductor 35 is formed from this gate electrode material 324B.

[0101] 28, unnecessary gate electrode material 324B is removed from surface 30B of semiconductor substrate 30, and the surface of gate electrode material 324B is planarized. For example, CMP is used for this planarization.

[0102] 29, a mask 378 is formed on the gate electrode material 324B. For example, a photoresist is used for the mask 378. In the mask 378, openings 378H are formed in the respective formation regions of the gate electrode 322 of the transfer transistor TR, the gate electrode 324 of the amplifying transistor AMP, and the gate electrode 327 of the reset transistor RST.

[0103] The gate electrode material 324B is patterned using the mask 378. For example, anisotropic etching is used for the patterning. As a result, the gate electrode 322 of the transfer transistor TR, the gate electrode 324 of the amplification transistor AMP, and the gate electrode 327 of the reset transistor RST are each formed from the gate electrode material 324B (see FIG. 30). The mask 378 is stripped away, as shown in FIG.

[0104] 31, sidewall spacers (not shown) are formed on the sidewalls of the gate electrode 322, the gate electrode 324, and the gate electrode 327. The sidewall spacers are formed by depositing an insulator such as SiN by using a CVD method, a sputtering method, or the like, and then performing anisotropic etching by an amount equivalent to the amount of the deposited film.

[0105] Subsequently, a mask 379 is formed on the entire surface 30B of the semiconductor substrate 30 (see FIG. 32). For example, a photoresist is used for the mask 379. In the mask 379, openings 379H are formed in regions for forming the floating diffusion FD, the pair of main electrodes 325 of the amplifying transistor AMP, and the pair of main electrodes 328 of the reset transistor RST. 32, the floating diffusion FD, the pair of main electrodes 325, and the pair of main electrodes 328 are formed using a mask 379. These are formed by introducing n-type impurities using, for example, an ion implantation method. Subsequently, the mask 379 is stripped.

[0106] Here, when the floating diffusion FD is formed, the floating diffusion FD is formed in a state of being electrically connected to the side surface of the conductor 35. Then, the floating diffusions FD of the adjacent pixels 10 are electrically connected to each other with the conductor 35 as a shared wiring. Furthermore, when the pair of main electrodes 325 is formed, the amplification transistor AMP is formed. The amplification transistor AMP is formed as a gate electrode 324 including a conductor 35, and is therefore formed in a fin structure. The gate electrode 324 is electrically connected to the floating diffusion FD with the conductor 35 interposed therebetween. Furthermore, when a floating diffusion FD (n-type semiconductor region 330) is formed, a transfer transistor TR is formed. In addition, when a pair of main electrodes 328 are formed, a reset transistor RST is formed.

[0107] Subsequently, a mask 380 is formed all over the surface 30B of the semiconductor substrate 30. For example, a photoresist is used for the mask 380. An opening 380H is formed in the mask 380 in a region for forming the connection region 36 that overlaps with the pixel isolation region 31 (see FIG. 33). 33, the connection region 36 is formed using a mask 380. The connection region 36 is formed by introducing p-type impurities using, for example, ion implantation. Subsequently, the mask 380 is stripped.

[0108] Subsequently, the insulator 301, the second base 1B, the selection transistor SEL, the insulator 401, the through wiring 5, etc. are formed in sequence, completing the photodetector 1 according to the first embodiment as shown in the above-mentioned FIGS.

[0109] [Effects] As shown in FIGS. 4 to 7, the photodetector 1 according to the first embodiment includes a photoelectric conversion element PD, a floating diffusion FD, a conductor 35, and an amplifying transistor AMP. The photoelectric conversion element PD is disposed inside the first base body 1A and converts light into electric charges. The floating diffusion FD is disposed on the surface 30B of the first base body 1A and is electrically connected to the photoelectric conversion element PD. The conductor 35 is electrically connected to a side of the floating diffusion FD. The amplification transistor AMP has a gate electrode 324 including the conductor 35. In the photodetector 1 configured in this manner, the gate electrode 324 of the amplification transistor AMP is electrically connected to the side surface of the floating diffusion FD through the conductor 35. That is, the length of the wiring path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP can be shortened to the limit. Therefore, the parasitic capacitance value added to the wiring path becomes extremely small, so that random noise can be effectively suppressed. As a result, the charge conversion efficiency from the photoelectric conversion element PD to the pixel circuit 20 can be improved.

[0110] 6 and 7, in the photodetector 1, the conductor 35 is embedded in the semiconductor substrate 30 of the first base 1A from the surface 30B toward the surface 30A. That is, the conductor 35 constitutes a fin portion of the gate electrode 324 extended from the surface 30B toward the surface 30A, and the amplification transistor AMP has a fin structure. In the photodetector 1 configured in this manner, the gate width dimension of the amplification transistor AMP can be increased, thereby improving the current driving capability of the amplification transistor AMP. As a result, the area occupied by the amplification transistor AMP can be reduced, and the area of ​​the pixel 10 can be made smaller.

[0111] In the photodetector 1, as shown in FIGS. 6 and 7, the conductor 35 is formed integrally or integrally with the gate electrode 324 of the amplification transistor AMP. In the photodetector 1 configured in this manner, as described above, the length of the wiring path from the floating diffusion FD to the gate electrode 324 of the amplifying transistor AMP can be shortened to the minimum.

[0112] In the photodetector 1, as shown in FIGS. 4 and 6, the conductor 35 is formed as a shared wiring that electrically connects the floating diffusions FD disposed in each of a plurality of adjacent pixels 10. The photodetector 1 configured in this manner does not require wiring for electrically connecting the multiple floating diffusions FD to each other, a connection region between the wiring and the floating diffusions FD, etc. This allows the area of ​​the pixel 10 to be further reduced.

[0113] Furthermore, in the photodetector 1, as shown in FIGS. 4 and 6, the conductor 35 is disposed so as to overlap the pixel isolation region 31 in a plan view. In the photodetection device 1 configured in this manner, the conductor 35 is arranged utilizing the occupied area of ​​the pixel isolation region 31, so that the occupied area of ​​the pixel 10 can be further reduced compared to the case where the pixel isolation region 31 and the conductor 35 are each arranged in separate regions.

[0114] Furthermore, in the photodetector 1, as shown in FIGS. 4 and 6, the amplification transistor AMP is disposed so as to overlap the pixel isolation region 31 in plan view. In the photodetection device 1 configured in this manner, the amplification transistor AMP is disposed utilizing the occupied area of ​​the pixel isolation region 31, so that the occupied area of ​​the pixel 10 can be further reduced compared to the case where the pixel isolation region 31 and the amplification transistor AMP are disposed in separate regions.

[0115] Furthermore, in the photodetector 1, as shown in FIGS. 4 and 6, the reset transistor RST is disposed so as to overlap the pixel isolation region 31 in plan view. In the photodetection device 1 configured in this manner, the reset transistor RST is disposed utilizing the occupied area of ​​the pixel isolation region 31, so that the occupied area of ​​the pixel 10 can be further reduced compared to a case in which the pixel isolation region 31 and the reset transistor RST are disposed in separate regions.

[0116] <2. Second embodiment> A photodetector 1 according to a second embodiment of the present disclosure will be described with reference to FIG. In the second and subsequent embodiments, components that are the same as or substantially the same as the components of the photodetector 1 according to the first embodiment are given the same reference numerals, and duplicated explanations will be omitted.

[0117] [Device configuration of photodetector 1] FIG. 34 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. As shown in FIG. In the photodetector 1 according to the second embodiment, one main electrode (for example, a source region) 328 of the reset transistor RST is electrically connected to the gate electrode 324 of the amplification transistor AMP through a wiring 302.

[0118] The wiring 302 is disposed in an insulator 301. A wiring (flag wiring) 303 is used for electrical connection between the main electrode 328 and the wiring 302. Similarly, the wiring 303 is also used for electrical connection between the gate electrode 324 and the wiring 302. The wiring 303 is formed of a conductive material such as copper (Cu), polycrystalline silicon (poly-Si), or tungsten.

[0119] The components of the second embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0120] [Effects] According to the photodetector 1 of the second embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the first embodiment.

[0121] In the photodetector 1, one main electrode 328 of the reset transistor RST is electrically connected to the gate electrode 324 of the amplification transistor AMP through a wiring 302, as shown in FIG. In the photodetector 1 configured in this manner, a coupling capacitance of the wiring 302 can be added to the wiring path between one main electrode 328 of the reset transistor RST and the gate electrode 324 of the amplification transistor AMP. This makes it easier to read out the charge converted by the photoelectric conversion element PD in the pixel circuit 20.

[0122] <3. Third embodiment> A photodetector 1 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0123] [Device configuration of photodetector 1] FIG. 35 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. As shown in FIG. In the photodetector 1 according to the third embodiment, the conductor 35 is extended to the channel formation region of the amplification transistor AMP, and the conductor 35 extended to the channel formation region is formed integrally or integrally with the gate electrode 324. In other words, the gate electrode 324 is formed by utilizing the conductor 35. In the third embodiment, since there is no fin portion, the amplification transistor AMP does not have a fin type structure.

[0124] The components of the third embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0125] [Effects] According to the photodetector 1 of the third embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the first embodiment.

[0126] In the photodetector 1, the conductor 35 is extended to the channel formation region of the amplification transistor AMP, and is formed integrally with or integrally formed with the gate electrode 324, as shown in FIG. In the photodetector 1 configured in this manner, the structure and manufacturing method of the gate electrode 324 of the amplifying transistor AMP including the conductor 35 can be simplified.

[0127] <4. Fourth embodiment> A photodetector 1 according to a fourth embodiment of the present disclosure will be described with reference to FIG.

[0128] [Device configuration of photodetector 1] FIG. 36 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. As shown in FIG. In the photo-detecting device 1 according to the fourth embodiment, a p-type semiconductor region 31C is disposed in the pixel isolation region 31 on the front surface 30B side of the semiconductor substrate 30. The p-type semiconductor region 31C is configured as a part of the pixel isolation region 31. A p-type well region 305 is disposed on the surface 30A side of the p-type semiconductor region 300 where the amplifying transistor AMP and the like are disposed. The p-type well region 305 is formed to have the same conductivity type as the p-type semiconductor region 300, is formed to have a high impurity density, and is electrically connected. The p-type well region 305 is formed to have a sheet resistance value lower than that of the p-type semiconductor region 300. That is, in the p-type well region 305, the power supply speed from the connection region 36 can be improved.

[0129] The components of the fourth embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0130] [Effects] According to the photodetector 1 of the fourth embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the first embodiment.

[0131] <5. Fifth embodiment> A photodetector 1 according to a fifth embodiment of the present disclosure will be described with reference to FIG.

[0132] [Device configuration of photodetector 1] FIG. 37 shows an example of the planar configuration of the pixel 10 of the photodetector 1. As shown in FIG. In the photodetector 1 according to the fifth embodiment, a selection transistor SEL is disposed on the front surface 30B of the semiconductor substrate 30 of the first base body 1A, similar to the amplification transistor AMP and the reset transistor RST.

[0133] Like the reset transistor RST, the selection transistor SEL is disposed so as to overlap the pixel isolation region 31 in a plan view. Like the reset transistor RST, the selection transistor SEL includes a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328 as main components.

[0134] Furthermore, in the fifth embodiment, the pixel circuit 20 includes an FD conversion gain switching transistor FDG (see FIG. 41). Like the reset transistor RST, the FD conversion gain switching transistor FDG is disposed so as to overlap the pixel isolation region 31 in a plan view. Also, like the reset transistor RST, the FD conversion gain switching transistor FDG includes a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328 as main components.

[0135] In the fifth embodiment, an amplifier transistor AMP is disposed in the center of a unit pixel. A selection transistor SEL is disposed on the extension of the gate length direction (arrow Y direction) of the amplifier transistor AMP. A reset transistor RST is disposed on one side of the extension of the gate width direction (arrow X direction) of the amplifier transistor AMP, and an FD conversion gain switching transistor FDG is disposed on the other side.

[0136] The components of the fifth embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0137] [Effects] According to the photodetector 1 of the fifth embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the first embodiment.

[0138] 37, in the photodetector 1, the amplifying transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG that constitute the pixel circuit 20 are disposed on the first base 1A. Therefore, the second base 1B shown in FIG. 2 can be combined with the first base 1A to form one base, so that the photodetector 1 can be constructed in a two-layer structure.

[0139] <6. Sixth embodiment> A photodetector 1 according to a sixth embodiment of the present disclosure will be described with reference to FIGS.

[0140] [Device configuration of photodetector 1] Fig. 38 shows an example of a planar configuration of a portion of the pixel 10 and the pixel circuit 20 of the photodetector 1. Fig. 39 shows an example of a planar configuration of another portion of the pixel circuit 20 of the photodetector 1. Fig. 40 shows an example of a cross-sectional configuration of the pixel 10 and the pixel circuit 20 of the photodetector 1.

[0141] In the photodetector 1 according to the sixth embodiment, the amplification transistor AMP constituting the pixel circuit 20 is disposed on a first substrate 1A. The reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG constituting the pixel circuit 20 are disposed on a second substrate 1B.

[0142] The components of the sixth embodiment other than the above components are the same or substantially the same as the components of the photodetector 1 according to the first embodiment or the photodetector 1 according to the second embodiment.

[0143] [Effects] According to the photodetector 1 of the sixth embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the first embodiment.

[0144] <7. Seventh embodiment> A photodetector 1 according to a seventh embodiment of the present disclosure will be described with reference to FIGS. [Circuit configuration of pixel 10 and pixel circuit 20 of photodetector 1] FIG. 41 shows an example of a circuit configuration of the pixel 10 and the pixel circuit 20 of the photodetector 1. As shown in FIG. In comparison with the pixel 10 and pixel circuit 20 of the photodetector 1 according to the first embodiment shown in FIG. 3 described above, the photodetector 1 according to the seventh embodiment further includes an FD conversion gain switching transistor FDG in the pixel circuit 20, as shown in FIG. A detailed explanation will be given. As described above, the FD conversion gain switching transistor FDG is disposed between the floating diffusion FD and the reset transistor RST. One main electrode (e.g., source region) of the FD conversion gain switching transistor FDG is electrically connected to the floating diffusion FD. The other main electrode (e.g., drain region) of the FD conversion gain switching transistor FDG is electrically connected to one main electrode (e.g., source region) of the reset transistor RST. The other main electrode (e.g., drain region) of the reset transistor RST is electrically connected to the power supply voltage VDD.

[0145] [Device configuration of photodetector 1] Fig. 42 shows an example of a planar configuration of the pixels 10 and pixel circuits 20 in the first base 1A of the photodetector 1. Fig. 43 and Fig. 44 each show an example of a cross-sectional configuration of the pixels 10 and pixel circuits 20 of the photodetector 1.

[0146] (1) Device configuration of pixel isolation region 31 Like the pixel isolation region 31 of the photodetection device 1 according to the fourth embodiment, the pixel isolation region 31 of the photodetection device 1 according to the seventh embodiment is configured to include a p-type semiconductor region 31C arranged on the surface 30B side of the semiconductor substrate 30.

[0147] (2) Device configuration of conductor 35 Like the conductor 35 of the photodetector 1 according to the first embodiment, the conductor 35 of the photodetector 1 according to the seventh embodiment is disposed so as to overlap the pixel isolation region 31 in plan view. In the unit pixel, the conductor 35 is electrically connected to the floating diffusions FD of two pixels 10 adjacent in the direction of the arrow X, and is shared by the two pixels 10. In other words, in the unit pixel, the conductor 35 is electrically connected to two transfer transistors TR adjacent in the direction of the arrow X, and is used as a shared wiring for the two transfer transistors TR. In the unit pixel, two conductors 35 are disposed spaced apart in the direction of the arrow Y.

[0148] Like the conductor 35 in the first embodiment, the conductor 35 is embedded in the pixel isolation region 31, and therefore the side surface of the conductor 35 and the side surface of the floating diffusion FD are electrically connected. Here, the floating diffusion FD is formed by an n-type semiconductor region 330. In other words, the n-type semiconductor region 330 is also the main electrode of the transfer transistor TR. Meanwhile, in the seventh embodiment, the conductor 35 is formed by, for example, polycrystalline silicon doped with n-type impurities.

[0149] For this reason, a diffusion region 35n diffused laterally along the surface 30B from the side surface of the conductor 35 is interposed between the side surface of the floating diffusion FD and the side surface of the conductor 35. The diffusion region 35n is of n-type, which is the same conductivity type as the n-type impurity added to the conductor 35 and the floating diffusion FD (n-type semiconductor region 330).

[0150] Furthermore, the conductor 35 is electrically connected to the transfer transistor TR via a floating diffusion FD. When the conductor 35 is made of a metal, the diffusion region 35n is not formed.

[0151] (3) Configuration of the amplifier transistor AMP Like the amplification transistor AMP of the photodetector 1 according to the first embodiment, the amplification transistor AMP of the photodetector 1 according to the seventh embodiment is arranged so as to overlap the pixel isolation region 31 that separates the four pixels 10 constituting the unit pixel in plan view. A more detailed explanation will be given. The amplification transistor AMP is arranged in the center of the unit pixel. In other words, the amplification transistor AMP is formed in a shape sandwiched between two conductors 35 arranged in the direction of the arrow Y.

[0152] The amplification transistor AMP includes a channel formation region, a gate insulating film 323, a gate electrode 324, and a pair of main electrodes 325 as main components.

[0153] Although the reference numeral is omitted, the channel formation region is formed in a surface portion of the p-type semiconductor region 31C in the pixel isolation region 31. Here, impurities for forming a channel are introduced into the surface portion of the p-type semiconductor region 31C.

[0154] The gate insulating film 323 is disposed in the channel formation region. The gate electrode 324 is disposed on the gate insulating film 323. An intermediate portion of the gate electrode 324 in the gate length direction extends in the direction of the arrow Y and in the direction opposite to the direction of the arrow Y, and is formed to overlap the conductor 35 in a plan view. In other words, the gate electrode 324 is formed in a shape that partially protrudes in the gate width direction. In an overlapping region between the extending portion of the gate electrode 324 and the conductor 35, a connection hole 323H is provided in the gate insulating film 323. The gate electrode 324 and the conductor 35 are electrically connected to each other through the connection hole 323H. A pair of main electrodes 325 are disposed on both sides of the gate electrode 324 in the gate length direction, with the gate electrode 324 at the center, so as to overlap the pixel isolation region 31 .

[0155] (4) Device configuration of FD conversion gain switching transistor FDG The FD conversion gain switching transistor FDG is disposed so as to overlap the pixel isolation region 31 from between the pixels 10 adjacent in the arrow X direction to between the unit pixels adjacent in the arrow Y direction in plan view. The FD conversion gain switching transistor FDG includes a channel formation region, a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328 as main components.

[0156] Although the reference numeral is omitted for the channel formation region, it is formed in the surface portion of the p-type semiconductor region 31C of the pixel isolation region 31, similar to the amplifying transistor AMP. The gate insulating film 326 is disposed in the channel forming region. The gate electrode 327 is disposed on the gate insulating film 326. One main electrode 328 extending in the direction of arrow Y is disposed on one side of the gate length direction of the gate electrode 327 with the gate electrode 327 at the center, and the other main electrode 328 extending in the direction of arrow X is disposed on the other side. In other words, the FD conversion gain switching transistor FDG is bent from the direction of arrow X to the direction of arrow Y and is disposed so as to overlap the pixel isolation region 31.

[0157] One of a pair of main electrodes 328 of the FD conversion gain switching transistor FDG (for example, a source region) is electrically connected to the conductor 35. A detailed explanation will be given below. That is, one of the main electrodes (n-type semiconductor region) 328 is electrically connected to a side surface of the conductor 35 via a diffusion region 35n diffused from the side surface of the conductor 35. In other words, the floating diffusion FD and one of the main electrodes 328 of the FD conversion gain switching transistor FDG are electrically connected by the shortest distance through the conductor 35 without using wiring arranged in an upper layer.

[0158] (5) Device configuration of reset transistor RST The reset transistor RST is disposed between unit pixels adjacent to each other in the direction of the arrow Y in plan view, and overlaps with the pixel isolation region 31. The reset transistor RST, like the FD conversion gain switching transistor FDG, includes a channel formation region, a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328 as main components.

[0159] A pair of main electrodes 328 are disposed on both sides of the gate electrode 327 in the gate length direction, with the gate electrode 327 at the center. One main electrode 328 is formed integrally with the other main electrode 328 of the FD conversion gain switching transistor FDG. In other words, one main electrode 328 of the reset transistor RST is electrically connected to the conductor 35 with the FD conversion gain switching transistor FDG interposed therebetween.

[0160] In the seventh embodiment, the pixel circuit 20 includes an FD conversion gain switching transistor FDG. As in the pixel circuit 20 of the first embodiment described above, when the FD conversion gain switching transistor FDG is not included, one main electrode 328 of the reset transistor RST is directly or directly electrically connected to the conductor 35. Here, "directly connected" means that one main electrode 328 and the conductor 35 are electrically connected without an intervening region such as the diffusion region 35n. Also, "directly connected" means that one main electrode 328 and the conductor 35 are electrically connected with an intervening region such as the diffusion region 35n.

[0161] (6) Device configuration of selection transistor SEL The selection transistor SEL is disposed between the pixels 10 adjacent to each other in the direction of the arrow Y in plan view, and is disposed so as to overlap the pixel isolation region 31 . Like the reset transistor RST, the selection transistor SEL includes a channel formation region, a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328 as main components.

[0162] A pair of main electrodes 328 are disposed on both sides in the gate length direction of the gate electrode 327, with the gate electrode 327 at the center. One main electrode 328 is formed integrally with the other main electrode 325 of the amplification transistor AMP.

[0163] Other components of the seventh embodiment than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment. Note that in the seventh embodiment and the eighth and ninth embodiments described below, illustrations and descriptions of the optical filter 7 and the optical lens of the photodetector 1 according to the first embodiment are omitted.

[0164] [Effects] According to the photodetector 1 of the seventh embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the first embodiment.

[0165] As shown in FIGS. 42 to 44, the photodetector 1 further includes a photoelectric conversion element PD, a floating diffusion FD, a conductor 35, and an amplifying transistor AMP. The photoelectric conversion element PD is disposed inside the first base body 1A and converts light into electric charges. The floating diffusion FD is disposed on the surface 30B of the first base body 1A and is electrically connected to the photoelectric conversion element PD. The conductor 35 is electrically connected to the floating diffusion FD. The amplification transistor AMP is disposed such that a part of the gate electrode 324 overlaps with the conductor 35, and the gate electrode 324 is electrically connected to the conductor 35. Here, the gate electrode 324 and the conductor 35 are electrically connected to each other through a connection hole 323H formed in the gate insulating film 323. In the photodetector 1 configured in this manner, the gate electrode 324 of the amplification transistor AMP is electrically connected to the floating diffusion FD via the conductor 35. That is, the length of the wiring path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP can be shortened to the minimum. Therefore, the parasitic capacitance value added to the wiring path becomes extremely small, so that random noise can be effectively suppressed. This allows the charge conversion efficiency from the photoelectric conversion element PD to the pixel circuit 20 to be improved.

[0166] As shown in FIGS. 42 to 44, the photodetector 1 also includes a photoelectric conversion element PD, a floating diffusion FD, a pixel isolation region 31, a conductor 35, and a reset transistor RST. The photoelectric conversion element PD is disposed inside the first substrate 1A and converts light into electric charges. The floating diffusion FD is disposed on the surface 30B of the first substrate 1A and is electrically connected to the photoelectric conversion element PD. The pixel isolation region 31 is disposed between the photoelectric conversion element PD and another photoelectric conversion element PD adjacent to the photoelectric conversion element PD, and electrically or optically isolates the photoelectric conversion element PD from the other photoelectric conversion element PD. The conductor 35 is disposed overlapping the pixel isolation region 31 and is electrically connected to the floating diffusion FD. The reset transistor RST electrically connects one main electrode 328 of a pair of main electrodes 328 to the conductor 35 and electrically connects the other main electrode 328 to a power supply voltage VDD. In the photodetector 1 configured in this manner, one of the main electrodes 328 of the reset transistor RST is electrically connected to the floating diffusion FD via the conductor 35. Here, the floating diffusion FD is electrically connected to the reset transistor RST via the conductor 35 and the FD conversion gain switching transistor FDG. That is, the length of the wiring path from the floating diffusion FD to the reset transistor RST can be shortened to the limit. Therefore, the parasitic capacitance value added to the wiring path becomes extremely small, so that random noise can be effectively suppressed. As a result, the charge conversion efficiency from the photoelectric conversion element PD to the pixel circuit 20 can be improved.

[0167] 43 and 44, in the photodetector 1, the conductor 35 is connected to the FD conversion gain switching transistor FDG or the reset transistor RST via one main electrode 328 and a diffusion region 35n that is diffused from the side surface of the conductor 35 along the surface 30B and has the same conductivity type as the one main electrode 328. Since the one main electrode 328 and the diffusion region 35n are provided, a reliable electrical connection can be achieved.

[0168] <8. Eighth embodiment> The photodetector 1 according to the eighth embodiment of the present disclosure will be described with reference to FIGS. [Device configuration of photodetector 1] Fig. 45 shows an example of a planar configuration of the pixels 10 and pixel circuits 20 in the first base 1A of the photodetector 1. Figs. 46 and 47 each show an example of a cross-sectional configuration of the pixels 10 and pixel circuits 20 of the photodetector 1.

[0169] The photodetector 1 according to the eighth embodiment has a different configuration of the conductor 35 from that of the photodetector 1 according to the seventh embodiment. A detailed explanation will be given. The conductor 35 is formed by an n-type semiconductor region formed from the surface 30B toward the surface 30A of the semiconductor substrate 30, overlapping the pixel isolation region 31. In other words, the conductor 35 is disposed within the semiconductor substrate 30 (first base 1A). The conductor 35 is formed by injecting n-type impurities into the surface portion of the pixel isolation region 31 by, for example, ion implantation, and activating the injected n-type impurities. Since the n-type impurities are isotropically diffused by activation, the conductor 35 also includes a region similar to the diffusion region 35n that diffuses laterally as described above.

[0170] Like the conductor 35 in the seventh embodiment, the conductor 35 is electrically connected to the gate electrode 324 of the amplification transistor AMP through a connection hole 323H formed in the gate insulating film 323.

[0171] In addition, an element isolation region 31D is disposed between the channel formation region of the amplification transistor AMP and the conductor 35. Although the reference numeral is omitted, the element isolation region 31D is formed to include, for example, a groove and an insulating material filled in the groove.

[0172] The components of the eighth embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment.

[0173] [Effects] According to the photodetector 1 of the eighth embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the seventh embodiment.

[0174] <9. Ninth embodiment> A photodetector 1 according to a ninth embodiment of the present disclosure will be described with reference to FIGS. [Device configuration of photodetector 1] 48 and 49 each show an example of a cross-sectional configuration of the pixel 10 and the pixel circuit 20 of the photodetector 1. FIG.

[0175] The photodetector 1 according to the ninth embodiment has a different configuration of the conductor 35 from that of the photodetector 1 according to the seventh embodiment. This will be explained in detail. The conductor 35 is disposed on the surface 30B of the semiconductor substrate 30, overlapping the pixel isolation region 31. The conductor 35 is made of, for example, polycrystalline silicon or a metal. Here, the conductor 35 and the gate electrode 324 of the amplification transistor AMP are each made of the same conductive material and formed by separate manufacturing processes.

[0176] The conductor 35 and the gate electrode 324 of the amplifier transistor AMP may be formed from the same conductive material and in the same manufacturing process. Alternatively, the conductor 35 and the gate electrode 324 of the amplifier transistor AMP may be formed from different conductive materials and in different manufacturing processes.

[0177] The components of the ninth embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment.

[0178] [Effects] According to the photodetector 1 of the ninth embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the seventh embodiment.

[0179] <10. Tenth embodiment> The photodetector 1 according to the tenth embodiment of the present disclosure will be described with reference to FIG. [Device configuration of photodetector 1] FIG. 50 shows an example of a planar configuration of the pixels 10 and pixel circuits 20 of the photodetector 1. As shown in FIG. The photodetector 1 according to the tenth embodiment is configured with two pixels 10 arranged in the direction of the arrow X as unit pixels in the photodetector 1 according to the seventh embodiment. Also, the pixel circuit 20 of the photodetector 1 does not include an FD conversion gain switching transistor FDG, like the pixel circuit 20 of the photodetector 1 according to the first embodiment (see FIG. 3).

[0180] In the photodetection device 1 configured in this manner, similar to the photodetection device 1 of the seventh embodiment, the conductor 35 and the gate electrode 324 of the amplification transistor AMP overlap with and are electrically connected to the pixel isolation region 31. On the other hand, the gate electrode 324 of the amplification transistor AMP and one main electrode 328 of the reset transistor RST are electrically connected to each other through an upper layer wiring 501. The wiring 501 is disposed on the second base 1B, for example, and is made of a metal material.

[0181] The components of the tenth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment.

[0182] [Effects] According to the photodetector 1 of the tenth embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the seventh embodiment. <11. Eleventh embodiment> The photodetector 1 according to the eleventh embodiment of the present disclosure will be described with reference to FIG. [Device configuration of photodetector 1] FIG. 51 shows an example of a planar configuration of the pixels 10 and pixel circuits 20 of the photodetector 1. As shown in FIG. The photodetection device 1 of the eleventh embodiment is the same as the photodetection device 1 of the seventh embodiment in that the conductor 35 and the gate electrode 324 of the amplification transistor AMP overlap with and are electrically connected to the pixel isolation region 31. On the other hand, the gate electrode 324 of the amplification transistor AMP and one main electrode 328 of the FD conversion gain switching transistor FDG are electrically connected to each other through an upper layer wiring 501. The wiring 501 is disposed on the second base 1B, for example, and is made of a metal material.

[0183] The components of the eleventh embodiment other than the above-mentioned components are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment.

[0184] [Effects] According to the photodetector 1 of the eleventh embodiment, it is possible to obtain the same advantageous effects as those obtained by the photodetector 1 of the seventh embodiment.

[0185] <12. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0186] FIG. 52 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0187] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 52, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

[0188] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0189] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0190] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0191] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0192] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0193] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0194] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0195] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0196] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 52, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0197] FIG. 53 is a diagram showing an example of the installation position of the imaging unit 12031.

[0198] In FIG. 53, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0199] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield in the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0200] 53 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0201] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0202] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0203] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0204] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0205] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to realize an imaging unit 12031 that can improve charge conversion efficiency.

[0206] <13. Other embodiments> The present technology is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit and scope of the present technology. For example, in the present technology, among the photodetection devices according to the first to eleventh embodiments, the photodetection devices according to two or more of the embodiments may be combined. As a specific example, the present technology may combine a connection structure between a conductor of a photodetector device according to the first embodiment and a gate electrode of an amplifying transistor with a connection structure between a conductor of a photodetector device according to the seventh embodiment and an FD conversion gain switching transistor.

[0207] The photodetector according to the first embodiment of the present disclosure includes a photoelectric conversion element, a floating diffusion, a conductor, and an amplifying transistor. The photoelectric conversion element is disposed inside the first substrate and converts light into an electric charge. The floating diffusion is disposed on a first surface of the first substrate and is electrically connected to the photoelectric conversion element. The conductor is electrically connected to a side surface of the floating diffusion. The amplifying transistor has a gate electrode including a conductor. According to a photodetector configured in this manner, the wiring path length from the floating diffusion to the gate electrode of the amplifying transistor can be shortened to the minimum possible extent, thereby effectively suppressing random noise and improving charge conversion efficiency.

[0208] In a photodetector according to a second embodiment of the present disclosure, in the photodetector according to the first embodiment, the conductor is formed integrally or integrally with the gate electrode. According to the photodetector configured in this manner, the length of the wiring path from the floating diffusion to the gate electrode of the amplifying transistor can be shortened to the minimum.

[0209] A photodetector according to a third embodiment of the present disclosure is the photodetector according to the first embodiment, further comprising a transfer transistor, one of a pair of main electrodes being electrically connected to the photoelectric conversion element and the other being electrically connected to the floating diffusion. The photoelectric conversion element and the transfer transistor constitute a pixel. A plurality of pixels are arranged in a first direction and a second direction intersecting the first direction. In the first substrate, a pixel isolation region is disposed around at least the side surface of the photoelectric conversion element of each pixel, electrically or optically isolating adjacent pixels. The conductor is formed as a shared wiring that electrically connects the floating diffusions disposed in each of a plurality of adjacent pixels. A photodetector configured in this manner does not require wiring for electrically connecting the floating diffusion, a connection region between this wiring and the floating diffusion, etc. This makes it possible to reduce the area of ​​the pixel.

[0210] In a photodetection device according to a fourth embodiment of the present disclosure, in the photodetection device according to the third embodiment, when viewed from the direction of incidence of light or the side opposite to the direction of incidence of light, the conductor is arranged to overlap the pixel isolation region. In a photodetector configured in this manner, the conductor is disposed utilizing the area occupied by the pixel isolation region, so that the area occupied by the pixel can be reduced.

[0211] In a photodetection device according to a fifth embodiment of the present disclosure, in the photodetection device according to the third embodiment, when viewed from the direction of incidence of light or the side opposite to the direction of incidence of light, the amplification transistor is arranged to overlap the pixel isolation region. In a photodetector configured in this manner, the area occupied by the pixel isolation region is utilized to provide the amplifying transistor, so that the area occupied by the pixel can be reduced.

[0212] A photodetector according to a sixth embodiment of the present disclosure includes a photoelectric conversion element, a floating diffusion, a pixel isolation region, a conductor, and a reset transistor. The photoelectric conversion element is disposed inside the first substrate and converts light into an electric charge. The floating diffusion is disposed on a first surface of the first substrate and is electrically connected to the photoelectric conversion element. The pixel isolation region is disposed between the photoelectric conversion element and another photoelectric conversion element adjacent to the photoelectric conversion element, and electrically or optically isolates the photoelectric conversion element from the other photoelectric conversion elements. The conductor is disposed overlapping the pixel isolation region and is electrically connected to the floating diffusion. The reset transistor electrically connects one first main electrode of a pair of main electrodes to the conductor and electrically connects the other second main electrode to a power supply voltage. According to a photodetector configured in this manner, the wiring path length from the floating diffusion to one of the main electrodes of the reset transistor can be shortened to the minimum possible extent, thereby effectively suppressing random noise and improving charge conversion efficiency.

[0213] A photodetector according to a seventh embodiment of the present disclosure is the photodetector according to the sixth embodiment, further comprising an FD conversion gain switching transistor in which a third main electrode of one of the pair of main electrodes is electrically connected to a conductor and a fourth main electrode of the other is electrically connected to a first main electrode of the reset transistor. The first main electrode of the reset transistor is electrically connected to the conductor via the FD conversion gain switching transistor. According to a photodetector configured in this manner, the wiring path length from the floating diffusion to one of the main electrodes of the reset transistor can be shortened to the minimum possible extent, thereby effectively suppressing random noise and improving charge conversion efficiency.

[0214] <Configuration of this technology> The present technology includes the following configuration: According to the present technology having the following configuration, it is possible to improve the charge conversion efficiency in a photodetector.

[0215] (1) a photoelectric conversion element disposed inside the first substrate for converting light into electric charges; a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element; A conductor electrically connected to a side surface of the floating diffusion; an amplifying transistor having a gate electrode including the conductor; A light detection device comprising: (2) The conductor is embedded in the first substrate from the first surface toward a second surface opposite to the first surface. The light detection device according to (1) above. (3) the conductor constitutes a fin portion of the gate electrode extending from the first surface of the first base toward the second surface thereof, The amplifying transistor has a fin structure. The optical detection device according to (2) above. (4) The floating diffusion is a semiconductor region in the first substrate, the semiconductor region having a junction depth from the first surface toward the second surface. The optical detection device according to (2) or (3). (5) The conductor is integral or formed integrally with the gate electrode. The photodetector according to any one of (1) to (4). (6) The conductor is formed of polycrystalline silicon, metal, or a semiconductor region. The photodetector according to any one of (1) to (4). (7) a transfer transistor, one of a pair of main electrodes being electrically connected to the photoelectric conversion element and the other being electrically connected to the floating diffusion; The photoelectric conversion element and the transfer transistor constitute a pixel, The pixels are arranged in a first direction and a second direction intersecting the first direction. The photodetector according to any one of (1) to (6). (8) In the first substrate, a pixel isolation region is disposed around at least a side surface of the photoelectric conversion element of each of the pixels, electrically or optically isolating adjacent pixels from each other. The light detection device according to (7) above. (9) The conductor is formed as a shared wiring that electrically connects floating diffusions disposed in a plurality of adjacent pixels. The photodetector according to (8) above. (10) When viewed from the light incidence direction or the opposite side to the light incidence direction, the conductor is disposed so as to overlap the pixel isolation region. The light detection device according to (9) above. (11) When viewed from the light incidence direction or the opposite side to the light incidence direction, the amplifying transistor is disposed so as to overlap the pixel isolation region. The optical detection device according to (10) above. (12) The amplifying transistor constitutes a pixel circuit that reads out the electric charge converted by the photoelectric conversion element. The photodetector according to any one of (1) to (11). (13) The pixel circuit is constructed to include, in addition to the amplification transistor, a reset transistor and a selection transistor, or further a floating diffusion conversion transistor. The light detection device according to (12) above. (14) One or more transistors selected from the reset transistor, the selection transistor, and the floating diffusion conversion transistor of the pixel circuit are disposed on the first surface of the first substrate. The light detection device according to (13) above. (15) A second substrate is further provided on the first surface side of the first substrate, At least one transistor selected from the reset transistor, the selection transistor, and the floating diffusion conversion transistor of the pixel circuit is disposed on the second substrate. The optical detection device according to (13) or (14). (16) One of a pair of main electrodes of the reset transistor is electrically connected to a gate electrode of the amplification transistor through a wiring. The photodetector according to any one of (13) to (15).

[0216] (17) a photoelectric conversion element disposed inside the first substrate for converting light into electric charges; a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element; a pixel isolation region disposed between the photoelectric conversion element and another photoelectric conversion element adjacent to the photoelectric conversion element, electrically or optically isolating the photoelectric conversion element from the other photoelectric conversion element; a conductor disposed so as to overlap the pixel isolation region and electrically connected to the floating diffusion; a reset transistor, one of a pair of main electrodes of which, a first main electrode, is electrically connected to the conductor and the other, a second main electrode, is electrically connected to a power supply voltage; A light detection device comprising: (18) a floating diffusion conversion gain switching transistor, one of a pair of main electrodes of which a third main electrode is electrically connected to the conductor and the other of which a fourth main electrode is electrically connected to the first main electrode of the reset transistor; The first main electrode of the reset transistor is electrically connected to the conductor via the floating diffusion conversion gain switching transistor. The light detection device according to (17) above. (19) The conductor is connected to the reset transistor or the floating diffusion conversion gain switching transistor via the first main electrode or the third main electrode and a diffusion region that is diffused from a side surface of the conductor along the first surface and has the same conductivity type as the conductivity type of the first main electrode or the third main electrode. The optical detection device according to (18) above. (20) The conductor is formed of polycrystalline silicon, metal, or a semiconductor region. The photodetector according to any one of (17) to (19). (twenty one) the polycrystalline silicon or the metal is embedded in the first substrate or disposed on the first surface of the first substrate; The semiconductor region is disposed within the first substrate. The optical detection device according to (20) above. (twenty two) a transfer transistor electrically connected to the photoelectric conversion element; another transfer transistor electrically connected to the other photoelectric conversion element; The conductor is formed as a shared wiring electrically connected to the transfer transistor and the other transfer transistor. The photodetector according to any one of (17) to (21) above. (twenty three) The amplifier further includes an amplifier transistor having a gate electrode electrically connected to the conductor. The photodetector according to any one of (17) to (22). (twenty four) When viewed from the light incidence direction or the opposite side to the light incidence direction, the reset transistor and the amplification transistor are disposed so as to overlap the pixel isolation region. The light detection device according to (23) above. [Explanation of symbols]

[0217] 1...photodetector, 1A...first substrate, 1B...second substrate, 1C...third substrate, 10...pixel, 30, 40...semiconductor substrate, 300...p-type semiconductor region, 31, 31A, 31B, 31C...pixel isolation region, 31D...element isolation region, 321, 323, 326...gate insulating film, 322, 324, 327...gate electrode, 330...n-type semiconductor region, 35...conductor, 35n...diffusion region, 36...connection region, 5...through wiring, 7...optical filter, 8...optical lens, PD...photoelectric conversion element, TR...transfer transistor, RST...reset transistor, AMP...amplification transistor, SEL...selection transistor, FD...floating diffusion, FDG...FD conversion gain switching transistor.

Claims

1. a photoelectric conversion element disposed inside the first substrate for converting light into electric charges; a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element; A conductor electrically connected to a side surface of the floating diffusion; an amplifying transistor having a gate electrode including the conductor; A light detection device comprising:

2. The conductor is embedded in the first substrate from the first surface toward a second surface opposite to the first surface.

2. The optical detection device according to claim 1.

3. the conductor constitutes a fin portion of the gate electrode extending from the first surface of the first base toward the second surface thereof, The amplifying transistor has a fin structure.

3. The optical detection device according to claim 2.

4. The floating diffusion is a semiconductor region in the first substrate, the semiconductor region having a junction depth from the first surface toward the second surface.

3. The optical detection device according to claim 2.

5. The conductor is integral or formed integrally with the gate electrode.

2. The optical detection device according to claim 1.

6. The conductor is formed of polycrystalline silicon, metal, or a semiconductor region.

2. The optical detection device according to claim 1.

7. a transfer transistor, one of a pair of main electrodes being electrically connected to the photoelectric conversion element and the other being electrically connected to the floating diffusion; The photoelectric conversion element and the transfer transistor constitute a pixel, The pixels are arranged in a first direction and a second direction intersecting the first direction.

2. The optical detection device according to claim 1.

8. In the first substrate, a pixel isolation region is disposed around at least a side surface of the photoelectric conversion element of each of the pixels, electrically or optically isolating adjacent pixels from each other.

8. The optical detection device according to claim 7.

9. The conductor is formed as a shared wiring that electrically connects floating diffusions disposed in a plurality of adjacent pixels.

9. The optical detection device according to claim 8.

10. When viewed from the light incidence direction or the opposite side to the light incidence direction, the conductor is disposed so as to overlap the pixel isolation region.

10. The optical detection device according to claim 9.

11. When viewed from the light incidence direction or the opposite side to the light incidence direction, the amplifying transistor is disposed so as to overlap the pixel isolation region. The optical detection device according to claim 10.

12. The amplifying transistor constitutes a pixel circuit that reads out the electric charge converted by the photoelectric conversion element.

2. The optical detection device according to claim 1.

13. The pixel circuit is constructed to include, in addition to the amplification transistor, a reset transistor and a selection transistor, or further a floating diffusion conversion transistor.

13. The optical detection device of claim 12.

14. One or more transistors selected from the reset transistor, the selection transistor, and the floating diffusion conversion transistor of the pixel circuit are disposed on the first surface of the first substrate.

14. The optical detection device of claim 13.

15. A second substrate is further provided on the first surface side of the first substrate, At least one transistor selected from the reset transistor, the selection transistor, and the floating diffusion conversion transistor of the pixel circuit is disposed on the second substrate.

14. The optical detection device of claim 13.

16. One of a pair of main electrodes of the reset transistor is electrically connected to a gate electrode of the amplification transistor through a wiring.

14. The optical detection device of claim 13.

17. a photoelectric conversion element disposed inside the first substrate for converting light into electric charges; a floating diffusion disposed on a first surface of the first substrate and electrically connected to the photoelectric conversion element; a pixel isolation region disposed between the photoelectric conversion element and another photoelectric conversion element adjacent to the photoelectric conversion element, electrically or optically isolating the photoelectric conversion element from the other photoelectric conversion element; a conductor disposed so as to overlap the pixel isolation region when viewed from a light incidence direction or an opposite side to the light incidence direction and electrically connected to the floating diffusion; a reset transistor, one of a pair of main electrodes of which, a first main electrode is electrically connected to the conductor and the other, a second main electrode of which is electrically connected to a power supply voltage; A light detection device comprising:

18. a floating diffusion conversion gain switching transistor, one of a pair of main electrodes of which a third main electrode is electrically connected to the conductor and the other of which a fourth main electrode is electrically connected to the first main electrode of the reset transistor; The first main electrode of the reset transistor is electrically connected to the conductor via the floating diffusion conversion gain switching transistor.

18. The optical detection device of claim 17.

19. The conductor is connected to the reset transistor or the floating diffusion conversion gain switching transistor via the first main electrode or the third main electrode and a diffusion region that is diffused from a side surface of the conductor along the first surface and has the same conductivity type as the conductivity type of the first main electrode or the third main electrode.

20. The optical detection device of claim 18.

20. The conductor is formed of polycrystalline silicon, metal, or a semiconductor region.

18. The optical detection device of claim 17.

21. the polycrystalline silicon or the metal is embedded in the first substrate or disposed on the first surface of the first substrate; The semiconductor region is disposed within the first substrate.

21. The optical detection device of claim 20.

22. a transfer transistor electrically connected to the photoelectric conversion element; another transfer transistor electrically connected to the other photoelectric conversion element; The conductor is formed as a shared wiring electrically connected to the transfer transistor and the other transfer transistor.

18. The optical detection device of claim 17.

23. The amplifier further includes an amplifier transistor having a gate electrode electrically connected to the conductor.

18. The optical detection device of claim 17.

24. When viewed from the light incidence direction or the opposite side to the light incidence direction, the reset transistor and the amplification transistor are disposed so as to overlap the pixel isolation region.

24. The optical detection device of claim 23.

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