Circuit board and semiconductor module

Abstract

To provide a circuit board and a semiconductor module that can be made low profile while maintaining mechanical strength.SOLUTION: A semiconductor module 1 has a circuit board 10 and first and second transistors 11, 12 mounted on the circuit board 10. The circuit board 10 has a ceramic substrate 2 and a metal substrate 3 bonded to one side 2a of the ceramic substrate 2. The metal substrate 3 has recesses 101, 102 that accommodate the first and second transistors 11, 12.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit board using a ceramic substrate, and a semiconductor module in which a semiconductor chip is mounted on a circuit board using a ceramic substrate. [Background technology]

[0002] Conventionally, ceramic substrates have been used as circuit boards for mounting heat-generating electronic components. Ceramic substrates have high heat resistance and are less prone to warping, so they can be suitably used as components of circuit boards that mount power elements that generate a large amount of heat, such as power transistors.

[0003] The module substrate described in Patent Document 1 is made of fired ceramics having a laminated structure of multiple dielectric layers, and multiple via conductors are formed penetrating the multiple dielectric layers. In addition, in order to reduce the height of the module substrate, a recessed area for accommodating low-profile components such as amplifiers and switches is formed so as to be recessed in the thickness direction.

[0004] The power module substrate described in Patent Document 2 has an insulating substrate made of ceramics, a circuit layer brazed to one surface of the insulating substrate, and a metal layer brazed to the other surface of the insulating substrate. The circuit layer and the metal layer are formed by punching an aluminum plate. A wiring pattern is formed on the circuit layer during punching, and a semiconductor chip is bonded to the surface of the circuit layer via a solder layer. A heat sink is brazed to the surface of the metal layer opposite the insulating substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-197402 [Patent Document 2] JP 2008-277654 A Summary of the Invention [Problem to be solved by the invention]

[0006] As described in Patent Document 1, a circuit is formed on a ceramic substrate using via conductors and a recessed region is formed, which allows for a low profile, but has low mechanical strength and is limited to applications where the target is not subject to vibration or impact. Also, as described in Patent Document 2, a circuit layer and a metal layer are laminated on one and the other sides of an insulating substrate made of ceramics and a semiconductor chip is bonded to the surface of the circuit layer, which results in a large thickness in the lamination direction.

[0007] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a circuit board and a semiconductor module that can be made low-profile while ensuring mechanical strength. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, the present invention provides a circuit board on which electronic components are mounted, comprising a ceramic substrate and a metal substrate joined to one surface of the ceramic substrate, wherein a recess for accommodating at least a portion of the electronic component is formed in the metal substrate.

[0009] In addition, with the objective of solving the above-mentioned problems, the present invention provides a semiconductor module comprising a ceramic substrate, a metal substrate joined to one surface of the ceramic substrate, and a semiconductor chip mounted on the metal substrate, wherein a recess for accommodating at least a portion of the semiconductor chip is formed in the metal substrate. Effect of the Invention

[0010] According to the circuit board and semiconductor module of the present invention, it is possible to reduce the height of the circuit board while ensuring the mechanical strength of the circuit board. [Brief description of the drawings]

[0011] [Figure 1]1 is a configuration diagram showing a semiconductor module according to a first embodiment of the present invention. [Diagram 2] 1. (b) to (d) are enlarged views of parts B, C, and D in (a). [Diagram 3] 1A is a plan view showing a second metal plate formed by a press process, and FIG. 1B is a cross-sectional view taken along line EE of FIG. [Figure 4] 1A is a cross-sectional view showing an example of use of a semiconductor module, and FIG. 1B and FIG. 1C are enlarged views of portions F and G in FIG. [Diagram 5] FIG. 11 is a configuration diagram showing a circuit board and a semiconductor module according to a second embodiment of the present invention. [Figure 6] 6(a) is a cross-sectional view taken along line HH in Fig. 5. 6(b) to 6(d) are enlarged views of parts I, J and K in 6(a). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [First embodiment] Fig. 1 is a configuration diagram showing a semiconductor module 1 according to a first embodiment of the present invention. Fig. 2(a) is a cross-sectional view taken along line AA in Fig. 1. Figs. 2(b) to (d) are enlarged views of parts B, C, and D in Fig. 2(a).

[0013] The semiconductor module 1 includes a circuit board 10 and first and second transistors 11, 12 as semiconductor chips mounted on the circuit board 10. The circuit board 10 includes a flat ceramic substrate 2, a metal substrate 3 bonded to one surface 2a of the ceramic substrate 2, and a metal heat sink 4 bonded to the other surface 2b of the ceramic substrate 2. Specific examples of the ceramic substrate 2 that can be used include an aluminum nitride (AlN) substrate, a silicon nitride (Si3N4) substrate, an aluminum oxide (Al2O3) substrate, a silicon carbide (SiC) substrate, an alumina zirconia (ZTA) substrate, and a beryllium oxide (BeO) substrate.

[0014] The metal substrate 3 has a laminated structure formed by laminating a plurality of metal plates in a stacking direction perpendicular to the ceramic substrate 2. In the present embodiment, the metal substrate 3 has a two-layer structure formed by laminating a first metal plate 31 and a second metal plate 32 in a stacking direction perpendicular to the ceramic substrate 2. The first metal plate 31 and the second metal plate 32 are brazed by a brazing material 51, and the first metal plate 31 is brazed to one surface 2a of the ceramic substrate 2 by a brazing material 52. The heat sink 4 is brazed to the other surface 2b of the ceramic substrate 2 by a brazing material 53.

[0015] In the present embodiment, the first metal plate 31, the second metal plate 32, and the heat sink 4 are made of copper or a copper alloy. However, the materials of the first metal plate 31, the second metal plate 32, and the heat sink 4 are not limited thereto, and may be, for example, aluminum or an aluminum alloy. As the brazing materials 51, 52, 53, for example, an active metal brazing material of a silver (Ag)-copper (Cu)-titanium (Ti) system can be used. For example, by heating the brazing materials 51, 52, 53 to 700 °C or higher and joining them, a strong joining strength can be obtained. The joining strength between the first metal plate 31 and the second metal plate 32 is, for example, 10 MPa or more and 130 MPa or less.

[0016] The thickness of the ceramic substrate 2 is, for example, 0.32 mm. The thickness of the metal substrate 3 is, for example, 1.0 mm or more and 3.0 mm or less. The thickness of the brazing materials 51, 52, 53 is, for example, 0.01 mm or more and 0.10 mm or less. Considering the heat dissipation of the heat generated by the first and second transistors 11, 12, it is desirable that the thickness of the first metal plate 31 is thicker than the thickness of the second metal plate 32. The thickness of the first metal plate 31 is, for example, 0.5 mm or more. In the present embodiment, as shown in Fig. 2(b), when the thickness of the ceramic substrate 2 is T2, the thickness of the first metal plate 31 is T 31 , the thickness of the second metal plate 32 is T 32 , and the thickness of the heat sink 4 is T4, these thicknesses satisfy the relationship of T2 < T 32 < T 31 < T4.

[0017] The metal substrate 3 is formed with first and second recesses 101, 102 for accommodating the first and second transistors 11, 12, respectively. In this embodiment, two through holes are formed in the second metal plate 32, which is the surface layer side of the metal substrate 3, and these through holes are the first and second recesses 101, 102. The first and second recesses 101, 102 penetrate the second metal plate 32 in the stacking direction. The first metal plate 31 forms the bottom surfaces 101a, 102a of the first and second recesses 101, 102. The first and second transistors 11, 12 are mounted on the metal substrate 3 with their lower surfaces 11a, 12a facing the bottom surfaces 101a, 102a joined to the first metal plate 31 by, for example, soldering. 2(c) and (d) show solder 50 between the first and second transistors 11, 12 and the bottom surfaces 11a, 12a.

[0018] The first and second transistors 11 and 12 are provided with base electrodes 111 and 121, emitter electrodes 112 and 122, and collector electrodes 113 and 123 on upper surfaces 11b and 12b opposite to lower surfaces 11a and 12a, respectively. The first transistor 11 and the second transistor 12 are Darlington-connected to increase the current amplification factor, and the emitter electrode 112 of the first transistor 11 is electrically connected to the base electrode 121 of the second transistor 12.

[0019] The metal substrate 3 is provided with a groove 30 formed by etching, and the groove 30 divides the metal substrate 3 into first to fourth electrode portions 301 to 304. The groove 30 reaches the ceramic substrate 2 from a surface 32a, which is the surface of the second metal plate 32 opposite to the first metal plate 31, and the first to fourth electrode portions 301 to 304 are electrically insulated from each other. The first electrode portion 301 is electrically connected to the base electrode 111 of the first transistor 11, and the second electrode portion 302 is electrically connected to the emitter electrode 122 of the second transistor 12. The third electrode portion 303 is electrically connected to the emitter electrode 112 of the first transistor 11 and the base electrode 121 of the second transistor 12. The fourth electrode portion 304 is electrically connected to the collector electrodes 113 and 123 of the first transistor 11 and the second transistor 12, respectively.

[0020] In this embodiment, these connections are made by wire bonding. Specifically, as shown in Fig. 1, the base electrodes 111, 121, the emitter electrodes 112, 122, and the collector electrodes 113, 123 of the first and second transistors 11, 12 are connected to the first to fourth electrode portions 301-304 by the bonding wires 61-66. One end of each of the bonding wires 61-66 is fused to the surface layer surface 32a of the second metal plate 32.

[0021] In this embodiment, the first and second transistors 11, 12 are entirely housed in the first and second recesses 101, 102, respectively, and the positions of the base electrodes 111, 121, the emitter electrodes 112, 122, and the collector electrodes 113, 123 in a direction perpendicular to the ceramic substrate 2 are closer to the ceramic substrate 2 than the position of the surface 32a of the second metal plate 32. This makes it possible to shorten the length of the bonding wires 61 to 66, for example, compared to the case where the first and second transistors 11, 12 are mounted on the surface 32a of the second metal plate 32.

[0022] However, a part of the upper surface 11b, 12b side of the first and second transistors 11, 12, or the base electrodes 111, 121, the emitter electrodes 112, 122, and the collector electrodes 113, 123 may protrude from the first and second recesses 101, 102. Even in this case, by housing at least a part of the first and second transistors 11, 12 including the lower surfaces 11a, 12a in the first and second recesses 101, 102, the difference in position between the base electrodes 111, 121, the emitter electrodes 112, 122, and the collector electrodes 113, 123 and the surface 32a of the second metal plate 32 in the direction perpendicular to the ceramic substrate 2 becomes small, and the length of the bonding wires 61 to 66 can be shortened. That is, it is sufficient that at least a part of the first and second transistors 11, 12 is housed in the first and second recesses 101, 102.

[0023] Next, a description will be given of a manufacturing method for the circuit board 10. The circuit board 10 is manufactured by a manufacturing method including a pressing step of pressing a plate-shaped material made of a metal material to form the first metal plate 31, the second metal plate 32, and the heat sink 4, a brazing step of joining the ceramic substrate 2, the first metal plate 31, the second metal plate 32, and the heat sink 4 in the stacking direction with brazing materials 51, 52, and 53, and an etching step of forming grooves 30 by etching to partition the metal substrate 3 into first to fourth electrode portions 301-304.

[0024] FIG. 3(a) is a plan view showing the second metal plate 32 formed by the pressing process. FIG. 3(b) is a cross-sectional view taken along the line EE in FIG. 3(a). In the second metal plate 32 after the pressing process, two through holes 321, 322 are formed penetrating in the thickness direction between the joint surface 32b with the first metal plate 31 and the surface surface 32a. These through holes 321, 322 are formed by punching the second metal plate 32 from the joint surface 32b side toward the surface surface 32a side with a protrusion provided on a die used in the pressing process. The through holes 321, 322 become the first and second recesses 101, 102 that accommodate the first and second transistors 11, 12 in the circuit board 10 after the etching process.

[0025] As shown in Fig. 2(c), the side surface 101b of the first recess 101 is inclined so that the opening area of ​​the first recess 101 in the surface layer 32a is larger than the area of ​​the bottom surface 101a of the first recess 101. Also, as shown in Fig. 2(d), the side surface 102b of the second recess 102 is inclined so that the opening area of ​​the second recess 102 in the surface layer 32a is larger than the area of ​​the bottom surface 102a of the second recess 102. The inclination angles θ1, θ2 of the side surfaces 101b, 102b at the center of the depth direction of the first and second recesses 101, 102 with respect to the direction perpendicular to the ceramic substrate 2 are 1 degree or more and 10 degrees or less. A side surface 101b of the first recess 101 is an inner surface 321a of the through hole 321 after the pressing process, and a side surface 102b of the second recess 102 is an inner surface 322a of the through hole 322 after the pressing process.

[0026] Fig. 4(a) is a cross-sectional view showing an example of use of the semiconductor module 1. Figs. 4(b) and 4(c) are enlarged views of parts F and G in Fig. 4(a). In the semiconductor module 1, the surface 32a of the second metal plate 32 is covered with the resin 7 together with the first and second transistors 11, 12 and the bonding wires 61 to 66, and the heat sink 4 is thermally coupled to the heat sink 8. Fig. 4 shows a case where the heat sink 4 and the heat sink 8 are thermally coupled by brazing with a brazing material 54, but the heat sink 4 and the heat sink 8 may be thermally coupled via a thermally conductive member such as thermally conductive grease.

[0027] The resin 7 is a thermosetting resin such as epoxy resin, and is interposed between the side surfaces 101b, 102b of the first and second recesses 101, 102 and the first and second transistors 11, 12. This configuration facilitates heat conduction from the first and second transistors 11, 12 to the side surfaces 101b, 102b of the first and second recesses 101, 102 through the resin 7. In addition, the resin 7 prevents discharge between the bonding wires 61 to 66 and prevents the bonding wires 61 to 66 from bending due to an external force. Furthermore, by sealing the first and second transistors 11, 12 with the resin 7, it is possible to protect the first and second transistors 11, 12 from the external environment such as external force and humidity.

[0028] The resin 7 is applied to the circuit board 10 and the first and second transistors 11, 12 in a liquid state before hardening, and then hardened by heating. Since the side surfaces 101b, 102b are inclined as described above, the resin 7 can easily enter the side surfaces 101b, 102b of the first and second recesses 101, 102 from the first and second transistors 11, 12. The material of the resin 7 may be a sealant such as silicone gel.

[0029] Heat generated in the first and second transistors 11, 12 is transferred from the first metal plate 31 to the ceramic substrate 2, and then passes through the heat sink 8 via the heat dissipation plate 4, before being dissipated to the atmosphere.

[0030] (Functions and Effects of the First Embodiment) According to the first embodiment described above, the configuration in which the ceramic substrate 2 and the metal substrate 3 are joined increases the mechanical strength of the circuit substrate 10 compared to a case in which the substrate is made of fired ceramics as described in the above-mentioned Patent Document 1. In addition, by accommodating the first and second transistors 11, 12 in the first and second recesses 101, 102, the thickness of the semiconductor module 1 in the direction perpendicular to the ceramic substrate 2 can be reduced, enabling a low profile.

[0031] (Modification of the first embodiment) In the above-mentioned first embodiment, the case where the first and second transistors 11, 12 are mounted on the circuit board 10 has been described, but the circuit board 10 can be mounted with various electronic components that generate heat, such as light-emitting elements and resistors, in addition to transistors. In addition, in the first embodiment, the case where the metal board 3 has a two-layer structure in which the first and second metal plates 31, 32 are laminated has been described, but the present invention is not limited to this, and the metal board 3 may have a three-layer or more laminate structure in which three or more metal plates are laminated. In this case, a through hole is formed in at least one of the multiple metal plates in the lamination direction as a recess for accommodating an electronic component, and the bottom surface of the recess is formed by at least one of the other metal plates.

[0032] [Second embodiment] Next, a second embodiment of the present invention will be described with reference to Figs. 5 and 6. Fig. 5 is a configuration diagram showing a circuit board 10A and a semiconductor module 1A according to the second embodiment of the present invention. Fig. 6(a) is a cross-sectional view taken along line HH in Fig. 5. Figs. 6(b) to (d) are enlarged views of parts I, J, and K in Fig. 6(a). In Figs. 5 and 6, components common to those described in the first embodiment are designated by the same reference numerals as those in Figs. 1 and 2, and duplicated descriptions will be omitted.

[0033] In the first embodiment, the case where the metal substrate 3 of the circuit board 10 has a two-layer structure in which the first and second metal plates 31 and 32 are laminated has been described, but in the second embodiment, the metal substrate 9 of the circuit board 10A is made of a single metal plate. The metal substrate 9 is made of, for example, copper or a copper alloy, and is brazed to one surface 2a of the ceramic substrate 2 with a brazing material 52.

[0034] The metal substrate 9 has first and second recesses 101, 102 for accommodating the first and second transistors 11, 12, respectively, formed by etching so as to recess from a surface 9a of the metal substrate 9 toward a back surface 9b on the ceramic substrate 2 side. The first and second transistors 11, 12 have their lower surfaces 11a, 12a joined to bottom surfaces 101a, 102a of the first and second recesses 101, 102 by solder 50. The depth D of the first and second recesses 101, 102 in a direction perpendicular to the ceramic substrate 2 is 91 ,D 92 is shallower than the thickness T9 of the metal substrate 9, and the first and second recesses 101, 102 do not open to the rear surface 9b.

[0035] Since the first and second recesses 101, 102 are not open to the rear surface 9b, the heat dissipation of the first and second transistors 11, 12 is improved compared to, for example, a case in which the first and second recesses 101, 102 penetrate the metal substrate 9 and open to the rear surface 9b, and the first and second transistors 11, 12 are joined to the ceramic substrate 2. This is because the heat generated in the first and second transistors 11, 12 is transferred to the ceramic substrate 2 via the metal substrate 9. More specifically, the depth D of the first and second recesses 101, 102 is 91 ,D 92 is shallower than the thickness T9 of the metal substrate 9, and the first and second transistors 11, 12 and the ceramic substrate 2 are separated by a thickness T9 and a depth D 91 ,D 92 Since the metal substrate 9 is interposed between the first and second transistors 11, 12 and the ceramic substrate 2, the heat generated in the first and second transistors 11, 12 is first transferred to the metal substrate 9, and then diffused by the metal substrate 9 and efficiently transferred to the ceramic substrate 2. 90 (See Fig. 6(a)) is an example of a depth D 91 ,D 92 and is 50% or more of the thickness T9 of the metal substrate 9.

[0036] Depth D of the first and second recesses 101, 102 91 ,D 92is the thickness T of the second metal plate 32 in the first embodiment. 32 and the first and second transistors 11, 12 are entirely housed in the first and second recesses 101, 102, respectively. The inclination angles θ1, θ2 of the side surfaces 101b, 102b at the center in the depth direction of the first and second recesses 101, 102 with respect to the direction perpendicular to the ceramic substrate 2 are equal to or greater than 1 degree and equal to or less than 10 degrees, similar to the first embodiment.

[0037] The metal substrate 9 is provided with grooves 90 formed by etching, and the grooves 90 divide the metal substrate 9 into first to fourth electrode portions 901 to 904. The grooves 90 extend from the surface 9a of the metal substrate 9 to the ceramic substrate 2, and the first to fourth electrode portions 901 to 904 are electrically insulated from each other. The first to fourth electrode portions 901 to 904 are connected to the base electrodes 111 and 121, the emitter electrodes 112 and 122, and the collector electrodes 113 and 123 of the first and second transistors 11 and 12 by bonding wires 61 to 66. One end of each of the bonding wires 61 to 66 is fused to the surface 9a of the metal substrate 9.

[0038] The second embodiment also provides the same effects as the first embodiment.

[0039] (Summary of the embodiment) Next, the technical ideas grasped from the first and second embodiments explained above will be described by using the reference numerals and the like in the first and second embodiments. However, the reference numerals in the following description do not limit the components in the claims to the members and the like specifically shown in the first and second embodiments.

[0040] [1] A circuit board (10, 10A) on which an electronic component (11, 12) is mounted, the circuit board (10, 10A) comprising: a ceramic substrate (2); and a metal substrate (3, 9) joined to one surface (2a) of the ceramic substrate (2), the metal substrate (3, 9) having a recess (101, 102) formed therein for accommodating at least a portion of the electronic component (11, 12).

[0041] [2] The circuit board (10) described in [1] above, wherein the metal substrate (3, 9) has a laminated structure formed by stacking a plurality of metal plates (31, 32) in a stacking direction perpendicular to the ceramic substrate (2), at least one of the metal plates (32) has a through hole (321, 322) formed therethrough as the recess (101, 102) in the stacking direction, and at least one other of the metal plates (31) forms a bottom surface (101a, 102a) of the recess (101, 102).

[0042] [3] The metal substrate (3, 9) has a two-layer structure formed by laminating a first metal plate (31) joined to the ceramic substrate (2) and a second metal plate (32) on the surface side joined to the first metal plate (31) in a lamination direction perpendicular to the ceramic substrate (2), the second metal plate (32) has through holes (321, 322) formed therethrough as the recesses (101, 102) in the lamination direction, the first metal plate (31) forms bottom surfaces (101a, 102a) of the recesses (101, 102), and the thickness (T 31 ) is the thickness (T 32 ) The circuit board (10) according to [1] above.

[0043] [4] The circuit board (10) according to the above [3], wherein the bonding strength between the first metal plate (31) and the second metal plate (32) is 10 MPa or more.

[0044] [5] The circuit board (10A) according to the above item [1], wherein the metal substrate (9) is made of a single metal plate, and the recesses (101, 102) are formed shallower than a thickness (T9) of the metal plate (9) from a surface (surface surface 9a) of the metal plate (9) opposite the ceramic substrate (2) toward a back surface (9b) on the ceramic substrate (2) side.

[0045] [6] The circuit board (10, 10A) according to any of [1] to [5] above, wherein the side surfaces (101b, 102b) of the recesses (101, 102) are inclined so that the opening area of ​​the recesses (101, 102) is larger than the area of ​​the bottom surfaces (101a, 102a) of the recesses (101, 102), and the inclination angle (θ1, θ2) of the side surfaces (101b, 102b) at the center of the depth direction of the recesses (101, 102) with respect to a direction perpendicular to the ceramic substrate (2) is 1 degree or more.

[0046] [7] A semiconductor module (1, 1A) comprising a ceramic substrate (2), a metal substrate (3, 9) joined to one surface (2a) of the ceramic substrate (2), and a semiconductor chip (11, 12) mounted on the metal substrate (3, 9), wherein a recess (101, 102) for accommodating at least a portion of the semiconductor chip (11, 12) is formed in the metal substrate (3, 9).

[0047] [8] The semiconductor module (1, 1A) described in [7] above, wherein the semiconductor chip (11, 12) has electrodes (111-113, 121-123) connected to the metal substrate (3, 9) by wire bonding, and the positions of the electrodes (111-113, 121-123) in a direction perpendicular to the ceramic substrate (2) are closer to the ceramic substrate (2) than the positions of the surface (surface surface 32a, 9a) of the metal substrate (3, 9) opposite the ceramic substrate (2).

[0048] Although the first and second embodiments of the present invention have been described above, the invention according to the claims is not limited to the first and second embodiments. It should be noted that not all of the combinations of features described in the first and second embodiments are essential to the means for solving the problems of the invention. [Explanation of symbols]

[0049] 1. Semiconductor module 10,10A…Circuit board 11, 12...First and second transistors (electronic components, semiconductor chips) 101, 102...First and second recesses 101a, 102a…Bottom surface 101b,102b…side 111, 121...Base electrode 112, 122…Emitter electrode 113, 123…Collector electrode 2...Ceramic substrate 2a...One side 3,9…Metal substrate 31…First metal plate 32…Second metal plate 32a,9a…Surface surface θ1, θ2…Inclination angle

Claims

1. A circuit board on which electronic components are mounted, A ceramic substrate and a metal substrate bonded to one surface of the ceramic substrate, A recess for accommodating at least a portion of the electronic component is formed in the metal substrate. Circuit board.

2. the metal substrate has a laminated structure formed by laminating a plurality of metal plates in a lamination direction perpendicular to the ceramic substrate, At least one of the metal plates has a through hole formed therein as the recess in the stacking direction, and at least one of the other metal plates forms a bottom surface of the recess. The circuit board according to claim 1 .

3. the metal substrate has a two-layer structure formed by laminating a first metal plate joined to the ceramic substrate and a second metal plate on a surface side joined to the first metal plate in a lamination direction perpendicular to the ceramic substrate, a through hole as the recess is formed in the second metal plate so as to penetrate in the stacking direction, and the first metal plate forms a bottom surface of the recess, The thickness of the first metal plate is greater than the thickness of the second metal plate. The circuit board according to claim 1 .

4. The bonding strength between the first metal plate and the second metal plate is 10 MPa or more. The circuit board according to claim 3 .

5. The metal substrate is made of a single metal plate, the recess is formed from a surface of the metal plate opposite to the ceramic substrate toward a back surface of the metal plate facing the ceramic substrate, the recess being shallower than a thickness of the metal plate; The circuit board according to claim 1 .

6. a side surface of the recess is inclined so that an opening area of ​​the recess is larger than an area of ​​a bottom surface of the recess, an inclination angle of the side surface at a center portion in a depth direction of the recess with respect to a direction perpendicular to the ceramic substrate is 1 degree or more; The circuit board according to claim 1 .

7. A ceramic substrate; a metal substrate bonded to one surface of the ceramic substrate; A semiconductor chip mounted on the metal substrate, A recess for accommodating at least a portion of the semiconductor chip is formed in the metal substrate. Semiconductor module.

8. the semiconductor chip has electrodes connected to the metal substrate by wire bonding; a position of the electrode in a direction perpendicular to the ceramic substrate is closer to the ceramic substrate than a position of a surface of the metal substrate opposite to the ceramic substrate; The semiconductor module according to claim 7 .

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