Information processing apparatus and method of measuring CPU usage

Abstract

To provide an information processing apparatus with which CPU usage can be measured with simple configuration, and a method of measuring CPU usage.SOLUTION: An information processing apparatus 10 includes: a total processing timer 40 for measuring processing time required by a CPU 20 for processing the whole of a program P; a partial processing timer 42 for measuring the time elapsed from the time at which the CPU 20 reads a command recorded in the first address, which is an arbitrary address in addresses in which commands constituting the program P are stored, to the time at which the CPU 20 reads a command recorded in an end address which is later than the first address; and an output unit 44 which outputs the usage of the CPU 20 calculated based on the elapsed time measured by the partial processing timer 42 and the processing time measured by the total processing timer 40.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to an information processing device and a method for measuring a CPU utilization rate. [Background technology]

[0002] For example, Patent Document 1 discloses a CPU usage time monitoring method in which, when a job is run, an address / accumulation table creation means creates an address table of the programs that make up the job and also secures a CPU cumulative usage time table, and when the program start / end means confirms that the address of the program pointer is the same as the first address in the address table, it sends a program start notification to the cumulative time collection means, which then extracts the CPU cumulative usage time of the program that has started processing from the CPU cumulative usage time table and sets it in a time accumulation counter to be counted, and then, when a program end notification is received, the cumulative time collection means stops counting the time accumulation counter and writes the count value into the CPU cumulative usage time table. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 05-324418 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in information processing devices with simple configurations such as microcontrollers, adopting a high-performance CPU (Central Processing Unit) leads to increased costs, so it is desirable to minimize the hardware configuration. On the other hand, in order to minimize the hardware configuration, it is necessary to measure the CPU utilization rate of the installed programs. If an OS (Operating System) is installed to measure the CPU utilization rate, this leads to the above-mentioned increased costs.

[0005] The present disclosure provides an information processing device and a method for measuring CPU usage that are capable of measuring CPU usage when a CPU processes instructions recorded from any forward address to any backward address of a program, even in an information processing device with a simple configuration. [Means for solving the problem]

[0006] An information processing device of a first embodiment comprises an overall processing timer that measures the processing time it takes a CPU to process an entire program, a partial processing timer that measures the elapsed time from the time the CPU reads an instruction recorded at an early address, which is any address among addresses at which instructions constituting the program are stored, to the time the CPU reads an instruction recorded at a later address that is later than the early address, and an output unit that outputs a utilization rate of the CPU calculated based on the elapsed time measured by the partial processing timer and the processing time measured by the overall processing timer.

[0007] In the information processing device according to this aspect, the partial processing timer measures the time from when the CPU reads an instruction recorded in a leading address of the program data until when it reads an instruction recorded in a trailing address of the program data. Therefore, the partial processing timer measures the time elapsed from when the CPU executes an instruction recorded in a leading address until when it executes an instruction recorded in a trailing address.

[0008] The information processing device also has an overall processing timer that measures the processing time required for program processing, and an output unit that outputs a CPU usage rate calculated based on the elapsed time measured by the partial processing timer and the processing time measured by the overall processing timer.

[0009] Therefore, according to the information processing device of this embodiment, even when the instructions executed by the CPU do not include a process for measuring CPU utilization, that is, even in an information processing device with a simple configuration, it is possible to measure the CPU utilization when the CPU processes instructions recorded from any forward address to any backward address of the program. Effect of the Invention

[0010] According to the present disclosure, an information processing device and a method for measuring CPU utilization are provided that are capable of measuring CPU utilization when a CPU processes instructions recorded from any forward address to any backward address of a program, even in an information processing device with a simple configuration. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating a configuration of an information processing device according to a first embodiment. [Diagram 2] 4 is a diagram illustrating addresses registered in an address registration unit according to the first embodiment. FIG. [Diagram 3] FIG. 4 is a flow diagram illustrating a method for measuring a CPU utilization rate according to the first embodiment. [Figure 4] FIG. 11 is a diagram illustrating a configuration of an information processing device according to a second embodiment. [Diagram 5] FIG. 11 is a flow diagram illustrating a method for measuring a CPU utilization rate according to the second embodiment. [Figure 6] FIG. 13 is a diagram illustrating a configuration of an information processing device according to a third embodiment. [Figure 7] FIG. 13 is a diagram illustrating addresses registered in an address registration unit according to the third embodiment. [Figure 8] 13A to 13C are diagrams illustrating the operation of a stack unit according to a third embodiment. [Figure 9] 9 is a diagram illustrating the operation of the stack unit according to the third embodiment, following FIG. 8. [Figure 10] FIG. 13 is a flow diagram illustrating a method for measuring a CPU utilization rate according to the third embodiment. [Figure 11] 13A to 13C are diagrams illustrating the operation of a sub-processing timer in the method for measuring a CPU utilization rate according to the third embodiment. [Figure 12] FIG. 13 is a diagram illustrating addresses registered in an address registration unit according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an example of an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. In addition, the dimensional ratios of the drawings are exaggerated for the convenience of explanation and may differ from the actual ratios.

[0013] [First embodiment] (composition) Fig. 1 is a diagram illustrating an information processing device 10 according to the present embodiment. As shown in Fig. 1, the information processing device 10 according to the present embodiment includes, as an example, a CPU 20, a peripheral circuit 26, a ROM 22, a RAM 24, an overall processing timer 40, a partial processing timer 42, an output unit 44, and an address registration unit 30. The information processing device 10 according to the present embodiment is, for example, a microcomputer incorporated in an electric device and used to control the electric device.

[0014] The CPU 20 (Central Processing Unit) is a central processing unit. In this embodiment, the CPU 20 is a component that sequentially reads (fetches) instructions included in a program P recorded in a ROM 22 as shown in Fig. 1, analyzes (decodes) the instructions, and executes (executes) the instructions. The CPU 20 also controls a peripheral circuit 26 by executing instructions included in the program P. The peripheral circuit 26 controlled by the CPU 20 may have any configuration, and examples thereof include an A / D conversion circuit and a communication interface circuit such as I2C or SPI.

[0015] ROM22 (Read Only Memory) is an example of a "storage unit" according to this embodiment, and is a non-volatile storage device in which various programs P and various data executed by CPU 20 are recorded. As shown in Fig. 2, the program P recorded in ROM22 further has a first function F1, a second function F2, and a third function F3, which are examples of a "subprogram" according to this embodiment, and each function is recorded by dividing it into address areas AS.

[0016] The RAM 24 (Random Access Memory) is a volatile storage device that temporarily stores the programs P or data as a working area in which the CPU 20 executes the various programs P.

[0017] The overall processing timer 40 is a component that starts and stops in a method for measuring CPU utilization rate, which will be described later, and records the elapsed time while it is running. The overall processing timer 40 may measure the elapsed time in any manner, but as an example, it measures the elapsed time by measuring the number of pulse waves included in the clock signal output from the CPU 20.

[0018] The partial processing timer 42, like the overall processing timer 40, is a component that can be activated and deactivated in a method for measuring a CPU usage rate, which will be described later, and records the elapsed time while activated. That is, the overall processing timer 40 may measure the elapsed time in any manner, but as an example, it is desirable to measure the elapsed time by measuring the number of pulse waves contained in a clock signal output from the CPU 20. In other words, it is desirable for the partial processing timer 42 to be configured to measure the elapsed time based on the same clock signal as the overall processing timer 40.

[0019] The output unit 44 is configured to output the CPU utilization rate calculated based on the measurement results by the overall processing timer 40 and the partial processing timer 42 in a method for measuring the CPU utilization rate, which will be described later. In this embodiment, the output unit 44 calculates the CPU utilization rate according to the following formula (1) in the method for measuring the CPU utilization rate, which will be described later.

[0020]

number

[0021] In addition, in the formula (1), T F is the measurement value of the partial processing timer 42, and T A is the measurement value of the overall processing timer 40.

[0022] As shown in FIG. 1 and FIG. 2, the address registration unit 30 is a component in which the addresses of the functions recorded in the ROM 22 in the address area AS of the ROM 22 are registered, and which notifies the addresses in response to the processing operation of the CPU 20. More specifically, as shown in FIG. 2, the address registration unit 30 according to this embodiment has a front address registration unit 32 and a rear address registration unit 34. In this embodiment, the front address registration unit 32 registers "AAAA_AAAA", which is the first address of the address area AS in which the first function F1 is recorded. In addition, the rear address registration unit 34 registers "BBBB_BBBB", which is the end address of the address area AS in which the first function F1 is recorded. Note that the first address of the address area AS in which the first function F1 is recorded is an example of the "front address" in this embodiment, and the end address of the address area AS in which the first function F1 is recorded is an example of the "rear address" in this embodiment.

[0023] In this embodiment, as shown in FIG. 1, the address registration unit 30, the output unit 44, the overall processing timer 40, and the partial processing timer 42 are illustrated as components separate from the CPU 20, but these components may be configured as functions executed by the CPU 20. For example, in this embodiment, the address registration unit 30 may be configured by the CPU 20 starting the information processing device 10, determining the addresses of the respective functions stored in the ROM 22, and storing them in the RAM 24. Similarly, the overall processing timer 40, the partial processing timer 42, and the output unit 44 may be configured by the CPU 20 executing a subprogram. Also, instead of the CPU 20, a component such as a DMAC (Direct Memory Access Controller) (not shown) may execute a subprogram to assume the functions of the various components described above. In the flowchart of FIG. 3 below, a case in which the CPU 20 executes various functions and operations will be described.

[0024] Next, a method for measuring the CPU utilization rate in this embodiment will be described with reference to FIG.

[0025] (Method of measuring CPU usage) In the method for measuring the CPU utilization rate according to this embodiment, first, in step S102, the CPU 20 determines whether the program P has started. Then, while the CPU 20 makes a negative determination in step S102, that is, when the program P has not started, the CPU 20 waits by repeating step S102. Also, when the CPU 20 makes a positive determination in step S102, in other words, when the CPU 20 has started the program P, the CPU 20 proceeds to step S104.

[0026] Next, in step S104, the CPU 20 starts the overall processing timer 40. Then, the process proceeds to step S106.

[0027] Next, in step S106, the CPU 20 judges whether the instruction recorded in the function start address of the ROM 22 has been read. In other words, the CPU 20 judges whether the instruction recorded in the address registered in the destination address registration unit 32 has been read. Then, while the negative judgment is made in step S106, that is, while the CPU 20 has not read the instruction recorded in the function start address registered in the destination address registration unit 32, the CPU 20 waits by repeating step S106. Also, when the positive judgment is made in step S106, that is, when the CPU 20 has read the instruction recorded in the function start address, the CPU 20 proceeds to step S108. In other words, when the instruction recorded in the start of the address registration unit 30 in which the first function F1 is recorded is read into the CPU 20, or in other words, when the CPU 20 starts processing the first function F1, the CPU 20 proceeds to step S108.

[0028] Next, in step S108, the CPU 20 starts the partial processing timer 42. Then, the process proceeds to step S110.

[0029] Next, in step S110, the CPU 20 judges whether the instruction recorded in the function end address has been read. In other words, the CPU 20 judges whether the instruction recorded in the address registered in the rear address registration unit 34 has been read. Then, while the CPU 20 makes a negative judgment in step S110, that is, while the CPU 20 does not read the instruction recorded in the function end address registered in the rear address registration unit 34, the CPU 20 waits by repeating step S110. Also, when the CPU 20 makes a positive judgment in step S110, that is, when the CPU 20 reads the instruction recorded in the function end address, the CPU 20 proceeds to step S112. In other words, when the CPU 20 reads the instruction recorded at the end of the address registration unit 30 in which the first function F1 is recorded, or in other words, when the CPU 20 ends the processing of the first function F1, the CPU 20 proceeds to step S112.

[0030] Next, in step S112, the CPU 20 stops the partial processing timer 42. Then, the process proceeds to step S114.

[0031] Next, in step S114, the CPU 20 determines whether the program P has ended. Then, while the CPU 20 makes a negative determination in step S114, that is, when the program P has not ended, the CPU 20 waits by repeating step S114. Also, when the CPU 20 makes a positive determination in step S114, in other words, when the CPU 20 has ended the program P, the CPU 20 proceeds to step S116.

[0032] Next, in step S116, the CPU 20 stops the overall processing timer 40. Then, the process proceeds to step S118.

[0033] Next, in step S118, the CPU 20, as the output unit 44, calculates the CPU utilization rate based on the measurement values ​​of the partial processing timer 42 measured from steps S108 to S112 and the measurement values ​​of the overall processing timer 40 measured from steps S104 to S116. More specifically, the output unit 44 calculates the CPU utilization rate as shown in equation (1) based on the time elapsed from steps S108 to S112 and the time elapsed from steps S104 to S116. Then, the output unit 44 outputs the CPU utilization rate calculated based on equation (1).

[0034] In the above-mentioned method for measuring CPU utilization, there are no limitations on the specific start and stop times of the overall processing timer 40, so long as it starts before the partial processing timer 42 and stops after the partial processing timer 42. In other words, the elapsed time measured by the overall processing timer 40 is set to any period within the processing time of the program P for which measurement of the CPU utilization is desired.

[0035] In the information processing device 10 according to this embodiment, the time from when the CPU 20 reads an instruction recorded in a leading address of the first function F1 to when it reads an instruction recorded in a trailing address of the first function F1 is measured by the partial processing timer 42. Therefore, the time elapsed from when the CPU 20 executes an instruction recorded in a leading address to when it executes an instruction recorded in a trailing address is measured by the partial processing timer 42.

[0036] The information processing device 10 also has an overall processing timer 40 that measures the processing time required for processing the program P, and an output unit 44 that outputs the utilization rate of the CPU 20 calculated based on the elapsed time measured by the partial processing timer 42 and the processing time measured by the overall processing timer 40. Therefore, even if the instructions executed by the CPU 20 do not include a process for measuring the CPU utilization rate, it is possible to measure the CPU utilization rate when the CPU 20 processes instructions recorded from any leading address to any trailing address of the program P. In other words, according to the information processing device 10 of this embodiment, even an information processing device 10 with a simple configuration is able to measure the CPU utilization rate when the CPU 20 processes instructions recorded from any leading address to any trailing address of the program P.

[0037] Moreover, in the information processing device 10 according to the present embodiment, the front address is the start address of the first function F1, and the back address is the end address of the first function F1.

[0038] Therefore, according to the information processing device 10 of this embodiment, it is possible to measure the processing time of the CPU 20 required to execute the first function F1, that is, the utilization rate of the CPU 20 when the CPU 20 executes a subprogram.

[0039] The method for measuring CPU utilization according to this embodiment also includes a procedure for measuring the processing time for processing program P using overall processing timer 40. The method for measuring CPU utilization according to this embodiment also includes a procedure for measuring the elapsed time from the time an instruction recorded in a front address is read to the time an instruction recorded in a rear address is read. The method also includes a procedure for calculating the utilization of CPU 20 based on the elapsed time measured by partial processing timer 42 and the processing time measured by overall processing timer 40.

[0040] Furthermore, according to the method for measuring CPU utilization rate of this embodiment, the overall processing timer 40 and the partial processing timer 42 measure the time that has elapsed until the CPU 20 processes the instructions recorded from the first address to the latter address of the program P. In other words, according to the method for measuring CPU utilization rate of this embodiment, it is possible to measure the CPU utilization rate even in an information processing device 10 with a simple configuration in which the instructions executed by the CPU 20 cannot be provided with a process for measuring the CPU utilization rate.

[0041] Next, an information processing device 10 according to a second embodiment of the present disclosure will be described with reference to Fig. 4 and Fig. 5. Note that, in the information processing device 10 according to the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed descriptions thereof will be omitted.

[0042] [Second embodiment] (composition) Fig. 4 is a diagram showing the configuration of an information processing device 110 according to this embodiment. As shown in Fig. 4, the information processing device 110 according to this embodiment further includes a measurement unit 50, as compared with the information processing device 10 according to the first embodiment.

[0043] The measurement unit 50 has a function of storing the number of times the CPU 20 reads out an instruction. The measurement unit 50 also measures the number of times the CPU 20 according to this embodiment reads out an instruction at a forward address registered in the forward address registration unit 32 and the number of times the CPU 20 reads out an instruction at an address registered in the rear address registration unit 34. More specifically, when the CPU 20 reads out an instruction recorded in the start address of the first function F1, the measurement unit 50 increments the stored value by 1. When the CPU 20 reads out an instruction recorded in the end address of the first function F1, the measurement unit 50 decrements the stored value by 1.

[0044] In this embodiment, the number of times that the CPU 20 reads the instruction recorded in the start address of the first function F1 is an example of the "first number of times" in this embodiment. Also, the number of times that the CPU 20 reads the instruction recorded in the end address of the first function F1 is an example of the "second number of times" in this embodiment. That is, when the value stored by the measurement unit 50 is 0, this is an example of when the "first number of times and the second number of times are equal" in this embodiment.

[0045] In this embodiment, as shown in Fig. 1, the measurement unit 50 is illustrated as a separate component from the CPU 20, but this component may be configured as a function executed by the CPU 20. Also, for example, in this embodiment, the measurement unit 50 may assume the functions of the various components described above by storing numerical values ​​in the RAM 24 by a component such as a DMAC (not shown). The following flowchart in Fig. 5 will explain the case where the CPU 20 executes various functions and operations.

[0046] Other configurations are the same as those of the information processing device 10 according to the first embodiment. Next, a method for measuring the CPU utilization rate in this embodiment will be described with reference to FIG.

[0047] (Method of measuring CPU usage) First, in step S202, the CPU 20 judges whether the program P has been started. Then, while the judgment in step S202 is negative, that is, when the program P has not been started, the CPU 20 waits by repeating step S202. Also, when the judgment in step S202 is positive, in other words, when the CPU 20 has started the program P, the CPU 20 proceeds to step S204.

[0048] In step S204, the CPU 20 starts the overall processing timer 40. Then, the process proceeds to step S206.

[0049] Next, in step S206, the CPU 20 judges whether the CPU 20 has read the instruction recorded in the function start address of the ROM 22. In other words, the CPU 20 judges whether the CPU 20 has read the instruction recorded in the address registered in the destination address registration unit 32. Then, if the CPU 20 judges in step S206 as positive, that is, if the CPU 20 has read the instruction recorded in the function start address, the CPU 20 proceeds to step S208. In other words, if the instruction recorded in the start of the address registration unit 130 in which the first function F1 is recorded is read into the CPU 20, or in other words, if the CPU 20 starts processing the first function F1, the CPU 20 proceeds to step S208. On the other hand, if the CPU 20 judges in step S206 as negative, the CPU 20 proceeds to step S210.

[0050] Next, the CPU 20 increments the value of the measurement unit 50 by 1 in step S208, and proceeds to step S214.

[0051] Next, in step S214, the CPU 20 determines whether the value of the measurement unit 50 is 1 or greater. In other words, the CPU 20 determines the number of times the instruction recorded in the function start address has been read. If the value of the measurement unit 50 is 1 or greater, the process proceeds to step S216. On the other hand, if the value of the measurement unit 50 is less than 1 (i.e., 0), the process proceeds to step S218.

[0052] Next, in step S216, CPU 20 starts the partial processing timer 42, and proceeds to step S206. Note that, as described below, in the CPU 20 measurement method according to this embodiment, there are cases where the process proceeds to step S216 with the partial processing timer 42 running, but in this case, the partial processing timer 42 does not change from the running state and continues measuring the elapsed time.

[0053] Also, in step S210, it is determined whether the CPU 20 has read the instruction recorded in the function end address. In other words, it is determined whether the CPU 20 has read the instruction recorded in the address registered in the rear address registration unit 34. Then, if the determination in step S210 is affirmative, that is, if the CPU 20 has read the instruction recorded in the function end address, the process proceeds to step S212. In other words, if the instruction recorded in the end of the address registration unit 130 in which the first function F1 is recorded is read by the CPU 20, or in other words, if the CPU 20 has finished processing the first function F1, the process proceeds to step S212. On the other hand, if the determination in step S210 is negative, the process proceeds to step S206.

[0054] Next, the CPU 20 decrements the value of the measurement unit 50 by 1 in step S212, and proceeds to step S214.

[0055] Furthermore, in step S218, the CPU 20 stops the partial processing timer 42. Then, the process proceeds to step S220.

[0056] Next, in step S220, the CPU 20 determines whether the program P has ended. Then, while the CPU 20 makes a negative determination in step S220, that is, when the program P has not ended, the CPU 20 waits by repeating step S220. Also, when the CPU 20 makes a positive determination in step S220, in other words, when the CPU 20 has ended the program P, the CPU 20 proceeds to step S222.

[0057] Next, in step S222, the CPU 20 stops the overall processing timer 40. Then, the process proceeds to step S224.

[0058] Next, the CPU 20, as the output unit 44, calculates the CPU utilization rate based on the measurement value of the partial processing timer 42 measured from steps S216 to S218 and the measurement value of the overall processing timer 40 measured from steps S204 to S222. More specifically, the output unit 44 calculates the CPU utilization rate as shown in formula (1) based on the time elapsed from steps S216 to S218 and the time elapsed from steps S204 to S222. Then, the output unit 44 outputs the CPU utilization rate calculated based on formula (1).

[0059] 2 has a recursive process, the CPU 20 may read the top address again while reading instructions from the top to the bottom of the first function F1. In other words, if the first function F1 has a recursive process, the top address may be read multiple times.

[0060] Furthermore, if the first function F1 has a recursive process, after the CPU 20 reads the end address, the CPU 20 may read the instruction recorded at the address before the start address is read in the recursive process again. In other words, if the first function F1 has a recursive process, even if the end address is read, the process related to the first function F1 may not end.

[0061] In the information processing device 110 according to this embodiment, the measurement unit 50 measures a first number, which is the number of times an instruction recorded in a start address is read, and a second number, which is the number of times an instruction recorded in an end address is read. Then, the output unit 44 outputs the utilization rate of the CPU 20 when the first number and the second number measured by the measurement unit 50 become equal. In other words, the output unit 44 in this embodiment continues to execute the partial processing timer 42 until the processing of the first function F1, which is executed multiple times by recursive processing, is completed.

[0062] According to the information processing device 110 of this embodiment, even when the instruction recorded at the start address is repeatedly read by recursive processing, the partial processing timer 42 continues to measure the elapsed time. Even when the instruction recorded at the end address is read by recursive processing, the execution of the partial processing timer 42 continues until the processing of the first function F1 is completed. Therefore, according to the information processing device 110 of this embodiment, it is possible to measure the time that has elapsed since the instruction recorded at the start address of the first function F1 was first read until the instruction recorded at the end address of the first function F1 was last read.

[0063] In this embodiment, the same functions and effects as those of the first embodiment can be obtained with the same configuration as that of the first embodiment.

[0064] Next, an information processing device 210 according to a third embodiment of the present disclosure will be described with reference to Fig. 6 to Fig. 11. Note that, in the information processing device 210 according to the third embodiment, the same components as those in the first or second embodiment are denoted by the same reference numerals as those in the first or second embodiment, and detailed description thereof will be omitted.

[0065] [Third embodiment] (composition) Fig. 6 is a diagram showing a configuration of an information processing device 210 according to this embodiment. As shown in Fig. 6, the information processing device 210 according to this embodiment further includes a stack unit 250, as compared with the information processing device 10 according to the first embodiment. In addition, in the information processing device 210 according to this embodiment, the partial processing timer 42 includes a first partial processing timer 42A, a second partial processing timer 42B, and a third partial processing timer 42C. In addition, in the information processing device 210 according to this embodiment, the address registration unit 230 includes a first address registration unit 230A, a second address registration unit 230B, and a third address registration unit 230C.

[0066] The specific configurations and functions of the first partial processing timer 42A, the second partial processing timer 42B, and the third partial processing timer 42C are the same as those of the partial processing timer 42 according to the first embodiment. Each partial processing timer 42 is identified by a timer ID. In the description of this embodiment, when there is no need to distinguish between the first partial processing timer 42A, the second partial processing timer 42B, and the third partial processing timer 42C, they will simply be referred to as the partial processing timer 42.

[0067] The specific configurations and functions of the first address registration unit 230A, the second address registration unit 230B, and the third address registration unit 230C are the same as those of the address registration unit 230 according to the first embodiment. As shown in FIG. 2, the first destination address registration unit 32A, which is the destination address registration unit 32 of the first address registration unit 230A, has registered therein "AAAA_AAAA", which is the first address of the address area AS in which the first function F1 is recorded. Also, the first back address registration unit 34A, which is the destination address registration unit 32 of the first address registration unit 230A, has registered therein "BBBB_BBBB", which is the end address of the address area AS in which the first function F1 is recorded. Similarly, the second destination address registration unit 32B has registered therein "CCCC_CCCC", which is the first address of the address area AS in which the second function F2 is recorded. Also, the second back address registration unit 34B has registered therein "DDDD_DDDD", which is the end address of the address area AS in which the second function F2 is recorded. Similarly, the third destination address registration unit 32C has registered therein "EEEE_EEEE", which is the first address of the address area AS in which the third function F3 is recorded. The third back address registration unit 34C has registered therein "FFFF_FFFF", which is the last address of the address area AS in which the third function F3 is recorded.

[0068] The stack unit 250 is a storage device that holds data in a First In Last Out (FILO) structure. The stack unit 250 according to this embodiment stores timer IDs (names of partial processing timers 42). Specifically, as shown in FIG. 8, when a timer ID is stored (when pushed to the stack unit 250), the timer ID is stored at the top. Also, as shown in FIG. 9, when a timer ID is removed from the stack unit 250 (when popped from the stack unit 250), the timer ID at the top is removed, and the other timer IDs move to the top in order. That is, the stack unit 250 according to this embodiment can be said to be another example of the measurement unit 50 according to the second embodiment.

[0069] In this embodiment, the timer ID is associated with the name of the function. For example, the first sub-processing timer 42A is associated with the first function F1. Similarly, the second sub-processing timer 42B is associated with the second function F2, and the third sub-processing timer 42C is associated with the third function F3.

[0070] In this embodiment, the CPU 20 has a function of storing the number of times that the CPU 20 reads out the instructions of each of the first function F1, the second function F2, and the third function F3.

[0071] The output unit 44 in this embodiment is configured to output the CPU utilization rate calculated based on the measurement results by the overall processing timer 40 and the partial processing timer 42 in a method for measuring the CPU utilization rate, which will be described later. In this embodiment, the output unit 44 calculates the CPU utilization rate in accordance with the following formula (2) in the method for measuring the CPU utilization rate, which will be described later.

[0072]

number

[0073] In addition, in the formula (2), T Nis a measurement value of either the first partial processing timer 42A, the second partial processing timer 42B, or the third partial processing timer 42C, and T A is the measurement value of the overall processing timer 40.

[0074] Other configurations are the same as those of the information processing device 110 according to the second embodiment. Next, a method for measuring the CPU utilization rate in this embodiment will be described with reference to FIG.

[0075] (Method of measuring CPU usage) In the method for measuring the CPU utilization rate according to this embodiment, first, in step S302, the CPU 20 determines whether the program P has started. Then, while the CPU 20 makes a negative determination in step S302, that is, when the program P has not started, the CPU 20 waits by repeating step S302. Also, when the CPU 20 makes a positive determination in step S302, in other words, when the CPU 20 has started the program P, the CPU 20 proceeds to step S304.

[0076] Next, in step S304, the CPU 20 starts the overall processing timer 40. Then, the process proceeds to step S306.

[0077] Next, the CPU 20 judges whether the instruction recorded in the head address of the first function F1, the second function F2, or the third function F3 has been read in step S306. In other words, the CPU 20 judges whether the instruction recorded in the address registered in any of the first destination address registration unit 32A, the second destination address registration unit 32B, or the third destination address registration unit 32C has been read. Then, if the CPU 20 judges in step S306 as positive, that is, if the CPU 20 has read the instruction recorded in the head address of the first function F1, the second function F2, or the third function F3, the CPU 20 proceeds to step S308. In other words, if the CPU 20 has read the instruction recorded in the head of the address registration unit 230 in which any of the first function F1, the second function F2, or the third function F3 is recorded, the CPU 20 proceeds to step S308. In other words, when the CPU 20 starts processing any one of the first function F1, the second function F2, or the third function F3, the process proceeds to step S308. On the other hand, when the CPU 20 makes a negative decision in step S306, the process proceeds to step S310.

[0078] Next, in step S308, the CPU 20 stores the IDs associated with the first function F1, the second function F2, and the third function F3 in the stack section 250, and proceeds to step S316.

[0079] Next, in step S316, CPU 20 determines whether the number of IDs stored in stack section 250 is 1 or more. If the number of IDs stored in stack section 250 is 1 or more, CPU 20 proceeds to step S318. On the other hand, if the number of IDs stored in stack section 250 is less than 1 (i.e., 0), CPU 20 proceeds to step S320.

[0080] Next, in step S318, the CPU 20 starts the partial processing timer 42 for the timer ID stored first in the stack section 250, stops the partial processing timers 42 for the other IDs, and proceeds to step S306. Note that in this embodiment as well, there are cases where the process proceeds to step S318 with the partial processing timer 42 for the first timer ID in the stack section 250 still running, but in this case, measurement of the elapsed time continues as in the second embodiment.

[0081] Also, in step S310, the CPU 20 judges whether the CPU 20 has read an instruction recorded at the end address of the first function F1, the second function F2, or the third function F3. In other words, the CPU 20 judges whether the CPU 20 has read an instruction recorded at an address registered in any of the first rear address registration unit 34A, the second rear address registration unit 34B, or the third rear address registration unit 34C. That is, when the CPU 20 has read an instruction recorded at the end address of the first function F1, the second function F2, or the third function F3, the process proceeds to step S312. In other words, when the CPU 20 has read an instruction recorded at the end of the address registration unit 230 in which any of the first function F1, the second function F2, or the third function F3 is recorded, the process proceeds to step S318. In other words, when the CPU 20 has completed the processing of any of the first function F1, the second function F2, or the third function F3, the process proceeds to step S318. On the other hand, if a negative determination is made in step S310, the process proceeds to step S306.

[0082] Furthermore, the CPU 20 stops the sub-processing timers 42 associated with the first function F1, the second function F2, and the third function F3 in step S312, and then proceeds to step S324.

[0083] Next, the CPU 20 extracts one timer ID from the stack section 250 in step S314, and proceeds to step S316.

[0084] Next, in step S320, the CPU 20 determines whether the CPU 20 has ended the program P. Then, while the CPU 20 makes a negative determination in step S320, that is, when the program P has not ended, the CPU 20 waits by repeating step S320. Also, when the CPU 20 makes a positive determination in step S320, in other words, when the CPU 20 has ended the program P, the CPU 20 proceeds to step S322.

[0085] Next, in step S322, the CPU 20 stops the overall processing timer 40. Then, the process proceeds to step S324.

[0086] Next, in step S324, the CPU 20, as the output unit 44, calculates the CPU utilization rate based on the measurement values ​​of the partial processing timer 42 measured from steps S316 to S318 and the measurement values ​​of the overall processing timer 40 measured from steps S304 to S322. More specifically, the output unit 44 calculates the CPU utilization rate as shown in equation (2) based on the time elapsed from steps S316 to S318 and the time elapsed from steps S304 to S322. Then, the output unit 44 outputs the CPU utilization rates of the first function F1, the second function F2, and the third function F3 calculated based on equation (2).

[0087] Moreover, a more specific processing procedure of the method for measuring the CPU utilization rate in the information processing device 210 according to this embodiment will be described with reference to FIG.

[0088] In this processing procedure, first, in state 0 (initial state), execution of the program P is started. Next, in state 1, the first function F1 is executed, but during the execution of the first function F1, the second function F2 is executed, and the processing of the first function F1 is temporarily stopped. After the execution of the second function F2 is completed in state 2, the processing of the first function F1 is resumed. After the processing of the first function F1 is resumed in state 3, the third function F3 is executed, and the processing of the first function F1 is temporarily stopped. Then, in states 4 to 6, the third function F3 is processed recursively only once, and then the processing is completed. Then, after the processing of the third function F3 is completed, the processing of the first function F1 is resumed in state 7. Then, the processing of the first function F1 is completed in state 8, and the processing of the program P is completed.

[0089] First, in state 0, the first partial processing timer 42A, the second partial processing timer 42B, and the third partial processing timer 42C are stopped, and the overall processing timer 40 is started. This corresponds to steps S302 and S304.

[0090] Next, the first partial processing timer 42A is started in state 1. This corresponds to the processes in the order of step S306, step S308, step S316, and step S318 after the initial state.

[0091] Next, the second partial process timer 42B starts and the first partial process timer 42A stops in state 2. This corresponds to the processes in the order of step S306, step S308, step S316, and step S318 after state 1.

[0092] Next, the second partial process timer 42B stops and the first partial process timer 42A starts in state 3. This corresponds to the processes after state 2, in the order of step S306, step S310, step S312, step S314, step S316, and step S318.

[0093] Next, the third partial processing timer 42C starts and the first partial processing timer 42A stops in state 4. This corresponds to the processes in the order of step S306, step S308, step S316, and step S318 after state 3.

[0094] Next, the third partial processing timer 42C continues to run in state 5. This corresponds to the processes after state 4, that is, steps S306, S308, S316, and S318.

[0095] Next, the third partial processing timer 42C continues to run in state 6. This corresponds to the processes in the order of step S306, step S308, step S316, and step S318 after state 5.

[0096] Next, the third partial processing timer 42C stops and the first partial processing timer 42A starts in state 7. This corresponds to the processes after state 6, in the order of step S306, step S310, step S312, step S314, step S316, and step S318.

[0097] Next, the first partial processing timer 42A is stopped in state 8. This corresponds to the processes after state 7, in the order of step S306, step S310, step S312, step S314, step S316, and step S320.

[0098] The information processing device 210 according to this embodiment has a plurality of partial processing timers 42. Furthermore, the output section 44 outputs the utilization rate of the CPU 20 for each of a plurality of elapsed times measured by the plurality of partial processing timers 42.

[0099] Therefore, according to the information processing device 210 of this embodiment, it is possible to measure the CPU utilization rate when the CPU 20 processes each instruction recorded in a plurality of address ranges in the program P.

[0100] In this embodiment as well, the same functions and effects as those of the first to third embodiments can be obtained if the configuration is the same as that of the first or second embodiment.

[0101] Next, an information processing device 10 according to a fourth embodiment of the present disclosure will be described with reference to Fig. 12. Note that, in the information processing device 10 according to the fourth embodiment, the same components as those in the first to third embodiments are denoted by the same reference numerals as those in the first to third embodiments, and detailed description thereof will be omitted.

[0102] [Fourth embodiment] (composition) Fig. 12 is a diagram showing the address registration unit 330 of the information processing device 10 according to this embodiment. As shown in Fig. 12, in the information processing device 10 according to this embodiment, a plurality of addresses are registered in the first destination address registration unit 32A, the first destination address registration unit 34A, and the second destination address registration unit 34B.

[0103] More specifically, the first destination address registration unit 32A has registered therein the start address of the first function F1 and the start address of the second function F2, and the first destination address registration unit 34A has registered therein the end address of the first function F1 and the end address of the second function F2. Also, the second destination address registration unit 34B has registered therein the middle address of the third function F3 and the end address of the third function F3.

[0104] Other configurations are the same as those of the information processing device 10 according to the second or third embodiment. Next, a method for measuring the CPU utilization rate in this embodiment will be described.

[0105] (Method of measuring CPU usage) The method of measuring the CPU utilization rate by the information processing device 10 in this embodiment is similar to that of the information processing device 10 in the second or third embodiment.

[0106] For example, the CPU 20 starts the first partial processing timer 42A when it reads an instruction of the first function F1 start address or the second function F2 start address registered in the first destination address registration unit 32A. Then, the CPU 20 stops the first partial processing timer 42A when it reads an instruction of the first function F1 end address or the second function F2 end address registered in the first destination address registration unit 34A.

[0107] That is, both the CPU utilization rate when the CPU 20 executes the processing of the first function F1 and the CPU utilization rate when the CPU 20 executes the processing of the second function F2 are measured by the first sub-processing timer 42A.

[0108] For example, when the CPU 20 reads an instruction for the start address of the third function F3 registered in the second destination address registration unit 32B, the CPU 20 starts the second partial processing timer 42B. Then, when the CPU 20 reads an instruction for the middle address or the end address of the third function F3 registered in the second destination address registration unit 32B, the CPU 20 stops the second partial processing timer 42B.

[0109] In other words, in the method of measuring CPU usage in this embodiment, both the CPU usage when the CPU 20 executes the processing of the third function F3 from start to finish, and the CPU usage when the CPU 20 executes the processing of the third function F3 halfway through are measured by the first partial processing timer 42A.

[0110] In the information processing device 10 according to the present embodiment, addresses of a plurality of functions are registered in the first destination address registration unit 32A and the first destination address registration unit 34A. Therefore, according to the information processing device 10 according to the present embodiment, the CPU utilization rate when the CPU 20 processes each of the plurality of functions can be measured by one partial processing timer 42.

[0111] Furthermore, in the information processing device 10 according to the present embodiment, an intermediate address of the third function F3 is registered in the second back address registration unit 34B. Therefore, according to the information processing device 10 according to the present embodiment, the CPU usage rate when the CPU 20 processes a part of the function can be measured by the partial processing timer 42.

[0112] [Other embodiments] In the above description, the leading address of the first function F1, the second function F2, or the third function F3 is registered in the leading address registration unit 32, but the technology according to the present disclosure is not limited to this. Similarly, the trailing address registration unit 34 is registered with the trailing address of the first function F1, the second function F2, or the third function F3, but the technology according to the present disclosure is not limited to this. That is, the leading address of the instruction to be read in sequence in any of the functions may be registered in the leading address registration unit 32, and the trailing address of the instruction to be read in sequence in any of the functions may be registered in the trailing address registration unit 34. In this case, as in the fourth embodiment, it is possible to measure the CPU usage rate when the CPU 20 processes an instruction registered in a leading address to an instruction registered in a trailing address.

[0113] The above describes an embodiment of the present disclosure with reference to the attached drawings. However, it is clear that a person with ordinary knowledge in the technical field to which the present disclosure pertains can conceive of various modifications or applications within the scope of the technical ideas described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0114] Furthermore, preferred aspects of the present disclosure will be described below.

[0115] (Appendix 1) An overall processing timer that measures the time it takes for the CPU to process the entire program; a partial processing timer that measures the elapsed time from when the CPU reads an instruction recorded in a forward address, which is an arbitrary address among addresses at which instructions constituting the program are stored, to when the CPU reads an instruction recorded in a rear address that is later than the forward address; an output unit that outputs the CPU usage rate calculated based on the elapsed time measured by the partial processing timer and the processing time measured by the entire processing timer; An information processing device comprising:

[0116] (Appendix 2) a measurement unit that measures a first number of times that the command recorded in the first address is read and a second number of times that the command recorded in the second address is read; Further equipped with the output unit outputs the CPU usage rate when the first number of times measured by the measurement unit becomes equal to the second number of times. 2. An information processing device according to claim 1.

[0117] (Appendix 3) The partial processing timer is provided in plurality, The plurality of partial processing timers each measure an elapsed time until an instruction recorded from a different arbitrary forward address to a different arbitrary rear address is read; the output unit outputs the utilization rate of the CPU for each of a plurality of elapsed times measured by a plurality of sub-processing timers. 3. An information processing device according to claim 1 or 2.

[0118] (Appendix 4) The program includes a subprogram, the first address is an address at which a leading instruction among the instructions constituting the subprogram is recorded, The latter address is an address at which a final instruction among the instructions constituting the subprogram is recorded. 4. An information processing device according to any one of claims 1 to 3.

[0119] (Appendix 5) a step of measuring a processing time required for a CPU to process the entire program recorded in a recording unit by using an entire processing timer; a step of measuring, using a partial processing timer, the elapsed time from the time when the CPU reads an instruction recorded in a first address, which is an arbitrary address among addresses at which instructions constituting a program are stored, to the time when the CPU reads an instruction recorded in a second address, which is an address subsequent to the first address; a step of outputting the CPU usage rate calculated based on the elapsed time measured by the partial processing timer and the processing time measured by the entire processing timer; How to measure CPU usage, including: [Explanation of symbols]

[0120] 10, 110, 210 Information processing device 20 CPU 22 ROM (an example of a recording unit) 24 RAM 26 Peripheral Circuits 30, 130, 230, 330 Address Registration Section 30A First Address Registration Section 30B Secondary address registration section 30C Third Address Registration Section 32 Destination address registration section 34 Rear address registration section 32A First Destination Address Registration Section 34A First rear address registration section 32B Secondary Address Registration Section 34B Second rear address registration section 32C Third Party Address Registration Section 34C Third rear address registration section 40 Overall Processing Timer 42 Partial Processing Timer 42A First partial processing timer 42B Second partial processing timer 42C Third partial processing timer 50 Measuring part 250 Stack Section AS Address Space P Program F1 First function (an example of a subprogram) F2 Second function (an example of a subprogram) F3 Third function (an example of a subprogram) 44 Output section

Claims

1. an overall processing timer for measuring the processing time taken by the CPU to process the entire program; a partial processing timer that measures the elapsed time from a time when the CPU reads an instruction recorded in a leading address, which is an arbitrary address among addresses at which instructions constituting the program are stored, to a time when the CPU reads an instruction recorded in a trailing address that is later than the leading address; an output unit that outputs the CPU usage rate calculated based on the elapsed time measured by the partial processing timer and the processing time measured by the entire processing timer; An information processing device comprising:

2. a measurement unit that measures a first number of times that the command recorded in the first address is read and a second number of times that the command recorded in the second address is read; Further equipped with the output unit outputs the CPU usage rate when the first number of times measured by the measurement unit becomes equal to the second number of times. The information processing device according to claim 1 .

3. The partial processing timer is provided in plurality, The plurality of partial processing timers each measure an elapsed time until an instruction recorded from a different arbitrary forward address to a different arbitrary rear address is read; the output unit outputs the utilization rate of the CPU for each of a plurality of elapsed times measured by a plurality of sub-processing timers. The information processing device according to claim 1 .

4. The program includes a subprogram, the first address is an address at which a leading instruction among the instructions constituting the subprogram is recorded, The latter address is an address at which a final instruction among the instructions constituting the subprogram is recorded. The information processing device according to claim 1 .

5. a step of measuring a processing time required for the CPU to process the entire program recorded in the recording unit by using an overall processing timer; a step of measuring, using a partial processing timer, the elapsed time from the time when the CPU reads an instruction recorded in a first address, which is an arbitrary address among addresses at which instructions constituting a program are stored, to the time when the CPU reads an instruction recorded in a second address, which is an address subsequent to the first address; a step of outputting the CPU usage rate calculated based on the elapsed time measured by the partial processing timer and the processing time measured by the entire processing timer; A method for measuring CPU utilization, comprising:

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