Packaging substrate, method for manufacturing element package, and method for manufacturing packaging substrate

Abstract

To provide a packaging substrate which uses a glass core and in which an element package having a recess portion formed on the upper surface thereof is inserted into a cavity portion, and a method for manufacturing the same.SOLUTION: A packaging substrate includes a core layer comprising a glass core and a cavity portion, wherein the glass core is a glass substrate having a first surface and a second surface facing each other, the cavity portion is a portion obtained by recessing a part of the glass core or penetrating the glass core, and has a storage space for storing an electronic element 40. An element package 80 is disposed in the storage space of the cavity portion, the element package includes a molding portion 64 that contains a plurality of arranged electronic elements and a molding material and that is arranged to encase the electronic element. A recess portion 81 on which an array of dimples is arranged is disposed in the molding portion of the element package.SELECTED DRAWING: Figure 8A

Description

[Technical field]

[0001] This document relates to packaging substrates, methods of manufacturing device packages, methods of manufacturing packaging substrates, and the like. [Background technology]

[0002] In the manufacture of electronic components, the process of forming circuits on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE). This back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology.

[0004] Semiconductor technology has evolved into various forms, including nano-level line widths below the micron level, more than 10 million cells, high-speed operation, and large amounts of heat emission, but the technology to perfectly package these has not been fully supported.

[0005] As a result, the electrical performance of a semiconductor may be determined by the packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0006] The packaging substrate is made of ceramic or resin. Ceramic substrates such as silicon substrates have high resistance or high dielectric constant, so it is not easy to mount high-performance, high-frequency semiconductor elements on them. Resin substrates can mount relatively high-performance, high-frequency semiconductor elements, but there is a limit to how much the wiring pitch can be reduced.

[0007] Recently, silicon or glass can be applied to high-end packaging substrates. By forming through holes in the silicon or glass substrate and applying a conductive material to the through holes, the wiring length between the device and the motherboard can be shortened, resulting in excellent electrical characteristics.

[0008] Related prior art includes Korean Patent Publication No. 10-2023-0029115 and Korean Patent Publication No. 10-2015-0143309. Summary of the Invention [Problem to be solved by the invention]

[0009] The purpose of the embodiment is to provide a packaging substrate using a glass core, in which an element package (element molding package) having a recess formed on the upper surface is inserted into a cavity portion, and a packaging substrate using the same.

[0010] In addition, an object of the embodiment is to provide a method for manufacturing an element package that maintains the arrangement distance of elements by using a mold having a protrusion formed on the top of the mold, and a packaging substrate using the same. [Means for solving the problem]

[0011] In order to achieve the above object, one embodiment provides a packaging substrate, a method for manufacturing a device package, and a method for manufacturing a packaging substrate.

[0012] The packaging substrate according to the present specification includes a core layer, the core layer including a glass core and a cavity portion, the glass core being a glass substrate having a first surface and a second surface facing each other, the cavity portion being a portion of the glass core recessed or penetrated and having an accommodating space for accommodating an electronic element, an element package being disposed in the accommodating space of the cavity portion, the element package including i) a plurality of arranged electronic elements, and ii) a molding portion containing a molding material and arranged so that the molding material encases the electronic element, and the element package includes a recess in which dimples are arranged in the molding portion.

[0013] The dimples may be located between adjacent electronic elements.

[0014] The recessed portion may include a large number of dimples arranged in a dotted line shape when viewed from the first surface to the second surface.

[0015] The packaging substrate may further include an insulating layer disposed on the cavity portion.

[0016] The dimples of the recess may be filled with an insulating material of the insulating layer.

[0017] The molding material may include liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF), or modified polyimide (MPI).

[0018] The insulating layer includes an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin.

[0019] The cavity portion may be located at a boundary between the molding portion and the insulating layer.

[0020] The boundary may have a recess having a dimple that is concave toward the electronic element.

[0021] In order to achieve the above object, a method for manufacturing an element package according to one embodiment includes an element placement step of providing a mold having an injection port and placing an electronic element at a predetermined position of the mold, an injection step of injecting a molding material into the injection port, and a mold formation step of hardening the molding material to form a molding part, to manufacture the above-mentioned element package.

[0022] The mold has a protruding portion with an array of protrusions arranged around the injection port, the element package includes a molding portion that includes an array of electronic elements and a molding material and is arranged to encase the electronic elements, and the element package has a recessed portion in which dimples are arranged arranged in the molding portion, and the recessed portion and the protruding portion are positioned corresponding to each other.

[0023] In the element placement step, the electronic element may be placed on an adhesive surface and fixed in position.

[0024] The position at which the electronic element is disposed in the mold forming step is substantially the same as the position at which the electronic element is disposed in the element disposing step.

[0025] The protrusions may be disposed between adjacent electronic elements.

[0026] The device package may be produced by a transfer molding process using a transfer mold having a protrusion formed on the top of the mold.

[0027] Meanwhile, in order to achieve the above object, a manufacturing method of a packaging substrate according to one embodiment includes the steps of providing a glass core having a cavity portion and an element package, disposing the element package in the cavity portion, and disposing an insulating material on the glass core or the cavity portion and hardening it to form an insulating layer, thereby manufacturing the above-mentioned packaging substrate.

[0028] In the step of forming the insulating layer, the insulating material flows and a part of it can move to the concave portion of the dimple on the cavity element. Effect of the Invention

[0029] The method for manufacturing a packaging substrate and a packaging substrate using the same according to the embodiment may produce a device package while maintaining a distance between electronic devices, thereby preventing short circuits of the electronic devices.

[0030] In addition, by using a mold having a protrusion formed on the top, the position of the electronic elements can be prevented from being changed during the molding process, thereby preventing contact between the electronic elements and preventing problems such as the occurrence of short circuits. [Brief description of the drawings]

[0031] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5]1 is a flowchart illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] FIG. 1 is a flow chart illustrating in cross section the process of producing a device package using a conventional transfer molding process, where (a) shows the process of attaching a mold to a lower part, (b) shows the process of arranging the device, and (c) shows the process of injecting the molding material (F stands for flow). [Figure 7] 1 is a flowchart illustrating, in cross section, the process of producing a device package through a transfer molding process according to an embodiment, where (a) shows the process of attaching a mold to a lower part, (b) shows the process of arranging a device, and (c) shows the process of injecting a molding material (F stands for flow). [Figure 8A] 1 is a conceptual cross-sectional view illustrating a device package produced by a transfer molding process using a transfer mold having a protrusion according to an embodiment; [Figure 8B] 1 is a conceptual cross-sectional view illustrating a device package produced by a transfer molding process using a transfer mold having a protrusion according to an embodiment; [Figure 8C] 1 is a conceptual cross-sectional view illustrating a device package produced by a transfer molding process using a transfer mold having a protrusion according to an embodiment; [Figure 9A] 1 is a conceptual diagram illustrating a transfer mold having protrusions formed according to an embodiment, and a portion of a device package produced by the transfer mold; [Figure 9B] 1 is a conceptual diagram illustrating a transfer mold having protrusions formed according to an embodiment, and a portion of a device package produced by the transfer mold; [Figure 10A] 1 is a conceptual diagram illustrating a transfer mold having protrusions formed according to an embodiment, and a portion of a device package produced by the transfer mold; [Figure 10B] 1 is a conceptual diagram illustrating a transfer mold having protrusions formed according to an embodiment, and a portion of a device package produced by the transfer mold; [Figure 11] 1 is a flowchart illustrating, in cross-section, a method for manufacturing a packaging substrate according to an embodiment, in which (a) shows a process for providing a molding package, (b) shows a process for inserting the molding package into a cavity space, (c) shows a process for forming an upper insulating layer, (d) shows a process for forming a lower insulating layer, and (e) shows a process for hardening the upper insulating layer and the lower insulating layer. BEST MODE FOR CARRYING OUT THEINVENTION

[0032] The following detailed description is provided to facilitate a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalents of the method, device and / or system described herein will become apparent after the contents presented in this application are understood. For example, the order of operations described herein is merely exemplary and is not limited to the operations described herein. Except for steps that necessarily proceed in a certain order, the order of operations may be changed depending on the understanding of the contents presented in this application. In addition, the description of known features may be omitted to improve clarity and conciseness after the disclosure of this application is understood. However, the omission of such features and their descriptions is not intended to be an admission of common knowledge.

[0033] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein, but rather the embodiments described herein are provided to illustrate some of the many possible ways of implementing the methods, apparatus and / or systems described herein that will become apparent after reading the present disclosure.

[0034] As used herein, terms such as "first," "second," and "third" may be used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections to these words. Instead, such terms are used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in any embodiment described herein could also be a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0035] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "bonded" to another element, it may be described as being directly "on," "connected," or "bonded" to the other element, or there may be one or more intervening elements between them. In contrast, when an element is described as being "directly on," "directly connected," or "directly bonded," there may not be any other intervening elements between them. Similarly, expressions such as "between" and "directly between," and "adjacent" and "directly adjacent" may be interpreted as previously described.

[0036] The terms used herein are merely for describing particular examples and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any one or more combinations of the associated listed items. As used herein, the terms "comprises," "comprises," and "has" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the use of the term "can" in connection with an example or embodiment (e.g., what the example or embodiment can include or embody) means that there is at least one example or embodiment in which such feature is included or embodied, but not all examples are limited thereto.

[0037] In this application, "B is located on A" means that B is in direct contact with A or that B is disposed on A with another layer or structure therebetween, and therefore should not be construed as B being in direct contact with A.

[0038] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0039] In one or more of the above examples, the term "A and / or B" means "A, B, or A and B."

[0040] In one or more of the above examples, terms such as "first," "second," "A," or "B" are used to distinguish identical terms from one another.

[0041] In one or more of the above instances, the singular forms are to be construed as including the plural forms as well as the singular forms unless specifically stated otherwise.

[0042] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0043] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0044] The packaging substrate 20 according to an embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which an electronic element 40 can be disposed.

[0045] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0046] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0047] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0048] The core layer 22 may include a glass core 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness, a plurality of core vias 23 penetrating the glass core 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass core 21 or the core vias 23 and electrically connecting a first surface 213 of the glass core 21 to a second surface 214 opposite the first surface via the core vias 23.

[0049] The second region 222 of the core layer 22 may serve as a cavity structure.

[0050] Within the same area, the glass core 21 has a first surface 213 and a second surface 214 opposed to each other, and the two surfaces are generally parallel to each other, so that the glass core 21 has a constant thickness throughout.

[0051] An internal space 281 formed by the difference in thickness between the first region 221 and the second region 222 serves to accommodate a part or the whole of the electronic element 40 .

[0052] The glass core 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first region 221 and the second region 222 and may be formed at any desired pitch and pattern.

[0053] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0054] In the embodiment, to solve this problem, the glass core 21 is used as a support for the core layer 22. In addition, by using the glass core 21 and the core via 23 formed penetrating the glass core 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0055] The glass core 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0056] The core via 23 penetrates the glass core 21. The core via 23 may be formed by removing a predetermined region of the glass core 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0057] Specifically, the formation of the core via 23 may be achieved by forming a defect (scratch) on the surface of the glass core using a method such as a laser, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0058] The core vias 23 may be positioned in a number of 100 to 3000, 100 to 2500, or 225 to 1024 per unit area (1 cm×1 cm) of the glass core 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0059] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass core through a through via, and a core insulating layer 223 that encases the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass core 21, and connects the upper and lower parts of the glass core over a relatively short distance, allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0060] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0061] The electronic element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0062] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the electronic element 40 and the core distribution layer 24, and an insulating layer that encases the cavity distribution pattern.

[0063] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed by the same process as the process of forming the core via 23, and the area and shape penetrating the glass core 21 may be different from those of the core via 23.

[0064] In this embodiment, an insulating layer may be formed in the cavity after the electronic device 40 is arranged in the cavity. That is, an insulating layer may be formed in the cavity through the process of forming the core insulating layer 223 described above.

[0065] The core distribution pattern 241 may be patterned so as to be electrically connectable to the electronic element 40 .

[0066] The electronic element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0067] When an element such as a transistor that converts electrical signals between a motherboard and a semiconductor element portion to an appropriate level is applied as the electronic element 40, a transistor or the like is applied to the passage of the packaging substrate 20, so that a more efficient and faster semiconductor device 100 can be provided.

[0068] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0069] Meanwhile, the electronic device 40 may be applied by inserting passive devices such as capacitors individually, or a device group including a number of passive devices embedded between insulating layers (electronic device insulating layers) may be formed with electrodes exposed and then inserted into the electronic device. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex devices.

[0070] The glass core 21 acts as an intermediate or mediator connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting electrical signals, thereby ensuring smooth signal transmission.

[0071] A top layer 26 is positioned on the first surface 213 .

[0072] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0073] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251, which is an electrically conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, embedded in the upper insulating layer 253. The upper distribution pattern 251 can be connected to an upper or lower electrically conductive layer through a blind via 252.

[0074] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0075] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0076] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0077] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0078] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval each of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0079] The upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253 and at least a portion of which is electrically connected to the upper distribution pattern 251, and an upper connection electrode 271 electrically connecting the semiconductor element portion 30 and the upper connection pattern 272.

[0080] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by a method such as plating, and when the upper surface connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching.

[0081] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0082] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0083] The cavity portion 28 is located above and / or below the second region 222 and includes a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the electronic element 40 is located.

[0084] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the electronic element 40 can be positioned in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass core 21 serve as an electrical connection structure that connects the electronic element 40 to an external element.

[0085] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass core 21, rather than the second area 222, and an electronic element 40 may be arranged in the cavity portion.

[0086] The packaging substrate 20 is also connected to the motherboard 10. The core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 may be directly connected to a terminal of the motherboard 10, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. The core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22.

[0087] The connection part 50 refers to a medium that connects the packaging substrate 20 to the motherboard 10 and / or the semiconductor device part 30, and may be, for example, a connection part such as a solder ball having the same or different size. The size of the solder ball disposed between the packaging substrate 20 and the motherboard 10 may be the same as or different from the size of the solder ball disposed between the packaging substrate 20 and the semiconductor device part 30.

[0088] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass core 21 .

[0089] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. This is understood to be the case for at least two reasons: one is that there is a scale problem in directly bonding the fine patterns of the device to the motherboard, and the other is that there is a risk of damage to the wiring due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device.

[0090] In the embodiment, this problem is solved by applying a glass core with a thermal expansion coefficient similar to that of a semiconductor device, and forming a fine pattern having a fine scale sufficient for mounting devices on the first surface and upper layer of the glass core.

[0091] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0092] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0093] First, as shown in (a) of FIG. 4, a glass core 21a having flat first and second surfaces is prepared, and defects (scratches) 21b are formed on the glass surface at predetermined positions for the formation of core vias. The glass core may be a glass core applied to a substrate of an electronic device, for example, but is not limited to, an alkali-free glass core. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be applied. The defects (scratches) may be formed by mechanical etching, laser irradiation, or other methods.

[0094] As shown in Fig. 4(b), the glass core 21a having the defect (scratch) 21b undergoes an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass core forms a via at the defect, and the surface of the glass core 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but in consideration of the troublesome process of applying and removing the masking film, the glass core having the defect itself may be etched, and in this case, the thickness of the glass core having the core via may be somewhat thinner than the thickness of the initial glass core.

[0095] Thereafter, a core layer manufacturing step can be performed by forming an electrically conductive layer 21d on the glass core as shown in Fig. 4(c) and (d). The electrically conductive layer can be a metal layer typically including, but not limited to, copper metal.

[0096] The adhesion between the glass surface (including the glass core surface and the core via surface) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0097] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0098] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0099] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0100] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0101] FIG. 5 illustrates the manufacturing steps for forming an insulating layer and an upper distribution pattern according to one embodiment.

[0102] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step in which an insulating layer is used to fill empty spaces after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be in the form of a film, and may be, for example, a method of vacuum laminating an insulating layer in the form of a film. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the empty spaces inside the core via, thereby forming a core insulating layer without the formation of voids.

[0103] 5(b)-(e) illustrate the top layer fabrication steps.

[0104] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers in which no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass core at least partially, and therefore has sufficient adhesion. Specifically, the glass core and the upper insulating layer preferably have a characteristic that satisfies an adhesion test value of 4B or more according to ASTM D3359.

[0105] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0106] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0107] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed by forming openings (not shown) at positions corresponding to the upper connection electrodes to expose the upper connection electrodes and to allow direct connection to the element connection parts or terminals of the elements.

[0108] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0109] Meanwhile, as described above, the core layer may include a glass core and a cavity portion, the glass core being a glass substrate having a first surface and a second surface facing each other, and the cavity portion being a recessed or perforated portion of the glass core, and having an accommodating space for accommodating an electronic element.

[0110] An electronic element may be arranged in the receiving space of the cavity. In addition, when embedding a plurality of electronic elements, particularly when arranging and incorporating a plurality of electronic elements in adjacent positions, spacing between the elements is necessary to prevent short circuits. This increases the amount of empty space in the cavity that must be filled with a film-like insulating layer, and it may be difficult to maintain the flatness of the top surface of the insulating layer over the entire area of ​​the substrate. The insulating layer may include inorganic particles and polymer resin, such as ABF (Ajinomoto Build-up Film).

[0111] Therefore, an element package (element molding package) in which a plurality of electronic elements are embedded may be prepared, and the element package may be placed in an accommodating space of a cavity to prepare an element-embedded substrate. Here, an element molding package manufactured by molding an element is referred to as an element package.

[0112] Here, the device package can be manufactured by a transfer molding process using a transfer mold.

[0113] FIG. 6 is a flow chart illustrating, in cross section, a process for producing a device package by a conventional transfer molding process.

[0114] For example, according to a conventional transfer molding process, multiple electronic devices can be placed into a mold cavity of a transfer mold and a molding material can be poured into the mold cavity and cured to produce a device package having multiple electronic devices embedded therein.

[0115] For example, referring to (a) of Fig. 6, a mold lower part 62 may be disposed on the bottom surface of a transfer mold 60 having a mold cavity 63. The mold lower part 62 may be made of, but is not limited to, a PI tape.

[0116] Next, referring to FIG. 6(b), an electronic device 40 can be arranged in a mold cavity 63 of a transfer mold 60, and as shown in FIG. 6(c), a mold top 61 can be placed on the top surface of the transfer mold 60, and a molding material can be poured through a gate of the mold top 61 and hardened to produce a device package.

[0117] The device package may include a plurality of electronic devices and a molding part.

[0118] The plurality of electronic elements may be arranged in a predetermined pattern.

[0119] The molding part may be a molding material that is arranged and cured to encase and maintain the arrangement of the electronic elements.

[0120] The molding material may be a polymer resin, or a mixture of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.).

[0121] For example, the polymer resin may be an acrylic resin, an epoxy resin, or a modified resin thereof, and may be a material applicable to electronic devices for the purpose of molding, etc. For example, a liquid crystal polymer (LCP) may be used.

[0122] For example, the mixed material may be a mixture of an acrylic resin and a filler, a mixture of an acrylic resin, an epoxy resin, and a filler, or a mixture of an epoxy resin and a filler. The filler may be inorganic particles, for example, silica particles. Commercially available products may include, but are not limited to, ABF (Ajinomoto Build-up Film), EMC (Epoxy Molding Compound), and MPI (Modified Polyimide).

[0123] Specifically, the molding material may include epoxy molding compound (EMC), liquid crystal polymer (LCP), and / or Ajinomoto Build-up Film (ABF), and the like.

[0124] In the conventional transfer molding process for producing the above-mentioned device package, the lower part of the mold (e.g., PI tape) may not be able to adequately fix the position of the individual devices during the process of injecting the molding material (e.g., due to insufficient adhesive strength, the need for a fast injection process to improve process efficiency, etc.), which may result in the device becoming detached from its original position.

[0125] Since the phenomenon of elements detaching from their original positions can cause contact between elements and lead to problems such as short circuits, this specification proposes an embodiment that can prevent element movement during the process of generating an element package.

[0126] As an example, an embodiment may be proposed in which a device package having a plurality of electronic devices embedded therein is produced by a transfer molding process using a transfer mold having a protrusion formed on the top of the mold.

[0127] FIG. 7 is a flow chart illustrating a process of producing a device package by a transfer molding process according to an embodiment.

[0128] A method for manufacturing a device package according to an embodiment of the present disclosure is as follows.

[0129] For example, an element package can be manufactured by including an element placement step of providing a mold having an injection port and placing an electronic element at a predetermined position on the mold, an injection step of injecting a molding material into the injection port, and a mold formation step of hardening the molding material to form a molding portion.

[0130] Here, the mold may have a protruding portion on which protrusions are arranged around the injection port, and the protruding portion may correspond in position to a recessed portion on which dimples of the device package are arranged.

[0131] 7(a), as an example, a mold lower portion 62 may be attached to the bottom surface of a transfer mold 60 having a mold cavity 63. A PI tape may be disposed on a part or the whole of the mold lower portion 62.

[0132] Next, referring to Fig. 7(b), electronic devices can be arranged in a mold cavity 63 of a transfer mold 60, and as shown in Fig. 7(c), a mold upper part 61 is placed on the top surface of the transfer mold 60, and a molding material is poured through a gate of the mold upper part 61 and hardened to form a molding part, thereby producing a device package. The gate refers to an injection port through which the molding material is injected.

[0133] For example, the mold upper portion 61 may be formed with a protrusion 70 having protrusions arranged on its inner side.

[0134] The protrusion 70 formed on the upper part 61 of the mold can reduce the force applied to the element by the flow of the molding material when the molding material is poured, and can substantially prevent the element from coming off from its original position.

[0135] For example, the protrusions formed on the upper part of the mold 61 may be located between electronic elements when viewed in a cross section of the transfer mold 60. That is, the protrusions formed on the upper part of the mold 61 may be disposed between adjacent electronic elements.

[0136] The description of the molding material overlaps with that given above, so a detailed description will be omitted.

[0137] Meanwhile, the positions of the protrusions (protrusions) arranged on the mold shown in FIG. 7 are merely examples and are not limited thereto.

[0138] For example, the mold may have a protrusion disposed around the injection port.

[0139] 7, a protrusion 70 may be formed on the upper mold part 61. Alternatively, for example, the protrusion 70 may be formed on the lower mold part 62. Alternatively, for example, the protrusion 70 may be formed on both the upper mold part 61 and the lower mold part 62. The protrusion may help to maintain a position where an electronic component is arranged in a component arrangement step substantially the same as a position where the electronic component is arranged in a mold formation step.

[0140] 8A to 8C are conceptual cross-sectional views illustrating a device package produced by a transfer molding process using a transfer mold having protrusions according to an embodiment.

[0141] For example, referring to Figures 8A to 8C, the device package 80 may include an arranged plurality of electronic devices 40 and a molding portion 64 containing a molding material and arranged so that the molding material encases the electronic devices.

[0142] For example, the molding material that encapsulates the electronic elements may be a polymer resin, a mixture of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), etc., as described above.

[0143] In addition, the device package may have a recess in which dimples are arranged, disposed in a portion of the molding material of the molding part, and the recess and the protrusion may correspond in position to each other.

[0144] For example, referring to FIG. 8A, the upper surface of the molding portion of the device package 80 may be provided with a recess with an array of dimples.

[0145] Or, for example, referring to FIG. 8B, the bottom surface of the molding portion of the device package 80 may be provided with a recess with an array of dimples.

[0146] Alternatively, for example, referring to FIG. 8C, the top and bottom surfaces of the molding portion of the device package 80 may each be provided with a recess with an array of dimples.

[0147] For example, a protrusion 70 formed on the mold upper portion 61 may form a recess 81 on the upper surface of the molding part of the device package 80 .

[0148] Alternatively, for example, a protrusion 70 formed on the mold lower portion 62 may form a recess 81 on the bottom surface of the molding portion of the device package 80 .

[0149] Alternatively, for example, recesses 81 may be formed on the top and bottom surfaces of the molding part of the device package 80 by protrusions 70 formed on the mold upper part 61 and the mold lower part 62 .

[0150] The dimples may be disposed between adjacent electronic components 40 of the device package 80. For example, the dimples may be disposed between adjacent first and second electronic components of the device package 80.

[0151] The recess 81 may have various shapes depending on the shape of the protrusion 70. For example, the shape of the cavity of the glass core may have various shapes such as a cross shape, a T shape, a rectangle, etc., and the shape of the cavity of the transfer mold 60 may be changed similarly. The overall shape of the recess 81 or the protrusion 70 may have various shapes taking into account the shape of the cavity.

[0152] In addition, the shape of the protrusion 70 formed on the mold may have various shapes. For example, the shape of the protrusion 70 formed on the mold may have an interrupted structure so as not to hinder the flow of the molding material when the molding material is injected.

[0153] 9A and 9B are conceptual diagrams illustrating a transfer mold having protrusions formed according to an embodiment and a portion of a device package produced by the transfer mold.

[0154] For example, a mold having an injection port may be provided, and protrusions may be arranged around the injection port (gate) of the mold. For example, a protruding portion with an array of protrusions may be arranged on the upper part of the mold. Or, for example, a protruding portion may be arranged on the lower part of the mold. Or, for example, protruding portions may be arranged on both the upper and lower parts of the mold. The positions of the protruding portions and the arrangement of the protrusions arranged on the mold are merely examples, and are not limited thereto.

[0155] 9A, a protrusion 70 may be disposed on the upper mold part 61 and / or the lower mold part 62. For example, the protrusion formed on the upper mold part 61 and / or the lower mold part 62 may be a triangular prism having a triangular cross section. The protrusion may be formed such that one rectangular surface of the triangular prism contacts the upper mold part 61 and / or the lower mold part 62.

[0156] The protrusions disposed in the upper mold portion 61 and / or the lower mold portion 62 may be disposed between adjacent electronic components of the device package 80. For example, the protrusions disposed in the upper mold portion 61 may be disposed between adjacent first and second electronic components of the device package 80. The illustrated embodiments are merely illustrative, and various modifications and improvements may be made by those skilled in the art using the basic concept of the embodiments.

[0157] FIG. 9B exemplarily illustrates a partial surface of a device package 80 produced by the transfer mold 60 in which the protrusion 70 shown in FIG. 9A is formed.

[0158] For example, referring to FIG. 9A, a top and / or bottom surface of the molding portion of the device package 80 may be formed with a recess 81 that is arrayed with dimples.

[0159] 9B, a protrusion 70 having an array of protrusions disposed in a portion of a mold may form a recess 81 having an array of dimples in a portion of a molding material of a molding portion of the device package 80. The recess and the protrusion may correspond in position. Also, the dimples and the protrusion may correspond in position.

[0160] For example, the aspect ratio of the dimple may be the aspect ratio of the opening of the dimple, which is the ratio of the major axis to the minor axis of the entrance (opening) of the dimple when viewed from above.

[0161] Exemplarily, if the entrance of the dimple is rectangular, the aspect ratio may be the ratio of the width to the length. Exemplarily, if the entrance of the dimple is elliptical, the aspect ratio may be the ratio of the major axis to the minor axis. Exemplarily, if the entrance of the dimple is triangular, the aspect ratio may be the ratio of the base to the height.

[0162] The aspect ratio of the dimples may be 1-12, or may be 1.5-8.

[0163] The protrusions 70 formed on the mold proposed in this specification may be small projections arranged in a dotted line pattern to maximize the flow of the molding material while substantially restricting movement of the element position.

[0164] The dotted line shape means that a number of protrusions are arranged at intervals in a space in which a cavity is mounted. In this case, the protrusion 70 may be an arrangement of adjacent individual protrusions arranged at intervals. The intervals may be regular or irregular. That is, the size of the protrusions and / or the arrangement between the protrusions may be regular or irregular. The dotted line shape means that all or at least a part of the protrusions may be arranged between the electronic elements in the space in which the electronic elements are arranged.

[0165] 10A and 10B are conceptual diagrams illustrating a transfer mold having protrusions formed according to an embodiment and a portion of a device package produced by the transfer mold.

[0166] Referring to FIG. 10A, the upper mold portion 61 and / or the lower mold portion 62 may have a protrusion 70 disposed thereon.

[0167] For example, protrusions spaced apart at regular intervals may be disposed on the upper mold portion 61 and / or the lower mold portion 62. A certain number of protrusions disposed on the upper mold portion 61 and / or the lower mold portion 62 may be disposed between adjacent electronic devices of the device package 80.

[0168] For example, the protrusion may include protrusions arranged in a dotted line shape. The description of the dotted line shape overlaps with the description above, so a detailed description will be omitted.

[0169] For example, a certain number of protrusions 70 formed on the upper mold portion 61 and / or the lower mold portion 62 may be disposed between adjacent first and second electronic devices of the device package 80. The illustrated embodiments are merely illustrative, and various modifications and improvements may be made by those skilled in the art using the basic concept of the embodiments.

[0170] FIG. 10B exemplarily illustrates a partial surface of a device package 80 produced by the transfer mold 60 in which the protrusion 70 shown in FIG. 10A is formed.

[0171] For example, a recess 81 with an array of dimples may be formed on an upper surface and / or a bottom surface of the molding part of the device package 80. For example, referring to Fig. 10A, a protrusion 70 formed on a part of a mold may form a recess 81 with an array of dimples on a part of the molding part of the device package 80. For example, the recess and the protrusion may correspond to each other in position. Also, the protrusion and the dimple may correspond to each other in position.

[0172] Referring to FIG. 10B, the recess 81 may be a number of dimples arranged in a dotted line shape when viewed from a first surface (e.g., a top surface of the device package) to a second surface (e.g., a bottom surface of the device package).

[0173] The dotted line shape means that a number of dimples are spaced apart in the space in which the cavity is mounted. In this case, the recesses 81 may be individual dimples arranged at intervals between adjacent dimples. The intervals may be regular or irregular. That is, the size of the dimples and / or the arrangement between the dimples may be regular or irregular. The dotted line shape means that all or at least a portion of the recesses or dimples may be arranged between electronic elements in the space in which the electronic elements are disposed.

[0174] Meanwhile, the present specification is not limited to the above-mentioned embodiment of the protrusion formed on the upper part of the mold and the recess formed in the molding part of the device package. For example, various shapes of the protrusion and the recess may be applied in consideration of the shape of the cavity part in which the device package is disposed.

[0175] The present specification also proposes a manufacturing method for producing a packaging substrate according to an embodiment.

[0176] A manufacturing method for producing a packaging substrate according to an embodiment of the present specification may include the steps of providing a glass core having a cavity portion and a device package, disposing the device package in the cavity portion, and disposing an insulating material on the glass core or the cavity portion and hardening it to form an insulating layer.

[0177] FIG. 11 is a flowchart illustrating a method for manufacturing a packaging substrate according to an embodiment in cross section.

[0178] Referring to FIG. 11(a), a glass core having a cavity disposed therein and a device package 80 can be provided.

[0179] For example, the packaging substrate may include a core layer including a glass core having a first surface and a second surface opposed to each other and a cavity portion penetrating the glass core. A glass core having a first surface and a second surface opposed to each other may be provided, and a cavity portion penetrating the glass core may be disposed in the glass core.

[0180] Also, for example, the device package 80 may be produced by a transfer molding process using a transfer mold 60 having a protrusion 70. For example, a mold having an injection port may be provided, and the mold may have a protrusion disposed around the injection port.

[0181] For example, a protrusion may be arranged on the upper mold part 61 of the mold. Or, for example, a protrusion may be arranged on the lower mold part 62 of the mold. Or, for example, a protrusion may be arranged on both the upper mold part 61 and the lower mold part 62 of the mold.

[0182] The shape of the protrusions and the arrangement of the projections are the same as those described above.

[0183] An electronic device may then be placed in a predetermined location on the mold and molding material may be injected into the injection port.

[0184] For example, multiple electronic elements may be arranged in a mold cavity 63 of a transfer mold 60 having a protrusion 70 formed on the upper mold portion 61 and / or the lower mold portion 62, and a molding material may be poured into the mold cavity 63 and hardened to generate a molding portion of an element package 80.

[0185] The device package 80 may include a plurality of arranged electronic devices and a molding portion including a molding material and arranged to encase the electronic devices.

[0186] The description of the element package overlaps with that given above, so a detailed description will be omitted.

[0187] Furthermore, the die may be formed with protrusions of various shapes.

[0188] For example, the protrusions disposed on the upper mold part 61 and / or the lower mold part 62 may have a triangular prism shape with a triangular cross section. The protrusions may be disposed such that one rectangular surface of the triangular prism contacts the upper mold part 61 and / or the lower mold part 62. Alternatively, for example, protrusions spaced apart at regular intervals may be disposed on the upper mold part 61 and / or the lower mold part 62. The protrusions may be disposed between the first electronic component and the second electronic component adjacent to each other of the device package 80.

[0189] Also, for example, a recess with an array of dimples may be disposed in the molding portion of the device package 80. For example, dimples of various shapes may be disposed on the top and / or bottom surface of the molding portion.

[0190] For example, the dimple may be formed such that one surface of a quadrangle of a triangular prism contacts the upper mold portion 61 and / or the lower mold portion 62. Alternatively, for example, the dimples may be arranged in a dotted line shape when viewed from the first surface to the second surface. In this case, for example, dimples spaced apart at regular intervals may be disposed on the upper mold portion 61 and / or the lower mold portion 62. The dimples may be disposed between adjacent first and second electronic components of the device package 80.

[0191] Next, for example, referring to FIG. 11(b), the device package 80 can be placed in the cavity portion .

[0192] For example, the glass core 21 may be attached to an adhesive film such as a PI tape (Polyimide Tape), and the device package 80 may be disposed in the cavity portion 28. The electronic device 40 of the device package 80 may include an active device such as a transistor, or a power transfer device such as a capacitor, i.e., a passive device.

[0193] An insulating layer may then be laminated to the glass core. An insulating material may be placed on the glass core or the cavity and cured to form an insulating layer.

[0194] For example, referring to FIG. 11(c), a process of laminating a top insulating layer onto a first surface of the glass core 21 (Lamination on top) may be performed.

[0195] If necessary, the adhesive film may be removed during a subsequent process. For example, the adhesive film may be an adhesive film whose adhesive strength can be reduced by exposure to ultraviolet light or the like.

[0196] The adhesive film can be easily removed from the glass core by reducing the adhesive strength of the adhesive film, for example, by irradiating the adhesive film with ultraviolet light directly or through the glass core.

[0197] Next, referring to FIG. 11(d), a process of laminating a bottom insulating layer on a second surface of the glass core 21 (Lamination on bottom) may be performed.

[0198] 11(e), the upper and lower insulating layers may be pre-cured. The upper insulating layer may be filled into the recess 81 of the device package 80 and / or the internal space of the cavity portion 28.

[0199] The insulating material may be a polymer resin, or a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.).

[0200] For example, the polymer resin may be an acrylic resin, an epoxy resin, or a modified resin thereof, and may be a material applicable to electronic devices for the purpose of molding, etc. For example, a liquid crystal polymer (LCP) may be used.

[0201] For example, the mixed material may be a mixture of an acrylic resin and a filler, a mixture of an acrylic resin, an epoxy resin, and a filler, or a mixture of an epoxy resin and a filler. The filler may be inorganic particles, for example, silica particles. Commercially available products may include, but are not limited to, ABF (Ajinomoto Build-up Film), EMC (Epoxy Molding Compound), and MPI (Modified Polyimide).

[0202] Specifically, the insulating material applied to the insulating layer may include an insulating mixture, which may include inorganic particles and a polymer resin.

[0203] The insulating material may include Epoxy Molding Compound (EMC) and / or Ajinomoto Build-up Film (ABF).

[0204] The insulating material flows and some of it can migrate into the dimples on the cavity element.

[0205] In a cross section of the packaging substrate, the insulating layer and the cavity element may be separated, that is, a boundary between the insulating layer and the element package may be observed. The boundary is observed at a cavity portion.

[0206] In one embodiment, the insulating layer and the device package are stacked one on top of the other, and the molding material of the device package and the insulating material of the insulating layer may be substantially the same. In this case, the boundary between the insulating layer and the cavity device package may be substantially difficult to distinguish, i.e., the shape of the recess or dimple may be substantially difficult to observe.

[0207] In another embodiment, the insulating layer and the cavity device may be stacked one above the other, such that the molding part of the device package and the insulating material are separated from each other, and in a cross section of the cavity, the boundary between the molding part and the insulating layer may be separated and a depression (or dimple) may be observed at the boundary.

[0208] Even if the materials of the molding portion and the insulating layer are substantially the same, the boundary between the molding portion and the insulating layer can be created by setting different curing pressures and temperatures.

[0209] The boundary may be distinguished by applying different materials to the cavity. In this case, the boundary and the recess (or dimple) may be more easily distinguished in the cross section of the cavity.

[0210] In cross section, the boundary can be seen as a line of color difference.

[0211] In a cross section, the boundary may be observed as a band of color that changes with a relatively constant thickness (e.g., a gradation-like color change).Exemplarily, the constant interval may be 2 to 30 μm, or 3 to 10 μm.

[0212] In a cross section, the boundary may be distinguished by including fillers having different sizes based on the boundary, which may make it easier to control and adjust the stress on the glass substrate due to the difference in thermal expansion coefficient of the insulating materials.

[0213] Here, the fillers having different sizes refer to fillers having different d50 values ​​measured by a particle size analysis method.

[0214] The molding part and the insulating layer may be made of materials having the same or different coefficients of thermal expansion (CTE), preferably a material having a small difference between the coefficients of thermal expansion of the molding part and the insulating layer.

[0215] The difference in thermal expansion coefficient between the molding part and the insulating layer may be 2 ppm / ° C. or less, 1.5 ppm / ° C. or less, 1 ppm / ° C. or less, or 0.5 ppm / ° C. or less. The difference in thermal expansion coefficient may be 0 ppm / ° C. or more, 0.1 ppm / ° C. or more, or 0.2 ppm / ° C. or more.

[0216] The thermal expansion coefficient of the molding part may be 8 ppm / ° C. or more, 10 ppm / ° C. or more, 12 ppm / ° C. or more, or 14 ppm / ° C. or more. The thermal expansion coefficient may be 20 ppm / ° C. or less, 18 ppm / ° C. or less, or 17 ppm / ° C. or less.

[0217] The thermal expansion coefficient of the insulating layer may be 8 ppm / ° C. or more, 10 ppm / ° C. or more, or 12 ppm / ° C. or more. The thermal expansion coefficient may be 20 ppm / ° C. or less, 18 ppm / ° C. or less, 16 ppm / ° C. or less, or 16 ppm / ° C. or less.

[0218] The molding part and the insulating layer may be made of materials having different dielectric constants. Preferably, the material of the insulating layer may be selected so that the dielectric constant of the molding part is lower than the dielectric constant of the insulating layer.

[0219] The molding part and the insulating layer may be made of materials having different dielectric constants Dk at a high frequency of 5.8 GHz. Exemplarily, the difference between the Dk of the molding part and the Dk of the insulating layer may be 0.1 or more. The difference in Dk may be 0.1 or more, 0.13 or more, 0.16 or more, or 0.2 or more. The difference in Dk may be 1 or less, 0.8 or less, 0.6 or less, 0.5 or less, 0.4 or less, 0.3 or less, or 0.25 or less.

[0220] The Dk of the molding portion may be 2.3 or more, 2.5 or more, 2.7 or more, or 2.9 or more. The Dk may be 3.4 or less, 3.2 or less, or 3.1 or less.

[0221] The insulating layer may have a Dk of 3.0 or more, 3.1 or more, or 3.2 or more. The Dk may be 3.6 or less, 3.5 or less, or 3.4 or less.

[0222] The molding part and the insulating layer may be made of materials having the same or different dielectric loss factors Df. Preferably, a material having a difference between Df of the molding part and Df of the insulating layer of 0.0001 or more may be used. The difference in Df may be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df may be 0.02 or less.

[0223] The Df of the molding part may be 0.004 or less, 0.0038 or less, or 0.0036 or less. The Df may be 0.001 or more, 0.0015 or more, 0.0018 or more, or 0.002 or more.

[0224] The insulating layer may have a Df of 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0225] For example, the insulating layer may be made of ABF and the molding part may be made of LCP. For example, the insulating layer may be made of EMC and the molding part may be made of LCP. For example, the insulating layer and the molding part may be made of ABP having different dielectric constants.

[0226] The packaging substrate manufacturing method according to the above-described embodiment and the packaging substrate using the same can prevent the phenomenon of multiple elements being embedded and moving away from their arranged positions by inserting an element package produced using a mold having a protrusion into a cavity portion.

[0227] This makes it possible to maintain the arranged position of the elements through an element package having a recess disposed in a portion of the molding part, thereby preventing contact between the elements and preventing problems such as short circuits from occurring.

[0228] The above description of the present specification has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present specification is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present specification must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0229] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21,21a Glass core 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 252 Blind Via 253 Upper insulating layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 281 Interior Space 282 Cavity Distribution Layer 40 Electronic Elements 50 Connection 51 Element connection part 52 Board connection 60 Transfer mold 61 Upper part of mold 62 Lower part of mold 63 Mold Cavity 64 Molding section 70 Protrusion 80 element package 81 Recess

Claims

1. A core layer is included. The core layer includes a glass core and a cavity portion, the glass core is a glass substrate having a first surface and a second surface opposed to each other; the cavity portion is a recess or a through hole in the glass core, and has an accommodating space for accommodating an electronic element; a device package is disposed in the receiving space of the cavity portion, The device package includes: i) a plurality of electronic devices arranged in an array; and ii) a molding part containing a molding material, the molding material being arranged to encase the electronic devices; The packaging substrate, wherein the element package has a recess in which dimples are arranged in a portion of the molding portion.

2. The packaging substrate of claim 1 , wherein the dimples are disposed between adjacent electronic elements.

3. The packaging substrate according to claim 1 , wherein the recess includes a number of dimples arranged in a dotted line shape when viewed from the first surface to the second surface.

4. the packaging substrate further includes an insulating layer disposed on the cavity portion; The packaging substrate according to claim 1 , wherein the dimples of the recess are filled with an insulating material of the insulating layer.

5. 2. The packaging substrate of claim 1, wherein the molding material comprises a liquid crystal polymer (LCP), an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), or a modified polyimide (MPI).

6. the insulating layer comprises an insulating compound; The packaging substrate as claimed in claim 4 , wherein the insulating mixture comprises inorganic particles and polymer resin.

7. The cavity portion is located at a boundary between the molding portion and the insulating layer, The packaging substrate according to claim 4 , wherein the boundary is provided with a recess having a dimple that is concave toward the electronic element.

8. 1. A method for manufacturing a device package, comprising: an element placement step of providing a mold having an injection port and placing an electronic element at a predetermined position of the mold; an injection step of injecting a molding material into the injection hole; and forming a mold by hardening the molding material to form a molding part, thereby manufacturing a device package. The mold has a protruding portion having an array of protrusions arranged around the injection port, The device package includes: i) a plurality of electronic devices arranged in an array; and ii) a molding part including a molding material and arranged to encase the electronic devices, the device package including a recess in which dimples are arranged in a portion of the molding part; The recess and the protrusion correspond in position to each other.

9. In the element placement step, the electronic element is placed on an adhesive surface and fixed in position; The method of claim 8 , wherein the position where the electronic element is arranged in the mold forming step is substantially the same as the position where the electronic element is arranged in the element placing step.

10. The method for manufacturing a device package according to claim 8 , wherein the protrusions are disposed between adjacent electronic devices.

11. The method of claim 8 , wherein the device package is produced by a transfer molding process using a transfer mold having a protrusion formed on an upper portion of the mold.

12. A method for manufacturing a packaging substrate, comprising: providing a glass core having a cavity and a device package; placing the device package in the cavity; and disposing an insulating material on the glass core or the cavity portion and curing the insulating material to form an insulating layer.

13. The method for manufacturing a packaging substrate according to claim 12 , wherein in the step of forming the insulating layer, the insulating material flows and a part of it moves to the concave portion of the dimple on the cavity element.

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