Packaging substrate and manufacturing method thereof

Abstract

To provide a packaging substrate enabling easy detection of defects that may occur in a glass substrate, and a manufacturing method thereof.SOLUTION: A packaging substrate 20 includes a glass substrate 21 having an edge region and containing a first surface and a second surface facing each other, and an upper layer 70 laminated on the first surface or a lower layer 80 laminated under the second surface. The edge region of the glass substrate includes an edge of the glass substrate and a region of the glass substrate which protrudes beyond the upper layer or the lower layer. A manufacturing method of the packaging substrate includes a step of preparing the glass substrate and forming the upper layer on the first surface, a step of removing a part of the upper layer along a cutting line which is a cutting-planned position, thereby forming a removal line, a filamentation forming step of forming a filamentation in the glass substrate along the removal line, and a step of cutting the glass substrate using the filamentation.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor packaging substrate and a method for manufacturing the same, and is directed to a packaging substrate including a glass substrate and a method for manufacturing the same. [Background technology]

[0002] In manufacturing electronic components, the process of creating circuits on a semiconductor wafer is called the front-end process (FE: Front-End), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE: Back-End), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, over 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections, rather than the performance of the semiconductor technology itself.

[0004] Ceramic or resin is currently used as a material for packaging substrates. Recently, however, research has been conducted into the application of silicon or glass to high-end packaging substrates. In particular, a packaging substrate having a cavity structure has been developed by applying a glass substrate.

[0005] Meanwhile, Re-Distribution Layer (RDL) is a packaging process that refers to a technology that changes the position of electrical terminals (ex: Aluminum Pad) that have already been formed using Wafer Level Package (WLP) process technology to any position. This RDL is used as a method to resolve design limitations in semiconductor manufacturing factories through packaging, that is, it is used for stacking semiconductor chips.

[0006] Related prior art includes U.S. Patent Publication US2022 / 0336481A1 and Korean Patent Publication No. 10-2020-0133340. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the embodiment is to provide a packaging substrate in which defects that may occur in a glass substrate and a packaging substrate in which a number of elements are mounted on the glass substrate can be easily detected, and a manufacturing method thereof.

[0008] Another object of the present embodiment is to provide a packaging substrate capable of simultaneously detecting defects occurring on the surface and cross section of a glass substrate, and a manufacturing method thereof.

[0009] Another object of the embodiment is to reduce time and costs involved in inspecting and quality checking glass substrates. [Means for solving the problem]

[0010] To achieve the above object, a packaging substrate according to an embodiment includes a glass substrate having a first surface and a second surface facing each other, an upper layer laminated on the first surface or a lower layer laminated under the second surface, and the glass substrate may have an edge region, the edge region including an edge of the glass substrate and a region of the glass substrate protruding beyond the upper layer or the lower layer.

[0011] The upper layer may include a first insulating layer laminated over the first surface.

[0012] An edge of the first insulating layer may be disposed inward from an edge of the glass substrate, and the edge region may include the edge of the glass substrate and the edge of the first insulating layer.

[0013] In addition, the lower layer may also include a second insulating layer stacked below the second surface, an edge of the second insulating layer being disposed inward from an edge of the glass substrate, and the edge region may include an edge of the glass substrate and an edge of the second insulating layer.

[0014] The width from an edge of the first insulating layer to an edge of the glass substrate may be 5 μm to 200 μm.

[0015] The width from the edge of the second insulating layer to the edge of the glass substrate may be 5 μm to 200 μm.

[0016] According to one embodiment, the edge region may be curved.

[0017] The corners of the glass substrate in the edge region may be curved.

[0018] In other embodiments, the edge region may be chamfered.

[0019] The corners of the glass substrate in the edge region may be chamfered.

[0020] The upper layer or the lower layer may each have a tapered shape thinning towards the edge region.

[0021] The upper layer or the lower layer may each have a tapered shape that becomes thinner in a cut surface direction of the glass substrate.

[0022] A semiconductor device may be mounted on the upper layer.

[0023] In order to achieve the above object, a manufacturing method for a packaging substrate according to one embodiment may include the steps of preparing a glass substrate having a first surface and a second surface facing each other, and forming an upper layer on the first surface; removing a portion of the upper layer along a cutting line at a position where cutting is planned to form a removal line; a filamentation process step of forming a filamentation in the glass substrate along the removal line; and cutting the glass substrate using the filamentation, thereby manufacturing the above-mentioned packaging substrate.

[0024] The method for manufacturing the packaging substrate may further include, before the filamentation process step, a step of forming a lower layer under the second surface; and a step of removing a portion of the lower layer along the cutting line to form a removal line.

[0025] The width of the removal line may be 5 μm or more, or may be 200 μm or less.

[0026] The upper layer and / or the lower layer may each have a tapered shape that becomes thinner in a cut surface direction of the glass substrate.

[0027] The step of cutting the glass substrate may include applying a tensile stress or a rotational force to the filamentation to separate the glass substrate into two or more portions, and forming a cut surface on the glass substrate.

[0028] The method for manufacturing a packaging substrate may further include, after the step of cutting the glass substrate, grinding a cut surface of the cut glass substrate.

[0029] Edge regions include: edges of the glass substrate; and regions of the glass substrate that protrude beyond the upper layer or the lower layer.

[0030] The method for manufacturing the packaging substrate may further include a step of detecting defects in any one selected from the group consisting of an edge region of the glass substrate, a cut surface of the glass substrate, a removal line of the upper layer, a removal line of the lower layer, and combinations thereof. Effect of the Invention

[0031] The embodiment may easily detect defects that may occur in a packaging substrate and / or a glass substrate, may simultaneously detect defects that occur on the surface and cross section of a glass substrate, and may effectively detect breaks, damage, cracks, etc. that may occur in a glass substrate at low cost. [Brief description of the drawings]

[0032] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5] 1 is a flowchart illustrating a process of forming an upper layer in a process of manufacturing a packaging substrate according to an embodiment, in a cross-sectional view. [Figure 6] 1A to 1C are views illustrating a cross section of a packaging substrate according to an embodiment. [Figure 7] 1 is a diagram showing a state in which a packaging substrate according to an embodiment is viewed from above, in which Gr indicates a glass crack and Gh (glass chipping) indicates glass chipping. [Figure 8]1A to 1C are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment, where (a) is laser ablation, (b) is laser filamentation, and (c) is separation. [Figure 9] 11A to 11C are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to another embodiment, where (a) is laser ablation, (b) is laser filamentation, and (c) is separation. [Figure 10] (a) and (b) are photographs taken during the manufacturing process of a packaging substrate according to an embodiment, where the left side of (a) is a sectional view (Sectional View) and the right side is a top view (Top View). [Figure 11] 1 is a photograph of a cross section of a ground glass substrate according to an embodiment, in which a solid line indicates a cutting line CL and a dotted line indicates an edge of the ground glass. [Figure 12] 1A is a top view of a glass substrate according to another embodiment, and FIG. 1B is a photograph of a portion of the glass substrate. BEST MODE FOR CARRYING OUT THEINVENTION

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the embodiments. However, the embodiments may be embodied in many different forms and are not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0034] Throughout this specification, the term "combinations thereof" in a Markush form phrase means a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, including one or more selected from the group of elements.

[0035] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish identical terms from one another, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0036] In this specification, the term "-" may mean that the compound includes a compound that corresponds to "-" or a derivative of "-".

[0037] In this specification, the term "B is located on A" means that B is located on A in direct contact therewith, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0038] In this specification, the expression "B is linked to A" means that A and B are directly linked, or that A and B are linked via another component between them, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0039] In this specification, the term "singular" is to be construed as including the singular or plural as the context requires, unless otherwise specified.

[0040] The inventors recognized that in the process of developing a semiconductor device that can achieve high performance with a more integrated and thinner thickness, not only the element itself but also the packaging portion is an important factor in improving performance. As a result of their research, they discovered that unlike conventional interposers and organic substrates, which use two or more layers of cores on a motherboard as a packaging substrate, it is possible to make the packaging substrate thinner and help improve the electrical characteristics of the semiconductor device by applying a single layer of glass core and applying a cavity structure.

[0041] Meanwhile, the glass substrate may have cracks or chipping due to internal stress and / or external impact during processing, and in order to detect such cracks or chipping, cross-sectional analysis, which requires high costs, is required. For example, in order to detect cracks or chipping, it may be necessary to inspect all cut surfaces of the glass substrate using a microscope, etc., and such inspection may take a considerable amount of time and cost. In this regard, it has been confirmed that the inspection of the core substrate can be easily performed by making the glass substrate protrude in the cut surface direction beyond the layers laminated on the upper or lower side. In other words, it has been confirmed that by exposing a part of the glass substrate, it is possible to quickly detect defects on the surface and cross section of the glass substrate without a tool such as a microscope, and thus the invention has been completed.

[0042] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0043] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0044] The packaging substrate 20 according to one embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be disposed.

[0045] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0046] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0047] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0048] The core layer 22 may include a glass substrate 21 including a first region 221 having a first thickness 211, and a second region 222 adjacent to the first region 221 and having a second thickness 212 thinner than the first thickness, a number of core vias 23 penetrating the glass substrate 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting a first surface 213 of the glass substrate 21 to a second surface 214 facing the first surface through the core vias 23. That is, the core layer 22 may refer to a glass structure that is a glass substrate 21 including a first surface 213 and a second surface 214 facing each other, a core via 23, a cavity portion 28, or all of these.

[0049] The second region 222 of the core layer 22 may serve as a cavity structure.

[0050] In the same area, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are generally parallel to each other, so that the glass substrate 21 has a constant thickness throughout.

[0051] An internal space 281 formed by the difference in thickness between the first section 221 and the second section 222 serves to accommodate a part or the whole of the cavity element 40 .

[0052] The glass substrate 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222, and may be formed at a desired pitch and pattern.

[0053] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0054] In the embodiment, to solve this problem, the glass substrate 21 is used as a support for the core layer 22. In addition, by using the glass substrate 21 and the core via 23 formed penetrating the glass substrate 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0055] The glass substrate 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0056] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0057] Specifically, the formation of the core via 23 may be achieved by forming a defect (scratch) on the surface of the glass substrate using a method such as a laser, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0058] The core vias 23 may be positioned in a number of 100 to 3,000, 100 to 2,500, or 225 to 1,024 per unit area (1 cm×1 cm) of the glass substrate 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0059] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 that surrounds the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, and connects the upper and lower parts of the glass substrate over a relatively short distance, thereby allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0060] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0061] The cavity element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0062] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0063] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by the same process as the process of forming the core via 23, and the area and shape penetrating the glass substrate 21 may be different from those of the core via 23.

[0064] In this embodiment, an insulating layer may be formed in the cavity portion after the cavity element 40 is arranged in the cavity portion. That is, an insulating layer may be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0065] The core distribution pattern 241 may be patterned so as to be electrically connectable with the cavity element 40 .

[0066] The cavity element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0067] When an element such as a transistor that converts electrical signals between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, a transistor or the like is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0068] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0069] Meanwhile, the cavity element 40 may be applied by inserting passive elements such as capacitors individually, or an element group including a number of passive elements embedded between insulating layers (cavity element insulating layers) may be formed with electrodes exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex elements.

[0070] The glass substrate 21 acts as an intermediate or mediating role connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting these electrical signals, thereby ensuring smooth signal transmission. The core vias arranged in the first area 221 are referred to as first area core vias 231 to distinguish them from the core vias in the second area 222 described below.

[0071] A top layer 26 is positioned on the first surface 213 .

[0072] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0073] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251, which is an electrically conductive layer having a predetermined pattern and at least a part of which is electrically connected to the core distribution layer 24, embedded in the upper insulating layer 253. The upper distribution layers 25 arranged one above the other can be connected to each other through blind vias 252.

[0074] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0075] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0076] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0077] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0078] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval each of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0079] The upper connection layer 27 includes an upper connection pattern 272, at least a portion of which is electrically connected to the upper distribution pattern 251 and located on the upper insulating layer 253, and an upper connection electrode 271 that electrically connects the semiconductor device unit 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and when the upper connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by surface polishing, surface etching, or the like.

[0080] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0081] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0082] The cavity portion 28 is located above and / or below the second region 222 and includes a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the cavity element 40 is located. The cavity distribution layer 282 may be formed through a second region core via 232.

[0083] Specifically, the thickness of the glass substrate 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass substrate 21 serve as an electrical connection structure that connects the cavity element 40 to an external element.

[0084] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass substrate 1, rather than the second area 222, and a cavity element 40 may be arranged in the cavity portion.

[0085] The packaging substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 may be directly connected to a core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. The core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22. The element connection part 51 and the board connection part 52 are collectively referred to as a connection part 50.

[0086] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass substrate 21 .

[0087] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. This is understood to be applied in such a multi-layer form for at least two reasons. One is that there is a scale problem when directly bonding the fine pattern of the device to the motherboard, and the other is that there is a risk of damage to the wiring due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device. In the embodiment, this problem is solved by applying a glass substrate with a thermal expansion coefficient similar to that of the semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting the device on the first surface and the upper layer of the glass substrate.

[0088] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0089] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0090] First, as shown in (a) of FIG. 4, a glass substrate 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass substrate may be a glass substrate used for substrates of electronic devices, for example, but is not limited to, an alkali-free glass substrate. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or other methods.

[0091] 4(b), the glass substrate 21a having the defect (groove) 21b is subjected to an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass substrate forms a via in the defective portion, and the surface of the glass substrate 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but in consideration of the troublesome process of applying and removing the masking film, the glass substrate having the defect may itself be etched, and in this case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0092] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0093] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0094] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0095] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0096] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0097] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0098] FIG. 5 illustrates the manufacturing steps for forming an insulating layer and an upper distribution pattern according to one embodiment.

[0099] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step in which an insulating layer is used to fill empty spaces after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be in the form of a film, and may be, for example, a method of vacuum laminating an insulating layer in the form of a film. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the empty spaces inside the core via, thereby forming a core insulating layer without the formation of voids.

[0100] 5(b)-(e) illustrate the top layer fabrication steps.

[0101] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass substrate at least in part, and therefore has sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic of satisfying an adhesion test value of 4B or more according to ASTM D3359.

[0102] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0103] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0104] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed by forming openings (not shown) at positions corresponding to the upper connection electrodes to expose the upper connection electrodes and to allow direct connection to the element connection parts or terminals of the elements.

[0105] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0106] According to an embodiment, one or a plurality of semiconductor devices may be mounted on the packaging substrate 20. In a process of manufacturing the packaging substrate, a plurality of packaging substrates may be simultaneously manufactured on a large-area substrate, and the packaging substrate 20 may be cut into a predetermined unit, i.e., into individual packaging substrate units. Exemplarily, in a process of manufacturing the packaging substrate, there are a strip substrate in which a plurality of individual products are arranged with dummy regions therebetween, a quad substrate in which a dummy region is disposed between a plurality of strip substrates, and a panel substrate in which a dummy region is disposed between a plurality of quad substrates, and a glass substrate may be used as a core in the manufacture of the same. The glass substrate (core substrate or core layer) may be cut into a state in which an individual semiconductor chip or chip unit is mounted or can be mounted, having a pattern of a certain size, during or after the arrangement of the upper layer and / or the lower layer. Such a process of cutting, separating, and dividing the substrate may be referred to as dicing or singulation. In the following, packaging substrate refers to both a packaging substrate in which individual packaging substrates are arranged before being singulated, or a substrate in a singulated state into a single product, depending on the context.

[0107] In this specification, dicing or singulation may refer to dividing a packaging substrate including a glass substrate as a core layer into a plurality of units. Also, a substrate using a glass substrate as a core layer may be variously called a core substrate, a glass substrate, a packaging substrate, etc.

[0108] 6(a) to 6(c) are diagrams illustrating cross sections of a packaging substrate according to an embodiment.

[0109] As described with reference to FIGS. 1 to 5, a core via and a cavity portion may be formed in the glass substrate 21. A core distribution layer and a cover layer may be formed in the upper layer. The lower layer may also have a multi-layer structure including an insulating layer and a metal distribution pattern. In the following drawings, for convenience of explanation, a packaging substrate 20 including a glass substrate 21, an upper layer 70 formed on a first surface of the glass substrate 21, and a lower layer 80 formed on a second surface thereof will be described in a simplified manner, and detailed explanations of the remaining detailed configurations will be omitted.

[0110] 6, an upper layer 70 is disposed on a first surface of the glass substrate 21. Optionally, a lower layer 80 may be disposed on a second surface of the glass substrate 21.

[0111] The upper layer 70 may include an upper distribution layer 71 having a multi-layer laminate structure including an upper metal pattern (upper distribution pattern) and an upper insulating layer, and a first cover layer 72 formed on the upper distribution layer 71 to protect the substrate. The specific arrangement of the upper distribution pattern and the upper insulating layer in the upper distribution layer is omitted for illustration purposes.

[0112] The lower layer 80 may also include a lower distribution layer 81 having a multi-layer structure including a lower metal pattern (lower distribution pattern) and a lower insulating layer, and a second cover layer 82 formed on the upper part of the lower distribution layer 81 to finally planarize and protect the substrate. The arrangement of the lower distribution pattern and the lower insulating layer in the lower distribution layer is omitted in the drawing.

[0113] The first cover layer 72 and / or the second cover layer 82 may be implemented with a solder resist for protecting the surface circuit from the external environment, or may be implemented with a polyimide film (PI), which is a heat-resistant insulating film having high thermal stability and high mechanical strength, depending on the embodiment.

[0114] Core vias, cavities and metal pattern layers are created in the glass substrate 21, and semiconductor elements (not shown) are mounted on the top layer 70, or before being mounted, the packaging substrate can be cut into specific units.

[0115] The packaging substrate can be cut along cutting lines, which are locations where the cuts are planned to be made and are located at predetermined positions.

[0116] In an embodiment, a metal pattern layer may not be disposed on a portion of the upper layer 70 and / or a portion of the lower layer 80 corresponding to the cutting line, that is, only an insulating layer or a protective layer may be disposed on a portion of the upper layer 70 and / or a portion of the lower layer 80 that is to be cut and removed.

[0117] The cut packaging substrate 20 generally has a cross section as shown in Fig. 6(a) . That is, the cut surface and the first surface, or the cut surface and the second surface, of the packaging substrate 20 have a roughly angular shape, and the corners are relatively sharp.

[0118] In a structure such as that shown in (a) of FIG. 6, cracks and breakages can easily occur due to the edges or cut surfaces of the glass substrate 21, so an embodiment according to the present invention proposes a packaging substrate such as that shown in (b) or (c) of FIG. 6.

[0119] 6(b), the cut surface of the glass substrate 21 may have a shape that protrudes from the upper layer 70 and / or the lower layer 80. That is, the glass substrate 21 may have an edge region 213a that is an edge that protrudes from the upper layer 70 and / or the lower layer 80. In the edge region of the first surface and / or the edge region 213a of the second surface adjacent to the cut surface of the glass substrate 21, the upper layer 70 and / or the lower layer 80 may be removed, and the first surface and / or the second surface of the glass substrate 21 may be exposed to the outside.

[0120] 6(b), the cut surface of the glass substrate 21 may have a shape protruding from the upper distribution layer 71 and / or the lower distribution layer 81. That is, the glass substrate 21 may have an edge region 213a that is an edge protruding from the upper distribution layer 71 and / or the lower distribution layer 81. In the edge region of the first surface and / or the edge region of the second surface 213a adjacent to the cut surface of the glass substrate 21, the upper distribution layer 71 and / or the lower distribution layer 81 may be removed to expose the first surface and / or the second surface of the glass substrate 21 to the outside. The upper distribution layer 71 and / or the lower distribution layer 81 may be arranged in two or more layers, three or more layers, four or more layers, or five or more layers in the upper layer 70 and the lower layer 80, respectively. Also, ten or less layers, eight or less layers, or six or less layers may be arranged.

[0121] Depending on the embodiment, the upper layer 70 may further include an insulating layer, such as a first cover layer 72, stacked on the first surface, and the edge of the insulating layer may be disposed inward from the edge of the glass substrate 21, and the edge region 213a may include the area from the edge of the glass substrate 21 to the edge of the insulating layer.

[0122] Additionally, the lower layer 80 may further include an insulating layer such as a second cover layer 82 laminated on the second surface, where the edge of the insulating layer is disposed inward from the edge of the glass substrate 21, and the edge region 213a may include the area from the edge of the glass substrate 21 to the edge of the insulating layer.

[0123] The cutting step may be a step in which the panel substrate is cut into quad substrates.

[0124] The cutting step may be a step in which the quad substrate is cut into strip substrates.

[0125] The cutting step may be a step in which the strip substrate is cut into individual packaging substrates.

[0126] This process is collectively referred to as a process of cutting into units.

[0127] In a cutting process of the packaging substrate 20, i.e., a process of cutting into units, the upper layer 70 or the lower layer 80 may be removed, and through this process, after the cutting process, the side of the glass substrate 21 may protrude in the cutting direction beyond the layer laminated on the upper or lower side. The removal may be performed by a method such as laser irradiation, but is not limited thereto.

[0128] A portion of the upper layer or the lower layer may be removed so that the width of the edge region 213a where the glass substrate 21 is exposed by removing the upper layer 70 or the lower layer 80 is, for example, 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more from the edge of the insulating layer to the edge of the glass substrate 21. A portion of the upper layer or the lower layer may be removed so that the width of the edge region 213a is 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less. That is, the width of the removed portion (removal line) may be 2 times or more, or 2.2 times or more of the above-mentioned width. The width of the removed portion (removal line) may be 4 times or less, or 3 times or less.

[0129] As shown in FIG. 6(b), the glass substrate 21 protrudes in the cutting direction, so that the cross section of the packaging substrate decreases in thickness from the upper layer 70 or the lower layer 80 toward the glass substrate 21, and the cross section may have an overall "U" shape with tapered shapes facing each other.

[0130] The protruding edge region 213a of the glass substrate 21 may be ground to have rounded corners, as shown in Fig. 6(c) . That is, the edge region 213a disposed at the corner of the glass substrate 21 may be a curved surface.

[0131] Or, according to one example, the edge regions 213a located at the corners of the glass substrate 21 may be chamfered.

[0132] In one example, the top layer 70 or bottom layer 80 may also be removed or ground to create a tapered shape that thins in the direction of the cut.

[0133] As shown in FIG. 6, when the upper layer is removed from the edge region 213a of the glass substrate 21, the glass substrate 21 is exposed by the amount of the removed upper layer.

[0134] The width from the edge of the insulating layer to the edge of the glass substrate 21 may be, for example, 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more, and the width of the edge region 213a may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0135] FIG. 7 is a top view of a packaging substrate according to an embodiment.

[0136] As shown in the figure, when the packaging substrate cut into units is viewed from above, a first cover layer 72 is formed on a first surface of the glass substrate 21, and an upper layer including the first cover layer 72 is removed in an edge region 213a. When the glass substrate 21 has a rectangular shape, the upper layer may be removed along the four sides of the glass substrate 21. In other words, the edge of the first cover layer 72 is disposed inward from the edge of the glass substrate 21, and the edge region 213a may refer to the region from the edge of the glass substrate 21 to the edge of the first cover layer 72.

[0137] In the exposed edge region 213a of the glass substrate 21, as an example, cracks or chipping of the glass can be relatively easily observed.

[0138] As described above, when a glass substrate is used as a core structure of a packaging substrate, there is a high possibility that the substrate may be broken or cracked due to internal stress and external impact during the manufacturing process, and in order to detect this, analysis of all cross sections of the cut packaging substrate is required. For cross-sectional analysis, an inspection using a microscope or the like is required on the cut surface of the packaging substrate, which requires a considerable amount of time and cost.

[0139] According to this embodiment, defects such as cracks and chippings can be quickly and accurately detected by only inspecting the exposed region 213a of the glass substrate 21 as shown in Fig. 7. In other words, by detecting defects in the edge region 213a of the glass substrate 21 where the upper or lower layer has been removed and in the cut surface of the glass substrate, there is an advantage that surface inspection and cross-section inspection of the glass substrate can be performed simultaneously without expensive equipment.

[0140] FIG. 8 is a flowchart illustrating a process for manufacturing a packaging substrate according to an embodiment in cross section.

[0141] According to the embodiment of FIG. 8, an upper layer 70 may be formed on a first surface of a glass substrate 21, and a semiconductor device (not shown) may be stacked on the upper layer 70.

[0142] First, as shown in FIG. 8(a), a laser is used to remove the upper layer 70 along the cutting line by a predetermined width to form a removal line (Laser Ablation).

[0143] A green laser or an ultraviolet laser can be used to remove the laminated upper layer 70, specifically an insulating layer such as ABF, along a cutting line such as a dicing street.

[0144] At this time, the width of the upper layer 70 to be removed, i.e., the width of the removal line, may be approximately 10 μm to 600 μm. The width may be 10 μm or more, 14 μm or more, 20 μm or more, 30 μm or more, 40 μm or more, 50 μm or more, 60 μm or more, or 70 μm or more. The width may be 600 μm or less, 550 μm or less, 500 μm or less, 450 μm or less, 400 μm or less, 380 μm or less, 360 μm or less, 340 μm or less, 320 μm or less, 300 μm or less, 280 μm or less, 260 μm or less, 240 μm or less, 220 μm or less, 200 μm or less, or 180 μm or less. The width of the upper layer 70 to be removed may be set to approximately twice or more the width of the edge region of the glass substrate 21 to be protruded.

[0145] Meanwhile, as shown, when the upper layer 70 is removed using a laser, substantially no damage is formed in the glass substrate 21 .

[0146] Thereafter, as shown in FIG. 8(b), a filamentation process (Laser Filamentation) may be performed on the glass substrate 21 from which the upper layer has been removed to form filaments along the cutting lines.

[0147] The method of cutting a substrate using a laser beam such as an infrared laser (IR laser) is a method in which an ultrashort laser beam is focused inside the glass substrate 21 and irradiated along a desired cutting path to induce an internal filamentation phenomenon, etc., to form a cut groove of a certain depth inside the glass substrate 21. By forming the filamentation, defects can be formed inside the glass substrate 21 along the cutting surface.

[0148] As the ultrashort laser beam passes through the glass substrate 21, some of it is absorbed and energy is transferred to the constituent molecules. Due to the characteristics of the ultrashort laser pulse, which has a high energy density, the absorbed energy density is also high, so plasma is instantaneously formed inside the glass substrate 21. When continuous pulses are input, this plasma may affect the optical characteristics of the subsequent pulses. The plasma thus generated disappears after a certain lifetime, and may be deformed into a structure different from that of the surrounding material. Depending on the cutting conditions, a narrow and long empty space may be formed in the thickness direction in the irradiated part of the ultrashort laser beam, which is called "filamentation."

[0149] Filamentation is different from gaps or cracks caused by thermal expansion. Since the pulse width is shorter than the reaction time of the molecular bond structure, it is a long, narrow gap that is formed instantaneously when energy is concentrated in the irradiated area of ​​the ultrashort laser beam, rather than affecting surrounding molecules with thermal or vibrational energy.

[0150] Once the filamentation is formed, the glass substrate 21 can be cut using the filamentation, that is, the glass substrate 21 can be separated into units (Separation), as shown in FIG. 8(c).

[0151] As shown in the figure, in order to cut the glass substrate 21, a tensile stress or a rotational force (rotational torque) is applied to the filamentation, so that the glass substrate 21 can be separated into two or more units.

[0152] In other embodiments, the glass substrate 21 may be separated using a laser or a dicing saw.

[0153] In this manner, when the glass substrate 21 is separated into predetermined units, as shown in FIG. 8(c), the insulating layer of the upper layer 70 has a tapered shape that becomes thinner in the cut surface direction of the glass substrate 21, and the glass substrate 21 has a shape in which the upper layer 70 is exposed and protrudes in the cut surface direction.

[0154] Depending on the embodiment, when a green laser is used to remove the upper layer 70, the laser speed at which the upper layer 70 is irradiated may be 20 mm / s to 40 mm / s. The laser speed used for filamentation irradiation may be 50 mm / s to 150 mm / s, or 80 mm / s to 120 mm / s.

[0155] FIG. 9 is a flowchart illustrating a process for manufacturing a packaging substrate according to another embodiment in cross section.

[0156] As shown in (a) of Fig. 9, an upper layer 70 is formed on a first surface of a glass substrate 21, and a lower layer 80 is formed on a second surface. That is, in the glass substrate 21 of Fig. 8, the upper layer 70 is formed only on the first surface out of the first and second surfaces, and therefore only the upper layer 70 is removed, but in the case of Fig. 9, the lower layer 80 including an insulating layer is also formed on the second surface of the glass substrate 21, and therefore the insulating layer can be removed on both sides.

[0157] The width of the removed upper layer 70 and the width of the lower layer 80 may be in the same range. Specifically, the width of the removed lower layer 80 may be 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more based on the width from the edge of the insulating layer to the edge of the glass substrate in the unit glass substrate. Also, the width may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0158] The width of the upper layer 70 and the lower layer 80 to be removed may vary depending on the design of the semiconductor device or motherboard to be mounted. The removal width of the lower layer 80 may be larger than that of the upper layer 70, and specifically, the difference between the removal width of the upper layer and the removal width of the lower layer may be 1 μm or more, 3 μm or more, 5 μm or more, or 10 μm or more. The difference may be 20 μm or less.

[0159] The laser irradiation intensity for removing the insulating layer is not greater than the irradiation intensity for forming filamentation, and no damage or defects are formed in the glass substrate 21 even if the laser is used on both sides.

[0160] The insulating layer may be removed by irradiating the laser simultaneously or sequentially on both sides on which the upper layer 70 and the lower layer 80 are formed. Meanwhile, the laser for removing the upper layer 70 and the lower layer 80 may act on either side, but the laser for generating filamentation may be irradiated only on a single side, either the first side or the second side, as shown in FIG. 9(b).

[0161] Separation of the glass substrate 21 after the filamentation process can be performed based on tension or rotational torque due to an external force, as shown in FIG. 9(c).

[0162] 10(a) and (b) are photographs showing a manufacturing process of a packaging substrate according to an embodiment.

[0163] Fig. 10(a) is a sectional view and a top view of the glass substrate 21 (before being separated into units) from which the upper layer 70 has been removed as shown in Fig. 8(a) or Fig. 9(a). That is, it is a photograph corresponding to an enlargement of the dotted rectangular region in Fig. 9(a), which is a part of the substrate.

[0164] 10(a), it can be seen that the upper layer 70 is removed by a predetermined width w, and the glass substrate 21 is exposed by the removed width w in the top view. As can be seen in the cross section, no defects are formed in the glass substrate 21 even when the upper layer 70 is removed. The removed upper layer 70 may have a tapered shape that becomes thinner in the direction of the cut surface.

[0165] Fig. 10(b) is a photograph showing the cut edges of the glass substrate 21 after it has been cut into units according to Fig. 8(a) and Fig. 9(a). The glass substrate 21 is separated in a generally straight line, with the upper layer 70 and the lower layer 80 disposed on both sides of the glass substrate, each at a certain distance inward from the edge of the glass substrate.

[0166] As shown in the figure, the glass substrate 21 can be separated based on the filamentation formed along a predetermined cutting line. Such separation reduces the possibility of defects occurring or existing in the glass, and even if defects do occur, they can be detected in a quick and relatively simple manner, thereby further improving the efficiency of the manufacturing process of the semiconductor packaging substrate, including the unitization process of the glass substrate.

[0167] Meanwhile, according to one embodiment, the edge region disposed at the corner of the glass substrate 21 may be processed to have a curved surface. That is, the edge region of the glass substrate 21 may be ground. That is, the corner of the glass substrate 21 may be rounded from a sharp cut state (see the example photograph of FIG. 11).

[0168] FIG. 11 is a photograph of a cross section of a ground glass substrate according to an embodiment.

[0169] As shown, the cut surface (indicated as "CL" in FIG. 11) of the glass substrate 21 protruding from the upper layer or the lower layer can be polished to be round in cross section through grinding. The edge of the glass substrate removed through the grinding process may be approximately 10 μm or more, 20 μm or more, 30 μm or more, or 50 μm or more, or approximately 100 μm or less.

[0170] Through grinding, the corners of the cut surface may be curved as shown in FIG. 11, or may be deformed into a C-shape (curved shape) or R-shape (round shape) chamfer shape according to other embodiments.

[0171] The packaging substrate 20 having a cut surface may have a side surface corresponding to the thickness in a side (or cross-sectional) view. Exemplarily, the shape of the ground side surface may be a shape in which a corner where the side surface and the top surface of the packaging substrate intersect is chamfered (Flat Edge), or a shape in which a side surface connecting the top surface and the bottom surface is rounded and ground so that a central portion of the side surface protrudes (Pencil Edge), etc.

[0172] The side (edge) of the packaging substrate 20 may be a straight line or a broken piece of glass immediately after the cut surface is formed, and may be manufactured into a shape having a certain radius of curvature by grinding. In this case, the radius of curvature is called the side radius of curvature.

[0173] The side curvature radius of the packaging substrate 20 may be 0.05 mm or more, 0.1 mm or more, 0.15 mm or more, or 0.2 mm or more. The side curvature radius may be 2.0 mm or less, 1.8 mm or less, 1.6 mm or less, 1.2 mm or less, 1 mm or less, 0.8 mm or less, or 0.6 mm or less. In this case, it is possible to improve workability by minimizing the occurrence of cracks in the packaging substrate or glass substrate during manufacturing, transportation, etc.

[0174] For example, when grinding is performed with a blade design angle of 90°±1° and a cutting amount of 0.08 to 0.14 mm, a packaging substrate with an edge curvature radius of 0.241 mm can be manufactured.

[0175] Also, for example, when grinding is performed with a blade design angle set to 120°±1° and a cutting amount set to 0.05 to 0.12 mm, a packaging substrate with an edge curvature radius of 0.522 mm can be manufactured.

[0176] Fig. 12 shows a glass substrate according to another embodiment as viewed from above and a photograph of a portion thereof. The glass substrate may be rounded not only in cross section but also in the corners of a rectangle as viewed from above. Fig. 12(a) shows a unit glass substrate as viewed from above, and the first surface 213 and the second surface 214 may also be rounded to have rounded corners as shown.

[0177] A packaging substrate having a rectangular shape has four corners when viewed from above, and the corners may be rounded to have a predetermined curvature to remove the sharp corners. This radius of curvature is called a substrate curvature radius. The substrate curvature radius may be 0.5 mm or more, 1 mm or more, 1.2 mm or more, or 1.5 mm or more. The substrate curvature radius may be 8 mm or less, 7 mm or less, 6 mm or less, or 5 mm or less. In this case, it is possible to minimize the occurrence of cracks at the corners and at the same time stably secure an area in which the upper and / or lower electrically conductive layers are disposed.

[0178] Meanwhile, depending on the embodiment, the apex of the rectangular glass substrate 21 may also be curved through grinding. When the apex portion is ground, the risk of damage or cracking can be reduced when the glass substrate 21 is moved or transported on a tray, etc. An appropriate value for the curvature of the ground apex portion can be derived by setting a diameter that generates the smallest deviation from a predetermined target value.

[0179] The cut surface of a glass substrate that has not been cut and processed has a non-uniform right-angle deviation, and hackles are also generated at the cut corners, which may cause further damage such as cracks or chipping of the glass substrate. A glass substrate having a curved edge or chamfered cut surface through grinding can significantly reduce the risk of such further damage. In addition, when the glass substrate or packaging substrate is moved or transported on a tray for additional processes, external impacts can be appropriately dispersed, minimizing defects due to cracks or chipping.

[0180] According to other embodiments, grinding may be applied not only to the protruding glass substrate 21, but also to the top or bottom layers.

[0181] The packaging substrate and the manufacturing method thereof according to the embodiments described above are effective for inspecting defects that may occur in a packaging substrate including a glass structure, and can effectively protect the glass substrate from external impacts.

[0182] The present invention described above has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. That is, the scope of the present invention is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concept of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0183] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21, 21a Glass substrate 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 213a Edge region 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26,70 Upper layer 25,71 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 281 Interior Space 282 Cavity Distribution Layer 40 Cavity element 60 Cover Layer 72 1st cover layer 80 Lower Tier 81 Lower distribution layer 82 Second Cover Layer

Claims

1. 1. A packaging substrate, comprising: a glass substrate including a first surface and a second surface opposed to each other; an upper layer laminated on the first surface or a lower layer laminated below the second surface; the glass substrate having an edge region; The edge region is An edge of the glass substrate; and a region of the glass substrate that protrudes beyond the upper layer or the lower layer.

2. the upper layer includes a first insulating layer laminated on the first surface; an edge of the first insulating layer is disposed inward from an edge of the glass substrate; The packaging substrate of claim 1 , wherein the edge region includes an edge of the glass substrate and an edge of the first insulating layer.

3. the lower layer includes a second insulating layer laminated below the second surface; an edge of the second insulating layer is disposed inward from an edge of the glass substrate; The packaging substrate of claim 1 , wherein the edge region includes an edge of the glass substrate and an edge of the second insulating layer.

4. 4. The packaging substrate according to claim 2, wherein a width from an edge of the first insulating layer to an edge of the glass substrate, a width from an edge of the second insulating layer to an edge of the glass substrate, or both of these widths are independently 5 μm to 200 μm.

5. The packaging substrate according to claim 1 , wherein the corners of the glass substrate disposed in the edge region are curved.

6. The packaging substrate of claim 1 , wherein the corners of the glass substrate disposed in the edge region are chamfered.

7. The packaging substrate of claim 1 , wherein the upper layer or the lower layer each has a tapered shape that thins toward the edge region.

8. The packaging substrate of claim 1 , wherein a semiconductor device is mounted on top of the top layer.

9. A method for manufacturing a packaging substrate, comprising: providing a glass substrate having opposing first and second surfaces and forming a top layer on the first surface; removing a portion of the upper layer along a cut line at a location where the cut is planned to be made to form a removal line; a filamentation process step of forming a filament in the glass substrate along the removal line; cutting the glass substrate using the filamentation; A method for producing the packaging substrate according to claim 1 , comprising:

10. Prior to the filamentation process step, forming a sublayer below the second surface; The method for manufacturing a packaging substrate according to claim 9 , further comprising the step of removing a portion of the lower layer along the cutting line to form a removal line.

11. The method for manufacturing a packaging substrate according to claim 9 or 10, wherein the width of the removal line is 5 μm or more.

12. The method for manufacturing a packaging substrate according to claim 9 or 10, wherein the upper layer or the lower layer has a tapered shape that becomes thinner in a cut surface direction of the glass substrate.

13. The step of cutting the glass substrate includes: The method for manufacturing a packaging substrate according to claim 9 , further comprising the step of: applying a tensile stress or a rotational force to the filamentation to separate the glass substrate into two or more portions, thereby forming a cut surface on the glass substrate.

14. After the step of cutting the glass substrate, The method for manufacturing a packaging substrate according to claim 9 , further comprising the step of grinding a cut surface of the cut glass substrate.

15. an edge region including an edge of the glass substrate and a region of the glass substrate that protrudes beyond the upper layer or the lower layer; The method for manufacturing the packaging substrate includes:

11. The method for manufacturing a packaging substrate according to claim 9 or 10, further comprising the step of detecting defects in any one selected from the group consisting of an edge region of the glass substrate, a cut surface of the glass substrate, a removal line of the upper layer, a removal line of the lower layer, and combinations thereof.

Images