Clock abnormality detection circuit

Abstract

To provide a clock abnormality detection circuit that can detect period abnormalities in a test clock with high accuracy using a simple configuration.SOLUTION: A test clock signal generating device includes a periodic signal generating circuit which generates a periodic signal whose level is inverted at the start of each cycle of a test clock signal, a delay circuit which delays the periodic signal by a time shorter or longer than a specified cycle of the test clock signal to output a delayed signal of the periodic signal, a hold circuit which holds the level of the delayed signal at the start of each cycle of the test clock signal to generate a held signal, and determination means which determines whether the level of the periodic signal and the level of the held signal match and generates a determination result.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a clock anomaly detection circuit that detects anomalies in the period of a clock signal. [Background technology]

[0002] General electronic circuits often operate in synchronization with an input clock signal, and if there is an abnormality in which the period of the clock signal is shorter than the specified period by even one period, the operation of the circuit cannot be guaranteed.Similarly, if there is an abnormality in which the period is longer than the specified period, it is expected that the operating performance required of the circuit will not be met.

[0003] 2. Description of the Related Art Conventionally, a clock anomaly detection circuit for detecting anomalies in the cycle of a clock signal is disclosed in, for example, Patent Document 1.

[0004] The clock anomaly detection circuit disclosed in Patent Document 1 includes a delay circuit that delays the test clock signal by one period, a comparison circuit that compares the test clock signal with the delayed clock signal obtained from the delay circuit, and a counter that measures the period during which the comparison circuit has a high-level output. When the test clock signal and the delayed clock signal match, the output signal of the comparison circuit goes to a low level, and the test clock signal is determined to be normal, whereas when the test clock signal and the delayed clock signal do not match, the output signal of the comparison circuit goes to a high level. The period during which the comparison circuit has a high-level output is measured by the counter. When the high-level period exceeds a preset period of period anomaly detection, the counter generates an anomaly detection signal, and the test clock signal is determined to be abnormal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 10-240374 Summary of the Invention [Problem to be solved by the invention]

[0006] In such a conventional clock anomaly detection circuit, a high-speed clock signal is supplied to the counter in addition to the clock signal under test in order to measure the period during which the comparator circuit is in a high-level output state by the counter. The counter measures the period during which the comparator circuit is in a high-level output state by counting the pulses of the high-speed clock signal.

[0007] However, in conventional clock anomaly detection circuits, it is necessary to prepare a high-speed clock signal and to have a counter for counting the pulses of the high-speed clock signal, which makes the circuit configuration complicated. In addition, since it is necessary to take into consideration the accuracy of the high-speed clock signal, it is necessary to predetermine the allowable range of the detection period for periodic anomalies in the inspected clock signal.

[0008] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a clock anomaly detection circuit that has a simple configuration and is capable of detecting period anomalies in a clock under test with high accuracy. [Means for solving the problem]

[0009] The clock anomaly detection circuit of the present invention is a clock anomaly detection circuit that detects an anomaly in the period of a clock signal to be tested, and is characterized by comprising: a periodic signal generation circuit that generates a periodic signal whose level is inverted at the start of each period of the clock signal to be tested; a delay circuit that delays the periodic signal by a time shorter or longer than a period specified for the clock signal to be tested, and outputs a delayed signal of the periodic signal; a hold circuit that holds the level of the delayed signal at the start of each period of the clock signal to be tested, and generates a held signal; and a discrimination circuit that determines whether the level of the periodic signal and the level of the held signal match and generates a discrimination result.

[0010] The clock anomaly detection circuit of the present invention is a clock anomaly detection circuit that detects an anomaly in the period of a clock signal to be tested, and is characterized in comprising: a periodic signal generation circuit that generates a periodic signal whose level is inverted at the start of each period of the clock signal to be tested; a first delay circuit that delays the periodic signal by a time shorter than a period specified for the clock signal to be tested and outputs a first delayed signal of the periodic signal; a second delay circuit that delays the periodic signal by a time longer than the specified period and outputs a second delayed signal of the periodic signal; a hold circuit that holds the level of the first delayed signal at the start of each period of the clock signal to be tested to generate a first held signal, and holds the level of the second delayed signal to generate a second held signal; a first discrimination circuit that determines whether the level of the periodic signal and the level of the first held signal match and generates a discrimination result; and a second discrimination circuit that determines whether the level of the periodic signal and the level of the second held signal match and generates a discrimination result. Effect of the Invention

[0011] According to the clock anomaly detection circuit of the present invention, a periodic signal whose level is inverted at the start of each cycle of the clock signal to be tested is delayed by a delay circuit by a time shorter or slightly longer than one specified cycle of the clock signal to be tested to generate a delayed signal, the level of the delayed signal is held at the start of each cycle of the clock signal to be tested to generate a held signal, and a discrimination circuit discriminates whether the level of the periodic signal and the level of the held signal match, making it possible to detect period anomalies in the clock signal to be tested with a simple configuration and with high accuracy. [Brief description of the drawings]

[0012] [Figure 1] 1 is a circuit diagram of a clock anomaly detection circuit 10 according to a first embodiment of the present invention. [Diagram 2] 4 is a time chart showing signal waveforms at various parts of the clock anomaly detection circuit 10 when the test clock signal is normal. [Diagram 3] 4 is a time chart showing signal waveforms at various parts of the clock anomaly detection circuit 10 when an abnormality occurs in the inspected clock signal. [Figure 4] FIG. 11 is a circuit diagram of a clock anomaly detection circuit 40 according to a second embodiment of the present invention. [Diagram 5] 4 is a time chart showing signal waveforms at various parts of the clock anomaly detection circuit 40 when the test clock signal is normal. [Figure 6] 4 is a time chart showing signal waveforms at various parts of the clock anomaly detection circuit 40 when an abnormality occurs in the inspected clock signal. [Figure 7] 1 is a circuit diagram showing a modified example of the clock anomaly detection circuit 10. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. EXAMPLES

[0014] 1 shows a circuit diagram of a clock anomaly detection circuit 10 according to a first embodiment. The clock anomaly detection circuit 10 includes three registers 11, 14, and 18, inverters 12 and 16, a delay circuit 13, an XOR circuit 15, OR circuits 17 and 20, and AND circuits 19 and 21. A test clock signal CK and a reset signal RS are input to the clock anomaly detection circuit 10. The clock anomaly detection circuit 10 detects a short cycle anomaly in which the actual cycle of the test clock signal CK becomes shorter than a cycle (a specified cycle TCK) specified in advance for the test clock signal CK.

[0015] The register 11, the inverter 12, and the AND circuit 19 constitute a frequency division circuit (periodic signal generating circuit) that divides the frequency of the test clock signal CK by two. A reset signal RS is supplied to one of the two input terminals of the AND circuit 19. The output terminal of the inverter 12 is connected to the input terminal of the register 11. In addition to the input terminal, the register 11 has a clock terminal and an output terminal. The test clock signal CK is supplied to the clock terminal of the register 11, and the output terminal is connected to the input terminal of the inverter 12. In response to the rising edge of the test clock signal CK supplied to the clock terminal, the register 11 holds the signal level of the input terminal and outputs the held signal from the output terminal. The inverter 12 inverts the level of the output terminal of the register 11 and outputs a signal having the inverted level. The AND circuit 19 performs a logical AND operation on the level of the reset signal RS and the output signal level of the inverter 12.

[0016] The delay circuit 13 delays the input signal by a delay time (less than the specified period TCK) slightly shorter than the specified period TCK of the test clock signal CK. The input terminal of the delay circuit 13 is connected to the output terminal of the register 11, and receives the held signal of the register 11 as an input signal. The output terminal of the delay circuit 13 is connected to one of the two input terminals of the OR circuit 20. The other input terminal of the OR circuit 20 is an inverting input terminal, to which a reset signal RS is supplied. The output terminal of the OR circuit 20 is connected to the input terminal of the register 14. In addition to the input terminal, the register 14 has a clock terminal and an inverting output terminal. The test clock signal CK is supplied to the clock terminal of the register 14, and the inverting output terminal is connected to one of the two input terminals of the XOR circuit 15. The register 14 holds the signal level of the input terminal in response to the rising edge of the test clock signal CK supplied to the clock terminal, and outputs the inverted level of the held level from the output terminal.

[0017] The other input terminal of the XOR circuit 15 is connected to the output terminal of the register 11. The XOR circuit 15 corresponds to a discrimination circuit, and takes the exclusive OR of the output signal levels of the registers 11 and 14. As will be described later, when the output signal level of the XOR circuit 15 changes from a low level (L) to a high level (H), this indicates that a short-period anomaly has been detected in the inspected clock signal CK.

[0018] The inverter 16, the OR circuit 17, the register 18, and the AND circuit 21 constitute a holding circuit that holds the high-level output of the XOR circuit 15. One of the two input terminals of the OR circuit 17 is connected to the output terminal of the XOR circuit 15, and the other input terminal is connected to the output terminal of the register 18. The output terminal of the OR circuit 17 is connected to one of the two input terminals of the AND circuit 21. A reset signal RS is supplied to the other input terminal of the AND circuit 21. The output terminal of the AND circuit 21 is connected to the input terminal of the register 18. In addition to its input terminals, the register 18 has a clock terminal and an output terminal. The clock terminal of the register 18 is supplied with the test clock signal CK via the inverter 16, and the output terminal is connected to the other input terminal of the OR circuit 17 as described above. In response to the rising edge of the inverted signal of the test clock signal CK supplied to the clock terminal, the register 18 holds the signal level of the input terminal and outputs it from the output terminal. An abnormality detection flag signal is output from the output terminal of the register 48, and when a high-level abnormality detection flag signal is output, this indicates that a short-period abnormality has been detected in the test clock signal CK.

[0019] Next, the operation of the clock anomaly detection circuit 10 having the above-mentioned configuration will be described with reference to the time charts of FIG. 2 and FIG.

[0020] The test clock signal CK shown in Figures 2 and 3 has a specified period TCK under normal conditions, and repeats low and high levels with a duty ratio of 50%. Of course, the duty ratio of the test clock signal CK may be other than 50%. In addition, although the start point of one cycle of the test clock signal CK is set to the rising timing of the test clock signal CK in this embodiment 1, the start point may be set to a timing other than this. In the example of the test clock signal CK shown in Figure 2, the period is always the normal period TCK, whereas in the example of the test clock signal CK shown in Figure 3, the period is shorter than the specified period TCK, causing a short period anomaly.

[0021] 2, the odd-numbered times T11, T13, ... among the times T11 to T22 are falling timings, and the even-numbered times T12, T14, ... are rising timings. At time T11, the clock signal CK to be inspected is at a low level, and at time T12, the clock signal CK to be inspected is at a high level, which is repeated at the following times T13 to T22.

[0022] Register 11 holds and outputs the level of its input end (the output signal level of AND circuit 19) at times T12, T14, . . . when the test clock signal CK rises, register 14 holds the level of its input end (the output signal level of OR circuit 20) at times T12, T14, . . . when the test clock signal CK rises and outputs the inverted level of that held level, and register 18 holds and outputs the level of its input end (the output signal level of AND circuit 21) at times T11, T13, . . . when the test clock signal CK falls.

[0023] 2, when the reset signal RS changes from low to high between time T12 and time T13, the reset signal RS is low at the previous time T11, so that the output signal level of the AND circuit 21 is low and the output signal level of the register 18 is low at time T11. The anomaly detection flag signal, which is a low-level output signal of the register 18, indicates that the test clock signal CK is normal.

[0024] At time T12, the reset signal RS is at a low level, so the output signal of the AND circuit 19 is at a low level. This low level causes the output signal of the register 11 to be at a low level at time T12. Also, at time T12, the output signal of the OR circuit 20 is at a high level, so this high level causes the output signal of the register 14 to be at a low level. Up until time T12, the clock anomaly detection circuit 10 is in a reset state.

[0025] At time T13, the reset signal RS is at a high level, so that the clock anomaly detection circuit 10, which was in the reset state, starts a clock anomaly detection operation, and the exclusive OR of the low-level output signal of the register 11 and the low-level output signal of the register 14 is obtained by the XOR circuit 15. Since the XOR circuit 15 generates a low-level output signal, a low-level output signal is supplied from the OR circuit 17 to the AND circuit 21, so that the output signal of the AND circuit 21 is maintained at a low level. The anomaly detection flag signal, which is the output signal of the register 18, is maintained at a low level at time T13, indicating that the inspected clock signal CK is normal. In other words, a high-level anomaly detection flag signal is not generated.

[0026] At the rising edge of the test clock signal CK after time T14, the level held in the register 11 up to that point is inverted by the inverter 12, so that the register 11 holds and outputs the inverted level of the held level at the next rising edge, and the output signal of the register 11 switches between high and low levels at each rising edge of the test clock signal CK. As a result, the output signal of the register 11 has a period twice that of the test clock signal CK.

[0027] At time T14, the output signal of register 11 is delayed by delay circuit 13 for a time slightly less than one specified period TCK of the test clock signal CK, and the delayed signal is input to the input terminal of register 14 via OR circuit 20. Since the delay time of delay circuit 13 is a time slightly less than one specified period TCK of the test clock signal CK, the low-level output signal of OR circuit 20 is held in register 14 at time T14, but a high-level signal is output from register 14 due to an inverted output.

[0028] At time T15, contrary to time T13, the high-level output signal of register 11 and the high-level output signal of register 14 are input to XOR circuit 15, but XOR circuit 15 continues to generate a low-level output signal, so that, as at time T13, a low-level output signal is supplied from OR circuit 17 to AND circuit 21, and the output signal of AND circuit 21 is maintained at a low level. The abnormality detection flag signal output from register 18 continues to be maintained at a low level at time T15, indicating that the inspected clock signal CK is normal.

[0029] Even after time T15, it continues to be confirmed that the output signal levels of registers 11, 14 are inverted at the rising edges (even-numbered time points) of the test clock signal CK, and that the output signal levels of registers 11, 14 match at the falling edges (odd-numbered time points) of the test clock signal CK (the signal levels held by registers 11, 14 are different from each other). In the example of Fig. 2 where the cycle of the test clock signal CK is not abnormal, the abnormality detection flag signal output from register 18 is always at a low level, indicating that the test clock signal CK is normal.

[0030] 3 where a short-period anomaly occurs, the odd-numbered times T31, T33, ... among the times T31 to T43 are falling timings, and the even-numbered times T32, T34, ... are rising timings. At time T31, the clock signal CK to be inspected is at a low level, and at time T32, the clock signal CK to be inspected is at a high level, which is repeated at the following times T33 to T43.

[0031] The register 11 holds and outputs the level of its input end (the output signal level of the AND circuit 19) at times T32, T34, . . . when the test clock signal CK rises, the register 14 holds the level of its input end (the output signal level of the OR circuit 20) at times T32, T34, . . . when the test clock signal CK rises and outputs the inverted level of that held level, and the register 18 holds and outputs the level of its input end (the output signal level of the AND circuit 21) at times T31, T33, . . . when the test clock signal CK falls.

[0032] 3, when the reset signal RS changes from low to high between time T32 and time T33, the reset signal RS is at low level at the previous time T31, so that the output signal level of the AND circuit 21 is low and the output signal level of the register 18 is low at time T31. The anomaly detection flag signal, which is a low-level output signal of the register 18, indicates that the inspected clock signal CK is normal.

[0033] At time T32, the reset signal RS is at a low level, so the output signal of the AND circuit 19 is at a low level. This low level causes the output signal of the register 11 to be at a low level at time T32. Also, at time T32, the output signal of the OR circuit 20 is at a high level, so this high level causes the output signal of the register 14 to be at a low level.

[0034] At time T33, the reset signal RS is at a high level, so that the clock anomaly detection circuit 10, which was in the reset state, starts a clock anomaly detection operation, and the exclusive OR of the low-level output signal of the register 11 and the low-level output signal of the register 14 is obtained by the XOR circuit 15. Since the XOR circuit 15 generates a low-level output signal, a low-level output signal is supplied from the OR circuit 17 to the AND circuit 21, so that the AND circuit 21 maintains its low-level output signal. The anomaly detection flag signal, which is the output signal of the register 18, is maintained at a low level at time T33, indicating that the inspected clock signal CK is normal. In other words, a high-level anomaly detection flag signal is not generated.

[0035] At the timing of the rising edge of the test clock signal CK after time T34, the level that had been held in the register 11 up to that point is inverted by the inverter 12, so that the register 11 holds and outputs the inverted level of the held level at the timing of the next rising edge, and the output signal of the register 11 switches between high and low levels at each rising edge of the test clock signal CK.

[0036] At time T34, the output signal of register 11 is delayed by delay circuit 13 for a time slightly less than one specified period TCK of the test clock signal CK, and the delayed signal is input to the input terminal of register 14 via OR circuit 20. Because the delay time of delay circuit 13 is a time slightly less than one specified period TCK of the test clock signal CK, at time T34 the low-level output signal of OR circuit 20 is held in register 14, but a high-level signal is output from register 14 due to an inverted output.

[0037] As shown in FIG. 3, the period from time T34 to time T36 is defined as a short-cycle abnormal clock period of the test clock signal CK, and this period is shorter than one specified cycle TCK.

[0038] At time T35 in the short-cycle abnormal clock period, contrary to time T33, the high-level output signal of register 11 and the high-level output signal of register 14 are input to XOR circuit 15, but since XOR circuit 15 continues to generate a low-level output signal, a low-level output signal is supplied from OR circuit 17 to AND circuit 21, as at time T33, and AND circuit 21 maintains a low-level output signal. The abnormality detection flag signal, which is the output signal of register 18, continues to be maintained at a low level at time T35, indicating that the inspected clock signal CK is normal.

[0039] At time T36 when the short-cycle abnormal clock period ends, the low-level output signal of the register 11 at time T34 is delayed by the delay circuit 13 for a time slightly less than one specified cycle TCK of the test clock signal CK, and the delayed low-level signal is input to the input terminal of the register 14 via the OR circuit 20. That is, although the delay time of the delay circuit 13 is a time slightly less than one specified cycle TCK of the test clock signal CK, the output signal of the delay circuit 13 remains at a low level at time T36 when the short-cycle abnormal clock period ends. Therefore, the low-level output signal of the OR circuit 20 is held in the register 14, and a high level continues to be output from the inverted output of the register 14.

[0040] At time T36, the XOR circuit 15 obtains the exclusive OR of the low-level output signal of the register 11 and the high-level output signal of the register 14. As shown in Fig. 3, the XOR circuit 15 generates a high-level output signal instead of a low-level output signal, and so the OR circuit 17 supplies a high-level output signal to the AND circuit 21. As a result, the output signal of the AND circuit 21 changes from a low level to a high level. This high level is held in the register 18 at time T37, so that the anomaly detection flag signal, which is the output signal of the register 18, changes from a low level to a high level at time T37, indicating an anomaly in the inspected clock signal CK.

[0041] After time T36, the period of the test clock signal CK returns to the specified period TCK and becomes normal. As a result, the output signal level of the register 11 and the output signal level of the register 14 match after time T38, so the output signal of the XOR circuit 15 returns to a low level. However, since the high-level output signal of the register 18 is supplied to the AND circuit 21 via the OR circuit 17, the AND circuit 21 maintains a high-level output signal, and the register 18 maintains this high level at odd-numbered time points T39, T41, ..., so that the anomaly detection flag signal, which is the output signal of the register 18, maintains a high level, indicating an anomaly in the test clock signal CK.

[0042] In this manner, in the clock anomaly detection circuit 10 of the first embodiment, a periodic signal whose level is inverted at each rising timing of the test clock signal CK is generated by a frequency divider circuit including a register 11, the periodic signal is delayed by a delay circuit 13 for a time slightly less than one specified period TCK of the test clock signal CK to generate a delayed signal, the level of the delayed signal is held in a register 14 at each rising timing of the test clock signal CK to generate a held signal, the level of the periodic signal and the level of the held signal are judged by the XOR circuit 15 to match, and if the XOR circuit 15 does not obtain a match judgment result, a high-level anomaly detection flag signal indicating an anomaly in the test clock signal CK is generated, so that a short-period anomaly in which the period of the test clock signal CK is shorter than the specified period TCK can be detected with a simple configuration and with high accuracy. EXAMPLES

[0043] 4 shows a circuit diagram of a clock anomaly detection circuit 40 according to the second embodiment. The clock anomaly detection circuit 40 includes three registers 41, 44, and 48, inverters 42 and 46, a delay circuit 43, an XOR circuit 45, OR circuits 47 and 50, and AND circuits 49, 51, and 52. A test clock signal CK and a reset signal RS are input to the clock anomaly detection circuit 40. The clock anomaly detection circuit 40 detects a long period anomaly in which the actual period of the test clock signal CK becomes longer than a specified period.

[0044] The register 41, the inverter 42, and the AND circuit 49 constitute a frequency division circuit that divides the test clock signal CK by two. A reset signal RS is supplied to one of the two input terminals of the AND circuit 49. The output terminal of the inverter 42 is connected to the other input terminal of the AND circuit 49. The output terminal of the AND circuit 49 is connected to the input terminal of the register 41. In addition to the input terminal, the register 41 has a clock terminal and an output terminal. The test clock signal CK is supplied to the clock terminal of the register 41, and the output terminal is connected to the input terminal of the inverter 42. In response to the rising edge of the test clock signal CK supplied to the clock terminal, the register 41 holds the signal level of the input terminal and outputs it from the output terminal. The inverter 42 inverts the level of the output terminal of the register 41 and outputs a signal having the inverted level. The AND circuit 49 takes the logical product of the level of the reset signal RS and the output signal level of the inverter.

[0045] One of the two input terminals of the OR circuit 50 is an inverting input terminal to which a reset signal RS is supplied. The other input terminal of the OR circuit 50 is a non-inverting input terminal and is connected to the output terminal of the register 41. The output terminal of the OR circuit 50 is connected to the input terminal of the delay circuit 13.

[0046] The delay circuit 43 delays the input signal by a delay time (regular period TCK strong) slightly longer than the regular period TCK of the test clock signal CK. The output terminal of the delay circuit 43 is connected to one of the two input terminals of an AND circuit 51. A reset signal RS is supplied to the other input terminal of the AND circuit 51. The output terminal of the AND circuit 51 is connected to the input terminal of a register 44. In addition to its input terminals, the register 44 has a clock terminal and an output terminal. The test clock signal CK is supplied to the clock terminal of the register 44, and the output terminal is connected to one of the two input terminals of an XOR circuit 45. In response to the rising edge of the test clock signal CK supplied to the clock terminal, the register 44 holds the signal level of the input terminal and outputs it from the output terminal.

[0047] The other input terminal of the XOR circuit 45 is connected to the output terminal of the register 41. The XOR circuit 45 corresponds to a discrimination circuit, and takes the exclusive OR of the output signal levels of the registers 41 and 44. As will be described later, when the output signal level of the XOR circuit 45 changes from a low level (L) to a high level (H), this indicates that a long-period abnormality has been detected in the test clock signal CK.

[0048] The inverter 46, the OR circuit 47, the register 48, and the AND circuit 52 constitute a holding circuit that holds the high-level output of the XOR circuit 45. One of the two input terminals of the OR circuit 47 is connected to the output terminal of the XOR circuit 45, and the other input terminal is connected to the output terminal of the register 48. The output terminal of the OR circuit 47 is connected to one of the two input terminals of the AND circuit 52. A reset signal RS is supplied to the other input terminal of the AND circuit 52. The output terminal of the AND circuit 52 is connected to the input terminal of the register 48. In addition to the input terminals, the register 48 has a clock terminal and an output terminal. The clock terminal of the register 48 is supplied with the test clock signal CK via the inverter 46, and the output terminal is connected to the other input terminal of the OR circuit 47 as described above. In response to the rising edge of the inverted signal of the test clock signal CK supplied to the clock terminal, the register 48 holds the signal level of the input terminal and outputs it from the output terminal. An abnormality detection flag signal is output from the output terminal of the register 48, and when a high-level abnormality detection flag signal is output, this indicates that a long-period abnormality has been detected in the test clock signal CK.

[0049] Next, the operation of the clock anomaly detection circuit 40 having the above-mentioned configuration will be described with reference to the time charts of FIGS.

[0050] The test clock signal CK shown in Figures 5 and 6 has a specified period TCK under normal conditions, and alternates between low and high levels with a duty ratio of 50%. Of course, the duty ratio of the test clock signal CK may be other than 50%. In this second embodiment, the start point of one cycle of the test clock signal CK is set to the rising edge of the test clock signal CK, but the start point may be set to another timing. In the example of the test clock signal CK shown in Fig. 5, the period is always the normal period TCK, whereas in the example of the test clock signal CK shown in Fig. 6, the period is longer than the specified period TCK, causing a long period anomaly.

[0051] 5, the odd-numbered times T51, T53, ... among the times T51 to T64 are falling timings, and the even-numbered times T52, T54, ... are rising timings. At time T51, the clock signal CK to be inspected is at a low level, and at time T52, the clock signal CK to be inspected is at a high level, and this is repeated at the following times T53 to T64.

[0052] The register 41 holds and outputs the level of its input end (the output signal level of the AND circuit 49) at times T52, T54, . . . when the test clock signal CK rises, the register 44 holds and outputs the level of its input end (the output signal level of the AND circuit 51) at times T52, T54, . . . when the test clock signal CK rises, and the register 48 holds and outputs the level of its input end (the output signal level of the AND circuit 52) ​​at times T51, T53, . . . when the test clock signal CK falls.

[0053] 5, when the reset signal RS changes from low to high between time points T54 and T55, the reset signal RS is low at the previous time points T51, T52, and T53, so that the output signal level of the AND circuit 52 is low and the output signal level of the register 48 is low at time point T51. The anomaly detection flag signal, which is a low-level output signal of the register 48, indicates that the inspected clock signal CK is normal.

[0054] At time T52, the reset signal RS is at a low level, so the output signal of the AND circuit 49 is at a low level. This low level causes the output signal of the register 41 to be at a low level at time T52. Also, at time T52, the output signal of the AND circuit 51 is at a low level, so the output signal of the register 44 is at a low level.

[0055] At time T53, as described above, the reset signal RS is at a low level, so that the output signal level of the AND circuit 52 is at a low level, as in the case of time T51, and the output signal level of the register 48 is at a low level at time T53. The anomaly detection flag signal, which is a low-level output signal of the register 48, indicates that the test clock signal CK is normal.

[0056] At time T54, the reset signal RS is at a low level, so the output signal of the AND circuit 49 is at a low level, just as at time T52. This low level causes the output signal of the register 41 to be at a low level at time T54. Also, since the output signal of the AND circuit 51 is at a low level at time T54, this low level causes the output signal of the register 44 to be at a low level. The clock anomaly detection circuit 40 is in a reset state until time T54.

[0057] At time T55, the reset signal RS becomes high level, so that the clock anomaly detection circuit 40, which was in the reset state, starts the clock anomaly detection operation, and the low-level output signal level of the register 41 is supplied to the delay circuit 43 via the OR circuit 50. Also, the exclusive OR of the low-level output signal of the register 41 and the low-level output signal of the register 44 is obtained by the XOR circuit 45. Since the XOR circuit 45 generates a low-level output signal, a low-level output signal is supplied from the OR circuit 47 to the AND circuit 52, so that the AND circuit 52 maintains its low-level output signal. The anomaly detection flag signal, which is the output signal of the register 48, is maintained at a low level at time T55, indicating that the inspected clock signal CK is normal. In other words, a high-level anomaly detection flag signal is not generated.

[0058] At the rising edge of the test clock signal CK after time T56, the level held in the register 41 up to that point is inverted by the inverter 42, so that the register 41 holds and outputs the inverted level of the held level at the next rising edge, and the output signal of the register 41 switches between high and low levels at each rising edge of the test clock signal CK. As a result, the output signal of the register 41 has a period twice that of the test clock signal CK.

[0059] At time T56, the high-level output signal of register 41 is supplied as is to delay circuit 43 via OR circuit 50, so that the high-level output signal of register 41 is delayed by delay circuit 43 for a time period corresponding to one specified period TCK of the test clock signal CK, and the delayed signal is input to the input terminal of register 44 via AND circuit 51. Since the delay time of delay circuit 43 is a time period corresponding to one specified period TCK of the test clock signal CK, the high-level output signal of AND circuit 51 is held and output by register 44 at time T56.

[0060] At time T57, contrary to time T55, the high-level output signal of register 41 and the high-level output signal of register 44 are input to XOR circuit 45, but since XOR circuit 45 generates a low-level output signal as is, a low-level output signal is supplied from OR circuit 47 to AND circuit 52, similar to time T55, and AND circuit 52 maintains a low-level output signal. The output signal of register 48 continues to be maintained at a low level at time T57, indicating that the test clock signal CK is normal.

[0061] Even after time T57, it continues to be confirmed that the output signal levels of the registers 41, 44 are inverted at the rising edge (even-numbered time points) of the test clock signal CK, and that the output signal levels of the registers 41, 44 match at the falling edge (odd-numbered time points) of the test clock signal CK (the signal levels held by the registers 41, 14 are different from each other). In the example of Fig. 5 where the cycle of the test clock signal CK is not abnormal, the abnormality detection flag signal output from the register 48 is always at a low level, indicating that the test clock signal CK is normal.

[0062] 6, where a long-period anomaly occurs, odd-numbered times T71, T73, ... among times T71 to T84 are falling timings, and even-numbered times T72, T74, ... are rising timings. At time T71, the clock signal CK to be inspected is at a low level, and at time T72, the clock signal CK to be inspected is at a high level, which is repeated at the following times T73 to T84.

[0063] The register 41 holds and outputs the level of its input end (the output signal level of the AND circuit 49) at times T72, T74, . . . when the test clock signal CK rises, the register 44 holds and outputs the level of its input end (the output signal level of the AND circuit 51) at times T72, T74, . . . when the test clock signal CK rises, and the register 48 holds and outputs the level of its input end (the output signal level of the AND circuit 52) ​​at times T71, T73, . . . when the test clock signal CK falls.

[0064] 6, when the reset signal RS changes from low to high between time points T74 and T75, the reset signal RS is at low level at the previous time points T71, T72, and T73, so that the output signal level of the AND circuit 52 is low and the output signal level of the register 48 is low at time point T71. The anomaly detection flag signal, which is a low-level output signal of the register 48, indicates that the inspected clock signal CK is normal.

[0065] At time T72, the reset signal RS is at a low level, so the output signal of the AND circuit 49 is at a low level. This low level causes the output signal of the register 41 to be at a low level at time T72. Also, at time T72, the output signal of the AND circuit 51 is at a low level, so the output signal of the register 44 is at a low level.

[0066] At time T73, as described above, the reset signal RS is at a low level, so that the output signal level of the AND circuit 52 is at a low level, as in the case of time T71, and the output signal level of the register 48 is at a low level at time T73. The anomaly detection flag signal, which is a low-level output signal of the register 48, indicates that the test clock signal CK is normal.

[0067] At time T74, the reset signal RS is at a low level, so that the output signal of the AND circuit 49 is at a low level, as in the case of time T72. Due to this low level, the output signal of the register 41 continues to be at a low level at time T74. Also, since the output signal of the AND circuit 51 is at a low level at time T74, the output signal of the register 44 is at a low level due to this low level.

[0068] At time T75, the reset signal RS becomes high level, so that the clock anomaly detection circuit 40, which was in the reset state, starts the clock anomaly detection operation, and the low-level output signal level of the register 41 is supplied to the delay circuit 43 via the OR circuit 50. Also, the exclusive OR of the low-level output signal of the register 41 and the low-level output signal of the register 44 is obtained by the XOR circuit 45. Since the XOR circuit 45 generates a low-level output signal, a low-level output signal is supplied from the OR circuit 47 to the AND circuit 52, so that the AND circuit 52 maintains its low-level output signal. The anomaly detection flag signal, which is the output signal of the register 48, is maintained at a low level at time T75, indicating that the inspected clock signal CK is normal. In other words, a high-level anomaly detection flag signal is not generated.

[0069] At the timing of the rising edge of the test clock signal CK after time T76, the level that had been held in the register 41 up to that point is inverted by the inverter 42, so that the register 41 holds and outputs the inverted level of the held level at the timing of the next rising edge, and the output signal of the register 41 switches between high and low levels at each rising edge of the test clock signal CK.

[0070] At time T76, the high-level output signal of register 41 is supplied as is to delay circuit 43 via OR circuit 50, so that the high-level output signal of register 41 is delayed by delay circuit 43 for a time period corresponding to one specified period TCK of the test clock signal CK, and the delayed signal is input to the input terminal of register 44 via AND circuit 51. Since the delay time of delay circuit 43 is a time period corresponding to one specified period TCK of the test clock signal CK, the high-level output signal of AND circuit 51 is held and output by register 44 at time T76.

[0071] At time T77, contrary to time T75, the high-level output signal of register 41 and the high-level output signal of register 44 are input to XOR circuit 45, but XOR circuit 45 continues to generate a low-level output signal, and similarly to time T75, a low-level output signal is supplied from OR circuit 47 to AND circuit 52, so that the output signal of AND circuit 52 is maintained at a low level. The output signal of register 48 continues to be maintained at a low level at time T77, indicating that the test clock signal CK is normal.

[0072] At time T78, the low-level output signal of the register 41 is supplied as is to the delay circuit 43 via the OR circuit 50, so that the low-level output signal of the register 41 is delayed by the delay circuit 43 for a time period corresponding to one specified period TCK of the test clock signal CK, and the delayed signal is input to the input terminal of the register 44 via the AND circuit 51. Since the delay time of the delay circuit 43 is a time period corresponding to one specified period TCK of the test clock signal CK, the low-level output signal of the AND circuit 51 is held and output by the register 44 at time T78.

[0073] As shown in FIG. 6, the period from time T78 to time T80 is defined as a long-cycle abnormal clock period of the test clock signal CK, and this period is longer than one specified cycle TCK.

[0074] At time T79 within the long-cycle abnormal clock period, the opposite of time T77 is that the low-level output signal of register 41 and the low-level output signal of register 44 are input to XOR circuit 45, but XOR circuit 45 continues to generate a low-level output signal, and as before, a low-level output signal is supplied from OR circuit 47 to AND circuit 52, so that AND circuit 52 maintains its low-level output signal. The output signal of register 48 continues to be maintained at a low level at time T79, indicating that the inspected clock signal CK is normal.

[0075] At time T80 when the long-period abnormal clock period ends, the delay time of the delay circuit 43 from time 78 has already ended, and the output signal level of the delay circuit 43 is low. Since the low level is supplied to the register 44 via the AND circuit 51, the register 44 maintains a low-level output signal at time T80, and the low-level output signal is supplied to one input terminal of the XOR circuit 45. Also, at time T80, the register 41 generates a high-level output signal, which is supplied as is to the delay circuit 43 via the OR circuit 50, while the high-level output signal of the register 41 is input to the other input terminal of the XOR circuit 45. Therefore, the XOR circuit 45 performs an exclusive OR operation on the high-level output signal of the register 41 and the low-level output signal of the register 44. 6, the XOR circuit 45 generates a high-level output signal instead of a low-level output signal at time 80, so that a high-level output signal is supplied from the OR circuit 47 to the AND circuit 52, causing the output signal of the AND circuit 52 to change from a low level to a high level. This high level is held in the register 48 at time T81, so that the anomaly detection flag signal which is the output signal of the register 48 changes from a low level to a high level at time T81, indicating an anomaly in the inspected clock signal CK.

[0076] After time T80, the period of the test clock signal CK returns to the specified period TCK and becomes normal. As a result, the output signal level of the register 41 and the output signal level of the register 44 match after time T82, so the output signal of the XOR circuit 45 returns to a low level. However, since the high-level output signal of the register 48 is supplied to the AND circuit 52 via the OR circuit 47, the AND circuit 52 maintains a high-level output signal, and the register 48 holds this high level at odd-numbered time points T83, ..., the anomaly detection flag signal, which is the output signal of the register 48, maintains a high level, indicating an anomaly in the test clock signal CK.

[0077] In this manner, in the clock anomaly detection circuit 40 of the second embodiment, a periodic signal whose level is inverted at each rising timing of the test clock signal CK is generated by a frequency divider circuit including a register 41, the periodic signal is delayed by a delay circuit 43 for a time that is slightly longer than one specified period TCK of the test clock signal CK to generate a delayed signal, the level of the delayed signal is held in a register 44 at each rising timing of the test clock signal CK to generate a held signal, the level of the periodic signal and the level of the held signal are judged by the XOR circuit 45 to match, and if the XOR circuit 45 does not obtain a match result, an anomaly detection flag signal of a high level indicating an anomaly in the test clock signal CK is generated, so that a long period anomaly in which the period of the test clock signal CK is longer than the specified period TCK can be detected with a simple configuration and with high accuracy.

[0078] The specific circuit configurations of the clock anomaly detection circuit 10 of the first embodiment and the clock anomaly detection circuit 40 of the second embodiment are not limited to those described above. For example, in the clock anomaly detection circuit 10, an AND circuit 20a can be used instead of the OR circuit 20, as shown in FIG. 7. When the AND circuit 20a is used, it is not necessary to use a register 44a connected to the output terminal of the AND circuit 20a that outputs an inverted signal, as in the register 44. The other configurations are the same as those of the clock anomaly detection circuit 10 shown in FIG. 1.

[0079] The clock anomaly detection circuit 10 of the first embodiment is configured to detect a short-period anomaly in which the period of the test clock signal CK is shorter than the specified period TCK, and the clock anomaly detection circuit 40 of the second embodiment is configured to detect a long-period anomaly in which the period of the test clock signal CK is longer than the specified period TCK. However, the clock anomaly detection circuit 10 and the clock anomaly detection circuit 40 may be combined into one clock anomaly detection circuit to detect both short-period anomalies and long-period anomalies of the test clock signal CK. In this one clock anomaly detection circuit, the circuits can be shared between the short-period anomaly detection system and the long-period anomaly detection system. For example, the frequency divider circuit that doubles the period of the test clock signal CK and the period anomaly signal generation circuit that holds the high-level output of the XOR circuit 15 or 45 to generate a high-level anomaly detection flag signal can be shared between both the short-period anomaly detection system and the long-period anomaly detection system.

[0080] Furthermore, the delay time of the delay circuits 13, 43 in the clock anomaly detection circuits 10, 40 in the first and second embodiments is set to a time slightly less than one specified cycle TCK of the inspection clock signal CK in the case of detecting a short cycle anomaly, and is set to a time slightly more than one specified cycle TCK of the inspection clock signal CK in the case of detecting a long cycle anomaly, but the delay circuits 13, 43 may each be configured to allow several types of delay time to be selectively set from the outside.

[0081] The delay time of the delay circuit 13 is shorter than the specified period TCK of the test clock signal CK, but the closer to the specified period TCK the delay time is set, the higher the accuracy of detecting short-period anomalies can be. Similarly, the delay time of the delay circuit 43 is longer than the specified period TCK of the test clock signal CK, but the closer to the specified period TCK the delay time is set, the higher the accuracy of detecting long-period anomalies can be. [Explanation of symbols]

[0082] 10, 40 Clock abnormality detection circuit 11, 14, 14a, 18, 41, 44, 48 Registers 12, 16, 42, 46 Inverter 13, 43 Delay circuit 15, 45 XOR circuit 17, 20, 47, 50 OR circuit 19, 20a, 21, 49, 51, 52 AND circuit

Claims

1. A clock anomaly detection circuit for detecting an anomaly in a period of a test clock signal, comprising: a periodic signal generating circuit for generating a periodic signal whose level is inverted at each start point of one period of the test clock signal; a delay circuit that delays the periodic signal by a time shorter or longer than a period defined for the test clock signal, and outputs a delayed signal of the periodic signal; a hold circuit that holds the level of the delayed signal at each start point of one cycle of the test clock signal to generate a hold signal; a determination circuit that determines whether a level of the periodic signal and a level of the held signal match, and generates a determination result.

2. 2. The clock abnormality detection circuit according to claim 1, further comprising a period abnormality signal generating circuit which generates and holds a period abnormality flag signal indicating an abnormality in the period of the inspected clock signal when the discrimination result indicates a mismatch between the level of the periodic signal and the level of the held signal.

3. 2. The clock anomaly detection circuit according to claim 1, wherein said periodic signal generating circuit comprises a frequency dividing circuit which divides the frequency of said clock signal to be inspected by two.

4. 2. The clock anomaly detection circuit according to claim 1, wherein said determination circuit comprises an XOR circuit which takes an exclusive OR between the level of said periodic signal and the level of said hold signal.

5. A clock anomaly detection circuit for detecting an anomaly in a period of a test clock signal, comprising: a periodic signal generating circuit for generating a periodic signal whose level is inverted at each start point of one period of the test clock signal; a first delay circuit that delays the periodic signal by a time shorter than a period defined for the test clock signal, and outputs a first delayed signal of the periodic signal; a second delay circuit that delays the periodic signal by a time longer than the specified period and outputs a second delayed signal of the periodic signal; a holding circuit that holds a level of the first delayed signal at each start point of one cycle of the test clock signal to generate a first held signal, and holds a level of the second delayed signal to generate a second held signal; a first determination circuit that determines whether a level of the periodic signal and a level of the first held signal match with each other to generate a determination result; a second determination circuit that determines whether or not a level of the periodic signal and a level of the second hold signal match, and generates a determination result.

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