Method for reducing surface roughness of material

Abstract

To provide a method for depositing a material with reduced surface roughness.SOLUTION: A deposition method includes delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber, and providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor. A flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater. The method further includes forming a plasma of all the precursors in the processing region of the semiconductor processing chamber, and depositing the silicon and boron material on a substrate disposed in the processing region of the semiconductor processing chamber. The method also optionally includes thermally annealing the formed silicon and boron-containing material, and optionally etching the material.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. patent application Ser. No. 62 / 933,012, filed Nov. 8, 2019, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] Technical Field

[0002] The present technology relates to semiconductor deposition processes. More specifically, the present technology relates to methods of depositing materials with reduced surface roughness. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods of forming and removing exposed material. As device sizes continue to shrink, the uniformity of materials can affect subsequent operation. For example, the surface roughness of a masking material can affect the uniformity of subsequent etching.

[0004]

[0004] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technique addresses these and other needs. Summary of the Invention

[0005]

[0005] An exemplary deposition method may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may include providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor. A flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. The method may include forming a plasma of all the precursors in the processing region of the semiconductor processing chamber. The method may include depositing the silicon and boron materials on a substrate disposed in the processing region of the semiconductor processing chamber.

[0006] In some embodiments, the silicon and boron materials may be characterized by an as-deposited surface roughness of about 2 nm or less. The plasma power density is about 0.5 W / cm during formation of the plasma of all precursors in the processing region of the semiconductor processing chamber. 2 The substrate temperature may be maintained at or above about 400° C. during deposition of the silicon and boron material on the substrate. The pressure may be maintained at or below about 10 Torr during deposition of the silicon and boron material on the substrate. The method may include providing an argon precursor to the silicon-containing precursor and the boron-containing precursor. The method may include performing a thermal annealing of the silicon and boron material following deposition. The silicon-containing precursor may be or include silane. The boron-containing precursor may be or include diborane.

[0007]

[0007] Some embodiments of the present technique may include a deposition method. The method may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may include forming a plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of the semiconductor processing chamber. The method may include depositing a silicon and boron material on a substrate disposed in the processing region of the semiconductor processing chamber. The silicon and boron material may be characterized by an as-deposited surface roughness of about 1.5 nm or less.

[0008] In some embodiments, the method may include providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor. A flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. The method may include providing an argon precursor to the silicon-containing precursor and the boron-containing precursor. A flow ratio of the argon precursor to the hydrogen-containing precursor may be about 1:1 or less. The method may include, following deposition, thermally annealing the silicon and boron material for a first period of time. The substrate may be maintained at a first temperature during deposition. The substrate may be maintained at a second temperature during thermal annealing the silicon and boron material, the second temperature being greater than the first temperature. The second temperature may be about 500° C. or greater. The plasma power may be maintained at about 2.0 kW or greater during forming a plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of the semiconductor processing chamber.

[0009]

[0009] Some embodiments of the present technique may include a deposition method. The method may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may include forming a plasma of all the precursors in the processing region of the semiconductor processing chamber. The plasma power may be maintained at about 1.0 kW or greater while forming the plasma of all the precursors in the processing region of the semiconductor processing chamber. The method may include depositing the silicon and boron materials on a substrate disposed in the processing region of the semiconductor processing chamber.

[0010] In some embodiments, the method may include providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor. The flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. The method may include providing an argon precursor to the silicon-containing precursor and the boron-containing precursor. The flow ratio of the argon precursor to the hydrogen-containing precursor may be about 1:1 or less. The method may include, following the deposition, performing a thermal annealing of the silicon and boron materials for a first period of time. The substrate may be maintained at a first temperature during the deposition. The substrate may be maintained at a second temperature during the thermal annealing of the silicon and boron materials, and the second temperature may be higher than the first temperature.

[0011]

[0011] Such techniques may provide numerous advantages over conventional systems and techniques. For example, the process may produce films characterized by reduced surface roughness. Additionally, operation of embodiments of the present techniques may produce improved mask materials that may facilitate processing operations. These and other embodiments, together with their many advantages and features, are described in more detail in the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed techniques may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 2]

[0014] 1 illustrates an exemplary operation of a deposition method according to some embodiments of the present technique. [Diagram 3]

[0015] 1 shows a schematic diagram of a substrate prior to deposition in accordance with some embodiments of the present technique; [Figure 4A-4B]

[0016] 1 shows a schematic diagram of an exemplary substrate during deposition in accordance with some embodiments of the present technique. [Figure 5A-5B]

[0017] 1 shows a schematic diagram of an exemplary substrate during deposition in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0018] Some drawings are included as schematics. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to a realistic depiction and may include material that is emphasized for illustrative purposes.

[0015]

[0019] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016]

[0020] During semiconductor manufacturing, structures can be created on a substrate using various deposition and etching operations. A mask material can be used to partially etch the material or to etch features across the substrate. As device sizes continue to shrink and selectivity between materials improves, structure formation may be easier, and improved hard masks may facilitate manufacturing. For example, compared to thermally generated amorphous silicon hard masks, boron-incorporated silicon films may feature improved hardness and other material properties, facilitating the use of the films as mask materials. However, while thermally generated silicon may feature a substantially smooth surface, boron-incorporated silicon films may feature improved surface roughness.

[0017]

[0021] The present technique may overcome these limitations by adjusting deposition parameters and materials to perform surface treatments during deposition. For example, the technique may include etching exposed features of the film layer during deposition. This may facilitate a more uniform surface profile, which may reduce or limit surface roughness during deposition. After describing the general aspects of a chamber according to embodiments of the present application in which the plasma processing operations described below may be performed, specific methods and component configurations may be discussed. It should be understood that the present technique is not intended to be limited to the specific films and processes discussed, as the described techniques may be used to improve many film formation processes and may be applicable to a variety of processing chambers and operations.

[0018]

[0022] FIG. 1 shows a schematic cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technique. The diagram may show a schematic of a system incorporating one or more aspects of the present technique and / or which may perform one or more operations according to embodiments of the present technique. Further details of the chamber 100 or the method performed may be further described below. Although the chamber 100 may be utilized to form a film layer according to some embodiments of the present technique, it should be understood that the method may be similarly performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled with the chamber body 102 and confining the substrate support 104 within a processing space 120. A substrate 103 may be provided to the processing space 120 through an opening 126. The opening 126 may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be mounted on a surface 105 of the substrate support during processing. The substrate support 104 is rotatable along an axis 147, as indicated by arrow 145, where the shaft 144 of the substrate support 104 may be located. Alternatively, the substrate support 104 may be elevated and rotated as needed during the deposition process.

[0019]

[0023] The plasma profile modulator 111 may be disposed in the process chamber 100 to control the plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the process chamber 100 surrounding the process space 120 or may be discontinuous at selected locations as desired. The first electrode 108 may be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor.

[0020]

[0024] The insulator(s) 110a, 110b may be a dielectric material such as a ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors into the process space 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to a process chamber. In some embodiments, the first power source 142 may be an RF power source.

[0021]

[0025] The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive while the faceplate of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered by, for example, a first power source 142 as shown in FIG. 1, or the gas distributor 112 can be coupled to ground in some embodiments.

[0022]

[0026] The first electrode 108 may be coupled to a first tuning circuit 128 that may control a ground path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as shown, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134. This may provide some degree of closed loop control of the plasma conditions within the process space 120.

[0023]

[0027] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be incorporated into the substrate support 104 or may be coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by a conduit 146 (e.g., a cable having a selected resistance (e.g., 50 ohms, etc.)) disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138, a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the process space 120.

[0024]

[0028] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148. The filter 148 may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0025]

[0029] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. During operation, the processing chamber 100 may provide real-time control of plasma conditions within the processing space 120. The substrate 103 may be disposed on the substrate support 104. Processing gases may be flowed through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may be exhausted from the processing chamber 100 through the outlet 152. Power may be coupled with the gas distributor 112 to establish a plasma within the processing space 120. In some embodiments, the substrate may be subjected to an electrical bias using the third electrode 124.

[0026]

[0030] Upon exciting a plasma in the process space 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and uniformity of the plasma density from the center to the edge of the substrate. In an embodiment where the electronic controllers are both variable capacitors, these variable capacitors may be independently adjusted by electronic sensors to maximize the deposition rate and minimize thickness non-uniformity.

[0027]

[0031] Each of the tuning circuits 128, 136 may have a variable impedance that may be adjusted using the corresponding electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the respective capacitance range of the variable capacitor and the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and the capacitance range of each variable capacitor may be minimum. Thus, when the capacitance of the first electronic controller 134 is minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with minimal spatial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 reaches a value that minimizes the impedance of the first tuning circuit 128, the spatial coverage of the plasma may grow to a maximum and effectively cover the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and reduce spatial coverage of the substrate support. The second electronic controller 140 has a similar effect, and as the capacitance of the second electronic controller 140 changes, the spatial coverage of the plasma above the substrate support may increase or decrease.

[0028]

[0032] The electronic sensors 130, 138 may be used to tune the corresponding circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be attached to each sensor, and the sensors may be provided with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the plasma shape may be selected and dynamically controlled during processing. Although the above description is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic components having adjustable characteristics may be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0029]

[0033] FIG. 2 illustrates an exemplary operation of a deposition method 200 according to an embodiment of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. The method 200 may include several optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of structure formation, but may not be critical to the technology or may be performed by alternative methodologies as will be readily understood. The method 200 may describe operations shown generally in FIGS. 3-5B. These figures will be described in conjunction with the operations of the method 200. It should be understood that the figures are only partial schematic views, and that the substrate may include any number of additional materials and features having various properties and aspects, as shown in the figures.

[0030]

[0034] Method 200 may include additional operations prior to the initiation of the recited operations. For example, the additional processing operations may include forming structures on the semiconductor substrate, which may include both the formation and removal of materials. Prior to delivery of the substrate into a semiconductor processing chamber in which method 200 may be performed, processing operations may be performed in the chamber in which method 200 may be performed, or processing may be performed in one or more other processing chambers. In any case, method 200 may include, in some cases, delivering a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chamber that may include the components described above. The substrate may be deposited on a substrate support. The substrate support may be a pedestal, such as substrate support 104, and may be present in a processing region of the chamber, such as processing space 120 described above. An exemplary substrate 305 is shown in FIG. 3 prior to the initiation of deposition.

[0031]

[0035] The substrate 305 can be any number of materials on which a material may be deposited. The substrate can be silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials (which may be the substrate 305 or the material formed on the substrate 305). In some embodiments, optional processing operations such as pre-treatments may be performed to prepare the surface of the substrate 305 for deposition. For example, pre-treatments may be performed to provide specific ligand terminations on the surface of the substrate, which may facilitate nucleation of the deposited film. For example, other molecular terminations such as amidogens or other functional groups, as non-limiting examples including hydrogen, oxygen, carbon, nitrogen, or any combination of these atoms or radicals, may be adsorbed, reacted, or formed on the surface of the substrate 305. Additionally, removal of material, such as reduction of native oxides or etching of materials, or any other operations that may prepare one or more exposed surfaces of the substrate 305 for deposition may be performed.

[0032]

[0036] In operation 205, one or more precursors may be delivered to the processing region of the chamber. For example, in an exemplary embodiment where a boron-incorporated silicon film may be formed, a silicon-containing precursor and a boron-containing precursor may be delivered to the processing region of the processing chamber. In some embodiments of the present technology, plasma deposition may be performed, which may facilitate the reaction and deposition of materials. As mentioned above, some embodiments of the present application may involve the formation or deposition of silicon and boron materials, which may be characterized by increased surface roughness compared to conventionally, e.g., thermally produced silicon films. Nucleation of these silicon and boron materials may form islands 405a on the substrate 305 in some embodiments, as shown in FIG. 4A. These islands may be formed three-dimensionally to different heights during initial film formation, which may be maintained during film growth.

[0033]

[0037] Some embodiments of the present technique may further include providing a hydrogen-containing precursor in operation 210, where the hydrogen-containing precursor is provided to the silicon-containing precursor and the boron-containing precursor. The delivered precursors may all be used to form a plasma in a processing region of the semiconductor processing chamber in operation 215. In operation 220, silicon and boron materials may be deposited on the substrate 305. In some embodiments, the incorporation of a hydrogen-containing precursor may reduce or limit islands formed during nucleation.

[0034]

[0038] For example, as shown in FIG. 4B, islands 405b may be formed to a lesser or lesser extent than islands 405a. By incorporating an additional hydrogen source, film modification, or profile etching, may be performed simultaneously with the deposition of the material. For example, hydrogen radicals may trim the island formation while a more uniform formation profile is generated through reaction and / or physical interaction with features formed of silicon and boron materials. As a result, the islands may not expand as much compared to conventional processes. To provide sufficient hydrogen radicals for the process, the hydrogen-containing precursor may be included at a higher flow rate than one or both of the silicon-containing precursor or the boron-containing precursor. For example, in some embodiments, the flow ratio of the hydrogen-containing precursor to either or both of the silicon-containing precursor and / or the boron-containing precursor may be about 1:1 or more, and in some embodiments, may be about 2:1 or more, about 3:1 or more, about 4:1 or more, about 5:1 or more, or more, about 6:1 or more, about 8:1 or more, about 10:1 or more, about 15:1 or more, about 20:1 or more, about 25:1 or more, about 30:1 or more, about 35:1 or more, about 40:1 or more, about 45:1 or more, about 50:1 or more, or more. As further described below, in some embodiments, further dilution may be performed and the ratio of hydrogen to silicon and / or boron precursor may be about 100:1 or more, and may be about 500:1 or more, about 1,000:1 or more, about 1,500:1 or more, about 2,000:1 or more, about 2,500:1 or more, or more.

[0035]

[0039] For example, depending on the precursor used, the silicon-containing precursor may be delivered at a flow rate of about 500 sccm or less, and may be delivered at a flow rate of about 400 sccm or less, about 300 sccm or less, about 200 sccm or less, about 100 sccm or less, about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, or less. Similarly, the boron-containing precursor may be delivered at a flow rate of about 1,000 sccm or less, and may be delivered at a flow rate of about 800 sccm or less, about 600 sccm or less, about 500 sccm or less, about 450 sccm or less, about 400 sccm or less, about 350 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, or less. Additional ranges may be used within these ranges or as combinations of recited or unrecited numbers.

[0036]

[0040] The hydrogen-containing precursor may be delivered at about 1,000 sccm or greater, and may be delivered at a flow rate of about 1,200 sccm or greater, about 1,400 sccm or greater, about 1,600 sccm or greater, about 1,800 sccm or greater, about 2,000 sccm or greater, about 2,200 sccm or greater, about 2,400 sccm or greater, about 2,600 sccm or greater, about 2,800 sccm or greater, about 3,000 sccm or greater, or greater. Increasing the hydrogen-containing precursor may result in a smoother surface of the film being deposited, but may also increase hydrogen incorporation within the deposited film. Thus, in some embodiments, the hydrogen-containing precursor may be delivered at a flow rate of about 4,000 sccm or less, and may be delivered at a flow rate of about 3,800 sccm or less, about 3,600 sccm or less, about 3,400 sccm or less, about 3,200 sccm or less, about 3,000 sccm or less, about 2,800 sccm or less, about 2,600 sccm or less, or less. Further, in some embodiments where greater dilution may be implemented, the hydrogen-containing precursor may be delivered at a flow rate of about 5,000 sccm or more, and may be delivered at a flow rate of about 10,000 sccm or more, about 15,000 sccm or more, about 20,000 sccm or more, about 25,000 sccm or more, or more. In some embodiments, the flow rate of the silicon or boron precursor may be further reduced, such as to about 200 sccm or less, and may be reduced to about 150 sccm or less, about 100 sccm or less, about 50 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or even less.

[0037]

[0041] The film may be deposited on the substrate 305 to any thickness. The surface roughness of the produced film may not be limited to issues during the nucleation of the film as described above. For example, film growth and plasma termination may also affect the surface roughness in some aspects of the present technology. For example, once sufficient film growth occurs, the process may be stopped by extinguishing the plasma in the processing chamber, such as by turning off the power to the plasma generating electrodes. Plasma termination may also increase the surface roughness by causing physical interaction of a certain amount of residual ions after deposition is completed. Both the effect of nucleation and the effect of plasma termination may be presumed to be consistent regardless of the thickness of the film formed. However, tests have shown that the roughness of the deposited film increases as the film thickness increases. As a result, the roughness effect also occurs during film growth, and as the film thickness increases, the roughness of the film may also increase further. As shown in FIG. 5A, the islands 405a formed during nucleation may not only be maintained, but may also grow or expand during deposition without one or more of the characteristics described throughout the present technology. Thus, the resulting film 505a may be characterized by increased roughness that may affect the uniformity of subsequent etching.

[0038]

[0042] For example, thermally produced silicon, such as polysilicon or other silicon materials, may be characterized by a relatively low average roughness, such as about 0.5 nm or less, or about 0.2 nm or less. The film may also be characterized by a relatively low roughness range, such as the difference between the highest and lowest peaks on the formed film. For example, the roughness range may be about 1.5 nm or less, or about 1 nm or less. However, for silicon and boron films produced without one or more aspects of the present technology, as described, the roughness may increase with increasing film thickness, but for films of similar thickness, the average roughness may be about 2 nm or more, about 3 nm or more, or greater. Furthermore, the roughness range of the produced silicon and boron materials may be about 10 nm or more, and may be about 15 nm or more, again depending on the film pressure. During subsequent etching operations, these larger disparities across the film may pose challenges to the uniformity of the etching operation and may require additional operations, such as additional chemical mechanical polishing operations, to be performed.

[0039]

[0043] However, the present technique may reduce or significantly reduce both the average roughness and the roughness range of the produced silicon and boron films by performing a substantially simultaneous etch utilizing an additional hydrogen-containing precursor or by performing one or more additional adjustments detailed below. As shown in FIG. 5B, the produced film 505b may be characterized by an average roughness of about 2 nm or less, and may be characterized by an average roughness of about 1.5 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, about 0.4 nm or less, about 0.3 nm or less, about 0.2 nm or less, or less. Furthermore, the roughness may be substantially controlled regardless of film thickness in some embodiments. This may allow for the avoidance of additional chemical mechanical polishing operations, since the as-deposited film may be characterized by any of the average roughness ranges shown. Additionally, the roughness range across the as-deposited film may be about 10 nm or less, and may be about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, about 2 nm or less, about 1 nm or less, or less, etc. As a result, improved materials may be produced, providing film and mask advantages over conventional materials and processes, as well as reducing manufacturing operations by limiting or reducing the number of polishing operations in the sequence.

[0040]

[0044] Regarding silicon-containing precursors and boron-containing precursors, any number of precursors can be used in the present technology.For example, silicon-containing precursors can include any silicon-containing material, such as organosilanes, which can include silanes, disilanes, and other materials.Additional silicon-containing materials can include silicon, carbon, oxygen, or nitrogen, such as trisilylamine.Boron-containing materials can include boranes, such as borane, diborane, or other multi-center bonded boron materials, as well as any other boron-containing materials that can be used to generate silicon and boron-containing materials.The incorporation of boron into silicon film can be based on any percentage incorporation. For example, the produced film may comprise about 5% or greater boron incorporation, and in some embodiments may comprise about 10% or greater boron incorporation, about 15% or greater boron incorporation, about 20% or greater boron incorporation, about 25% or greater boron incorporation, about 30% or greater boron incorporation, about 35% or greater boron incorporation, about 40% or greater boron incorporation, about 45% or greater boron incorporation, about 50% or greater boron incorporation, about 55% or greater boron incorporation, about 60% or greater boron incorporation, about 65% or greater boron incorporation, about 70% or greater boron incorporation, about 75% or greater boron incorporation, about 80% or greater boron incorporation, about 85% or greater boron incorporation, about 90% or greater boron incorporation, about 95% or greater boron incorporation, or greater than that.

[0041]

[0045] One or more additional aspects of the deposition may also be adjusted to improve the aspect of the deposition being performed. For example, plasma power may affect the degree of hydrogen dissociation. Any number of hydrogen-containing precursors may be used, and in some embodiments, diatomic hydrogen may be included. For some silicon- and boron-containing materials, minimal plasma enhancement may be included because the materials are sufficiently reactive at the deposition temperature. For example, some conventional techniques utilize plasma powers of about 200 watts or less. The present technique may utilize higher or much higher plasma powers, which may promote hydrogen dissociation, and increase hydrogen radicals, which may reduce roughness as previously described.

[0042]

[0046] For example, in some embodiments, the plasma power may be maintained at about 1,000 watts or more, about 1,200 watts or more, about 1,400 watts or more, about 1,600 watts or more, about 1,800 watts or more, about 2,000 watts or more, about 2,200 watts or more, about 2,400 watts or more, about 2,600 watts or more, about 2,800 watts or more, about 3,000 watts, or higher wattages. This enhanced plasma power may also improve dissociation and activation of other precursors, which may increase the deposition rate as well. As a result, despite simultaneous etching of materials during deposition, the deposition rate of the film may be comparable, if not improved, than conventional deposition. The deposition and simultaneous etching for profile modification may then be maintained continuously or sequentially until the target film thickness is produced. Depending on the plasma process being performed, the plasma power density is also maintained, which may allow for adjustments in frequency and power. For example, in some embodiments, the plasma power density is about 0.25 W / cm 2 It may be maintained at about 0.5W / cm 2 Above, approximately 1.0W / cm 2 Above, about 1.5W / cm 2 Above, approximately 2.0W / cm 2 Above, about 2.5W / cm 2 or higher.

[0043]

[0047] The temperature of the substrate may further affect the deposition. For example, in some embodiments, the substrate may be maintained at a temperature of about 400° C. or higher, about 420° C. or higher, about 440° C. or higher, about 460° C. or higher, about 480° C. or higher, about 500° C. or higher. By performing deposition according to some embodiments of the present technique, hydrogen etching may be performed during deposition to reduce roughness of the formed film. However, the amount of hydrogen radicals generated, such as from the enhanced plasma and hydrogen delivery, may also increase the amount of hydrogen incorporation into the formed film. This may increase compressive stress in the film. For example, the as-deposited film may be characterized by a compressive stress of about −800 MPa or higher, which may be due in part to hydrogen incorporation. As a result, in some embodiments, the method 200 may include operations to reduce hydrogen incorporation into the film.

[0044]

[0048] For example, in some embodiments, the method 200 may include, in optional operation 225, thermally annealing the formed silicon and boron-containing material. While deposition may be performed at a first temperature, thermal annealing may be performed at a second temperature that is higher than the first temperature. For example, thermal annealing may be performed at a temperature of about 480° C. or greater, and thermal annealing may be performed at a temperature of about 500° C. or greater, about 510° C. or greater, about 520° C. or greater, about 530° C. or greater, about 540° C. or greater, about 550° C. or greater, about 560° C. or greater, about 570° C. or greater, about 580° C. or greater, about 590° C. or greater, about 600° C. or greater, or higher. Thermal annealing may be performed for a period that may be about 0.5 minutes or greater, about 1 minute or greater, about 2 minutes or greater, about 3 minutes or greater, about 4 minutes or greater, about 5 minutes or greater, about 6 minutes or greater, or longer.

[0045]

[0049] By carrying out thermal annealing, a certain amount of hydrogen trapped in the film may be removed, which may relieve the compressive stress. For example, in some embodiments, after thermal annealing, the compressive stress in the film may be maintained at about -700 MPa or less, about -650 MPa or less, about -600 MPa or less, about -550 MPa or less, about -500 MPa or less, about -450 MPa or less, about -400 MPa or less, about -350 MPa or less, about -300 MPa or less, about -250 MPa or less, about -200 MPa or less, about -150 MPa or less, about -100 MPa or less, or less.

[0046]

[0050] The pressure in the processing region can affect the amount of ionization and physical interactions that occur during deposition. Lowering the processing pressure can result in increased ionic interactions. Thus, in some embodiments, the processing pressure during deposition may be maintained at about 50 Torr or less, and may be maintained at about 40 Torr or less, about 30 Torr or less, about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr, or less.

[0047]

[0051] Tests have shown that argon incorporation can increase roughness, and thus limiting or excluding argon can improve film roughness. However, tests have shown that when argon is excluded from the process precursor, film peeling can increase. Thus, in some embodiments, argon can be included in the silicon-containing precursor and the boron-containing precursor. To limit the effect on roughness, the flow ratio of argon precursor to hydrogen-containing precursor can be maintained at about 2:1 or less, and can be maintained at about 1:1 or less, about 0.8:1 or less, about 0.7:1 or less, about 0.6:1 or less, about 0.5:1 or less, about 0.4:1 or less, about 0.3:1 or less, about 0.2:1 or less, about 0.1:1 or less, or less.

[0048]

[0052] Combinations or further adjustments of process parameters may also affect and improve additional aspects of the produced film. Incorporation of boron into the hardmask film may improve selectivity to many films. The film stack may provide improved selectivity, further reducing the number of additional operations being performed, since more material is involved in both the hardmask opening operation and the subsequent film etch. Increasing the crystallinity of the film may also increase the etch selectivity, but increasing the crystallinity of the film reduces or worsens line edge roughness and line width roughness in conventional techniques. As a result, many techniques attempt to maintain the film as amorphous silicon. The techniques may at least partially increase the crystallinity of the formed film, which may increase the etch selectivity, but by limiting the crystallinity, the techniques may maintain the line edge roughness and line width roughness.

[0049]

[0053] Compared to silicon and boron precursors, when an increased hydrogen flow rate is utilized according to embodiments of the present technology, the crystallinity may increase. However, by utilizing the aforementioned process parameters, the crystallinity may be maintained at about 50 Å or less, and may be maintained at about 40 Å or less, about 30 Å or less, about 20 Å or less, about 15 Å or less, about 10 Å or less, about 7 Å or less, about 5 Å or less, about 3 Å or less, or less, but improved etch selectivity can be obtained when the crystallinity is increased to about 2 Å or more.

[0050]

[0054] However, increasing hydrogen inclusion in the plasma may also increase hydrogen incorporation in the film. This may affect film stress as previously discussed and may further affect other film properties. For example, hardmask films may be characterized by extinction coefficients of light at different wavelengths, which may affect lithography operations. Amorphous silicon materials may be characterized by an extinction coefficient at a particular parameter of about 0.2, which may allow lithography at film thicknesses up to about 800 nm based on lower reflectivity, which may affect visibility through the mask. Silicon and boron films may be characterized by increased extinction coefficients of similar parameters, but with increased hydrogen incorporation, the extinction coefficient may at least partially decrease. For example, with increased boron incorporation, the extinction coefficient may increase by about 0.3 or more, about 0.35 or more, about 0.4 or more, about 0.45 or more, or more.

[0051]

[0055] The effect of a higher extinction coefficient of light is that lithography may become difficult and additional processing may be required. For example, these increased extinction coefficients may limit the visibility of lithography to about 400 nm or less, about 300 nm or less, or less. However, by utilizing increased plasma density to increase hydrogen incorporation, the extinction coefficient may decrease to about 0.35 or less, about 0.33 or less, about 0.30 or less, about 0.28 or less, about 0.25 or less. This may allow lithography to be extended to thicknesses of about 400 nm or more, about 450 nm or more, about 500 nm or more, or greater, without performing additional alignment key release operations. By increasing the temperature and plasma properties, film structures may be formed to improve properties such as extinction coefficient and etch selectivity, even with increased hydrogen incorporation. Hydrogen uptake can also be increased by processing at lower temperatures, such as below 400° C., or below about 350° C., but the resulting differences in film properties can lead to additional hydrogen outgassing with subsequent processing, as discussed above. By performing processing at higher temperatures, increased thermal stability can be obtained with the films thus formed with increased hydrogen uptake.

[0052]

[0056] The plasma characteristics may be adjusted in some embodiments, both in power and frequency. At lower frequencies, such as about 20 MHz or less, including 13.56 MHz, the described film characteristics may be generated, for example, by plasma powers of about 2000 W or more or about 2500 W or more. It should be understood that other plasma characteristics may also be used. For example, by adjusting the plasma frequency, the plasma power may also be adjusted. As the plasma frequency increases, for example, to about 40 MHz or more, about 60 MHz or more, or even into the microwave frequency range, the plasma power may be correspondingly reduced to improve the stability and resilience of the chamber. FTIR analysis shows that with these plasma characteristics, the peaks associated with boron and hydrogen may increase in transmission and shift slightly to higher wavelengths. This may indicate improved stability of the structure, which may result in increased thermal stability of the film during subsequent processing. As a result, in some embodiments, by increasing the crystallinity, a lower extinction coefficient and improved thermal stability may also be obtained. By performing deposition according to embodiments of the present technology, the roughness of silicon and boron-containing films may be reduced, which may improve the effectiveness of the hard mask. During the subsequent etching in optional operation 230, the etch critical dimensions may remain more uniform with the present technique than when the technique is not implemented. By reducing the surface roughness, improved etching and structural development may result.

[0053]

[0057] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

[0054]

[0058] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Thus, the above description should not be considered as limiting the scope of the present technology. Additionally, while a method or process may be described sequentially or stepwise, it should be understood that the operations may be performed simultaneously or in a different order than described.

[0055]

[0059] Where a range of values ​​is provided, it is to be understood that each intervening value between the upper and lower limits of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any narrower ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also encompassed. The upper and lower limits of these smaller ranges may be individually included or excluded from the range, and each range in which either, neither or both limits are included in the smaller ranges is also encompassed within the scope of the technology, subject to any specifically excluded limits in the stated range. Where one or both limits are included in a stated range, ranges excluding either or both of those inclusive limits are also included.

[0056]

[0060] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents known to those skilled in the art, and so forth.

[0057]

[0061] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. 1. A deposition method comprising the steps of: delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber; providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor, wherein a flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater; forming a plasma of all precursors in the processing region of a semiconductor processing chamber; depositing silicon and boron materials onto a substrate disposed within the processing region of the semiconductor processing chamber; and

2. 10. The deposition method of claim 1, wherein the silicon and boron materials are characterized by an as-deposited surface roughness of about 2 nm or less.

3. During the formation of the plasma of all precursors in the processing region of the semiconductor processing chamber, a plasma power density is about 0.5 W / cm ２ The deposition method of claim 1 , wherein the temperature is maintained at or above 100° C.

4. 10. The method of claim 1, wherein a substrate temperature is maintained at or above about 400[deg.] C. during deposition of the silicon and boron materials on the substrate.

5. 10. The method of claim 1, wherein a pressure is maintained at or below about 10 Torr while depositing the silicon and boron material on the substrate.

6. 10. The method of claim 1 further comprising providing an argon precursor to the silicon-containing precursor and the boron-containing precursor.

7. 10. The method of claim 1 further comprising performing a thermal anneal of said silicon and boron material after said deposition.

8. 2. The deposition method of claim 1, wherein the silicon-containing precursor comprises silane and the boron-containing precursor comprises diborane.

9. 1. A deposition method comprising the steps of: delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber; forming a plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of a semiconductor processing chamber; depositing a silicon and boron material on a substrate disposed within the processing region of the semiconductor processing chamber, the silicon and boron material being characterized by an as-deposited surface roughness of about 1.5 nm or less; and a deposition method comprising:

10. providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor, wherein a flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater; providing an argon precursor to the silicon-containing precursor and the boron-containing precursor, the flow ratio of the argon precursor to the hydrogen-containing precursor being about 1:1 or less; The deposition method of claim 9 further comprising:

11. 10. The method of claim 9, further comprising thermally annealing the silicon and boron material for a first period of time after said deposition, wherein the substrate is maintained at a first temperature during said deposition, and wherein the substrate is maintained at a second temperature greater than 500° C. while thermally annealing the silicon and boron material, the second temperature being greater than the first temperature.

12. 10. The deposition method of claim 9, wherein a plasma power is maintained at about 2.0 kW or greater while forming the plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of a semiconductor processing chamber.

13. 1. A deposition method comprising the steps of: delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber; forming a plasma of all precursors in the processing region of a semiconductor processing chamber, wherein a plasma power is maintained at about 1.0 kW or greater while forming the plasma of all precursors in the processing region of a semiconductor processing chamber; depositing silicon and boron materials onto a substrate disposed within the processing region of the semiconductor processing chamber; and

14. providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor, wherein a flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater; providing an argon precursor to the silicon-containing precursor and the boron-containing precursor, the flow ratio of the argon precursor to the hydrogen-containing precursor being about 1:1 or less; The deposition method of claim 13 further comprising:

15. 14. The method of claim 13, further comprising performing a thermal annealing of the silicon and boron material for a first period of time after said deposition, wherein during said deposition, said substrate is maintained at a first temperature, and during said thermal annealing of the silicon and boron material, said substrate is maintained at a second temperature, said second temperature being greater than said first temperature.

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