Processed lamination die

Abstract

To process a singulated die in preparation for bonding.SOLUTION: A typical implementation of the techniques and methods includes processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, each semiconductor die component has a substantially planar surface. Particles and debris of a material may be removed from the edges of a plurality of semiconductor die components. Additionally, one or more of the plurality of semiconductor die components can be bonded to the prepared bonding surface via the substantially planar surface.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] (CROSS REFERENCE TO PRIORITY CLAIM AND RELATED APPLICATIONS) This application claims the benefit under 35 U.S.C. §119(e)(1) of U.S. application Ser. No. 15 / 960,179, filed April 23, 2018, and U.S. Provisional Application No. 62 / 504,834, filed May 11, 2017, each of which is incorporated by reference in its entirety.

[0002] FIELD OF THEINVENTION The following description relates to integrated circuit ("IC") processing. More specifically, the following description relates to techniques for processing singulated die in preparation for bonding. [Background technology]

[0003] Dies can be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking one or more layers of dies on a larger base die, stacking multiple dies in a vertical arrangement, and various combinations of both. Dies can also be stacked on a wafer, or a wafer can be stacked on another wafer before singulation. In some cases, dies or wafers can be bonded in a stacked arrangement using various bonding techniques, including the use of direct dielectric bonding, non-adhesive techniques such as ZiBond® direct dielectric bonding technology or DBI® hybrid bonding technology, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), Xperi Corp (see, e.g., U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). Summary of the Invention [Problem to be solved by the invention]

[0004] When using direct bonding techniques to bond stacked dies, it is desirable that the surfaces of the dies to be bonded are extremely flat and smooth. For example, the surfaces should have very little surface topological variation so that the surfaces can fit tightly together to form a lasting bond. It is also desirable that the surfaces are clean and free of impurities, particles, and / or other residues. The presence of undesirable particles, for example, may cause the bond to be defective or unreliable at the location of the particle. For example, some particles and residues remaining on the bonding surface may result in voids at the bonding interface between the stacked dies. If the voids are substantially smaller than the metal electrical interconnect dimensions, they may be acceptable. However, particles that cause bond defects with dimensions approaching or exceeding the electrical interconnect dimensions may be unacceptable as they may adversely affect the electrical conductivity of the interconnects.

[0005] Because semiconductor wafers (such as silicon wafers) are brittle, it is common for defects or particles to occur on the edges of the singulated die. As an example, silicon may crack during cutting, forming loose particles. Mechanical cutting or sawing often leaves rough edges and may also leave particles or debris of silicon on or near the edges of the cut die. In addition, mechanical saw dicing typically transfers material from the dicing sheet to the sidewalls and edges of the singulated die. Laser cutting may also leave particles on the surface or edges of the die. Various processes can be used to clean the surface of the die after cutting. However, this process often leaves some particles on the periphery or on the edge walls of the die. Even when the surface of the die is polished, debris may be present on the edge or sidewall of the die. The loose particles and debris left behind can be problematic in forming a reliable bond. In addition, these loose or partially loose particles may recontaminate the bonding surface of the target or the bonding tool, etc. in subsequent operations. [Means for solving the problem]

[0006] Various embodiments and techniques can be used to process the singulated die in preparation for bonding. Embodiments include techniques for re-measuring the accumulation of defects found on the die, including removing, dissolving, or etching particles at the edge of the die to provide a smooth bonding surface. The die may be composed of semiconductor or non-semiconductor materials. Semiconductor materials may include, for example, direct band gap or indirect band gap semiconductors, and combinations thereof. Non-semiconductor materials may include, for example, dielectric materials such as glass, ceramic, glass ceramic, silicon carbide, silicon oxycarbide, silicon nitride or silicon oxynitride, diamond, silicon oxide, and the like, or combinations thereof.

[0007] The microelectronic system may include at least a first microelectronic component including a base semiconductor layer and a dielectric layer, the dielectric layer having a substantially planar surface. Additionally, the second microelectronic component may be directly bonded to the dielectric layer of the first microelectronic component without the use of adhesive, the dielectric layer having an undercut at the periphery of the dielectric layer such that the area of ​​the dielectric layer is smaller than the area of ​​the first and / or second microelectronic components. Alternatively, the second microelectronic component may include at least a second base semiconductor layer and a second dielectric layer, the second dielectric layer having a substantially planar surface. Additionally, the second dielectric layer may be directly bonded to the first dielectric layer without the use of adhesive, the first and second substantially planar surfaces of the first and second base semiconductor layers having an undercut at the periphery of the first and second base semiconductor layers such that the area of ​​the first and second base semiconductor layers is smaller than the area of ​​the first and / or second dielectric layers.

[0008] In a first embodiment, the undercut at the periphery of the base semiconductor layer of the first microelectronic component and / or the second microelectronic component may correspond to an undercut at the periphery of the dielectric layer of the first microelectronic component and / or the second microelectronic component.

[0009] In a second embodiment, the second microelectronic component may include at least a base semiconductor layer and a dielectric layer having a substantially planar surface, where the dielectric layer of the first microelectronic component is directly bonded to the dielectric layer of the second microelectronic component, and where the dielectric layer of the second microelectronic component has an undercut at a periphery of the dielectric layer of the second microelectronic component such that the area of ​​the dielectric layer of the second microelectronic component is smaller than the footprint of the first and / or second microelectronic components.

[0010] A method for forming a microelectronic system may include singulating a plurality of semiconductor die components from a wafer component, each of the semiconductor die components having a substantially planar surface. Particles and debris of material may be removed from edges of the plurality of semiconductor die components. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface via the substantially planar surface.

[0011] In a third embodiment, the particles and debris of material may be removed by etching the edges of the plurality of semiconductor die components. The edges of the plurality of semiconductor die components may be etched while the plurality of semiconductor die components are on a dicing carrier (e.g., a dicing sheet, a dicing tape, etc.). Additionally, the edges of the plurality of semiconductor die components may be etched using a chemical etchant. In one embodiment, the chemical etchant may include hydrofluoric acid and nitric acid along with Benzotriazole (BTA), or other chemicals that inhibit Cu dissolution in the etchant. Additionally, the edges of the plurality of semiconductor die components may be etched using plasma etching. Also, the edges of the plurality of semiconductor die components may be etched to reduce the thickness of the plurality of semiconductor die components such that a space is created at one or more of the edges of each of the plurality of semiconductor die components. The semiconductor die components may include an oxide layer as a substantially planar surface, and the etching may include removing at least a portion of the oxide layer at the edges of the plurality of semiconductor die components. Nevertheless, the substantially planar surfaces of the plurality of semiconductor die components may be etched. The substantially planar surface may be etched to a preselected depth or for a preselected duration.

[0012] In a fourth embodiment, prior to etching, a protective coating may be applied to the substantially planar surfaces of the plurality of semiconductor die components to protect the substantially planar surfaces from the etchant.

[0013] In a fifth embodiment, the plurality of semiconductor die components may be heated after singulation to recess the protective coating from the periphery of the plurality of semiconductor die components. Additionally, the periphery of the plurality of semiconductor die components may be etched to a preselected depth. Additionally, the plurality of semiconductor die components may include a dielectric layer on the base semiconductor layer. Additionally, the periphery of the plurality of semiconductor die components may be etched to remove the dielectric layer to expose the base semiconductor layer at the periphery of the plurality of semiconductor die components.

[0014] In a sixth embodiment, one or more of the multiple semiconductor die components may be bonded by either an adhesive-free direct bonding technique or by metal-to-metal diffusion bonding.

[0015] In a seventh embodiment, particles and debris of material may be removed from sidewalls of a plurality of semiconductor die components, where the particles and debris are removed from the sidewalls by etching the sidewalls of the plurality of semiconductor die components.

[0016] In one embodiment, after the singulation process, particles and debris of material may be removed from the sidewalls of the die by ultrasonic or megasonic radiation in one or more alkaline fluids. Following particle removal, the sidewalls of the die may be further etched to remove portions of the sidewalls and portions of the planar dielectric layer of the die.

[0017] Some of the disclosed processes may be illustrated using block flow diagrams, including graphic and / or textual flow diagrams. The order in which the disclosed processes are described is not intended to be construed as a limitation, and any number of the described process blocks may be combined in any order to perform the process, or alternative processes. Additionally, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. Additionally, the disclosed processes may be implemented in any suitable manufacturing or processing device or system with any hardware, software, firmware, or combination thereof without departing from the scope of the subject matter described herein.

[0018] The implementations are described in more detail below using several examples. Although various implementations and examples are described herein below, further implementations and examples may be possible by combining features and elements of the individual implementations and examples.

[0019] The detailed description will be set forth with reference to the accompanying drawings, in which the leftmost digit(s) of a reference number identifies the figure in which the reference number first appears. Use of the same reference number in different drawings indicates similar or identical items.

[0020] In this description, the devices and systems illustrated in the figures are shown as having a number of components. Various implementations of the devices and / or systems as described herein may include fewer components and remain within the scope of the present disclosure. Alternatively, other implementations of the devices and / or systems may include additional components or various combinations of the described components and remain within the scope of the present disclosure. [Brief description of the drawings]

[0021] [Figure 1] 1A is a profile showing a defect in a top surface of a die, (B) is a cross-sectional profile showing a bonded die with a defect, and (C) is a cross-sectional profile showing a bonded die without a defect, according to one embodiment. [Diagram 2] FIG. 1 is a graphical flow diagram illustrating an exemplary process for processing stacked dies, according to one embodiment. [Diagram 3] FIG. 11 is a graphical flow diagram illustrating an exemplary process for processing stacked dies, according to another embodiment. [Figure 4] FIG. 11 is a graphical flow diagram illustrating an exemplary process for processing stacked dies, according to a further embodiment. [Diagram 5] 1A is a profile view of a die with recessed oxide regions, (B) is a close-up of a profile view of a die with recessed oxide regions, and (C) is an example of a bonded die layout with recessed oxide regions, according to one embodiment. [Figure 6] FIG. 2 is a flow diagram illustrating an exemplary process for processing stacked dies, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] [overview] Various embodiments and techniques can be used to process the singulated die in preparation for bonding. The present embodiments include techniques for re-measuring the accumulation of particles found on the die, including particles generated during die singulation, and removing, dissolving, or etching debris at the edges of the die to provide a smooth bonding surface.

[0023] 1A is a profile diagram illustrating defects on a top surface of a die, according to one embodiment. As shown, a first die 102 is shown without any defects. In contrast, a second die 104 is shown having a defect 106. Of course, it should be understood that the defect 106 may occur on any surface, sidewall, and / or edge of the first die 102 and / or second die 104.

[0024] The first die 102 and / or the second die 104 may be singulated and / or removed from GaAs, diamond coated substrates, silicon carbide, silicon oxide, silicon nitride, silicon wafers, lithium niobate, lithium tantalum, flat panels, glass, ceramics, circuit boards, packages, interposers, structures with or without embedded metal layers, conductive interconnects 108, device(s), etc. In one embodiment, the defects 106 may include particles and / or debris and may result from die sawing, dicing, and / or singulating the first die 102 and / or the second die 104. For example, mechanical sawing (i.e., sawing) of the first die 102 and / or the second die 104 may cause defects such as particles 106, especially at the edges and / or sidewalls. Additionally, when the first die 102 and / or the second die 104 are cut (even using a laser), the first die 102 and / or the second die 104 may crack and / or generate particles 106 (such as silicon oxide particles). Furthermore, after grinding away the first die 102 and / or the second die 104 pieces of the particles 106 may still be present on the edges and / or sidewalls of the first die 102 and / or the second die 104.

[0025] 1(B) is a profile diagram illustrating a cross-section of bonded dies having a defect, such as a particle 106. As shown, the first die 102 cannot be fully bonded to the second die 104 if the defect 106 is present on a portion of the bonding surface of the second die 104. This is indicated by a gap 110 (or void) found between the first die 102 and the second die 104. This gap 110 may be unacceptable if the integrity of the bond is compromised or if the gap 110 is large enough to adversely affect the electrical conductivity of the mating electrical interconnects 108 if it is present on the bonding surfaces of the dies 102 and 104. As discussed above, the defect 106 may be found on the bonding surface of the second die 104, but additional or other defects (such as particles) may be found along other surfaces and / or sidewalls of the first die 102 and / or second die 104.

[0026] FIG. 1(C) is a profile diagram showing a cross section of the die tightly bonded without defects. As shown, the first die 102 is completely and completely bonded to the second die 104. Any conductive interconnects 108 on the surfaces of the dies 102 and 104 are bonded as well, with reliable electrical conductivity between the interconnects 108. FIG. 1(C) shows the first die 102 and the second die 104 after each has been properly prepared for bonding. For example, the edges and sidewalls of the first die 102 and / or the second die 104 may be cleaned and etched to remove silicon particles and debris. The edges of the first die 102 and / or the second die 104 may be etched with a dry (plasma) etch and / or a wet (chemical) etch while the first die 102 and / or the second die 104 are still on a carrier (e.g., a dicing sheet or tape, a grip ring, etc.) after singulation. A protective coating may be applied to the bonding surfaces of the first die 102 and / or the second die 104 to protect the surfaces during singulation and etching. In one example, the surfaces and sidewalls of the first die 102 and / or the second die 104 may be etched, while in another example, the etching may be limited to the sidewalls of the first die 102 and / or the second die 104. Note that the interconnects 108 are shown simplified and not to scale. For example, the interconnects 108 may include one or more layers that together form the interconnects 108. Furthermore, the interconnects 108 may extend partially or purely through either or both of the dies 102 and 104, or may be provided only on or along the surface(s) of the dies 102 and 104 as a pattern of trace interconnect devices within the dies 102 and 104.

[0027] [Example of embodiment] 2 illustrates an exemplary process 200 for processing stacked dies, according to one embodiment. In (A), a substrate 202 (which may be, for example, a silicon wafer) may include a bonding layer 204, which may include an insulator or dielectric layer, such as an oxide, or a composite bonding layer, for example, a combination of an insulating material (such as an oxide) and a conductive interconnect layer. This bonding layer 204 may be formed on one or both sides of the substrate 202. The layer(s) 204 may be protected by a first protective layer 206 and / or a second protective layer 208. Alternatively, the substrate 202 may be bare and / or have any number of protective layers.

[0028] In (B), the substrate 202 may be singulated into a plurality of singulated dies 210 on a carrier 212. In one embodiment, the carrier 212 may include a handling sheet, a dicing sheet or tape, a grip ring, etc. Additionally, the substrate 202 may be singulated using saw dicing, wet etching, or dry etching or laser methods, or a combination thereof. In one embodiment, the singulated dies 210 may have a substantially flat surface.

[0029] In (C), the singulated die 210 may be exposed to ultra-violet light (UV) (e.g., to cure an adhesive layer on a tape used as a carrier 212 for the substrate 202 to reduce adhesion between die 210 surfaces that contact the tape, etc.). Additionally, in one embodiment, while the singulated die 210 is on the carrier 212, the singulated die 210 may be cleaned and stretched on the carrier 212 in preparation for further processing. Further processing may include, for example, reducing the thickness of the singulated die 210.

[0030] At (D), the singulated die 210 may be cleaned and the sidewalls of the singulated die 210 may be etched. For example, cleaning may remove one or more protective layers including protective layer 206 and / or protective layer 208. In an embodiment, etching may dissolve silicon oxide, silicon nitride, and / or silicon to remove particles and / or debris. A chemical etchant 211 including an acid may be used to etch the periphery of the surface of the die 210 including the bonding layer 204 and may also be used to etch the sidewalls of the singulated die 210. In examples where the surface and / or sidewalls of the singulated die 210 are etched (e.g., for silicon die 210), the etchant 211 may include a chemical mixture of hydrofluoric acid and a suitable oxidizing agent, such as nitric acid. In some applications, the wet etchant may be comprised of a mixture of buffered hydrofluoric acid and a suitable organic acid combined with an oxidizing agent. In other applications, a suitable metal complexing agent may be added to the etching solution to protect the metal on the die 210 bonding surface from the etchant. In one example, the metal-complexing or passivating agent may be comprised of a molecule having a triazole moiety, such as benzotriazole (BTA), etc. In one embodiment, BTA can protect the copper on the surface of the singulated die 210 from being corroded or dissolved by the etching solution.

[0031] After etching the surface (and sidewalls) of the die 210 and stripping it from the protective layers 206 and / or 208, the complexing agent is removed from the mating surfaces of the die 210. As an alternative to wet etching, the sidewalls of the die 210 may also be cleaned using dry etching methods, including using plasma processes similar to those used for silicon etching. After the dry sidewall etching step, the protective layer 206 may be stripped from the mating surfaces of the sidewalls of the die 210. Cleaning the protective layer 206 may also include cleaning any organic material residue resulting from the dry etching. In one embodiment, the organic residue on the sidewalls of the processed die 210 may be left intact. Strongly adherent sidewall organic residue may minimize subsequent particles shed from the die 210.

[0032] Additionally, cleaning and / or further processing of the singulated die 210 may occur on a spin fixture 214 (or the like). A chemical etchant 211 is sprayed onto the diced wafer surface, forming a thin layer on the top surfaces of the die 210 and filling the gaps between the die 210. In one embodiment, defects on the sidewalls of the singulated die 210 may be removed by etching the sidewalls of the die 210.

[0033] Optionally, in one embodiment, the sidewalls of die 210 may be selectively coated to coat the sidewalls and any particles and / or debris that may be present on the sidewalls. For example, selective coating 218 may be applied to the sidewalls using a spin coating process, an electrocoating process, or the like. The particles and / or debris are coated onto the sidewalls with coating 218 to adhere the particles and / or debris to the sidewalls and prevent the particles and / or debris from contaminating other areas of die 210, including the bonding surfaces of die 210. In various embodiments, coating layer 218 includes a material, such as glass, boron doped glass, phosphorus doped glass, etc., that adheres to the silicon of the sidewalls and generally does not adhere to any other surfaces.

[0034] In various embodiments, coating layer 218 comprises a layer of about 50 nm or less that traps particles and debris on the sidewalls of die 210 and prevents them from shedding from the sidewalls. Coating layer 218 may be heat cured onto die 210 for stabilization at a predetermined temperature (such as, for example, about 80° C.) for a predetermined duration. Coating layer 218 may be added after cleaning die 210 as described above, although in various embodiments coating layer 218 may be deposited onto the sidewalls at other steps in process 200.

[0035] In (E), the singulated die 210 may be subjected to a plasma process (e.g., ashing, etc.) to remove any residue of the protective layer 206. In (F), the singulated die 210 may be cleaned to remove any residue or particles of residue resulting from step (E). In (G), the singulated die 210 (including one or both of the oxide layers 204) may be plasma activated (surface activated) to prepare the singulated die 210 for direct bonding. In (H), the plasma activated singulated die 210 may be cleaned. In (I), one or more of the singulated die 210 may be bonded to a prepared surface of the second substrate 216. In particular, the bonding layer 204 (e.g., an oxide or dielectric layer with or without a conductive layer) of the singulated die 210 may be directly bonded to a prepared surface of the second substrate 216. In one embodiment, the singulated die 210 (via bonding layer 204) may be bonded to the second substrate 216 using ZIBOND® direct bonding, or DBI® hybrid bonding, techniques, or the like, where the singulated die 210 is bonded (and in some cases electrically connected) directly to a portion of a surface of the second substrate 216 without the use of an adhesive.

[0036] In various implementations, the substrate 216 may comprise another prepared surface such as a silicon wafer, a GaAs diamond coated substrate, silicon carbide, silicon oxide, silicon nitride, lithium niobate, lithium tantalate, a flat panel, glass, ceramic, a circuit board, a package, an interposer, a structure with or without embedded devices, etc. In one embodiment, the prepared substrate 216 comprises a surface of another die 210 or another bonded die 304, as discussed further below.

[0037] 3 illustrates an exemplary process 300 for processing stacked dies, according to one embodiment. As described above, steps (A)-(D) of process 300 function in a manner consistent with steps (A)-(D) of process 200, including etching the surface and periphery of die 210 (either in the same or separate process steps) to remove silicon or oxide particles and debris from the surface and periphery of die 210.

[0038] As mentioned above, optionally, in one embodiment, the sidewalls of the die 210 may be selectively coated to coat the sidewalls and any particles and / or debris that may be present on the sidewalls. For example, the selective coating 218 may be applied to the sidewalls using a spin coating process, an electrocoating process, or the like. The particles and / or debris are coated onto the sidewalls with the coating 218 to adhere the particles and / or debris to the sidewalls and prevent the particles and / or debris from contaminating other areas of the die 210, including the bonding surfaces of the die 210. In various embodiments, the coating layer 218 includes a material, such as glass, boron doped glass, phosphorus doped glass, etc., that adheres to the silicon of the sidewalls and generally does not adhere to any other surfaces.

[0039] In various embodiments, coating layer 218 comprises a layer of about 50 nm or less that traps particles and debris on the sidewalls of die 210 and prevents them from shedding from the sidewalls. Coating layer 218 may be heat cured onto die 210 for stabilization at a predetermined temperature (such as, for example, about 80° C.) for a predetermined duration. Coating layer 218 may be added after cleaning die 210 as described above, although in various embodiments coating layer 218 may be deposited onto the sidewalls at other steps in process 300.

[0040] With continued reference to process 300 at (E), the singulated die 210 may be transferred to a spin fixture 214 (or the like) and processed / cleaned (including singulation in some embodiments) on a single carrier, such as spin plate 214. Alternatively, the singulated die 210 may be transferred between different carriers (such as spin plate 302) for one or more processes at each station. At (F), the singulated die 210 may undergo plasma treatment to remove any residue of protective layer 206 while on spin plate 302 (in a manner similar to step (E) of process 200).

[0041] At (G), the singulated die 210 can be cleaned to remove residues resulting from the plasma process at (F). At (H), the singulated die 210 can be plasma activated (surface activated) to prepare the singulated die 210 (including bonding layer(s) 204) for direct bonding. At (I), the plasma activated singulated die 210 can be cleaned.

[0042] At (J), one or more of the singulated dies 210 may be bonded to a prepared surface of the second substrate 216. Specifically, the bonding layer 204 (e.g., an oxide or dielectric layer with or without a conductive layer) may be bonded to the prepared surface of the second substrate 216. In one embodiment, the singulated die 210 (through the oxide layer 204) may be bonded directly to the second substrate 216 (e.g., without an adhesive or intervening layer) using ZIBOND® direct bonding, or DBI® hybrid bonding, techniques, or the like.

[0043] At (K), one or more additional singulated dies 304 (e.g., the dies 304 may also be singulated from the substrate 202) prepared similarly to the singulated dies 210 may be bonded to the exposed second surface of one or more of the singulated dies 210 forming one or more die stacks. In particular, the bonding layer 306 (e.g., an oxide or dielectric layer with or without a conductive layer) of the singulated dies 304 may be bonded directly to the second surface of the singulated dies 210 prepared for bonding. The preparation for bonding may include one or more cleaning steps, surface planarization steps, and plasma treatment process steps as desired. In addition, the second surface (including the periphery) of the die 210 may also be etched to remove undesired particles, debris, and the like.

[0044] Additional singulated dies 304 may be added in a similar manner to form a die stack having a desired amount of die layers. In some embodiments, the singulated die 210 and second substrate 216 may be heat treated after bonding, or additional heat treatments may be applied after each layer of singulated die 304 is added. Alternatively, the singulated die 210, singulated die 304, and second substrate 216 are heat treated once some or all layers of the stacked die (210, 304) are in place and bonded.

[0045] 4 illustrates another exemplary process 400 for processing stacked dies, according to one embodiment. In (A), a resist layer 402 is coated on a singulated die 210, including a bonding layer 204 (e.g., an insulating or dielectric layer with or without conductive layers or structures) and a substrate region 202 (e.g., silicon). In one implementation, the resist layer 402 may be patterned to expose a periphery of the singulated die 210, for example, while protecting the remaining surfaces of the singulated die 210. In various embodiments, the singulated die 210 may be singulated using dicing and / or scribing.

[0046] In (B), the exposed edges and sidewalls of the singulated die 210 may be cleaned and etched to create an undercut or recess at the periphery of the singulated die 210. For example, the roughened edges of the singulated die 210 may be smoothed by etching. In addition, the periphery of the singulated die 210 may be recessed to reduce the overall thickness of the singulated die 210 at the periphery and create space at the edge of the singulated die 210. For example, a singulated die 210 having a bonding layer 204 (e.g., dielectric, oxide, etc.) on a substrate 202 (e.g., silicon) may be etched to remove a portion of the oxide of the bonding layer 204 at the periphery of the singulated die 210, and possibly a portion of the silicon of the substrate 202 as well. The etching causes the dielectric oxide of the bonding layer 204 to move back into the recess from the edge of the singulated die 210, thereby exposing the silicon of the substrate 202 below in the recess. In one embodiment, the space created by the recess allows some resistance to the bonding surface during direct bonding, which can improve the reliability of the direct bonding technique and remove stress from the bond.

[0047] In one embodiment, the singulated die 210 may be treated at high temperature (e.g., 120° C.) such that the resist layer 402 disposed on the oxide layer 204 flows and pulls back from the edges of the singulated die 210. Once the edges of the singulated die 210 are etched, the exposed portions of the oxide layer 204 may be removed. Additionally, depending on the duration and formulation used for the etch, some of the silicon of the substrate 202 may be further removed. For example, the longer the duration, the more of the amount of substrate 202 may be removed. In some cases, the dielectric oxide layer 204 may have a sloped profile as a result of the etching of the singulated die 210. This sloped profile may extend into the substrate 202 (e.g., silicon) if the etch is performed to a depth of the substrate 202.

[0048] In some embodiments, the process of etching back the dielectric layer 204 can be performed using lithographic methods, in combination with dry etching, wet etching, or both, as needed. For example, the surface of the die 210 can be patterned, the undesired portions of the dielectric layer 204 can be removed by dry etching, and any undesired exposed conductive features can be removed, for example, by wet etching. In other applications, it may be preferable to remove the undesired dielectric and conductive portions in one operation. In one example, a wet etchant containing halide ions, for example, buffered hydrofluoric acid, and a formulation containing, for example, hydrogen peroxide or nitric acid (or the like) that can oxidize the conductive features can be applied to the surface of the die 210 to remove the undesired dielectric and conductive features. After removing the undesired dielectric and conductive features, a protective layer can be applied for the singulation operation.

[0049] In (C), the resist layer 402 may be removed from the surface of the singulated die 210. Additionally, in (D), the singulated die 210 may be washed.

[0050] In (E) and (F), the singulated die 210 may be bonded to a second substrate 404 (such as the second substrate 216 of another die 210 or 304) prepared for bonding as described above. In one embodiment, the singulated die 210 may be bonded to a prepared surface of the substrate 404 (e.g., without adhesive or intervening layers) using ZIBOND® or Hybrid DBI® technology, or the like. In the views of (E) and (F) of FIG. 4, only the die 210 is shown with the oxide layer 204. However, in some embodiments, both components to be bonded (e.g., the die 210, the die 304, or the substrate 216) may include oxide regions (e.g., the oxide layer 204, etc.) on the bonding surface. In other words, the components are bonded at their respective oxide regions. In some applications, the dielectric or oxide layer 204 of the die 210 and the prepared surface of the substrate 202 may include conductive features (not shown). The dielectric portions of the prepared surfaces of the die 210 and substrate 202 can first be bonded at a low temperature. Any conductive features can be joined at a higher temperature, between 150 and 350° C. In other applications, the bond between the dielectric portions and the conductive features is formed at the same temperature.

[0051] As a result of the etching of step (D), in the implementation shown in (E), the edge of the oxide layer 204 of the singulated die 210 may include undercuts 408. In the implementation, the singulated die 210 may include undercuts 408 at the periphery of the singulated die 210 such that the area of ​​the oxide layer 204 is smaller than the footprint of the substrate 202 and / or substrate 404. Additionally or alternatively, in the implementation shown in (F), as a result of the etching of step (D), the edge of the substrate 202 and substrate 404 may include undercuts 410. In this implementation, the singulated die 210 may include undercuts 410 at the periphery of the singulated die 210 such that the area of ​​the oxide layer 204 is larger than the footprint of the substrate 202 and / or substrate 404. In the implementation, the substrate 202 and substrate 404 may correspond to first and second bonded microelectronic components, respectively.

[0052] According to various embodiments, the edge or sidewall etching techniques described herein can provide reduced complexity and cost of the direct bonding process for high volume manufacturing of singulated die 210. Additionally, removing dicing particles and debris from the periphery and / or edges of the singulated die 210 can reduce process related defects in wafer-to-wafer, die-to-wafer, die-to-die, and die-to-die system packaging. Furthermore, stresses may be reduced in packaged singulated die 210 stacked in a three-dimensional arrangement by rounding the edges of the stacked singulated die 210. The techniques described herein can also result in fewer die processing steps, higher manufacturing throughput, and improved profit margins for ZiBond® and direct bond interconnect (DBI®) manufactured devices. Other advantages of the disclosed techniques will be apparent to those skilled in the art.

[0053] FIG. 5(A) is a profile view of a portion of an exemplary die 210 having a recessed bonding layer 204 (e.g., an insulating or dielectric layer with or without a conductive layer), according to one embodiment. In addition, FIG. 5(B) is an enlarged view of the profile view of the die 210 having a recessed bonding layer 204 (e.g., an oxide region). As shown, the die 210 may include a bonding layer 204 that is recessed back from the substrate 202. The profile view of FIG. 5(B) may correspond, for example, to the profile view shown in step (D) of FIG. 4. In addition, while FIG. 5(B) includes a recess on one side of the bonding layer 204, the recess may also be located on both (or other) sides of the bonding layer 204, as shown in step (D) of FIG. 4 and FIG. 5(C).

[0054] In particular, the sloped profile 502 of the oxide layer 204 may extend into the substrate 202 upon etching (e.g., as described with reference to step (D) of FIG. 4 ). In addition, the sloped profile 502 may provide, for example, a gap around the periphery of the substrate 202 such that a tight and intimate bond may be achieved between, for example, the singulated die 210 and a prepared surface of the second substrate 216 (or the like) even in the presence of particles around the substrate 202.

[0055] For example, this is shown in FIG. 5(C), where an exemplary die 210 is shown bonded to another die 210' forming an exemplary die stack or exemplary microelectronic assembly 500 (or the like). As shown in the diagram of FIG. 5(C), bonding layer 204, which includes an insulating or dielectric material such as an oxide, and also includes one or more conductive layers or structures 504, is bonded directly to bonding layer 204', which includes an insulating or dielectric material such as an oxide, and may also include one or more conductive layers or structures 504'. The conductive features 504 and 504' may extend only into the respective bonding layers 204 and 204', or may extend partially or entirely through the dies 201 and 210'. The recesses in bonding layer 204 and the recesses in bonding layer 204' (if present) may form gaps 506 at the periphery of assembly 500 where die 210 is bonded to die 210'. In various embodiments, the gap 506 may be sized such that any particles 508 remaining within the gap 506 do not prevent the formation of a tight and intimate bond between the bonding surfaces 204 and 204', including a tight and conductive reliable bond between the conductive structures 504 and 504'. In various embodiments, the gap 506 may be filled, for example, with an encapsulant, a dielectric material, an underfill material, etc., as desired. In other embodiments, the gap 506 may be left unfilled or filled with other inactive or active materials as desired. Similar profiles 5(A) and 5(B) as shown in the figures may be formed on the backsides of the dies 210 and 210', and two or more dies may be stacked together.

[0056] 6 is a flow chart 600 illustrating an exemplary process for processing stacked dies, according to one embodiment. At 602, the process includes singulating a plurality of semiconductor die components (e.g., singulated die 210 or singulated die 304, etc.) from a wafer component (e.g., substrate 202, etc.). In one embodiment, each of the semiconductor die components has a substantially planar surface. In another embodiment, the process includes depositing a protective coating (e.g., protective coating 206, etc.) on the substantially planar surfaces of the semiconductor die components (either before or after singulation).

[0057] In one embodiment, the process includes heating the semiconductor die components after singulation to recess a protective coating (such as protective coating 206) from the periphery of the semiconductor die components. Additionally, the periphery of the semiconductor die components and / or the substantially planar surfaces of the semiconductor die components may be etched to a preselected depth.

[0058] Alternatively, the plurality of semiconductor die components may include a dielectric layer over the base semiconductor layer. In addition, the dielectric layer may have a substantially planar surface, and as described above, the dielectric layer may include one or more conductive features. In one embodiment, the process includes etching a periphery of the plurality of semiconductor die components such that at least a portion of the dielectric layer is removed to expose the base semiconductor layer of the periphery of the plurality of semiconductor die components.

[0059] At 604, the process includes removing particles and debris of material from the edges of the plurality of semiconductor die components. Alternatively, the particles and debris may be removed from the sidewalls of the plurality of semiconductor die components. In one embodiment, the particles and debris may be removed by etching the edges and / or sidewalls of the plurality of semiconductor die components. Optionally, the etching of the edges and / or sidewalls occurs while the plurality of semiconductor die components are on the dicing carrier. Additionally, the etching may use a plasma etch and / or a chemical etchant including hydrofluoric acid and nitric acid with benzotriazole (BTA). In an alternative implementation, a protective coating (such as protective coating 206) may be applied to the substantially planar surfaces of the plurality of semiconductor die components to protect the substantially planar surfaces from the etchant.

[0060] At 606, the process includes bonding one or more of the plurality of semiconductor die components via a substantially planar surface to the prepared bonding surface. For example, bonding may occur by direct bonding using, for example, ZIBOND® or DBI® bonding technology without an adhesive or intervening layer. Bonding may include electrically coupling opposing conductive features at the bonding surface(s) of the die and the prepared bonding surface.

[0061] The disclosed processes described herein are illustrated using block flow diagrams. The order in which the disclosed processes are described is not intended to be construed as a limitation, and any number of the described process blocks can be combined in any order to perform the process, or alternative processes. In addition, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. Furthermore, the disclosed processes can be implemented in any suitable manufacturing or processing device or system with any hardware, software, firmware, or combination thereof without departing from the scope of the subject matter described herein.

[0062] Although various implementations and examples are discussed herein, further implementations and examples may be possible by combining features and elements of the individual implementations and examples.

[0063] [Conclusion] Although implementations of the present disclosure have been described in language specific to structural features and / or methodological acts, it is to be understood that the implementations are not necessarily limited to the particular features or acts described. Rather, the particular features and acts are disclosed as representative forms of implementing example devices and techniques.

[0064] Each claim herein constitutes a separate embodiment, and embodiments that combine different claims and / or different embodiments are within the scope of this disclosure and will be apparent to those of skill in the art upon reviewing this disclosure.

Claims

1. 1. A microelectronic system comprising: a first microelectronic component comprised of at least a base semiconductor layer and a dielectric layer, the dielectric layer having a substantially planar surface; a second microelectronic component bonded directly to the dielectric layer of the first microelectronic component without the use of an adhesive, the dielectric layer having an undercut at a periphery of the dielectric layer such that an area of ​​the dielectric layer is smaller than an area occupied by the first and / or second microelectronic components.

2. 2. The microelectronic system of claim 1 , wherein the base semiconductor layer of the first microelectronic component has an undercut at a periphery of the base semiconductor layer that corresponds to the undercut at the periphery of the dielectric layer of the first microelectronic component.

3. 2. The microelectronic system of claim 1, wherein the second microelectronic component is comprised of at least a base semiconductor layer and a dielectric layer having a substantially planar surface, the dielectric layer of the first microelectronic component is directly bonded to the dielectric layer of the second microelectronic component, and the dielectric layer of the second microelectronic component has an undercut at a periphery of the dielectric layer of the second microelectronic component such that an area of ​​the dielectric layer of the second microelectronic component is smaller than the footprint of the first and / or second microelectronic components.

4. 4. The microelectronic system of claim 3, wherein an undercut at the periphery of the base semiconductor layer of the first microelectronic component and / or the second microelectronic component corresponds to an undercut at the periphery of the dielectric layer of the first microelectronic component and / or the second microelectronic component.

5. 1. A microelectronic system comprising: a first microelectronic component comprised of at least a first base semiconductor layer and a first dielectric layer, the first dielectric layer having a first substantially planar surface; a second microelectronic component comprising at least a second base semiconductor layer and a second dielectric layer, the second dielectric layer having a second substantially planar surface, the second dielectric layer being directly bonded to the first dielectric layer without the use of an adhesive, and the first and second substantially planar surfaces of the first and second base semiconductor layers having undercuts at the periphery of the first and second base semiconductor layers such that an area occupied by the first base semiconductor layer and an area occupied by the second base semiconductor layer are smaller than an area of ​​the first and / or second dielectric layers, respectively.

6. 6. The microelectronic system of claim 5, wherein the undercut corresponds to an undercut in the periphery of the first and / or second dielectric layers of the first microelectronic component and / or the second microelectronic component.

7. 1. A method for forming a microelectronic system, comprising: singulating a plurality of semiconductor die components from a wafer component, each of the semiconductor die components having a substantially flat surface; removing particles and debris of material from edges of the plurality of semiconductor die components; and bonding one or more of the plurality of semiconductor die components via the substantially flat surface to a prepared bonding surface.

8. 8. The method for forming a microelectronic system of claim 7, further comprising etching said edges of said plurality of semiconductor die components to remove said particles and debris from said edges of said plurality of semiconductor die components.

9. 9. The method for forming a microelectronic system of claim 8, further comprising etching the edges of the plurality of semiconductor die components while the plurality of semiconductor die components are on a dicing carrier.

10. 10. The method for forming a microelectronic system of claim 8, further comprising etching the edges of the plurality of semiconductor die components using a chemical etchant comprising hydrofluoric acid and nitric acid along with benzotriazole (BTA).

11. 9. The method for forming a microelectronic system of claim 8, further comprising etching said edges of said plurality of semiconductor die components using a plasma etch.

12. 9. The method for forming a microelectronic system of claim 8, further comprising etching edges of the plurality of semiconductor die components to reduce a thickness of the plurality of semiconductor die components such that a space is created at one or more of the edges of each of the plurality of semiconductor die components.

13. 9. The method for forming a microelectronic system of claim 8, wherein the semiconductor die components include an oxide layer as the substantially planar surface, and the etching includes removing at least a portion of the oxide layer at the edges of the plurality of semiconductor die components.

14. 9. The method for forming a microelectronic system of claim 8, further comprising applying a protective coating to said substantially planar surfaces of said plurality of semiconductor die components prior to said etching to protect said substantially planar surfaces from an etching solution.

15. heating the plurality of semiconductor die components after singulation to recede the protective coating from a periphery of the plurality of semiconductor die components; 15. The method for forming a microelectronic system of claim 14, further comprising: etching said periphery of said plurality of semiconductor die components to a preselected depth.

16. 16. The method for forming a microelectronic system of claim 15, wherein the plurality of semiconductor die components includes a dielectric layer over a base semiconductor layer, and etching the periphery of the plurality of semiconductor die components includes removing the dielectric layer and exposing the base semiconductor layer at the periphery of the plurality of semiconductor die components.

17. 8. The method for forming a microelectronic system of claim 7, further comprising etching said substantially planar surfaces of said plurality of semiconductor die components.

18. 20. The method for forming a microelectronic system of claim 17, further comprising etching the substantially planar surface to a preselected depth or for a preselected duration.

19. 8. The method for forming a microelectronic system of claim 7, wherein said one or more of said plurality of semiconductor die components are bonded using either an adhesive-free direct bonding technique or metal-to-metal diffusion bonding.

20. 8. The method for forming a microelectronic system of claim 7, further comprising removing particles and debris of material from sidewalls of said plurality of semiconductor die components, said particles and debris being removed from said sidewalls by etching said sidewalls of said plurality of semiconductor die components.

21. 8. The method for forming a microelectronic system of claim 7, further comprising coating sidewalls of the plurality of semiconductor die components with particles and debris of a material, the particles and debris being coated on the sidewalls by depositing a coating layer on the sidewalls of the plurality of semiconductor die components.

22. 22. The method for forming a microelectronic system of claim 21 further comprising spin coating or electrocoating said sidewalls of said plurality of semiconductor die components with glass, boron doped glass, or phosphorus doped glass.

23. 23. The method for forming a microelectronic system of claim 22, further comprising thermally curing said glass, said boron doped glass, or said phosphorus doped glass onto said sidewalls of said plurality of semiconductor die components.

24. An apparatus comprising: a first microelectronic component comprised of at least a dielectric layer, said dielectric layer having a substantially planar surface; a second microelectronic component directly bonded without an adhesive to the dielectric layer of the first microelectronic component, the dielectric layer having an undercut at a periphery of the first microelectronic component such that an area of ​​the dielectric layer is smaller than an area occupied by the first and / or second microelectronic components.

25. 22. The apparatus of claim 21, wherein the first microelectronic component or the second microelectronic component comprises a direct bandgap or an indirect bandgap semiconductor.

26. An apparatus comprising: a first component consisting of at least a planar dielectric layer; a second component bonded directly to the dielectric layer of the first component without the use of an adhesive, the dielectric layer having an undercut at a perimeter of the first component.

27. 27. The apparatus of claim 26, wherein the first component or the second component comprises a direct or indirect bandgap semiconductor.

28. 27. The apparatus of claim 26, wherein the first component or the second component comprises a non-semiconductor material.

29. 27. The apparatus of claim 26, wherein the first component and the second component comprise a microelectronic die.

30. 1. A method of forming a device, comprising: Singulating a microelectronic component having a substantially flat surface into a plurality of subcomponents; removing particles and debris of material from the edges of the sub-components; and bonding one or more of the sub-components to a prepared bonding surface having a substantially flat surface.

31. An apparatus comprising: a first component consisting of at least a planar dielectric layer; a second component directly bonded without adhesive to the dielectric layer of the first component such that an area of ​​the dielectric layer is smaller than a footprint of the first and / or second microelectronic components.

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